; --------------------------------------------------------------------------------
; @Title: AM62x On-Chip Peripherals
; @Props: Released
; @Author: NEJ
; @Changelog: 2022-09-07 NEJ
; @Manufacturer: TI - Texas Instruments
; @Doc: XML generated (TIXML2PER 2.1.5), based on: AM62x.xml (Rev. 2)
; @Core: CortexA53, CortexR5F, CortexM4F, PRU
; @Chip: AM623X, AM623X-CR5, AM623X-CM4-BLAZAR, AM623X-CM4-SMS0,
;        AM623X-CM4-SMS1, AM623X-ICSS0, AM625X, AM625X-CR5,
;        AM625X-CM4-BLAZAR, AM625X-CM4-SMS0, AM625X-CM4-SMS1, AM625X-ICSS0
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: peram62x.per 16159 2023-05-25 13:48:23Z apopow $

sif !cpuis("AM62*X-ICSS0")
sif (CORENAME()=="CORTEXA53")
tree "Core Registers (Cortex-A53)"
AUTOINDENT.PUSH
AUTOINDENT.ON center tree
tree.open "AArch64"
tree "ID Registers"
rgroup.quad spr:0x30000++0x0
line.long 0x0 "MIDR_EL1,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code"
bitfld.long 0x0 20.--23.  "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19.  "ARCH,Architecture" "Reserved,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CPUID scheme"
newline
hexmask.long.word 0x0 4.--15. 0x1 "PART,Primary Part Number"
bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x30005++0x00
line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register"
bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..."
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
newline
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
bitfld.quad 0x00 0.--1. "CPUID,CPU ID" "1,2,3,4"
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30005++0x00
line.quad 0x0 "MPIDR_EL1,Multiprocessor Affinity Register"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity level 3. Third highest level affinity field"
newline
bitfld.quad 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Largely independent,?..."
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
newline
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field"
endif
rgroup.quad SPR:0x30006++0x0
line.long 0x0 "REVIDR_EL1,Revision ID Register"
rgroup.quad SPR:0x30014++0x00
line.long 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30015++0x00
line.long 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..."
bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.quad SPR:0x30016++0x00
line.long 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.quad SPR:0x30017++0x00
line.long 0x00 "ID_MMFR3_EL1,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..."
bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,Reserved,?..."
newline
bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30026++0x00
line.long 0x00 "ID_MMFR4_EL1,Memory Model Feature Register 4"
bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..."
bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..."
bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..."
newline
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
newline
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,AArch64 Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "4KB,4KB granule supported" "Supported,?..."
bitfld.quad 0x00 24.--27. "64KB,64KB granule supported" "Supported,?..."
bitfld.quad 0x00 20.--23. "16KB,16KB granule supported" "Not supported,?..."
newline
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
newline
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..."
endif
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30071++0x00
line.quad 0x00 "ID_AA64MMFR1_EL1,AArch64 Memory Model Feature Register 1"
endif
rgroup.quad SPR:0x30020++0x00
line.long 0x00 "ID_ISAR0_EL1,Instruction Set Attribute Register 0"
bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..."
rgroup.quad SPR:0x30021++0x00
line.long 0x00 "ID_ISAR1_EL1,Instruction Set Attribute Register 1"
bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..."
rgroup.quad SPR:0x30022++0x00
line.long 0x00 "ID_ISAR2_EL1,Instruction Set Attribute Register 2"
bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30023++0x00
line.long 0x00 "ID_ISAR3_EL1,Instruction Set Attribute Register 3"
bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..."
bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.quad SPR:0x30024++0x00
line.long 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4"
bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..."
newline
bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30025++0x00
line.long 0x00 "ID_ISAR5_EL1,Instruction Set Attribute Register 5"
bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..."
newline
bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..."
rgroup.quad spr:0x30060++0x00
line.quad 0x00 "ID_AA64ISAR0_EL1,AArch64 Instruction Set Attribute Register 0"
bitfld.quad 0x00 16.--19. "CRC32,CRC32" "Reserved,Implemented,?..."
bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions are implemented" "Not implemented,Implemented,?..."
bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions are implemented" "Not implemented,Implemented,?..."
newline
bitfld.quad 0x00 4.--7. "AES,AES instructions are implemented" "Not implemented,Reserved,Implemented,?..."
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30061++0x00
line.quad 0x00 "ID_AA64ISAR1_EL1,AArch64 Instruction Set Attribute Register 1"
endif
rgroup.quad SPR:0x30010++0x00
line.long 0x00 "ID_PFR0_EL1,Processor Feature Register 0"
bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.quad SPR:0x30011++0x00
line.long 0x00 "ID_PFR1_EL1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0"
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..."
bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,?..."
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,?..."
newline
bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
newline
bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,AArch64 Processor Feature Register 0"
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..."
bitfld.quad 0x00 20.--23. "ADVSIMD,Advanced SIMD" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
newline
bitfld.quad 0x00 12.--15. "EL3H,EL3 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 8.--11. "EL2H,EL2 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 4.--7. "EL1H,EL1 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
newline
bitfld.quad 0x00 0.--3. "EL0H,EL0 exception handling" "Reserved,Reserved,AArch64/AArch32,?..."
endif
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30041++0x00
line.quad 0x00 "ID_AA64PFR1_EL1,AArch64 Processor Feature Register 1"
endif
if (CORENAME()=="CORTEXA57")
rgroup.quad SPR:0x30012++0x00
line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad SPR:0x30012++0x00
line.long 0x00 "ID_DFR0_EL1,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
endif
rgroup.quad spr:0x30050++0x00
line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register 0"
bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "Reserved,2,?..."
bitfld.quad 0x00 20.--23. "WRPS,The number of watchpoints minus 1" "Reserved,Reserved,Reserved,4,?..."
bitfld.quad 0x00 12.--15. "BRPS,The number of breakpoints minus 1" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
newline
bitfld.quad 0x00 8.--11. "PMUVER,Performance Monitors extension version" "Reserved,Implemented,?..."
bitfld.quad 0x00 4.--7. "TRACEVER,Trace extension" "Not implemented,?..."
bitfld.quad 0x00 0.--3. "DEBUGGER,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented,?..."
if (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x30051++0x00
line.quad 0x00 "ID_AA64DFR1_EL1,AArch64 Debug Feature Register 1"
rgroup.quad spr:0x30054++0x00
line.quad 0x00 "ID_AA64AFR0_EL1,AArch64 Auxiliary Feature Register 0"
rgroup.quad spr:0x30055++0x00
line.quad 0x00 "ID_AA64AFR1_EL1,AArch64 Auxiliary Feature Register 1"
endif
rgroup.quad SPR:0x30013++0x00
line.long 0x00 "ID_AFR0_EL1,Auxiliary Feature Register 0"
rgroup.quad SPR:0x31007++0x00
line.long 0x00 "AIDR_EL1,Auxiliary ID Register"
rgroup.quad SPR:0x33007++0x00
line.long 0x00 "DCZID_EL0,Data Cache Zero ID"
bitfld.long 0x00 4. "DZP,Prohibit the DC ZVA instruction" "Not prohibited,Prohibited"
bitfld.long 0x00 0.--3. "BS,Block Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
tree.end
tree "System Control and Configuration"
group.quad spr:0x36111++0x00
line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register"
bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled"
bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled"
group.quad SPR:0x30100++0x0
line.long 0x00 "SCTLR_EL1,System Control Register (EL1)"
bitfld.long 0x0 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 24. "E0E,Endianness of explicit data access at EL0" "Little,Big"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled"
bitfld.long 0x0 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 9. "UMA,User Mask Access" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT instruction disable" "No,Yes"
newline
bitfld.long 0x00 6. "THEE,Thumb EE enable" "Disabled,Enabled"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled"
bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad SPR:0x34100++0x0
line.long 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad SPR:0x36100++0x0
line.long 0x00 "SCTLR_EL3,System Control Register (EL3)"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
rgroup.quad SPR:0x30101++0x0
line.long 0x00 "ACTLR_EL1,Auxiliary Control Register (EL1)"
group.quad SPR:0x34101++0x0
line.long 0x00 "ACTLR_EL2,Auxiliary Control Register (EL2)"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
group.quad SPR:0x36101++0x0
line.long 0x00 "ACTLR_EL3,Auxiliary Control Register (EL3)"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
group.quad SPR:0x30102++0x00
line.long 0x00 "CPACR_EL1,Architectural Feature Access Control Register"
bitfld.long 0x00 28. "TTA,Causes access to the Trace functionality to trap to EL1 when executed from EL0 or EL1" "Disabled,?..."
bitfld.long 0x00 20.--21. "FPEN,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution to trap to EL1 when executed from EL0 or EL1" "Trap all,Trap El0,Trap all,Not trapped"
group.quad SPR:0x36110++0x0
line.long 0x0 "SCR_EL3,Secure Configuration Register"
bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped"
bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped"
newline
bitfld.long 0x00 11. "ST,Enable secure EL1 access" "Disabled,Enabled"
bitfld.long 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64"
newline
bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes"
newline
bitfld.long 0x00 7. "SMD,Secure Monitor Call disable" "No,Yes"
bitfld.long 0x00 3. "EA,External Abort  exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
newline
bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
newline
bitfld.long 0x00 0. "NS,Secure mode" "Secure,Non-secure"
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes"
newline
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit"
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
newline
bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled"
bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled"
bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
newline
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending"
bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
group.quad spr:0x30510++0x00
line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)"
group.quad spr:0x30511++0x00
line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)"
group.quad spr:0x34510++0x00
line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)"
group.quad spr:0x34511++0x00
line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)"
group.quad spr:0x36510++0x00
line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)"
group.quad spr:0x36511++0x00
line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)"
tree.open "Exception Syndrome Registers"
if (CORENAME()=="CORTEXA57")
if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..."
elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 9. "EA,External abort type" "DECERR,SLVERR"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/TTBR[0/1],Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort,Reserved,Reserved,Reserved,Reserved,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity,Reserved,Reserved,Reserved,Reserved,Sync. parity/1st level,Sync. parity/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Debug,?..."
elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
elif (CORENAME()=="CORTEXA53")
if (((d.l(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x30520))&0xFC000000)==0x04000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x18000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==0x1C000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x30520))&0xFC000000)==0x60000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBD000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SES,System Error Source" "Processor,System,External,"
newline
hexmask.long.tbyte 0x00 0.--21. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x30520))&0xFD000000)==0xBC000000)
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x30520++0x00
line.long 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x34520))&0xFC000000)==0x04000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x18000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==0x1C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x5C000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x34520))&0xFC000000)==0x60000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBD000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x34520))&0xFD000000)==0xBC000000)
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.long 0x00 6. "EX,Exclusive operation" "No,Yes"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,%d..."
elif (((d.l(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x34520++0x00
line.long 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
if (((d.l(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000||0x4C000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((d.l(spr:0x36520))&0xFC000000)==0x04000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 17.--19. "Opc2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14.--16. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 16.--19. "Opc1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--14. "Rt2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x18000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
hexmask.long.byte 0x00 12.--19. 1 "IMM8,The immediate value from the issued instruction"
bitfld.long 0x00 5.--9. "Rn,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x1C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x5C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. "IMM16,The value of the immediate field from the issued SMC instruction"
elif (((d.l(spr:0x36520))&0xFC000000)==0x60000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.long 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.long 0x00 20.--21. "Op0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.long 0x00 17.--19. "Op2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "Op1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRn,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--9. "Rt,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 1.--4. "CRm,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((d.l(spr:0x36520))&0xFC000000)==0x7C000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long 0x00 0.--24. 1 "IMPL_DEF,Implementation defined"
elif (((d.l(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/0th level/base register,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1st level,Sync. external abort/2nd level,Sync. external abort/3rd level,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (((d.l(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
bitfld.long 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.long 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000))
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "No,Yes"
bitfld.long 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.long 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.long 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/0th level,Sync. parity/ECC/1st level,Sync. parity/ECC/2nd level,Sync. parity/ECC/3rd level,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0800000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.long 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.long 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((d.l(spr:0x36520))&0xFC800000)==0xB0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.long 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBD000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
hexmask.long.tbyte 0x00 0.--23. 1 "IS,Additional information about the SError interrupt"
elif (((d.l(spr:0x36520))&0xFD000000)==0xBC000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
elif (((d.l(spr:0x36520))&0xFC000000)==0xF0000000)
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
bitfld.long 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.long.word 0x00 0.--15. 1 "COMMENT,Set to the instruction comment field value"
else
group.quad SPR:0x36520++0x00
line.long 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.long 0x00 26.--31. "EC,Exception class"  "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,IMPLEMENTATION DEFINED,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved"
endif
endif
tree.end
newline
if (CORENAME()=="CORTEXA57")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
elif (CORENAME()=="CORTEXA53")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
endif
group.quad spr:0x30600++0x00
line.quad 0x00 "FAR_EL1,Fault Address Register"
group.quad spr:0x34600++0x00
line.quad 0x00 "FAR_EL2,Fault Address Register"
group.quad spr:0x36600++0x00
line.quad 0x00 "FAR_EL3,Fault Address Register"
group.quad spr:0x34604++0x00
line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register"
group.quad spr:0x30C00++0x00
line.quad 0x00 "VBAR_EL1,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address"
group.quad spr:0x34C00++0x00
line.quad 0x00 "VBAR_EL2,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address"
group.quad spr:0x36C00++0x00
line.quad 0x00 "VBAR_EL3,Vector Base Address Register"
hexmask.quad 0x00 11.--63. 0x800 "VBA,Vector base address"
rgroup.quad spr:0x36C01++0x00
line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register"
hexmask.quad 0x00 2.--43. 0x4 "RVBA,Reset Vector Base Address"
rgroup.quad SPR:0x30C10++0x00
line.long 0x00 "ISR_EL1,Interrupt Status Register"
bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending"
bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending"
newline
bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending"
group.quad SPR:0x36C02++0x00
line.long 0x00 "RMR_EL3,Reset Management Register"
bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warmreset" "AArch32,AArch64"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x31F30++0x00
line.quad 0x00 "CBAR_EL1,Configuration Base Address Register"
hexmask.quad.long 0x00 18.--43. 1. "PERIPHBASE[43:18],Periphbase[43:18]"
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x31F30++0x00
line.quad 0x00 "CBAR_EL1,Configuration Base Address Register"
hexmask.quad.tbyte 0x00 18.--39. 1. "PERIPHBASE[39:18],Periphbase[39:18]"
endif
group.quad spr:0x30D01++0x00
line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register"
group.quad spr:0x33D02++0x00
line.quad 0x00 "TPIDR_EL0,Software Thread ID Register"
group.quad spr:0x33D03++0x00
line.quad 0x00 "TPIDRRO_EL0,Software Thread ID Register"
group.quad spr:0x30D04++0x00
line.quad 0x00 "TPIDR_EL1,Software Thread ID Register"
group.quad spr:0x34D02++0x00
line.quad 0x00 "TPIDR_EL2,Software Thread ID Register"
group.quad spr:0x36D02++0x00
line.quad 0x00 "TPIDR_EL3,Software Thread ID Register"
tree.end
tree "Memory Management Unit"
group.quad spr:0x30100++0x0
line.quad 0x00 "SCTLR_EL1,System Control Register (EL1)"
bitfld.quad 0x00 26. "UCI,EL0 access enable (DC CVAU|DC CIVAC|DC CVAC|IC IVAU)" "Disabled,Enabled"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.quad 0x00 24. "E0E,Endianness of explicit data access at EL0" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.quad 0x00 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.quad 0x00 15. "UCT,EL0 access enable (CTR_EL0)" "Disabled,Enabled"
bitfld.quad 0x00 14. "DZE,EL0 access enable (DC ZVA)" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 9. "UMA,User Mask Access" "Disabled,Enabled"
newline
bitfld.quad 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.quad 0x00 7. "ITD,IT instruction disable" "No,Yes"
newline
bitfld.quad 0x00 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "SA0,EL0 stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x34100++0x0
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x36100++0x0
line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x30200++0x00
line.quad 0x00 "TTBR0_EL1,Translation Table Base Register 0 (EL1)"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad spr:0x30201++0x00
line.quad 0x00 "TTBR1_EL1,Translation Table Base Register 1 (EL1)"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x30202++0x00
line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)"
bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit"
bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..."
newline
bitfld.quad 0x00 30. "TG1,TTBR1_EL1 granule size" "4 KByte,64 KByte"
bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled"
bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB"
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x30202++0x00
line.quad 0x00 "TCR_EL1,Translation Control Register (EL1)"
bitfld.quad 0x00 38. "TBI1,Top Byte Ignored 1" "Not ignored,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte Ignored 0" "Not ignored,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID size" "8-bit,16-bit"
bitfld.quad 0x00 32.--34. "IPS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
newline
bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 granule size" "Reserved,Reserved,4 KB,64 KB"
bitfld.quad 0x00 28.--29. "SH1,Shareability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation table walk disable for translations using TTBR1_EL1" "Enabled,Disabled"
bitfld.quad 0x00 22. "A1,Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region addressed by TTBR1_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL1 granule size" "4 KB,64 KB,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 7. "EPD0,Translation table walk disable for translations using TTBR0" "Enabled,Disabled"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x34200++0x00
line.quad 0x00 "TTBR0_EL2,Translation Table Base Register 0 (EL2)"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..."
newline
bitfld.quad 0x00 14. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB"
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Register (EL2)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL2 granule size" "4 KB,64 KB,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x36200++0x00
line.quad 0x00 "TTBR0_EL3,Translation Table Base Register 0 (EL3)"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x36202++0x00
line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,42 bits/4 TB,44 bits/16 TB,48 bits/256 TB,?..."
newline
bitfld.quad 0x00 14. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB"
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x36202++0x00
line.quad 0x00 "TCR_EL3,Translation Control Register (EL3)"
bitfld.quad 0x00 20. "TBI,Top Byte Ignored" "Not ignored,Ignored"
bitfld.quad 0x00 16.--18. "PS,Intermediate Physical Address Size" "32 bits/4 GB,36 bits/64 GB,40 bits/1 TB,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,TTBR0_EL3 granule size" "4 KB,64 KB,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region addressed by TTBR0_EL3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad SPR:0x34300++0x00
line.long 0x00 "DACR32_EL2,Domain Access Control Register"
bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
if (CORENAME()=="CORTEXA57")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/0th level/TTBR0/TTBR1,Reserved,Reserved,Reserved,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
elif (CORENAME()=="CORTEXA53")
if (((per.q(spr:0x34501))&0x200)==0x200)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.quad 0x00 9. "LPAE,Translation table formats on taking a Data Abort exception" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
endif
rgroup.quad SPR:0x30510++0x00
line.long 0x00 "AFSR0_EL1,Auxiliary Fault Status Register 0 (EL1)"
rgroup.quad SPR:0x34510++0x00
line.long 0x00 "AFSR0_EL2,Auxiliary Fault Status Register 0 (EL2)"
rgroup.quad SPR:0x36510++0x00
line.long 0x00 "AFSR0_EL3,Auxiliary Fault Status Register 0 (EL3)"
rgroup.quad SPR:0x30511++0x00
line.long 0x00 "AFSR1_EL1,Auxiliary Fault Status Register 1 (EL1)"
rgroup.quad SPR:0x34511++0x00
line.long 0x00 "AFSR1_EL2,Auxiliary Fault Status Register 1 (EL2)"
rgroup.quad SPR:0x36511++0x00
line.long 0x00 "AFSR1_EL3,Auxiliary Fault Status Register 1 (EL3)"
if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device-not nGnRnE,?..."
newline
hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif (((per.q(spr:0x30740))&0x01)==0x00)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Reserved,Reserved,Reserved,Normal/Non-cacheable,Reserved,Reserved,Reserved,Normal/Write-Through,Normal/Write-Through/Write,Normal/Write-Through/Read,Normal/Write-Through/Write|Read,Normal/Write-Back,Normal/Write-Back/Write,Normal/Write-Back/Read,Normal/Write-Back/Write|Read"
newline
hexmask.quad 0x00 12.--47. 0x10 "PA[47:12],Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
else
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
newline
bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
newline
bitfld.quad 0x00 1.--6. "FST,Fault status field" "Address size/0th level/TTBR,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3d level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Reserved,Reserved,Reserved,Reserved,Sync. external abort/0th level,Sync. external abort/1th level,Sync. external abort/2th level,Sync. external abort/3th level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,?..."
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
endif
tree.open "Memory Attribute Indirection Registers"
group.quad spr:0x30A20++0x00
line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
group.quad spr:0x34A20++0x00
line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
group.quad spr:0x36A20++0x00
line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device memory,Write-through transient/Write-Allocate,Write-through transient/Read-Allocate,Write-through transient/Write-Allocate/Read-Allocate,Non-Cacheable,Write-back transient/Write-Allocate,Write-back transient/Read-Allocate,Write-back transient/Write-Allocate/Read-Allocate,Write-Through non-transient,Write-Through non-transient/Write-Allocate,Write-Through non-transient/Read-Allocate,Write-Through non-transient/Write-Allocate/Read-Allocate,Write-Back non-transient,Write-Back non-transient/Write-Allocate,Write-Back non-transient/Read-Allocate,Write-Back non-transient/Write-Allocate/Read-Allocate"
rgroup.quad spr:0x30A30++0x00
line.quad 0x00 "AMAIR_EL1,Memory Attribute Indirection Register (EL1)"
rgroup.quad spr:0x34A30++0x00
line.quad 0x00 "AMAIR_EL2,Memory Attribute Indirection Register (EL2)"
rgroup.quad spr:0x36A30++0x00
line.quad 0x00 "AMAIR_EL3,Memory Attribute Indirection Register (EL3)"
tree.end
newline
group.quad SPR:0x30D01++0x00
line.long 0x0 "CONTEXTIDR_EL1,Context ID Register"
tree.end
tree "Virtualization Extensions"
group.quad SPR:0x34000++0x0
line.long 0x0 "VPIDR_EL2,Virtualization Processor ID Register"
if (CORENAME()=="CORTEXA57")
group.quad spr:0x34005++0x00
line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register"
hexmask.quad.long 0x00 0.--31. 1. "VMPIDR_EL2,MPIDR value returned by Non-secure EL1 reads of the MPIDR_EL1"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x34005++0x00
line.quad 0x0 "VMPIDR_EL2,Virtualization Multiprocessor ID Register"
endif
group.quad spr:0x34100++0x0
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP stack alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register"
bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes"
newline
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit"
bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
newline
bitfld.quad 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unificiation to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency tp EL2" "Disabled,Enabled"
bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "Disabled,Enabled"
bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
newline
bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "No pending,Pending"
bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
bitfld.quad 0x00 5. "AMO,asynchronous abort and error interrupt routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.quad 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x34111++0x00
line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
newline
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
elif (CORENAME()=="CORTEXA53")
group.quad SPR:0x34111++0x00
line.long 0x00 "MDCR_EL2,Hypervisor Debug Control Register (EL2)"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
newline
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6"
endif
group.quad SPR:0x34112++0x00
line.long 0x00 "CPTR_EL2,Architectural Feature Trap Register (EL2)"
bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped"
group.quad SPR:0x36131++0x00
line.long 0x00 "MDCR_EL3,Hypervisor Debug Control Register (EL3)"
bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes"
bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes"
bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "SDD,AArch64 secure debug disable" "No,Yes"
bitfld.long 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
newline
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
group.quad SPR:0x36112++0x00
line.long 0x00 "CPTR_EL3,Architectural Feature Trap Register (EL3)"
bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.long 0x0 10. "TFP,Traps instructions that access registers associated with Advanced SIMD and Floating-point execution from a lower exception level to EL2" "Not trapped,Trapped"
group.quad SPR:0x34113++0x00
line.long 0x00 "HSTR_EL2,Hypervisor System Trap Register"
bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Not supported,?..."
bitfld.long 0x00 15. "T15,Trap coprocessor primary register CRn = 15" "No effect,Trapped"
bitfld.long 0x00 13. "T13,Trap coprocessor primary register CRn = 13" "No effect,Trapped"
newline
bitfld.long 0x00 12. "T12,Trap coprocessor primary register CRn = 12" "No effect,Trapped"
bitfld.long 0x00 11. "T11,Trap coprocessor primary register CRn = 11" "No effect,Trapped"
bitfld.long 0x00 10. "T10,Trap coprocessor primary register CRn = 10" "No effect,Trapped"
newline
bitfld.long 0x00 9. "T9,Trap coprocessor primary register CRn = 9" "No effect,Trapped"
bitfld.long 0x00 8. "T8,Trap coprocessor primary register CRn = 8" "No effect,Trapped"
bitfld.long 0x00 7. "T7,Trap coprocessor primary register CRn = 7" "No effect,Trapped"
newline
bitfld.long 0x00 6. "T6,Trap coprocessor primary register CRn = 6" "No effect,Trapped"
bitfld.long 0x00 5. "T5,Trap coprocessor primary register CRn = 5" "No effect,Trapped"
bitfld.long 0x00 3. "T3,Trap coprocessor primary register CRn = 3" "No effect,Trapped"
newline
bitfld.long 0x00 2. "T2,Trap coprocessor primary register CRn = 2" "No effect,Trapped"
bitfld.long 0x00 1. "T1,Trap coprocessor primary register CRn = 1" "No effect,Trapped"
bitfld.long 0x00 0. "T0,Trap coprocessor primary register CRn = 0" "No effect,Trapped"
rgroup.quad SPR:0x34117++0x00
line.long 0x00 "HACR_EL2,Hypervisor Auxiliary Configuration Register"
group.quad spr:0x34210++0x00
line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "VMID,VMID for the translation table"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x34212++0x00
line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,42 bits/4TB,44 bits/16TB,48 bits/256TB,?..."
bitfld.long 0x00 14. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3"
bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (CORENAME()=="CORTEXA53")
group.quad SPR:0x34212++0x00
line.long 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.long 0x00 16.--18. "PS,Physical Address Size" "32 bits/4GB,36 bits/64GB,40 bits/1TB,?..."
bitfld.long 0x00 14.--15. "TG0,Granule size for the corresponding translation table base address register" "4 KB,64 KB,?..."
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3"
bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x34604++0x00
line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register"
hexmask.quad 0x00 4.--39. 0x10 "FIPA,Faulting IPA bits"
tree.end
tree "Cache Control and Configuration"
if (CORENAME()=="CORTEXA57")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad spr:0x33001++0x0
line.long 0x0 "CTR_EL0,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
group.quad SPR:0x32000++0x0
line.long 0x0 "CSSELR_EL1,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..."
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
if (CORENAME()=="CORTEXA57")
rgroup.quad SPR:0x31001++0x0
line.long 0x0 "CLIDR_EL1,Cache Level ID Register"
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..."
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
newline
bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..."
bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..."
bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..."
newline
bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
rgroup.quad SPR:0x31000++0x0
line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register"
bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..."
bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported"
bitfld.long 0x00 29. "RA,Read-Allocate" "Reserved,Supported"
newline
bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.quad SPR:0x31001++0x0
line.long 0x0 "CLIDR_EL1,Cache Level ID Register"
bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..."
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..."
newline
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
rgroup.quad SPR:0x31000++0x0
line.long 0x0 "CCSIDR_EL1,Current Cache Size ID Register"
bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,?..."
bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported"
bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported"
newline
bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "1Reserved,Reserved,64 bytes,?..."
endif
tree "Level 1 memory system"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x30F10++0x00
line.long 0x00 "DL1DATA0_EL1,Data L1 Data 0 Register"
group.quad SPR:0x30F11++0x00
line.long 0x00 "DL1DATA1_EL1,Data L1 Data 1 Register"
group.quad SPR:0x30F12++0x00
line.long 0x00 "DL1DATA2_EL1,Data L1 Data 2 Register"
group.quad SPR:0x30F13++0x00
line.long 0x00 "DL1DATA3_EL1,Data L1 Data 3 Register"
group.quad SPR:0x30F00++0x00
line.long 0x00 "IL1DATA0_EL1,Instruction L1 Data 0 Register"
group.quad SPR:0x30F01++0x00
line.long 0x00 "IL1DATA1_EL1,Instruction L1 Data 1 Register"
group.quad SPR:0x30F02++0x00
line.long 0x00 "IL1DATA2_EL1,Instruction L1 Data 2 Register"
group.quad SPR:0x30F03++0x00
line.long 0x00 "IL1DATA3_EL1,Instruction L1 Data 3 Register"
group.quad spr:0x31F20++0x00
line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register"
bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced"
bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes"
bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes"
newline
bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled"
bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes"
bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes"
newline
bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled"
bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled"
bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes"
newline
bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes"
bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes"
bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes"
newline
bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes"
bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes"
bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
newline
bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes"
bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced"
bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes"
newline
bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced"
bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes"
bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes"
bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled"
bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced"
newline
bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled"
bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled"
bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
newline
bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled"
bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced"
bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced"
newline
bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes"
bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes"
bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes"
newline
bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes"
bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes"
bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced"
bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced"
bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled"
bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled"
bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced"
newline
bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes"
bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled"
bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled"
bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes"
bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes"
bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled"
group.quad spr:0x31F21++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes"
bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines"
bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines"
newline
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..."
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks,?..."
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x31F20++0x00
line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register"
bitfld.quad 0x00 44. "ENDCCASCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes"
bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes"
newline
bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled"
bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes"
newline
bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes"
bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes"
bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes"
newline
bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams"
bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled"
bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled"
newline
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,8"
bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes"
bitfld.quad 0x00 6. "L1DEIEN,L1 D-cache data RAM error injection enable" "Disabled,Enabled"
group.quad spr:0x31F21++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
endif
if (CORENAME()=="CORTEXA57")
group.quad spr:0x31F22++0x00
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address"
elif (CORENAME()=="CORTEXA53")
group.quad spr:0x31F22++0x00
line.quad 0x00 "CPUMERRSR_EL1,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address"
endif
tree.end
tree "Level 2 memory system"
if (CORENAME()=="CORTEXA57")
group.quad SPR:0x31B02++0x0
line.long 0x00 "L2CTLR_EL1,L2 Control Register"
bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes"
bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4"
rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
bitfld.long 0x00 20. "DIECCE,Data inline ECC enable" "Disabled,Enabled"
rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not presented,Presented"
newline
rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not presented,Presented"
rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not presented,1,2,?..."
bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle"
newline
bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles"
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle"
bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
group.quad SPR:0x31B03++0x0
line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad SPR:0x31F00++0x00
line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register"
bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled"
bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled"
bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced"
newline
bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled"
bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes"
bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes"
newline
bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled"
bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit"
bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes"
newline
bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled"
bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes"
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
newline
bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes"
bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes"
bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes"
newline
bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes"
bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled"
bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes"
newline
bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled"
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited"
newline
bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled"
bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes"
group.quad spr:0x31F23++0x00
line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index"
elif (CORENAME()=="CORTEXA53")
group.quad SPR:0x31B02++0x0
line.long 0x00 "L2CTLR_EL1,L2 Control Register"
bitfld.long 0x00 24.--25. "NCPU,Number of CPU" "1,2,3,4"
bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled"
rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
newline
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle"
rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles"
group.quad SPR:0x31B03++0x0
line.long 0x00 "L2ECTLR_EL1,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad SPR:0x31F00++0x00
line.long 0x00 "L2ACTLR_EL1,L2 Auxiliary Control Register"
bitfld.long 0x00 30.--31. "L2VC,L2 Victim Control" "0,1,2,3"
bitfld.long 0x00 29. "L2DEIEN,L2 cache data RAM error injection enable" "Disabled,Enabled"
bitfld.long 0x00 24. "L2TEIEN,L2 cache tag RAM error injection enable." "Disabled,Enabled"
newline
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
group.quad spr:0x31F23++0x00
line.quad 0x00 "L2MERRSR_EL1,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
newline
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address"
endif
tree.end
tree.end
tree "System Performance Monitor"
group.quad SPR:0x339C0++0x00
line.long 0x0 "PMCR_EL0,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
bitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
group.quad SPR:0x339C1++0x00
line.long 0x00 "PMCNTENSET_EL0,Count Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
bitfld.long 0x00  30. "P30,Event Counter 30 enable bit" "Disabled,Enabled"
bitfld.long 0x00  29. "P29,Event Counter 29 enable bit" "Disabled,Enabled"
bitfld.long 0x00  28. "P28,Event Counter 28 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  27. "P27,Event Counter 27 enable bit" "Disabled,Enabled"
bitfld.long 0x00  26. "P26,Event Counter 26 enable bit" "Disabled,Enabled"
bitfld.long 0x00  25. "P25,Event Counter 25 enable bit" "Disabled,Enabled"
bitfld.long 0x00  24. "P24,Event Counter 24 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  23. "P23,Event Counter 23 enable bit" "Disabled,Enabled"
bitfld.long 0x00  22. "P22,Event Counter 22 enable bit" "Disabled,Enabled"
bitfld.long 0x00  21. "P21,Event Counter 21 enable bit" "Disabled,Enabled"
bitfld.long 0x00  20. "P20,Event Counter 20 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  19. "P19,Event Counter 19 enable bit" "Disabled,Enabled"
bitfld.long 0x00  18. "P18,Event Counter 18 enable bit" "Disabled,Enabled"
bitfld.long 0x00  17. "P17,Event Counter 17 enable bit" "Disabled,Enabled"
bitfld.long 0x00  16. "P16,Event Counter 16 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  15. "P15,Event Counter 15 enable bit" "Disabled,Enabled"
bitfld.long 0x00  14. "P14,Event Counter 14 enable bit" "Disabled,Enabled"
bitfld.long 0x00  13. "P13,Event Counter 13 enable bit" "Disabled,Enabled"
bitfld.long 0x00  12. "P12,Event Counter 12 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  11. "P11,Event Counter 11 enable bit" "Disabled,Enabled"
bitfld.long 0x00  10. "P10,Event Counter 10 enable bit" "Disabled,Enabled"
bitfld.long 0x00  9. "P9,Event Counter 9 enable bit" "Disabled,Enabled"
bitfld.long 0x00  8. "P8,Event Counter 8 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  7. "P7,Event Counter 7 enable bit" "Disabled,Enabled"
bitfld.long 0x00  6. "P6,Event Counter 6 enable bit" "Disabled,Enabled"
bitfld.long 0x00  5. "P5,Event Counter 5 enable bit" "Disabled,Enabled"
bitfld.long 0x00  4. "P4,Event Counter 4 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00  3. "P3,Event Counter 3 enable bit" "Disabled,Enabled"
bitfld.long 0x00  2. "P2,Event Counter 2 enable bit" "Disabled,Enabled"
bitfld.long 0x00  1. "P1,Event Counter 1 enable bit" "Disabled,Enabled"
bitfld.long 0x00  0. "P0,Event Counter 0 enable bit" "Disabled,Enabled"
group.quad SPR:0x339C2++0x00
line.long 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00  30. "P30,Event Counter 30 clear bit" "Disabled,Enabled"
eventfld.long 0x00  29. "P29,Event Counter 29 clear bit" "Disabled,Enabled"
eventfld.long 0x00  28. "P28,Event Counter 28 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  27. "P27,Event Counter 27 clear bit" "Disabled,Enabled"
eventfld.long 0x00  26. "P26,Event Counter 26 clear bit" "Disabled,Enabled"
eventfld.long 0x00  25. "P25,Event Counter 25 clear bit" "Disabled,Enabled"
eventfld.long 0x00  24. "P24,Event Counter 24 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  23. "P23,Event Counter 23 clear bit" "Disabled,Enabled"
eventfld.long 0x00  22. "P22,Event Counter 22 clear bit" "Disabled,Enabled"
eventfld.long 0x00  21. "P21,Event Counter 21 clear bit" "Disabled,Enabled"
eventfld.long 0x00  20. "P20,Event Counter 20 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  19. "P19,Event Counter 19 clear bit" "Disabled,Enabled"
eventfld.long 0x00  18. "P18,Event Counter 18 clear bit" "Disabled,Enabled"
eventfld.long 0x00  17. "P17,Event Counter 17 clear bit" "Disabled,Enabled"
eventfld.long 0x00  16. "P16,Event Counter 16 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  15. "P15,Event Counter 15 clear bit" "Disabled,Enabled"
eventfld.long 0x00  14. "P14,Event Counter 14 clear bit" "Disabled,Enabled"
eventfld.long 0x00  13. "P13,Event Counter 13 clear bit" "Disabled,Enabled"
eventfld.long 0x00  12. "P12,Event Counter 12 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  11. "P11,Event Counter 11 clear bit" "Disabled,Enabled"
eventfld.long 0x00  10. "P10,Event Counter 10 clear bit" "Disabled,Enabled"
eventfld.long 0x00  9. "P9,Event Counter 9 clear bit" "Disabled,Enabled"
eventfld.long 0x00  8. "P8,Event Counter 8 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  7. "P7,Event Counter 7 clear bit" "Disabled,Enabled"
eventfld.long 0x00  6. "P6,Event Counter 6 clear bit" "Disabled,Enabled"
eventfld.long 0x00  5. "P5,Event Counter 5 clear bit" "Disabled,Enabled"
eventfld.long 0x00  4. "P4,Event Counter 4 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  3. "P3,Event Counter 3 clear bit" "Disabled,Enabled"
eventfld.long 0x00  2. "P2,Event Counter 2 clear bit" "Disabled,Enabled"
eventfld.long 0x00  1. "P1,Event Counter 1 clear bit" "Disabled,Enabled"
eventfld.long 0x00  0. "P0,Event Counter 0 clear bit" "Disabled,Enabled"
group.quad SPR:0x339C3++0x00
line.long 0x00 "PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
eventfld.long 0x00  30. "P30,Event Counter 30 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  29. "P29,Event Counter 29 clear bit" "Disabled,Enabled"
eventfld.long 0x00  28. "P28,Event Counter 28 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  27. "P27,Event Counter 27 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  26. "P26,Event Counter 26 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  25. "P25,Event Counter 25 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  24. "P24,Event Counter 24 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  23. "P23,Event Counter 23 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  22. "P22,Event Counter 22 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  21. "P21,Event Counter 21 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  20. "P20,Event Counter 20 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  19. "P19,Event Counter 19 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  18. "P18,Event Counter 18 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  17. "P17,Event Counter 17 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  16. "P16,Event Counter 16 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  15. "P15,Event Counter 15 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  14. "P14,Event Counter 14 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  13. "P13,Event Counter 13 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  12. "P12,Event Counter 12 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  11. "P11,Event Counter 11 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  10. "P10,Event Counter 10 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  9. "P9,Event Counter 9 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  8. "P8,Event Counter 8 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  7. "P7,Event Counter 7 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  6. "P6,Event Counter 6 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  5. "P5,Event Counter 5 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  4. "P4,Event Counter 4 overflow clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00  3. "P3,Event Counter 3 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  2. "P2,Event Counter 2 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  1. "P1,Event Counter 1 overflow clear bit" "Disabled,Enabled"
eventfld.long 0x00  0. "P0,Event Counter 0 overflow clear bit" "Disabled,Enabled"
wgroup.quad SPR:0x339C4++0x00
line.long 0x00 "PMSWINC_EL0,Performance Monitor Software Increment"
bitfld.long 0x00  30. "P30,Increment PMN30" "No action,Increment"
bitfld.long 0x00  29. "P29,Increment PMN29" "No action,Increment"
bitfld.long 0x00  28. "P28,Increment PMN28" "No action,Increment"
bitfld.long 0x00  27. "P27,Increment PMN27" "No action,Increment"
newline
bitfld.long 0x00  26. "P26,Increment PMN26" "No action,Increment"
bitfld.long 0x00  25. "P25,Increment PMN25" "No action,Increment"
bitfld.long 0x00  24. "P24,Increment PMN24" "No action,Increment"
bitfld.long 0x00  23. "P23,Increment PMN23" "No action,Increment"
newline
bitfld.long 0x00  22. "P22,Increment PMN22" "No action,Increment"
bitfld.long 0x00  21. "P21,Increment PMN21" "No action,Increment"
bitfld.long 0x00  20. "P20,Increment PMN20" "No action,Increment"
bitfld.long 0x00  19. "P19,Increment PMN19" "No action,Increment"
newline
bitfld.long 0x00  18. "P18,Increment PMN18" "No action,Increment"
bitfld.long 0x00  17. "P17,Increment PMN17" "No action,Increment"
bitfld.long 0x00  16. "P16,Increment PMN16" "No action,Increment"
bitfld.long 0x00  15. "P15,Increment PMN15" "No action,Increment"
newline
bitfld.long 0x00  14. "P14,Increment PMN14" "No action,Increment"
bitfld.long 0x00  13. "P13,Increment PMN13" "No action,Increment"
bitfld.long 0x00  12. "P12,Increment PMN12" "No action,Increment"
bitfld.long 0x00  11. "P11,Increment PMN11" "No action,Increment"
newline
bitfld.long 0x00  10. "P10,Increment PMN10" "No action,Increment"
bitfld.long 0x00  9. "P9,Increment PMN9" "No action,Increment"
bitfld.long 0x00  8. "P8,Increment PMN8" "No action,Increment"
bitfld.long 0x00  7. "P7,Increment PMN7" "No action,Increment"
newline
bitfld.long 0x00  6. "P6,Increment PMN6" "No action,Increment"
bitfld.long 0x00  5. "P5,Increment PMN5" "No action,Increment"
bitfld.long 0x00  4. "P4,Increment PMN4" "No action,Increment"
bitfld.long 0x00  3. "P3,Increment PMN3" "No action,Increment"
newline
bitfld.long 0x00  2. "P2,Increment PMN2" "No action,Increment"
bitfld.long 0x00  1. "P1,Increment PMN1" "No action,Increment"
bitfld.long 0x00  0. "P0,Increment PMN0" "No action,Increment"
group.quad SPR:0x339C5++0x00
line.long 0x00 "PMSELR_EL0,Performance Monitor Select Register"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.open "Common Event Identification Registers"
if (CORENAME()=="CORTEXA57")
rgroup.quad SPR:0x339C6++0x0
line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
newline
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
newline
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
newline
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
newline
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
newline
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
newline
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
elif (CORENAME()=="CORTEXA53")
rgroup.quad SPR:0x339C6++0x0
line.long 0x00 "PMCEID0_EL0,Common Event Identification Register 0"
bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
newline
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
newline
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
newline
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
newline
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
newline
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
newline
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
endif
rgroup.quad SPR:0x339C7++0x0
line.long 0x00 "PMCEID1_EL0,Common Event Identification Register 1"
bitfld.long 0x00 0. "EVENT32,Level 2 cache allocate" "Not implemented,Implemented"
tree.end
newline
group.quad spr:0x339D0++0x00
line.quad 0x00 "PMCCNTR_EL0,Performance Monitor Cycle Count Register"
group.quad SPR:0x339D1++0x00
line.long 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register"
group.quad SPR:0x339D2++0x00
line.long 0x00 "PMXEVCNTR_EL0,Performance Monitor Event Count Register"
group.quad SPR:0x339E0++0x00
line.long 0x00 "PMUSERENR_EL0,Performance Monitor User Enable Register"
bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.long 0x00 2. "EC,Cycle counter read enable" "Disabled,Enabled"
bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled"
group.quad SPR:0x309E1++0x00
line.long 0x00 "PMINTENSET_EL1,Performance Monitor Interrupt Enable Set"
bitfld.long 0x00 31. "C,Cycle counter Overflow Interrupt clear" "Disabled,Enabled"
bitfld.long 0x00  30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00  3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00  0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.quad SPR:0x309E2++0x00
line.long 0x00 "PMINTENCLR_EL1,Performance Monitor Interrupt Enable Clear"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00  30. "P30,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  29. "P29,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  28. "P28,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  27. "P27,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  26. "P26,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  25. "P25,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  24. "P24,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  23. "P23,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  22. "P22,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  21. "P21,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  20. "P20,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  19. "P19,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  18. "P18,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  17. "P17,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  16. "P16,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  15. "P15,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  14. "P14,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  13. "P13,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  12. "P12,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  11. "P11,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  10. "P10,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  9. "P9,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  8. "P8,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  7. "P7,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  6. "P6,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  5. "P5,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  4. "P4,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00  3. "P3,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  2. "P2,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  1. "P1,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00  0. "P0,Overflow Interrupt Clear" "Disabled,Enabled"
group.quad SPR:0x339E3++0x00
line.long 0x00 "PMOVSSET_EL0,Performance Monitor Overflow Flag Status Set Register"
group.quad SPR:(0x33E80+0x0)++0x00
line.long 0x00 "PMEVCNTR0_EL0,Performance Monitors Event Count Register 0"
group.quad SPR:(0x33EC0+0x0)++0x00
line.long 0x00 "PMEVTYPER0_EL0,Performance Monitors Selected Event Type Register 0"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x1)++0x00
line.long 0x00 "PMEVCNTR1_EL0,Performance Monitors Event Count Register 1"
group.quad SPR:(0x33EC0+0x1)++0x00
line.long 0x00 "PMEVTYPER1_EL0,Performance Monitors Selected Event Type Register 1"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x2)++0x00
line.long 0x00 "PMEVCNTR2_EL0,Performance Monitors Event Count Register 2"
group.quad SPR:(0x33EC0+0x2)++0x00
line.long 0x00 "PMEVTYPER2_EL0,Performance Monitors Selected Event Type Register 2"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x3)++0x00
line.long 0x00 "PMEVCNTR3_EL0,Performance Monitors Event Count Register 3"
group.quad SPR:(0x33EC0+0x3)++0x00
line.long 0x00 "PMEVTYPER3_EL0,Performance Monitors Selected Event Type Register 3"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x4)++0x00
line.long 0x00 "PMEVCNTR4_EL0,Performance Monitors Event Count Register 4"
group.quad SPR:(0x33EC0+0x4)++0x00
line.long 0x00 "PMEVTYPER4_EL0,Performance Monitors Selected Event Type Register 4"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:(0x33E80+0x5)++0x00
line.long 0x00 "PMEVCNTR5_EL0,Performance Monitors Event Count Register 5"
group.quad SPR:(0x33EC0+0x5)++0x00
line.long 0x00 "PMEVTYPER5_EL0,Performance Monitors Selected Event Type Register 5"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.quad SPR:0x33EF7++0x00
line.long 0x00 "PMCCFILTR_EL0,Performance Monitors Cycle Count Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.quad SPR:0x33E00++0x00
line.long 0x00 "CNTFRQ_EL0,Counter Frequency Register"
rgroup.quad spr:0x33E01++0x00
line.quad 0x00 "CNTPCT_EL0,Counter Physical Count Register"
group.quad SPR:0x30E10++0x00
line.long 0x00 "CNTKCTL_EL1,Timer PL1 Control Register"
bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
newline
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.quad SPR:0x33E20++0x00
line.long 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue register"
group.quad SPR:0x33E21++0x00
line.long 0x00 "CNTP_CTL_EL0,Counter PL1 Physical Timer Control Register"
bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad SPR:0x33E30++0x00
line.long 0x00 "CNTV_TVAL_EL0,Counter PL1 Virtual Timer Value Register"
group.quad SPR:0x33E31++0x00
line.long 0x00 "CNTV_CTL_EL0,Counter PL1 Virtual Timer Control Register"
bitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x33E02++0x00
line.quad 0x00 "CNTVCT_EL0,Counter Virtual Count Register"
group.quad spr:0x33E22++0x00
line.quad 0x00 "CNTP_CVAL_EL0,Counter PL1 Physical Compare Value Register"
group.quad spr:0x33E32++0x00
line.quad 0x00 "CNTV_CVAL_EL0,Counter PL1 Virtual Compare Value Register"
group.quad spr:0x34E03++0x00
line.quad 0x00 "CNTVOFF_EL2,Counter Virtual Offset Register"
group.quad SPR:0x34E10++0x00
line.long 0x00 "CNTHCTL_EL2,Counter Non-secure PL2 Control Register"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit is the trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.quad SPR:0x34E20++0x00
line.long 0x00 "CNTHP_TVAL_EL2,Counter Non-secure PL2 Physical Timer Value Register"
group.quad SPR:0x34E21++0x00
line.long 0x00 "CNTHP_CTL_EL2,Counter Non-secure PL2 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x34E22++0x00
line.quad 0x00 "CNTHP_CVAL_EL2,Counter Non-secure PL2 Physical Compare Value Register"
group.quad SPR:0x37E20++0x00
line.long 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical SecureTimer TimerValue register"
group.quad SPR:0x37E21++0x00
line.long 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad spr:0x37E22++0x00
line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register"
tree.end
tree "Generic Interrupt Controller CPU Interface"
tree "AArch64 GIC Physical CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.quad spr:0x30C84++0x00
line.quad 0x00 "ICC_AP0R0_EL1,Interrupt Controller Active Priorities Group 0 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.quad spr:0x30C90++0x00
line.quad 0x00 "ICC_AP1R0_EL1,Interrupt Controller Active Priorities Group 1 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
if (((per.q(spr:0x30CB6))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated"
else
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.quad spr:0x30C83++0x00
line.quad 0x00 "ICC_BPR0_EL1,Interrupt Controller Binary Point Register 0"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
group.quad spr:0x30CC3++0x00
line.quad 0x00 "ICC_BPR1_EL1,Interrupt Controller Binary Point Register 1"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control and Interrupt Preemption Control" "Reserved,[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
group.quad spr:0x30CC4++0x00
line.quad 0x00 "ICC_CTLR_EL1,Interrupt Controller Control Register (EL1)"
rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported"
rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255"
newline
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Zero,Non-zero"
rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6. "PMHE,Controls whether the priority mask Register is used as a hint for interrupt distribution" "Disabled,Enabled"
bitfld.quad 0x00 1. "EOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "CBPR,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 interrupts" "Separate registers,Same Register"
group.quad spr:0x36CC4++0x00
line.quad 0x00 "ICC_CTLR_EL3,Interrupt Controller Control Register (EL3)"
rbitfld.quad 0x00 19. "ExtRange,Extended INTID range" "Not supported,Supported"
rbitfld.quad 0x00 18. "RSS,Range Selector Support" "0 - 15,0 - 255"
newline
rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.quad 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported"
newline
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
rbitfld.quad 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop"
bitfld.quad 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Priority drop/Deactivation,Priority drop"
bitfld.quad 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Enabled,Disabled"
newline
bitfld.quad 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same Register"
bitfld.quad 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same Register"
if (((per.q(spr:0x30CC4))&0x3800)==0x00)
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
elif (((per.q(spr:0x30CC4))&0x3800)==0x800)
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICC_DIR_EL1,Interrupt Controller Deactivate Interrupt Register"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICC_EOIR0_EL1,Interrupt Controller End Of Interrupt Register 0"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICC_EOIR1_EL1,Interrupt Controller End Of Interrupt Register 1"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICC_HPPIR0_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICC_HPPIR1_EL1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.quad.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the currentSecurity state and Exception level"
endif
hgroup.quad spr:0x30C80++0x00
hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0"
in
hgroup.quad spr:0x30CC0++0x00
hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1"
in
newline
group.quad SPR:0x30CC6++0x00
line.long 0x00 "ICC_IGRPEN0_EL1,Interrupt Group Enable Register 0"
bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad SPR:0x30CC7++0x00
line.long 0x00 "ICC_IGRPEN1_EL1,Interrupt Group Enable Register 1 (EL1)"
bitfld.long 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad SPR:0x36CC7++0x00
line.long 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)"
bitfld.long 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
group.quad SPR:0x30460++0x00
line.long 0x00 "ICC_PMR_EL1,Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.quad SPR:0x30CB3++0x00
line.long 0x00 "ICC_RPR_EL1,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
if (((per.q(spr:0x30CB7))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated."
else
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
if (((per.q(spr:0x30CB5))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated"
else
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register"
newline
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.quad SPR:0x30CC5++0x00
line.long 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.quad SPR:0x34C95++0x00
line.long 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.quad SPR:0x36CC5++0x00
line.long 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
tree.end
tree "AArch64 Virtual Interface Control System Registers"
tree.open "Hypervisor Active Priorities Registers"
group.quad SPR:0x34C80++0x00
line.long 0x00 "ICH_AP0R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
if (CORENAME()=="CORTEXA53")
group.quad SPR:0x34C90++0x00
line.long 0x00 "ICH_AP1R0_EL2,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
endif
tree.end
newline
rgroup.quad SPR:0x34CB3++0x00
line.long 0x00 "ICH_EISR_EL2,Interrupt Controller End of Interrupt Status Register"
bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt"
newline
bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt"
rgroup.quad SPR:0x34CB5++0x00
line.long 0x00 "ICH_ELRSR_EL2,Interrupt Controller Empty List Register Status Register"
bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt"
bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt"
bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt"
newline
bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt"
group.quad SPR:0x34CB0++0x00
line.long 0x00 "ICH_HCR_EL2,Interrupt Controller Hypervisor Control Register"
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped"
newline
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
newline
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
if (((d.q(spr:(0x34CC0+0x0)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x0)++0x00
line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x0)++0x00
line.quad 0x00 "ICH_LR0_EL2,Interrupt Controller List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((d.q(spr:(0x34CC0+0x1)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x1)++0x00
line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x1)++0x00
line.quad 0x00 "ICH_LR1_EL2,Interrupt Controller List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((d.q(spr:(0x34CC0+0x2)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x2)++0x00
line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x2)++0x00
line.quad 0x00 "ICH_LR2_EL2,Interrupt Controller List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
if (((d.q(spr:(0x34CC0+0x3)))&0x2000000000000000)==0x00)
group.quad spr:(0x34CC0+0x3)++0x00
line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
bitfld.quad 0x00 41. "PINTID_EOI,End of Interrupt" "Interrupt,No interrupt"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
else
group.quad spr:(0x34CC0+0x3)++0x00
line.quad 0x00 "ICH_LR3_EL2,Interrupt Controller List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical INTID, for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
endif
rgroup.quad SPR:0x34CB2++0x00
line.long 0x00 "ICH_MISR_EL2,Interrupt Controller Maintenance Interrupt State Register"
bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
newline
bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted"
bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
newline
bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted"
bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
group.quad SPR:0x34CB7++0x00
line.long 0x00 "ICH_VMCR_EL2,Interrupt Controller Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
newline
bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register"
bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs"
newline
bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt"
bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
group.quad SPR:0x34C94++0x00
line.long 0x00 "ICH_VSEIR_EL2,Interrupt Controller Virtual System Error Interrupt Register"
rgroup.quad SPR:0x34CB1++0x00
line.long 0x00 "ICH_VTR_EL2,Interrupt Controller VGIC Type Register"
bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported"
bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported"
newline
bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported"
bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "Debug Registers"
rgroup.quad SPR:0x23010++0x00
line.long 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
group.quad SPR:0x20020++0x00
line.long 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable register"
bitfld.long 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled"
bitfld.long 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled"
group.quad spr:0x23040++0x00
line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register"
rgroup.quad SPR:0x23050++0x00
line.long 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register"
wgroup.quad SPR:0x23050++0x00
line.long 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register"
group.quad SPR:0x24070++0x00
line.long 0x00 "DBGVCR32_EL2,Vector Catch Register"
bitfld.long 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Low,High"
newline
bitfld.long 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Low,High"
bitfld.long 0x00 7. "SF,FIQ vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 6. "SI,IRQ vector catch enable in Secure state" "Low,High"
newline
bitfld.long 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Low,High"
bitfld.long 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Low,High"
group.quad SPR:0x20002++0x00
line.long 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register"
group.quad SPR:0x20022++0x00
line.long 0x00 "MDSCR_EL1,Monitor Debug System Control Register"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 27. "RXO,Save/restore bit" "Low,High"
bitfld.long 0x00 26. "TXU,Save/restore bit" "Low,High"
newline
bitfld.long 0x00 22.--23. "INTDIS,Save/restore bits" "0,1,2,3"
bitfld.long 0x00 21. "TDA,Save/restore bit" "Low,High"
bitfld.long 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled"
bitfld.long 0x00 14. "HDE,Save/restore bit" "Low,High"
newline
bitfld.long 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled"
bitfld.long 0x00 12. "TDCC,Trap accesses to the debug comms channel in EL0" "Disabled,Enabled"
bitfld.long 0x00 6. "ERR,Save/restore bit" "Low,High"
bitfld.long 0x00 0. "SS,Software step control" "Disabled,Enabled"
group.quad SPR:0x20032++0x00
line.long 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register"
group.quad SPR:0x20062++0x00
line.long 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register"
rgroup.quad spr:0x20100++0x00
line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register"
hexmask.quad 0x00 12.--47. 0x1000 "ROMADDR,ROM base physical address"
bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid"
wgroup.quad SPR:0x20104++0x00
line.long 0x00 "OSLAR_EL1,OS Lock Access Register"
bitfld.long 0x00 0. "OSLK,OS lock" "Unlock,Lock"
rgroup.quad SPR:0x20114++0x00
line.long 0x00 "OSLSR_EL1,OS Lock Status Register"
bitfld.long 0x00 2. "NTT,Not 32-bit access" "Low,High"
bitfld.long 0x00 1. "OSLK,OS lock status" "Not locked,Locked"
bitfld.long 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Impelemented,?..."
group.quad SPR:0x20134++0x00
line.long 0x00 "OSDLR_EL1,OS Double-lock Register"
bitfld.long 0x00 0. "DLK,OS double-lock control" "Not locked,Locked"
group.quad SPR:0x20144++0x00
line.long 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register"
bitfld.long 0x00 0. "CORENPDRQ,Core no powerdown request" "No,Yes"
group.quad SPR:0x20786++0x00
line.long 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set"
bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set"
newline
bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set"
bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.quad SPR:0x20796++0x00
line.long 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
rgroup.quad SPR:0x207E6++0x00
line.long 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register"
bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
group.quad SPR:0x33450++0x00
line.long 0x00 "DSPSR_EL0,Debug Saved Processor Status Register"
group.quad spr:0x33451++0x00
line.quad 0x00 "DLR_EL0,Debug Link Register"
tree.end
tree "Breakpoint Registers"
if (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0"
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0"
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x0)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x0)++0x00 "Breakpoint 0"
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x0)++0x0
line.long 0x00 "DBGBCR0_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1"
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1"
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x10)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x10)++0x00 "Breakpoint 1"
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x10)++0x0
line.long 0x00 "DBGBCR1_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2"
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2"
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x20)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x20)++0x00 "Breakpoint 2"
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x20)++0x0
line.long 0x00 "DBGBCR2_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3"
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3"
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x30)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x30)++0x00 "Breakpoint 3"
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x30)++0x0
line.long 0x00 "DBGBCR3_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4"
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4"
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x40)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x40)++0x00 "Breakpoint 4"
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x40)++0x0
line.long 0x00 "DBGBCR4_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5"
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0x800000||0x900000||0xC00000||0xD00000))
group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5"
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif (((d.l(spr:(0x20005+0x50)))&0xF00000)==(0xA00000||0xB00000||0xE00000||0xF00000))
else
group.quad spr:(0x20004+0x50)++0x00 "Breakpoint 5"
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID"
endif
group.quad SPR:(0x20005+0x50)++0x0
line.long 0x00 "DBGBCR5_EL1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMC,Higher mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
tree.end
tree "Watchpoint Control Registers"
group.quad spr:(0x20006+0x0)++0x00 "Watchpoint 0"
line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
group.quad spr:(0x20006+0x10)++0x00 "Watchpoint 1"
line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
group.quad spr:(0x20006+0x20)++0x00 "Watchpoint 2"
line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
group.quad spr:(0x20006+0x30)++0x00 "Watchpoint 3"
line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
tree.end
tree.end
tree.open "AArch32"
tree "ID Registers"
rgroup.long c15:0x0000++0x0
line.long 0x0 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code"
bitfld.long 0x0 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19. "ARCH, Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8"
newline
hexmask.long.word 0x0 4.--15. 0x10 "PART,Primary Part Number"
bitfld.long 0x0 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (CORENAME()=="CORTEXA57")
rgroup.long c15:0x0100++0x0
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA53")
rgroup.long c15:0x0100++0x0
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
if corename()=="CORTEXA57"
rgroup.long c15:0x0300++0x0
line.long 0x0 "TLBTR,TLB Type Register"
endif
if corename()=="CORTEXA57"
rgroup.long c15:0x0500++0x0
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
newline
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented"
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
newline
bitfld.long 0x00 0.--1. "CPUID,Indicates the core number in the device" "1,2,3,4"
elif corename()=="CORTEXA53"
rgroup.long c15:0x0500++0x0
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
newline
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,?..."
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
newline
hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field"
endif
rgroup.long c15:0x0600++0x0
line.long 0x0 "REVIDR,Revision ID Register"
rgroup.long c15:0x0410++0x00
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0510++0x00
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Required,?..."
bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.long c15:0x0610++0x00
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c15:0x0710++0x00
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..."
bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "HCMOSW,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "HCMOMVA,Invalidate Cache MVA Support" "Reserved,Supported,?..."
rgroup.long c15:0x0620++0x00
line.long 0x00 "ID_MMFR4,ID_MMFR4"
bitfld.long 0x00 4.--7. "AC2,Extension of ACTLR and HACTLR by ACTLR2 and HACTLR2" "Not implemented, implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved"
rgroup.long c15:0x0020++0x00
line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0"
bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..."
rgroup.long c15:0x0120++0x00
line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1"
bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0220++0x00
line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2"
bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0320++0x00
line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3"
bitfld.long 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,Reserved,?..."
bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0420++0x00
line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4"
bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..."
newline
bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0520++0x00
line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5"
bitfld.long 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..."
bitfld.long 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..."
newline
bitfld.long 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SEVL,SEVL Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0010++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c15:0x0110++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
newline
bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
if corename()=="CORTEXA57"
rgroup.long c15:0x0210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "CDM_MM,Memory-Mapped Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
elif corename()=="CORTEXA53"
rgroup.long c15:0x0210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..."
endif
group.long c15:0x0310++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
if corename()=="CORTEXA57"
rgroup.long c15:0x6C9++0x0
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
newline
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
newline
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
newline
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
newline
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
newline
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
rgroup.long c15:0x7C9++0x0
line.long 0x00 "PMCEID1,Common Event Identification Register 1"
elif corename()=="CORTEXA53"
rgroup.long c15:0x6C9++0x0
line.long 0x00 "PMCEID0,Common Event Identification Register 0"
bitfld.long 0x00 31. "EVENT31,L1 Data cache allocate" "Not implemented,Implemented"
bitfld.long 0x00 30. "EVENT30,Chain" "Not implemented,Implemented"
newline
bitfld.long 0x00 29. "EVENT29,Bus cycle" "Not implemented,Implemented"
bitfld.long 0x00 28. "EVENT28,Instruction architecturally executed condition check pass" "Not implemented,Implemented"
bitfld.long 0x00 27. "EVENT27,Instruction speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 26. "EVENT26,Local memory error" "Not implemented,Implemented"
bitfld.long 0x00 25. "EVENT25,Bus access" "Not implemented,Implemented"
bitfld.long 0x00 24. "EVENT24,Level 2 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 23. "EVENT23,Level 2 data cache refill" "Not implemented,Implemented"
bitfld.long 0x00 22. "EVENT22,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "EVENT21,Level 1 data cache write-back" "Not implemented,Implemented"
newline
bitfld.long 0x00 20. "EVENT20,Level 1 instruction cache access" "Not implemented,Implemented"
bitfld.long 0x00 19. "EVENT19,Data memory access" "Not implemented,Implemented"
bitfld.long 0x00 18. "EVENT18,Predictable branch speculatively executed" "Not implemented,Implemented"
newline
bitfld.long 0x00 17. "EVENT17,Cycle" "Not implemented,Implemented"
bitfld.long 0x00 16. "EVENT16,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented"
bitfld.long 0x00 15. "EVENT15,Instruction architecturally executed condition check pass  unaligned load or store" "Not implemented,Implemented"
newline
bitfld.long 0x00 14. "EVENT14,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented"
bitfld.long 0x00 13. "EVENT13,Instruction architecturally executed  immediate branch" "Not implemented,Implemented"
bitfld.long 0x00 12. "EVENT12,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented"
newline
bitfld.long 0x00 11. "EVENT11,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented"
bitfld.long 0x00 10. "EVENT10,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented"
bitfld.long 0x00 9. "EVENT9,Exception taken" "Not implemented,Implemented"
newline
bitfld.long 0x00 8. "EVENT8,Instruction architecturally executed" "Not implemented,Implemented"
bitfld.long 0x00 7. "EVENT7,Instruction architecturally executed condition check pass  store" "Not implemented,Implemented"
bitfld.long 0x00 6. "EVENT6,Instruction architecturally executed condition check pass  load" "Not implemented,Implemented"
newline
bitfld.long 0x00 5. "EVENT5,Level 1 data TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 4. "EVENT4,Level 1 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 3. "EVENT3,Level 1 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 2. "EVENT2,Level 1 instruction TLB refill" "Not implemented,Implemented"
bitfld.long 0x00 1. "EVENT1,Level 1 instruction cache refill" "Not implemented,Implemented"
bitfld.long 0x00 0. "EVENT0,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented"
rgroup.long c15:0x7C9++0x0
line.long 0x00 "PMCEID1,Common Event Identification Register 1"
bitfld.long 0x00 0. "EVENT32,L2D Cache Allocate" "Not implemented,Implemented"
endif
group.long c15:0x020D++0x00
line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register"
group.long c15:0x030D++0x00
line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register"
group.long c15:0x040D++0x00
line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register"
group.long c15:0x420D++0x00
line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register"
tree.end
tree "System Control and Configuration"
if corename()=="CORTEXA57"
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,System Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
else
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
endif
group.quad c15:0x100F0++0x01
line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register"
bitfld.quad 0x00 63. "FPRCGEC,Force processor RCG enables active" "Not forced,Forced"
bitfld.quad 0x00 59. "DLPDMB,Disable load pass DMB" "No,Yes"
newline
bitfld.quad 0x00 58. "DDMBN,Disable DMB nullification" "No,Yes"
bitfld.quad 0x00 57. "TA,Treat DMB st/stand DMB ld/allas DMB all/all" "Disabled,Enabled"
newline
bitfld.quad 0x00 56. "DL1DCHP,Disable L1 Data Cache hardware prefetcher" "No,Yes"
bitfld.quad 0x00 55. "DLPS,Disable load pass store" "No,Yes"
newline
bitfld.quad 0x00 54. "TGRE,Treat GRE/nGRE as nGnRE" "Disabled,Enabled"
bitfld.quad 0x00 53. "TDMBADSB,Treat DMBand DSBas if their domain field is SY" "Disabled,Enabled"
newline
bitfld.quad 0x00 52. "DORFLDNPI,Disable over-read from LDNP instruction" "No,Yes"
bitfld.quad 0x00 51. "DCDAFEMP,Disable contention detection and fast exclusive monitor path" "No,Yes"
newline
bitfld.quad 0x00 50. "DSSONNCGREEMT,Disable store streaming on NC/GRE memory type" "No,Yes"
bitfld.quad 0x00 49. "DNHOWBNAMT,Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type" "No,Yes"
newline
bitfld.quad 0x00 48. "DESRAFLSTL2,Disable early speculative read access from LS to L2" "No,Yes"
bitfld.quad 0x00 47. "DL1L2HP,Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger" "No,Yes"
newline
bitfld.quad 0x00 44. "EDCCADCCI,Enable data cache clean as data cache clean/invalidate" "Disabled,Enabled"
bitfld.quad 0x00 39. "DIM,Disable instruction merging" "No,Yes"
newline
bitfld.quad 0x00 38. "FFPSCRWF,Force FPSCR write flush" "Not forced,Forced"
bitfld.quad 0x00 37. "DIGS,Disable instruction group split" "No,Yes"
newline
bitfld.quad 0x00 36. "FIDSBONASBE,Force implicit DSB on an ISB event" "Not forced,Forced"
bitfld.quad 0x00 34. "DSBP,Disable Static Branch Predictor" "No,Yes"
newline
bitfld.quad 0x00 33. "DL1ICWPIMBTB,Disable L1 Instruction Cache way prediction in micro-BTB" "No,Yes"
bitfld.quad 0x00 32. "DL1ICP,Disable L1 Instruction Cache prefetch" "No,Yes"
newline
bitfld.quad 0x00 31. "SDEH,Snoop-delayed exclusive handling" "Disabled,Enabled"
bitfld.quad 0x00 30. "FMCEA,Force main clock enable active" "Not forced,Forced"
newline
bitfld.quad 0x00 29. "FASIMDFPCEA,Force Advanced SIMD and floating-point clock enable active" "Disabled,Enabled"
bitfld.quad 0x00 27.--28. "WSNAT,Write streaming no-allocate threshold" "12th,128th,512th,Disabled"
newline
bitfld.quad 0x00 25.--26. "WSNL1AT,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
bitfld.quad 0x00 24. "NCSE,Non-cacheable streaming enhancement" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "FIORTTSSAW,Force in-order requests to the same set and way" "Not forced,Forced"
bitfld.quad 0x00 22. "FIOLI,Force in-order load issue" "Not forced,Forced"
newline
bitfld.quad 0x00 21. "DL2TLBP,Disable L2 TLB prefetching" "No,Yes"
bitfld.quad 0x00 20. "DL2TTWIPAPAC,Disable L2 translation table walk IPA PA cache" "No,Yes"
newline
bitfld.quad 0x00 19. "DL2S1TTWC,Disable L2 stage 1 translation table walk cache" "No,Yes"
bitfld.quad 0x00 18. "DL2S1TTWL2PAC,Disable L2 stage 1 translation table walk L2 PA cache" "No,Yes"
newline
bitfld.quad 0x00 17. "DL2TLBPO,Disable L2 TLB performance optimization" "No,Yes"
bitfld.quad 0x00 16. "EFSOADLR,Enable full Strongly-ordered and Device load replay" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "FIOIIBEU,Force in-order issue in branch execute unit" "Not forced,Forced"
bitfld.quad 0x00 14. "FLOFOIGCDAPC,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Forced"
newline
bitfld.quad 0x00 13. "FASPRW,Flush after Special Purpose Register (SPR) writes" "Disabled,Enabled"
bitfld.quad 0x00 12. "FPOSPRS,Force push of SPRs" "Disabled,Enabled"
newline
bitfld.quad 0x00 11. "LTOIPIG,Limit to one instruction per instruction group" "Disabled,Enabled"
bitfld.quad 0x00 10. "FSAEIG,Force serialization after each instruction group" "Not forced,Forced"
newline
bitfld.quad 0x00 9. "DFRO,Disable flag renaming optimization" "No,Yes"
bitfld.quad 0x00 8. "EWFIIAANOPI,Execute WFI instruction as a NOP instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 7. "EWFEIAANOPI,Execute WFE instruction as a NOP instruction" "Disabled,Enabled"
bitfld.quad 0x00 5. "EPLDPLDWIASNOP,Execute PLDand PLDWinstructions as a NOP" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "DIP,Disable indirect predictor" "No,Yes"
bitfld.quad 0x00 3. "DMBTB,Disable micro-BTB" "No,Yes"
newline
bitfld.quad 0x00 1. "DICMS,Disable Instruction Cache miss streaming" "No,Yes"
bitfld.quad 0x00 0. "EIOBTB,Enable invalidates of BTB" "Disabled,Enabled"
group.quad c15:0x110F0++0x01
line.quad 0x00 "CPUECTLR,CPU Extended Control Register"
bitfld.quad 0x00 38. "DTWDAP,Disable table walk descriptor access prefetch" "No,Yes"
bitfld.quad 0x00 35.--36. "L2IFPD,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines"
newline
bitfld.quad 0x00 32.--33. "L2LSDPD,L2 load/store data prefetch distance" "0 line,2 lines,4 lines,8 lines"
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
newline
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad c15:0x120F0++0x01
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--22. "B/W,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "INDEX,RAM address"
group.long c15:0x0101++0x0
line.long 0x0 "ACTLR,Auxiliary Control Register"
elif corename()=="CORTEXA53"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.quad c15:0x100F0++0x01
line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register"
bitfld.quad 0x00 30. "FPDIDIS,Disable floating-point dual issue" "No,Yes"
bitfld.quad 0x00 29. "DIDIS,Disable Dual Issue" "No,Yes"
newline
bitfld.quad 0x00 27.--28. "RADIS,Write streaming no-allocate threshold" "16th,128th,512th,Disabled"
bitfld.quad 0x00 25.--26. "L1RADIS,Write streaming no-L1-allocate threshold" "4th,64th,128th,Disabled"
newline
bitfld.quad 0x00 24. "DTAH,Disable Transient allocation hint" "No,Yes"
bitfld.quad 0x00 23. "STBPFRS,Disable ReadUnique request for prefetch streams initiated by STB accesses" "No,Yes"
newline
bitfld.quad 0x00 22. "STBPFDIS,Disable prefetch streams initiated from STB accesses" "No,Yes"
bitfld.quad 0x00 21. "IFUTHDIS,IFU fetch throttle disabled" "No,Yes"
newline
bitfld.quad 0x00 19.--20. "NPFSTRM,Number of independent data prefetch streams" "1 stream,2 streams,3 streams,4 streams"
bitfld.quad 0x00 18. "DSTDIS,Enable device split throttle" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "STRIDE,Enable stride detection" "Disabled,Enabled"
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control" "Disabled,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10. "DODMBS,Disable optimized Data Memory Barrier behavior" "No,Yes"
group.quad c15:0x110F0++0x01
line.quad 0x00 "CPUECTLR,CPU Extended Control Register"
bitfld.quad 0x00 6. "SMPEN,Enable hardware management of data coherency with other processors in the multiprocessor" "Disabled,Enabled"
bitfld.quad 0x00 3.--5. "FPRETCTL,Advanced SIMD and Floating-point retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
newline
bitfld.quad 0x00 0.--2. "CPURETCTL,CPU retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.quad c15:0x120F0++0x01
line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--20. "C/W,CPUID/Way" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.word 0x00 0.--11. 1. "RAD,RAM address"
group.long c15:0x0101++0x0
line.long 0x0 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
endif
if corename()=="CORTEXA57"
group.long c15:0x0201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 28. "TRCDIS,Disable CP14 access to trace registers" "No,Yes"
newline
bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full"
bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 or higher,Reserved,Full"
elif corename()=="CORTEXA53"
group.long c15:0x201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 22.--23. "CP11,Coprocessor access control" "Denied,EL1 only,Reserved,Full"
newline
bitfld.long 0x0 20.--21. "CP10,Coprocessor access control" "Denied,EL1 only,Reserved,Full"
endif
group.long c15:0x0011++0x0
line.long 0x00 "SCR,Secure Configuration Register"
bitfld.long 0x00 13. "TWE,Trap WFE Instructions" "Not trapped,Trapped"
bitfld.long 0x00 12. "TWI,Trap WFI Instructions" "Not trapped,Trapped"
newline
bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.long 0x00 8. "HCE,Hypervisor Call enable" "No,Yes"
newline
bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes"
bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
newline
bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
bitfld.long 0x00 3. "EA,External Abort  exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
newline
bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
newline
bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure"
group.long c15:0x0111++0x00
line.long 0x00 "SDER,Secure Debug Enable Register"
bitfld.long 0x00 1. "SUNIDEN,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
bitfld.long 0x00 0. "SUIDEN,Invasive Secure User Debug Enable bit" "Denied,Permitted"
group.long c15:0x0131++0x00
line.long 0x00 "SDCR,Secure Debug Control Register"
bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors registers disabled" "No,Yes"
bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes"
newline
bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
group.long c15:0x0211++0x00
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted"
newline
bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted"
if corename()=="CORTEXA57"
group.long c15:0x000C++0x00
line.long 0x00 "VBAR,Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
group.long c15:0x010C++0x00
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
elif corename()=="CORTEXA53"
group.long c15:0x000C++0x00
line.long 0x00 "VBAR,Vector Base Address Register"
group.long c15:0x010C++0x00
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
endif
rgroup.long c15:0x001C++0x00
line.long 0x00 "ISR,Interrupt Status Register"
bitfld.long 0x00 8. "A,External abort pending flag" "Not pending,Pending"
bitfld.long 0x00 7. "I,Interrupt pending flag" "Not pending,Pending"
newline
bitfld.long 0x00 6. "F,Fast interrupt pending flag" "Not pending,Pending"
group.long c15:0x020C++0x00
line.long 0x00 "RMR,Reset Management Register"
bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64"
group.long c15:0x0015++0x00
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
group.long c15:0x0115++0x00
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
if corename()=="CORTEXA57"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable"
bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable"
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Async. external,Reserved,Reserved,Sync. external/on TTW/0th level,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Async. parity/on memory access,Reserved,Reserved,Sync. parity/on memory access/on TTW/0th level,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 15. "UA,Unattributable fault" "Attributable,Unattributable"
bitfld.long 0x00 14. "UC,Uncontainable fault" "Containable,Uncontainable"
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/1st level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/1st level,Permission/1nd level,Sync. external/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..."
endif
elif corename()=="CORTEXA53"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX/STREX,?..."
else
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 13. "CM,Cache maintenance fault" "Not aborted,Aborted"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "DECERR,SLVERR"
newline
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/section,Instruction cache maintenance,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/1st level,Permission/section,Sync. external/2nd level,Permission/2nd level,TLB conflict,Reserved,Reserved,Reserved,Reserved,LDREX or STREX,Async. external,Reserved,Async. parity,Sync. parity,Reserved,Reserved,Sync. parity/1st level,Reserved,Sync. parity/2nd level,?..."
endif
endif
if corename()=="CORTEXA57"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Address size/1st level,Address size/2nd level,Address size/3rd level,Translation/0th level,Translation/1st level,Translation/2nd level,Translation/3rd level,Access flag/0th level,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Permission/0th level,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,?..."
else
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Alignment,Debug event,Access flag/1st level,Reserved,Translation/1st level,Access flag/2nd level,Translation/2nd level,Sync. external/non-translation,Domain/1st level,Reserved,Domain/2nd level,Sync. external/on TTW/1st level,Permission/1st level,Sync. external/on TTW/2nd level,Permission/2nd level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
elif corename()=="CORTEXA53"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault Status" "Address size/TTBR0/TTBR1,Reserved,Reserved,Reserved,Reserved,Translation/1st level,Translation/2nd level,Translation/3rd level,Reserved,Access flag/1st level,Access flag/2nd level,Access flag/3rd level,Reserved,Permission/1st level,Permission/2nd level,Permission/3rd level,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/1st level,Sync. external/on TTW/2nd level,Sync. external/on TTW/3rd level,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/1st level,Sync. parity/on memory access/on TTW/2nd level,Sync. parity/on memory access/on TTW/3rd level,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
else
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. "EXT,External Abort Type" "DECERR,SLVERR"
bitfld.long 0x00 9. "LPAE,Large physical address extension" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/1st level,Permission/section,Sync. external/on TTW/2nd level,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/1st level,Reserved,Sync. parity/on TTW/2nd level,?..."
endif
endif
group.long c15:0x0006++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
group.long c15:0x0206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
if corename()=="CORTEXA57"
rgroup.long c15:0x103F++0x00
line.long 0x00 "CBAR,Configuration Base Address Register"
hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]"
hexmask.long.word 0x00 0.--11. 1. "PERIPHBASE[42:32],Periphbase[42:32]"
elif corename()=="CORTEXA53"
rgroup.long c15:0x103F++0x00
line.long 0x00 "CBAR,Configuration Base Address Register"
hexmask.long.word 0x00 18.--31. 1. "PERIPHBASE[31:18],Periphbase[31:18]"
hexmask.long.byte 0x00 0.--7. 1. "PERIPHBASE[39:32],Periphbase[39:32]"
endif
group.long c15:0x000D++0x00
line.long 0x00 "FCSEIDR,FCSE Process ID register"
group.long c15:0x020D++0x00
line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register"
group.long c15:0x030D++0x00
line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register"
group.long c15:0x040D++0x00
line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register"
tree.end
tree "Memory Management Unit"
if corename()=="CORTEXA57"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 6. "THEE,ThumbEE Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,System Control Register"
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled"
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled"
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
// MPIDR[31]==1 case is missing here for TTBR0 and TTBR1
group.long c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Registers"
hexmask.long 0x00 6.--31. 0x40 "TTB1,Translation table base address"
bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner"
newline
bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 2. "IMP,Implementation" "Low,High"
newline
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable"
group.long c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base Registers"
hexmask.long 0x00 6.--31. 0x40 "TTBA,Translation table base address"
bitfld.long 0x00 5. "NOS,Not outer shareable bit" "Outer,Inner"
newline
bitfld.long 0x00 3.--4. "RGN,Region" "Normal,Outer Write-Back Write-Allocate Cacheable,Outer Write-Through Cacheable,Outer Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 2. "IMP,Implementation" "Low,High"
newline
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
bitfld.long 0x00 0. "C,Cacheable" "Non-cacheable,Cacheable"
else
group.quad c15:0x10020++0x01
line.quad 0x00 "TTBR0,Translation Table Base Registers"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad c15:0x11020++0x01
line.quad 0x00 "TTBR1,Translation Table Base Registers"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
endif
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes"
newline
bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes"
bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7"
else
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable"
newline
bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
newline
bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes"
bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected"
newline
bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Non-Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
endif
elif corename()=="CORTEXA53"
group.long c15:0x0001++0x0
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x0 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x0 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x0 18. "NTWE,Not trap WFE" "No,Yes"
bitfld.long 0x0 16. "NTWI,Not trap WFI" "No,Yes"
newline
bitfld.long 0x0 13. "V,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x0 6. "ITD,IT Disable" "No,Yes"
newline
bitfld.long 0x0 5. "CP15BEN,c15 barrier enable" "Disabled,Enabled"
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x0 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,System Control Register"
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled"
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.quad c15:0x10020++0x01
line.quad 0x00 "TTBR0,Translation Table Base Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.quad c15:0x11020++0x01
line.quad 0x00 "TTBR1,Translation Table Base Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "0,1,2,3"
newline
bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes"
bitfld.long 0x00 22. "A1,Select ASID from TTBR1 ASID field" "Selected,Not selected"
newline
bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
else
group.long c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Register 0"
hexmask.long 0x00 7.--31. 0x80 "TTB0,Translation table base 0 address"
bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable"
group.long c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base Register 1"
hexmask.long 0x00 7.--31. 0x80 "TTB1,Translation table base 1 address"
bitfld.long 0x00 0. 6. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable"
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes"
newline
bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes"
bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7"
endif
endif
if corename()=="CORTEXA57"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
elif corename()=="CORTEXA53"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
endif
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
group.long c15:0x0003++0x00
line.long 0x00 "DACR,Domain Access Control Register"
bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
if (((per.l(c15:0x202))&0x80000000)==0x80000000)
group.quad c15:0x10070++0x01
line.quad 0x00 "PAR,Physical Address Register"
else
group.long c15:0x0047++0x00
line.long 0x00 "PAR,Physical Address Register"
endif
tree.open "Memory Attribute Indirection Registers"
group.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0"
group.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1"
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x003A++0x00
line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
group.long c15:0x013A++0x00
line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x002A++0x0
line.long 0x00 "PRRR,Primary Region Remap Register"
bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner"
bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 19. "NS1,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
bitfld.long 0x00 18. "NS0,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
newline
bitfld.long 0x00 17. "DS1,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
bitfld.long 0x00 16. "DS0,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
newline
bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
newline
bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device-nGnRnE,Device-nGnRE,Normal,?..."
group.long c15:0x012A++0x0
line.long 0x00 "NMRR,Normal Memory Remap Register"
bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
newline
endif
tree.end
newline
if (((per.l(c15:0x202))&0x80000000)==0x00000000)
group.long c15:0x10d++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
else
group.long c15:0x10d++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process identifier"
hexmask.long.byte 0x00 0.--7. 1. "ASID,Address space identifier"
endif
tree.end
tree "Virtualization Extensions"
group.long c15:0x4000++0x0
line.long 0x00 "VPIDR,Virtualization Processor ID Register"
group.long c15:0x4500++0x00
line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register"
group.long c15:0x420D++0x00
line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register"
group.long c15:0x4001++0x0
line.long 0x00 "HSCTLR,System Control Register"
bitfld.long 0x0 30. "TE,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x0 21. "FI,Fast Interrupts configuration enable" "Disabled,Enabled"
bitfld.long 0x0 19. "WXN,Write permission implies XN" "Not forced,Forced"
newline
bitfld.long 0x0 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x0 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x0 7. "ITD,IT Disable" "No,Yes"
bitfld.long 0x0 5. "CP15BEN,CP15 barrier enable" "Disabled,Enabled"
newline
bitfld.long 0x0 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
bitfld.long 0x0 1. "A,Strict Alignment" "Disabled,Enabled"
newline
bitfld.long 0x0 0. "M,Enable address translation" "Disabled,Enabled"
group.long c15:0x4101++0x00
line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register"
bitfld.long 0x00 6. "L2ACTLRAC,L2ACTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 5. "L2ECTLRAC,L2ECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "L2CTLRAC,L2CTLR write access control" "Disabled,Enabled"
bitfld.long 0x00 1. "CPUECTLRAC,CPUECTLR write access control" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "CPUACTLRAC,CPUACTLR write access control" "Disabled,Enabled"
if corename()=="CORTEXA57"
group.long c15:0x4011++0x00
line.long 0x00 "HCR,Hypervisor Configuration Register"
bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled"
bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
newline
bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled"
bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
newline
bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
newline
bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3"
newline
bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "Not aborted,Aborted"
newline
bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt"
newline
bitfld.long 0x00 5. "AMO,A-bit Mask Override" "Not routed,Routed"
bitfld.long 0x00 4. "IMO,I-bit Mask Override" "Not routed,Routed"
newline
bitfld.long 0x00 3. "FMO,F-bit Mask Override" "Not routed,Routed"
bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override"
bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled"
elif corename()=="CORTEXA53"
group.long c15:0x4011++0x00
line.long 0x00 "HCR,Hypervisor Configuration Register"
bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "Disabled,Enabled"
bitfld.long 0x00 29. "HCD,Hypervisor Call Disable" "No,Yes"
newline
bitfld.long 0x00 27. "TGE,Trap General Exceptions" "Disabled,Enabled"
bitfld.long 0x00 26. "TVM,Trap Virtual Memory Controls" "Disabled,Enabled"
newline
bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "Disabled,Enabled"
bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled"
newline
bitfld.long 0x00 23. "TPC,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled"
bitfld.long 0x00 22. "TSW,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register Accesses" "Disabled,Enabled"
bitfld.long 0x00 20. "TIDCP,Trap Lockdown" "Disabled,Enabled"
newline
bitfld.long 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.long 0x00 18. "TID3,Trap ID Group 3" "Disabled,Enabled"
newline
bitfld.long 0x00 17. "TID2,Trap ID Group 2" "Disabled,Enabled"
bitfld.long 0x00 16. "TID1,Trap ID Group 1" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "TID0,Trap ID Group 0" "Disabled,Enabled"
bitfld.long 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.long 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
newline
bitfld.long 0x00 10.--11. "BSU,Barrier Shareability Upgrade" "0,1,2,3"
bitfld.long 0x00 9. "FB,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "VA,Virtual External Asynchronous Abort" "No aborted,Aborted"
bitfld.long 0x00 7. "VI,Virtual IRQ interrupt" "No interrupt,Interrupt"
newline
bitfld.long 0x00 6. "VF,Virtual FIQ interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 5. "AMO,A-bit Mask Override" "No override,Override"
newline
bitfld.long 0x00 4. "IMO,I-bit Mask Override" "No override,Override"
bitfld.long 0x00 3. "FMO,F-bit Mask Override" "No override,Override"
newline
bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "No override,Override"
newline
bitfld.long 0x00 0. "VM,Second Stage of Translation Enable" "Disabled,Enabled"
endif
group.long c15:0x4411++0x00
line.long 0x00 "HCR2,Hypervisor Configuration Register 2"
bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes"
group.long c15:0x4111++0x00
line.long 0x00 "HDCR,Hypervisor Debug Control Register"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No effect,Valid"
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related register Access" "No effect,Valid"
newline
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No effect,Valid"
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No effect,Valid"
newline
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No effect,Valid"
newline
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No effect,Valid"
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long c15:0x4211++0x00
line.long 0x00 "HCPTR,Hypervisor Architectural Feature Trap Register"
bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "Not trapped,Trapped"
bitfld.long 0x0 20. "TTA,Trap Trace Access" "Not trapped,?..."
newline
bitfld.long 0x0 15. "TASE,Trap Advanced SIMD extensions" "Not trapped,Trapped"
bitfld.long 0x0 11. "TCP11,Trap coprocessor 11" "Not trapped,Trapped"
newline
bitfld.long 0x0 10. "TCP10,Trap coprocessor 10" "Not trapped,Trapped"
group.long c15:0x4311++0x00
line.long 0x00 "HSTR,Hypervisor System Trap Register"
bitfld.long 0x00 16. "TTEE,Trap ThumbEE" "Disabled,Enabled"
bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "Reserved,?..."
newline
hexmask.long.word 0x00 5.--13. 1. "T4_15,Trap to Hypervisor mode Non-secure priv 5 - 13"
bitfld.long 0x00 0.--3. "T0_13,Trap to Hypervisor mode Non-secure priv 0 - 3," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x4711++0x00
line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register"
if corename()=="CORTEXA57"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
hexmask.quad 0x00 0.--47. 1. "BADDR,Translation table base address"
elif corename()=="CORTEXA53"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register"
endif
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hypervisor Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "0,1,2,3"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
group.long c15:0x4212++0x00
line.long 0x00 "VTCR,Virtualization Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "0,1,2,3"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "0,1,2,3"
bitfld.long 0x00 6.--7. "SL0,Starting Level for VTCR addressed region" "0,1,2,3"
newline
bitfld.long 0x00 4. "S,Sign-extension of the T0SZ field" "Low,High"
bitfld.long 0x00 0.--3. "T0SZ,The Size offset of the VTCR addressed region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x4015++0x00
line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register"
group.long c15:0x4115++0x00
line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Syndrome Register"
group.long c15:0x4006++0x00
line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register"
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hypervisor Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to c15,Trapped MCRR/MRRC to c15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,Reserved,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..."
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
hexmask.long 0x00 0.--24. 1. "ISS,Instruction specific syndrome"
group.long c15:0x4206++0x00
line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register"
group.long c15:0x4406++0x00
line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register"
hexmask.long 0x00 4.--31. 1. "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address"
tree.open "Hypervisor Memory Attribute Indirection Registers"
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient"
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient"
group.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0"
group.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1"
tree.end
newline
group.long c15:0x400C++0x00
line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "HVBADDR,Hypervisor Vector Base Address"
tree.end
tree "Cache Control and Configuration"
rgroup.long c15:0x0100++0x0
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x0 14.--15. "L1POLICY,L1 Instruction cache policy" "Reserved,Reserved,VIPT,PIPT"
newline
bitfld.long 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
if corename()=="CORTEXA57"
rgroup.long c15:0x1100++0x0
line.long 0x0 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,Level 3,?..."
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 2,?..."
newline
bitfld.long 0x00 18.--20. "CTYPE7,Cache type for levels 7" "No cache,?..."
bitfld.long 0x00 15.--17. "CTYPE6,Cache type for levels 6" "No cache,?..."
bitfld.long 0x00 12.--14. "CTYPE5,Cache type for levels 5" "No cache,?..."
newline
bitfld.long 0x00 9.--11. "CTYPE4,Cache type for levels 4" "No cache,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
elif corename()=="CORTEXA53"
rgroup.long c15:0x1100++0x0
line.long 0x0 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Not disclosed,?..."
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Reserved,Level 1,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,L1,L1/L2,?..."
newline
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Reserved,Level 1,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,?..."
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..."
newline
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate Inst/Data,?..."
endif
rgroup.long c15:0x1700++0x0
line.long 0x00 "AIDR,Auxiliary ID Register"
rgroup.long c15:0x1000++0x0
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
bitfld.long 0x00 31. "WT,Write-Through" "Not Supported,Supported"
bitfld.long 0x00 30. "WB,Write-Back" "Not Supported,Supported"
newline
bitfld.long 0x00 29. "RA,Read-Allocate" "Not Supported,Supported"
bitfld.long 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
newline
hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "16 bytes,32 bytes,64 bytes,128 bytes,?..."
group.long c15:0x2000++0x0
line.long 0x0 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,?..."
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
tree "Level 1 memory system"
if corename()=="CORTEXA57"
group.long c15:0x001F++0x00
line.long 0x00 "DL1DATA0,Data L1 Data 0 Register"
group.long c15:0x011F++0x00
line.long 0x00 "DL1DATA1,Data L1 Data 1 Register"
group.long c15:0x021F++0x00
line.long 0x00 "DL1DATA2,Data L1 Data 2 Register"
group.long c15:0x031F++0x00
line.long 0x00 "DL1DATA3,Data L1 Data 3 Register"
group.long c15:0x000F++0x00
line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register"
group.long c15:0x010F++0x00
line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register"
group.long c15:0x020F++0x00
line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register"
group.long c15:0x030F++0x00
line.long 0x00 "IL1DATA3,Instruction L1 Data 3 Register"
wgroup.long c15:0x04F++0x00
line.long 0x00 "RAMINDEX,RAM Index Operation Register"
elif corename()=="CORTEXA53"
rgroup.long c15:0x300F++0x00
line.long 0x00 "CDBGDR0,Cache Debug Data Register 0"
rgroup.long c15:0x310F++0x00
line.long 0x00 "CDBGDR1,Cache Debug Data Register 1"
rgroup.long c15:0x320F++0x00
line.long 0x00 "CDBGDR2,Cache Debug Data Register 2"
rgroup.long c15:0x330F++0x00
line.long 0x00 "CDBGDR3,Cache Debug Data Register 3"
wgroup.long c15:0x302F++0x00
line.long 0x00 "CDBGDCT,Cache Debug Data Cache Tag Read Operation Register"
wgroup.long c15:0x312F++0x00
line.long 0x00 "CDBGICT,Cache Debug Instruction Cache Tag Read Operation Register"
wgroup.long c15:0x304F++0x00
line.long 0x00 "CDBGDCD,Cache Debug Cache Debug Data Cache Data Read Operation Register"
wgroup.long c15:0x314F++0x00
line.long 0x00 "CDBGICD,Cache Debug Instruction Cache Data Read Operation Register"
wgroup.long c15:0x324F++0x00
line.long 0x00 "CDBGTD,Cache Debug TLB Data Read Operation Register"
endif
tree.end
tree "Level 2 memory system"
if corename()=="CORTEXA57"
group.long c15:0x1209++0x0
line.long 0x00 "L2CTLR,L2 Control Register"
bitfld.long 0x00 31. "L2RSTDM,L2RSTDISABLE monitor" "No,Yes"
bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4"
newline
rbitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Not supported,Supported"
bitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "DIECCE,Data in-line ECC enable" "Disabled,Enabled"
rbitfld.long 0x00 13. "L2AS,L2 arbitration slice" "Not present,Present"
newline
rbitfld.long 0x00 12. "L2TRAMS,L2 Tag RAM slice" "Not present,Present"
rbitfld.long 0x00 10.--11. "L2DRAMS,L2 Data RAM slice" "Not present,1,2,Present"
newline
bitfld.long 0x00 9. "L2TRAMS,L2 Tag RAM setup" "0 cycle,1 cycle"
bitfld.long 0x00 6.--8. "L2TRAML,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles"
newline
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "0 cycle,1 cycle"
bitfld.long 0x00 0.--2. "DRAML,L2 data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
group.long c15:0x1309++0x0
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
newline
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.long c15:0x100F++0x00
line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register"
bitfld.long 0x00 28. "FL2TBCEA,Force L2 tag bank clock enable active" "Disabled,Enabled"
bitfld.long 0x00 27. "FL2LCEA,Force L2 logic clock enable active" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "FL2GICRCGEA,Forces L2, GIC CPU interface, and Timer Regional Clock Gate(RCG) enables active" "Not forced,Forced"
bitfld.long 0x00 25. "ESIAA,Enables single issue across all tag banks when the L2 arbitration replay threshold is reached" "Disabled,Enabled"
newline
bitfld.long 0x00 23. "DPRFRUT,Disables prefetch requests from ReadUnique transactions" "No,Yes"
bitfld.long 0x00 22. "DDTLSPR,Disable dynamic throttling of load/store prefetch requests" "No,Yes"
newline
bitfld.long 0x00 20.--21. "DTL2PRFEQOC,Disable throttling of L2 prefetch requests based on Fill/Evict Queue(FEQ) occupancy count" "12,10,8,Disabled"
bitfld.long 0x00 18.--19. "DLASQ,Disable limit on NC/SO/Dev stores in Address Sequence Queue" "12 entries,10 entries,8 entries,No limit"
newline
bitfld.long 0x00 17. "DL2RRA,Disable L2 round-robin arbitration that only clocks through paths with an active requestor waiting to be arbitrated" "No,Yes"
bitfld.long 0x00 16. "ERTSI,Enable replay threshold single issue" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "DFFD,Disable fast forwarding of data from ACE or CHI to LS and IF" "No,Yes"
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
newline
bitfld.long 0x00 13. "DCEO,Disable clean evict optimization" "No,Yes"
bitfld.long 0x00 11. "DDSB,Disable DSB with no DVM synchronization" "No,Yes"
newline
bitfld.long 0x00 10. "DNSDAR,Disable Non-secure debug array read" "No,Yes"
bitfld.long 0x00 8. "DDVMCMOMB,Disable DVM and cache maintenance operation message broadcast" "No,Yes"
newline
bitfld.long 0x00 7. "EHDT,Enable hazard detect timeout" "Disabled,Enabled"
bitfld.long 0x00 6. "DACESCHIST,Disable ACE shareable or CHI snoopable transactions from master" "No,Yes"
newline
bitfld.long 0x00 4. "DWUWLUTFM,Disable WriteUnique and WriteLineUnique transactions from master" "Disabled,Enabled"
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
newline
bitfld.long 0x00 2. "LTORPTB,Limit to one request per tag bank" "Normal,Limited"
bitfld.long 0x00 1. "EARTT,Enable arbitration replay threshold timeout" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "DHPF,Disable hardware prefetch forwarding" "No,Yes"
group.quad c15:0x130F0++0x01
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.tbyte 0x00 0.--17. 1. "IND,Index"
elif corename()=="CORTEXA53"
group.long c15:0x1209++0x0
line.long 0x00 "L2CTLR,L2 Control Register"
bitfld.long 0x00 24.--25. "NCPU, Number of CPU" "1,2,3,4"
bitfld.long 0x00 22. "CPUCP,CPU Cache Protection" "Disabled,Enabled"
newline
rbitfld.long 0x00 21. "SCUL2CP,SCU-L2 Cache Protection" "Disabled,Enabled"
rbitfld.long 0x00 5. "DRAMIL,L2 data RAM input latency" "1 cycle,2 cycle"
newline
rbitfld.long 0x00 0. "DRAMOL,L2 data RAM output latency" "2 cycles,3 cycles"
group.long c15:0x1309++0x0
line.long 0x00 "L2ECTLR,L2 Extended Control Register"
bitfld.long 0x00 30. "L2INTASYNCERR,L2 internal asynchronous error" "No error,Error"
bitfld.long 0x00 29. "AXIASYNCERR,AXI asynchronous error" "No error,Error"
newline
bitfld.long 0x00 0.--2. "L2DRC,L2 dynamic retention control" "Disabled,2 ticks,8 ticks,32 ticks,64 ticks,128 ticks,256 ticks,512 ticks"
group.long c15:0x100F++0x00
line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register"
bitfld.long 0x00 30.--31. "L2VC,L2 victim Control" "0,1,2,3"
bitfld.long 0x00 14. "EUCE,Enables UniqueClean evictions with data" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "DCEPTE,Disables clean/evict push to external" "No,Yes"
group.quad c15:0x110F0++0x01
line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register"
bitfld.quad 0x00 63. "FATAL,Fatal bit" "0,1"
hexmask.quad.byte 0x00 40.--47. 1. "OEC,Other error count"
newline
hexmask.quad.byte 0x00 32.--39. 1. "REC,Repeat error count"
bitfld.quad 0x00 31. "VALID,Valid bit" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 24.--30. 1. "RAMID,RAM Identifier"
bitfld.quad 0x00 18.--21. "C/W,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..."
newline
hexmask.quad.word 0x00 3.--16. 1. "RAD,RAM index address"
endif
tree.end
tree.end
tree "System Performance Monitor"
group.long c15:0xc9++0x00
line.long 0x0 "PMCR,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. "LC,Long cycle count enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
newline
group.long c15:0x1c9++0x00
line.long 0x00 "PMNCNTENSET,Count Enable Set Register "
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
bitfld.long 0x00 30. "P30,Event Counter 30 enable bit" "Disabled,Enabled"
bitfld.long 0x00 29. "P29,Event Counter 29 enable bit" "Disabled,Enabled"
bitfld.long 0x00 28. "P28,Event Counter 28 enable bit" "Disabled,Enabled"
bitfld.long 0x00 27. "P27,Event Counter 27 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "P26,Event Counter 26 enable bit" "Disabled,Enabled"
bitfld.long 0x00 25. "P25,Event Counter 25 enable bit" "Disabled,Enabled"
bitfld.long 0x00 24. "P24,Event Counter 24 enable bit" "Disabled,Enabled"
bitfld.long 0x00 23. "P23,Event Counter 23 enable bit" "Disabled,Enabled"
bitfld.long 0x00 22. "P22,Event Counter 22 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "P21,Event Counter 21 enable bit" "Disabled,Enabled"
bitfld.long 0x00 20. "P20,Event Counter 20 enable bit" "Disabled,Enabled"
bitfld.long 0x00 19. "P19,Event Counter 19 enable bit" "Disabled,Enabled"
bitfld.long 0x00 18. "P18,Event Counter 18 enable bit" "Disabled,Enabled"
bitfld.long 0x00 17. "P17,Event Counter 17 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "P16,Event Counter 16 enable bit" "Disabled,Enabled"
bitfld.long 0x00 15. "P15,Event Counter 15 enable bit" "Disabled,Enabled"
bitfld.long 0x00 14. "P14,Event Counter 14 enable bit" "Disabled,Enabled"
bitfld.long 0x00 13. "P13,Event Counter 13 enable bit" "Disabled,Enabled"
bitfld.long 0x00 12. "P12,Event Counter 12 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "P11,Event Counter 11 enable bit" "Disabled,Enabled"
bitfld.long 0x00 10. "P10,Event Counter 10 enable bit" "Disabled,Enabled"
bitfld.long 0x00 9. "P9,Event Counter 9 enable bit" "Disabled,Enabled"
bitfld.long 0x00 8. "P8,Event Counter 8 enable bit" "Disabled,Enabled"
bitfld.long 0x00 7. "P7,Event Counter 7 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "P6,Event Counter 6 enable bit" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,Event Counter 5 enable bit" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,Event Counter 4 enable bit" "Disabled,Enabled"
bitfld.long 0x00 3. "P3,Event Counter 3 enable bit" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,Event Counter 2 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "P1,Event Counter 1 enable bit" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,Event Counter 0 enable bit" "Disabled,Enabled"
group.long c15:0x2c9++0x00
line.long 0x00 "PMCNTENCLR,Count Enable Clear Register"
eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00 30. "P30,Event Counter 30 clear bit" "Disabled,Enabled"
eventfld.long 0x00 29. "P29,Event Counter 29 clear bit " "Disabled,Enabled"
eventfld.long 0x00 28. "P28,Event Counter 28 clear bit " "Disabled,Enabled"
eventfld.long 0x00 27. "P27,Event Counter 27 clear bit " "Disabled,Enabled"
newline
eventfld.long 0x00 26. "P26,Event Counter 26 clear bit " "Disabled,Enabled"
eventfld.long 0x00 25. "P25,Event Counter 25 clear bit " "Disabled,Enabled"
eventfld.long 0x00 24. "P24,Event Counter 24 clear bit " "Disabled,Enabled"
eventfld.long 0x00 23. "P23,Event Counter 23 clear bit " "Disabled,Enabled"
eventfld.long 0x00 22. "P22,Event Counter 22 clear bit " "Disabled,Enabled"
newline
eventfld.long 0x00 21. "P21,Event Counter 21 clear bit " "Disabled,Enabled"
eventfld.long 0x00 20. "P20,Event Counter 20 clear bit " "Disabled,Enabled"
eventfld.long 0x00 19. "P19,Event Counter 19 clear bit " "Disabled,Enabled"
eventfld.long 0x00 18. "P18,Event Counter 18 clear bit " "Disabled,Enabled"
eventfld.long 0x00 17. "P17,Event Counter 17 clear bit " "Disabled,Enabled"
newline
eventfld.long 0x00 16. "P16,Event Counter 16 clear bit " "Disabled,Enabled"
eventfld.long 0x00 15. "P15,Event Counter 15 clear bit" "Disabled,Enabled"
eventfld.long 0x00 14. "P14,Event Counter 14 clear bit" "Disabled,Enabled"
eventfld.long 0x00 13. "P13,Event Counter 13 clear bit" "Disabled,Enabled"
eventfld.long 0x00 12. "P12,Event Counter 12 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00 11. "P11,Event Counter 11 clear bit" "Disabled,Enabled"
eventfld.long 0x00 10. "P10,Event Counter 10 clear bit" "Disabled,Enabled"
eventfld.long 0x00 9. "P9,Event Counter 9 clear bit" "Disabled,Enabled"
eventfld.long 0x00 8. "P8,Event Counter 8 clear bit" "Disabled,Enabled"
eventfld.long 0x00 7. "P7,Event Counter 7 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00 6. "P6,Event Counter 6 clear bit" "Disabled,Enabled"
eventfld.long 0x00 5. "P5,Event Counter 5 clear bit" "Disabled,Enabled"
eventfld.long 0x00 4. "P4,Event Counter 4 clear bit" "Disabled,Enabled"
eventfld.long 0x00 3. "P3,Event Counter 3 clear bit" "Disabled,Enabled"
eventfld.long 0x00 2. "P2,Event Counter 2 clear bit" "Disabled,Enabled"
newline
eventfld.long 0x00 1. "P1,Event Counter 1 clear bit" "Disabled,Enabled"
eventfld.long 0x00 0. "P0,Event Counter 0 clear bit" "Disabled,Enabled"
group.long c15:0x3c9++0x00
line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register"
eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
eventfld.long 0x00 30. "P30,PMN30 overflow" "No overflow,Overflow"
eventfld.long 0x00 29. "P29,PMN29 overflow" "No overflow,Overflow"
eventfld.long 0x00 28. "P28,PMN28 overflow" "No overflow,Overflow"
eventfld.long 0x00 27. "P27,PMN27 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 26. "P26,PMN26 overflow" "No overflow,Overflow"
eventfld.long 0x00 25. "P25,PMN25 overflow" "No overflow,Overflow"
eventfld.long 0x00 24. "P24,PMN24 overflow" "No overflow,Overflow"
eventfld.long 0x00 23. "P23,PMN23 overflow" "No overflow,Overflow"
eventfld.long 0x00 22. "P22,PMN22 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 21. "P21,PMN21 overflow" "No overflow,Overflow"
eventfld.long 0x00 20. "P20,PMN20 overflow" "No overflow,Overflow"
eventfld.long 0x00 19. "P19,PMN19 overflow" "No overflow,Overflow"
eventfld.long 0x00 18. "P18,PMN18 overflow" "No overflow,Overflow"
eventfld.long 0x00 17. "P17,PMN17 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 16. "P16,PMN16 overflow" "No overflow,Overflow"
eventfld.long 0x00 15. "P15,PMN15 overflow" "No overflow,Overflow"
eventfld.long 0x00 14. "P14,PMN14 overflow" "No overflow,Overflow"
eventfld.long 0x00 13. "P13,PMN13 overflow" "No overflow,Overflow"
eventfld.long 0x00 12. "P12,PMN12 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 11. "P11,PMN11 overflow" "No overflow,Overflow"
eventfld.long 0x00 10. "P10,PMN10 overflow" "No overflow,Overflow"
eventfld.long 0x00 9. "P9,PMN9 overflow" "No overflow,Overflow"
eventfld.long 0x00 8. "P8,PMN8 overflow" "No overflow,Overflow"
eventfld.long 0x00 7. "P7,PMN7 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 6. "P6,PMN6 overflow" "No overflow,Overflow"
eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow"
eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow"
eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow"
eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow"
eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow"
group.long c15:0x4c9++0x00
line.long 0x00 "PMSWINC,Performance Monitor Software Increment"
bitfld.long 0x00 30. "P30,Increment PMN30" "No action,Increment"
bitfld.long 0x00 29. "P29,Increment PMN29" "No action,Increment"
bitfld.long 0x00 28. "P28,Increment PMN28" "No action,Increment"
bitfld.long 0x00 27. "P27,Increment PMN27" "No action,Increment"
bitfld.long 0x00 26. "P26,Increment PMN26" "No action,Increment"
newline
bitfld.long 0x00 25. "P25,Increment PMN25" "No action,Increment"
bitfld.long 0x00 24. "P24,Increment PMN24" "No action,Increment"
bitfld.long 0x00 23. "P23,Increment PMN23" "No action,Increment"
bitfld.long 0x00 22. "P22,Increment PMN22" "No action,Increment"
bitfld.long 0x00 21. "P21,Increment PMN21" "No action,Increment"
newline
bitfld.long 0x00 20. "P20,Increment PMN20" "No action,Increment"
bitfld.long 0x00 19. "P19,Increment PMN19" "No action,Increment"
bitfld.long 0x00 18. "P18,Increment PMN18" "No action,Increment"
bitfld.long 0x00 17. "P17,Increment PMN17" "No action,Increment"
bitfld.long 0x00 16. "P16,Increment PMN16" "No action,Increment"
newline
bitfld.long 0x00 15. "P15,Increment PMN15" "No action,Increment"
bitfld.long 0x00 14. "P14,Increment PMN14" "No action,Increment"
bitfld.long 0x00 13. "P13,Increment PMN13" "No action,Increment"
bitfld.long 0x00 12. "P12,Increment PMN12" "No action,Increment"
bitfld.long 0x00 11. "P11,Increment PMN11" "No action,Increment"
newline
bitfld.long 0x00 10. "P10,Increment PMN10" "No action,Increment"
bitfld.long 0x00 9. "P9,Increment PMN9" "No action,Increment"
bitfld.long 0x00 8. "P8,Increment PMN8" "No action,Increment"
bitfld.long 0x00 7. "P7,Increment PMN7" "No action,Increment"
bitfld.long 0x00 6. "P6,Increment PMN6" "No action,Increment"
newline
bitfld.long 0x00 5. "P5,Increment PMN5" "No action,Increment"
bitfld.long 0x00 4. "P4,Increment PMN4" "No action,Increment"
bitfld.long 0x00 3. "P3,Increment PMN3" "No action,Increment"
bitfld.long 0x00 2. "P2,Increment PMN2" "No action,Increment"
bitfld.long 0x00 1. "P1,Increment PMN1" "No action,Increment"
newline
bitfld.long 0x00 0. "P0,Increment PMN0" "No action,Increment"
group.long c15:0x5c9++0x00
line.long 0x00 "PMSELR,Performance Monitor Select Register"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..."
group.long c15:0xd9++0x00
line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register"
group.long c15:0x1d9++0x00
line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register"
group.long c15:0x2d9++0x00
line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register"
group.long c15:0xe9++0x00
line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register"
bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled"
bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,User mode access enable" "Disabled,Enabled"
group.long c15:0x1e9++0x00
line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set"
bitfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
bitfld.long 0x00 30. "P30,PMCNT30 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 29. "P29,PMCNT29 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 28. "P28,PMCNT28 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 27. "P27,PMCNT27 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "P26,PMCNT26 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 25. "P25,PMCNT25 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 24. "P24,PMCNT24 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 23. "P23,PMCNT23 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 22. "P22,PMCNT22 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 21. "P21,PMCNT21 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 20. "P20,PMCNT20 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 19. "P19,PMCNT19 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 18. "P18,PMCNT18 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 17. "P17,PMCNT17 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 16. "P16,PMCNT16 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 15. "P15,PMCNT15 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 14. "P14,PMCNT14 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 13. "P13,PMCNT13 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 12. "P12,PMCNT12 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "P11,PMCNT11 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 10. "P10,PMCNT10 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 9. "P9,PMCNT9 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 8. "P8,PMCNT8 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 7. "P7,PMCNT7 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "P6,PMCNT6 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.long c15:0x2e9++0x00
line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear"
eventfld.long 0x00 31. "C,PMCCNTR enable" "Disabled,Enabled"
eventfld.long 0x00 30. "P30,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 29. "P29,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 28. "P28,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 27. "P27,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 26. "P26,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 25. "P25,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 24. "P24,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 23. "P23,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 22. "P22,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 21. "P21,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 20. "P20,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 19. "P19,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 18. "P18,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 17. "P17,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 16. "P16,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 15. "P15,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 14. "P14,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 13. "P13,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 12. "P12,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 11. "P11,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 10. "P10,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 9. "P9,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 8. "P8,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 7. "P7,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 6. "P6,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 5. "P5,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 4. "P4,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 3. "P3,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 2. "P2,Overflow Interrupt Clear" "Disabled,Enabled"
newline
eventfld.long 0x00 1. "P1,Overflow Interrupt Clear" "Disabled,Enabled"
eventfld.long 0x00 0. "P0,Overflow Interrupt Clear" "Disabled,Enabled"
group.long c15:0x3e9++0x00
line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register"
group.long c15:0x8E++0x00
line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0"
group.long c15:(0x8E+0x40)++0x00
line.long 0x00 "PMEVTYPER0,Performance Monitors Selected Event Type Register 0"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x18E++0x00
line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1"
group.long c15:(0x18E+0x40)++0x00
line.long 0x00 "PMEVTYPER1,Performance Monitors Selected Event Type Register 1"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x28E++0x00
line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2"
group.long c15:(0x28E+0x40)++0x00
line.long 0x00 "PMEVTYPER2,Performance Monitors Selected Event Type Register 2"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x38E++0x00
line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3"
group.long c15:(0x38E+0x40)++0x00
line.long 0x00 "PMEVTYPER3,Performance Monitors Selected Event Type Register 3"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x48E++0x00
line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4"
group.long c15:(0x48E+0x40)++0x00
line.long 0x00 "PMEVTYPER4,Performance Monitors Selected Event Type Register 4"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x58E++0x00
line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5"
group.long c15:(0x58E+0x40)++0x00
line.long 0x00 "PMEVTYPER5,Performance Monitors Selected Event Type Register 5"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
group.long c15:0x07FE++0x00
line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 30. "U,EL0 filtering bit" "Enabled,Disabled"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Enabled,Disabled"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled"
bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.long c15:0x000E++0x00
line.long 0x00 "CNTFRQ,Counter Frequency Register"
rgroup.quad c15:0x100E0++0x01
line.quad 0x00 "CNTPCT,Counter Physical Count Register"
group.long c15:0x001E++0x00
line.long 0x00 "CNTKCTL,Timer PL1 Control Register"
bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
newline
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 modes" "Not accessible,Accessible"
group.long c15:0x002E++0x00
line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Compare Value Register"
group.long c15:0x012E++0x00
line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.long c15:0x003E++0x00
line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register"
group.long c15:0x013E++0x00
line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x110E0++0x01
line.quad 0x00 "CNTVCT,Counter Virtual Count Register"
group.quad c15:0x120E0++0x01
line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register"
group.quad c15:0x130E0++0x01
line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register"
group.quad c15:0x140E0++0x01
line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register"
group.long c15:0x401E++0x00
line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register"
bitfld.long 0x00 4.--7. "EVNTI,Select trigger for the event stream generated from counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "EL1VCTEN,Controls whether the Non-secure copies of the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
group.long c15:0x402E++0x00
line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register"
group.long c15:0x412E++0x00
line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 1. "IMASK,Timer interrupt mask bit" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
group.quad c15:0x160E0++0x01
line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register"
tree.end
tree "Generic Interrupt Controller CPU Interface"
tree "AArch32 GIC Physical CPU Interface System Registers"
tree.open "Interrupt Controller Active Priorities Registers"
group.long c15:0x048C++0x00
line.long 0x00 "ICC_AP0R0,Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:0x009C++0x00
line.long 0x00 "ICC_AP1R0,Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
wgroup.quad c15:0x110C0++0x01
line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "SGIID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
group.long c15:0x038C++0x00
line.long 0x00 "ICC_BPR0,Binary Point Register 0"
bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7"
group.long c15:0x03CC++0x00
line.long 0x00 "ICC_BPR1,Binary Point Register 1"
bitfld.long 0x00 0.--2. "BINARYPOINT,Binary point" "0,1,2,3,4,5,6,7"
group.long c15:0x04CC++0x00
line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,Supported"
rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "EOIMODE,Alias of ICC_MCTLR.EOImode_EL1" "0,1"
newline
bitfld.long 0x00 0. "CBPR,Common Binary Point Register" "0,1"
group.long c15:0x64CC++0x00
line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3"
rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Not supported,Supported"
rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,Supported"
newline
rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled"
bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled"
bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt register also deactivates the interrupt(EL3)" "Enabled,Disabled"
newline
bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate registers,Same register"
bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate registers,Same register"
if (((per.l(c15:0x4CC))&0x3800)==0x00)
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.long c15:0x018C++0x00
line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.long c15:0x01CC++0x00
line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.long c15:0x028C++0x00
line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
rgroup.long c15:0x02CC++0x00
line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
elif (((per.l(c15:0x4CC))&0x3800)==0x800)
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICC_DIR,Interrupt Controller Deactivate Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.long c15:0x018C++0x00
line.long 0x00 "ICC_EOIR0,Interrupt Controller End Of Interrupt Register 0"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.long c15:0x01CC++0x00
line.long 0x00 "ICC_EOIR1,Interrupt Controller End Of Interrupt Register 1"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.long c15:0x028C++0x00
line.long 0x00 "ICC_HPPIR0,Interrupt Controller Highest Priority Pending Interrupt Register 0"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
rgroup.long c15:0x02CC++0x00
line.long 0x00 "ICC_HPPIR1,Interrupt Controller Highest Priority Pending Interrupt Register 1"
hexmask.long.tbyte 0x00 0.--23. 1. "INTID,The INTID of the highest priority pending interrupt if that interrupt is observable at the current security state and exception level"
endif
hgroup.long c15:0x008C++0x00
hide.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0"
in
hgroup.long c15:0x00CC++0x00
hide.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1"
in
group.long c15:0x06CC++0x00
line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x07CC++0x00
line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x0064++0x00
line.long 0x00 "ICC_PMR,Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.long c15:0x03BC++0x00
line.long 0x00 "ICC_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
wgroup.quad c15:0x120C0++0x01
line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
wgroup.quad c15:0x100C0++0x01
line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
group.long c15:0x05CC++0x00
line.long 0x00 "ICC_SRE,System Register Enable Register for EL1"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
if corename()=="CORTEXA53"
group.long c15:0x459C++0x00
line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
endif
group.long c15:0x65CC++0x00
line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3"
bitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Disabled,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
bitfld.long 0x00 0. "SRE,System Register Enable" "Disabled,Enabled"
group.long c15:0x67CC++0x00
line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable"
bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
tree.end
tree "AArch32 Virtual Interface Control System Registers"
tree.open "Hypervisor Active Priorities Registers"
group.long c15:0x408C++0x00
line.long 0x00 "ICH_AP0R0,Interrupt Controller Hypervisor Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt"
group.long c15:0x409C++0x00
line.long 0x00 "ICH_AP1R0,Interrupt Controller Hypervisor Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt"
bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt"
bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt"
bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt"
bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt"
bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt"
bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt"
bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt"
bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt"
bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt"
bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt"
bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt"
bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt"
bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt"
bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt"
bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt"
bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt"
tree.end
newline
rgroup.long c15:0x43BC++0x00
line.long 0x00 "ICH_EISR,Interrupt Controller End of Interrupt Status Register"
bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register 1" "No interrupt,Interrupt"
newline
bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register 0" "No interrupt,Interrupt"
rgroup.long c15:0x45BC++0x00
line.long 0x00 "ICH_ELRSR,Interrupt Controller Empty List Register Status Register"
bitfld.long 0x00 3. "STATUS3,Status bit for List register 3" "Interrupt,No interrupt"
bitfld.long 0x00 2. "STATUS2,Status bit for List register 2" "Interrupt,No interrupt"
bitfld.long 0x00 1. "STATUS1,Status bit for List register 1" "Interrupt,No interrupt"
newline
bitfld.long 0x00 0. "STATUS0,Status bit for List register 0" "Interrupt,No interrupt"
group.long c15:0x40BC++0x00
line.long 0x00 "ICH_HCR,Interrupt Controller Hypervisor Control Register"
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR" "Not trapped,Trapped"
bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "Not trapped,Trapped"
newline
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 1 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* System registers for Group 0 interrupts to EL2" "Not trapped,Trapped"
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "Not trapped,Trapped"
newline
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
group.long c15:(0x40CC+0x0)++0x00
line.long 0x00 "ICH_LR0,Interrupt Controller List Register 0"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x100)++0x00
line.long 0x00 "ICH_LR1,Interrupt Controller List Register 1"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x200)++0x00
line.long 0x00 "ICH_LR2,Interrupt Controller List Register 2"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40CC+0x300)++0x00
line.long 0x00 "ICH_LR3,Interrupt Controller List Register 3"
hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt"
group.long c15:(0x40EC+0x0)++0x00
line.long 0x00 "ICH_LRC0,Interrupt Controller List Register Extension 0"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x100)++0x00
line.long 0x00 "ICH_LRC1,Interrupt Controller List Register Extension 1"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x200)++0x00
line.long 0x00 "ICH_LRC2,Interrupt Controller List Register Extension 2"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
group.long c15:(0x40EC+0x300)++0x00
line.long 0x00 "ICH_LRC3,Interrupt Controller List Register Extension 3"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts"
rgroup.long c15:0x42BC++0x00
line.long 0x00 "ICH_MISR,Interrupt Controller Maintenance Interrupt State Register"
bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
newline
bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted"
bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
newline
bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted"
bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
group.long c15:0x459C++0x00
line.long 0x00 "ICH_SRE,Hypervisor System Register"
group.long c15:0x47BC++0x00
line.long 0x00 "ICH_VMCR,Interrupt Controller Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]"
newline
bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Disabled,Enabled"
bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate registers,Same register"
bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Virtual IRQs,Virtual FIQs"
newline
bitfld.long 0x00 2. "VACKCTL,Virtual FIQ enable" "1022,Corresponding interrupt"
bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
group.long c15:0x449C++0x00
line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register"
rgroup.long c15:0x41BC++0x00
line.long 0x00 "ICH_VTR,Interrupt Controller VGIC Type Register"
bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,24 bits,?..."
newline
bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,Supported"
bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Only zero values supported,Non-zero values supported"
bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,Not supported"
newline
bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Not supported,Supported"
bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List registers, minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree.end
tree "Debug Registers"
tree "Coresight Management Registers"
if corename()=="CORTEXA57"
rgroup.long c14:0x0000++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
newline
hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version"
bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported"
bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented"
elif corename()=="CORTEXA53"
rgroup.long c14:0x0000++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
newline
hexmask.long.byte 0x0 16.--19. 1. "VERSION,Debug Architecture Version"
bitfld.long 0x0 15. "DEVID,Debug Device ID" "Low,High"
bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Supported,Not supported"
newline
bitfld.long 0x0 13. "PCSR,PC Sample register implemented" "Not implemented,Implemented"
bitfld.long 0x0 12. "SE,Security Extensions implemented" "Not implemented,Implemented"
hexmask.long.byte 0x0 4.--7. 1. "VARIANT,Implementation-defined Variant Number"
newline
hexmask.long.byte 0x0 0.--3. 1. "REVISION,Implementation-defined Revision Number"
endif
rgroup.long c14:0x0060++0x0
line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register"
group.long c14:0x0070++0x0
line.long 0x00 "DBGVCR,Debug Vector Catch register"
bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled"
bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
group.long c14:0x0020++0x00
line.long 0x00 "DBGDCCINT,DCC Interrupt Enable Register"
bitfld.long 0x00 30. "RX,DCC interrupt request enable control for DTRRX" "Disabled,Enabled"
bitfld.long 0x00 29. "TX,DCC interrupt request enable control for DTRTX" "Disabled,Enabled"
group.long c14:0x0200++0x0
line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)"
group.long c14:0x0220++0x0
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 27. "RXO,Used for save/restore of EDSCR.RXO" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "TXU,Used for save/restore of EDSCR.TXU" "Disabled,Enabled"
bitfld.long 0x00 21. "TDA,Used for save/restore of EDSCR.TDA" "Disabled,Enabled"
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
newline
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 14. "HDE,Used for save/restore of EDSCR.HDE" "Disabled,Enabled"
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
bitfld.long 0x00 6. "ERR,Used for save/restore of EDSCR.ERR" "Disabled,Enabled"
newline
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
rgroup.long c14:0x0010++0x0
line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
newline
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,BKPT Instruction,Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
wgroup.long c14:0x0230++0x0
line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)"
group.long c14:0x0050++0x0
line.long 0x00 "DBGDTRTXINT,Debug Transmit/Receive Register (Internal View)"
group.long c14:0x0687++0x0
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set"
newline
bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set"
bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set"
newline
bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.long c14:0x0697++0x0
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
rgroup.long c14:0x06E7++0x0
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. "SNDFI,Secure non-invasive debug features implementation" "No effect,Implemented"
bitfld.long 0x00 6. "SNDE,Secure non-invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 5. "SIDFI,Secure invasive debug features implementation" "No effect,Implemented"
newline
bitfld.long 0x00 4. "SIDE,Secure invasive debug enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NSNDFI,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
bitfld.long 0x00 2. "NSNDE,Non-secure non-invasive debug enable" "0,1"
newline
bitfld.long 0x00 1. "NSIDFI,Non-secure invasive debug features implementation" "Not implemented,Implemented"
bitfld.long 0x00 0. "NSIDE,Non-secure invasive debug enable" "0,1"
rgroup.long c14:0x0707++0x0
line.long 0x0 "DBGDEVID2,Debug Device ID Register 2"
rgroup.long c14:0x0717++0x0
line.long 0x0 "DBGDEVID1,Debug Device ID Register 1"
bitfld.long 0x00 0.--3. "PCSROFFSET,This field defines the offset applied to DBGPCSR samples" "0,1,No offset,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c14:0x0727++0x00
line.long 0x00 "DBGDEVID,Debug Device ID Register 0"
bitfld.long 0x00 28.--31. "CIDMASK,Specifies the level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..."
bitfld.long 0x00 24.--27. "AUXREGS,Specifies support for the Debug External Auxiliary Control Register" "Not implemented,?..."
bitfld.long 0x00 20.--23. "DOUBLELOCK,Specifies support for the Debug OS Double Lock Register" "Reserved,Implemented,?..."
newline
bitfld.long 0x00 16.--19. "VIREXTNS,Specifies whether EL2 is implemented" "Reserved,Implemented,?..."
bitfld.long 0x00 12.--15. "VECTORCATCH,Defines the form of the vector catch event implemented" "Implemented,?..."
bitfld.long 0x00 8.--11. "BPADDRMASK,Indicates the level of support for the Immediate Virtual Address(IVA) matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implemented"
newline
bitfld.long 0x00 4.--7. "WPADDRMASK,Indicates the level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..."
bitfld.long 0x00 0.--3. "PCSAMPLE,Indicates the level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..."
tree.end
newline
rgroup.quad c14:0x10010++0x1
line.quad 0x0 "DBGDRAR,Debug ROM Address Register"
hexmask.quad.word 0x0 32.--47. 0x1 "ROMADDR,ROM physical address"
hexmask.quad.tbyte 0x0 12.--31. 0x10 "ROMADDR,ROM physical address"
bitfld.quad 0x0 1. "VALID1,ROM table address valid" "Not valid,Valid"
newline
bitfld.quad 0x0 0. "VALID0,ROM table address valid" "Not valid,Valid"
rgroup.quad c14:0x10020++0x1
line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register"
wgroup.long c14:0x0401++0x00
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
rgroup.long c14:0x0411++0x00
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required"
bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked"
bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..."
if (((per.l(c14:0x0411))&0x2)==0x2)
group.long c14:0x0260++0x00
line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
else
hgroup.long c14:0x0260++0x00
hide.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
endif
group.long c14:0x0431++0x00
line.long 0x00 "DBGOSDLR,Debug OS Double Lock Register"
bitfld.long 0x00 0. "DLK,OS Double Lock control bit" "Not locked,Locked"
group.long c14:0x0441++0x00
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Low,High"
tree.end
tree "Breakpoint Registers"
if (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0"
line.long 0x00 "DBGBVR0,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x0)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x0)++0x0 "Breakpoint 0"
hide.long 0x00 "DBGBVR0,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x0)++0x0 "Breakpoint 0"
line.long 0x00 "DBGBVR0,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x0)++0x0
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1"
line.long 0x00 "DBGBVR1,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x10)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x10)++0x0 "Breakpoint 1"
hide.long 0x00 "DBGBVR1,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x10)++0x0 "Breakpoint 1"
line.long 0x00 "DBGBVR1,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x10)++0x0
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2"
line.long 0x00 "DBGBVR2,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x20)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x20)++0x0 "Breakpoint 2"
hide.long 0x00 "DBGBVR2,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x20)++0x0 "Breakpoint 2"
line.long 0x00 "DBGBVR2,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x20)++0x0
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3"
line.long 0x00 "DBGBVR3,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x30)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x30)++0x0 "Breakpoint 3"
hide.long 0x00 "DBGBVR3,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x30)++0x0 "Breakpoint 3"
line.long 0x00 "DBGBVR3,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x30)++0x0
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4"
line.long 0x00 "DBGBVR4,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x40)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x40)++0x0 "Breakpoint 4"
hide.long 0x00 "DBGBVR4,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x40)++0x0 "Breakpoint 4"
line.long 0x00 "DBGBVR4,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x40)++0x0
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
if (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x000000||0x100000||0x400000||0x500000))
group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5"
line.long 0x00 "DBGBVR5,Breakpoint Value Register (Instruction address)"
hexmask.long 0x00 2.--31. 0x4 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:(0x500+0x50)))&0xF00000)==(0x800000||0x900000||0xA00000||0xB00000))
hgroup.long c14:(0x0400+0x50)++0x0 "Breakpoint 5"
hide.long 0x00 "DBGBVR5,Breakpoint Value Register (VMID)"
else
group.long c14:(0x0400+0x50)++0x0 "Breakpoint 5"
line.long 0x00 "DBGBVR5,Breakpoint Value Register (Context ID)"
endif
group.long c14:(0x0500+0x50)++0x0
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
bitfld.long 0x00 22. "BT[2],Mismatch" "Match,Mismatch"
bitfld.long 0x00 21. 23. "BT[31],Base type" "Address,Context ID,VMID,VMID and context ID"
bitfld.long 0x00 20. "BT[0],Enable linking" "Disabled,Enabled"
newline
bitfld.long 0x00 16.--19. "LBRPN,Linked BRP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x00 13. "HMM,Hypervisor mode match" "Not matched,Matched"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode"
bitfld.long 0x00 0. "BE,Breakpoint enable" "Disabled,Enabled"
group.long c14:0x0141++0x0
line.long 0x00 "DBGBXVR4,Debug Breakpoint Extended Value Register 4"
hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value"
group.long c14:0x0151++0x0
line.long 0x00 "DBGBXVR5,Debug Breakpoint Extended Value Register 5"
hexmask.long.byte 0x00 0.--7. 1. "VMID, VMID value"
tree.end
tree "Watchpoint Control Registers"
group.long c14:(0x0600+0x0)++0x00 "Breakpoint 0"
line.long 0x00 "DBGWVR0,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
group.long c14:(0x0600+0x10)++0x00 "Breakpoint 1"
line.long 0x00 "DBGWVR1,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
group.long c14:(0x0600+0x20)++0x00 "Breakpoint 2"
line.long 0x00 "DBGWVR2,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
group.long c14:(0x0600+0x30)++0x00 "Breakpoint 3"
line.long 0x00 "DBGWVR3,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x4 "DA,Data address"
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x0 24.--28. "MASK,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "WT,Watchpoint Type" "Unlinked data address match,Linked data address match"
bitfld.long 0x0 16.--19. "LBN,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
newline
bitfld.long 0x0 14.--15. "SSC,Secure state control" "Both,Non-secure,Secure,?..."
bitfld.long 0x0 13. "HMC,Hypervisor Mode Control" "Disabled,Enabled"
hexmask.long.byte 0x0 5.--12. "BAS,Byte address select"
newline
bitfld.long 0x0 3.--4. "LSC,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "PAC,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses"
bitfld.long 0x0 0. "WE,Watchpoint enable" "Disabled,Enabled"
tree.end
tree.end
AUTOINDENT.OFF
AUTOINDENT.POP
tree.end
elif (CORENAME()=="CORTEXR5F")
tree "Core Registers (Cortex-R5F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
width 0x8
; --------------------------------------------------------------------------------
;    Identification registers
; --------------------------------------------------------------------------------
tree "ID Registers"
rgroup.long c15:0x00++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL     ,Implementer code"
bitfld.long 0x0 20.--23.  "           VAR      ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19.  "           ARCH     ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
textline "                 "
hexmask.long.word 0x0 4.--15. 0x1 " PART     ,Primary Part Number"
bitfld.long 0x0 0.--3. "         REV      ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c15:0x100++0x00
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 24.--27. " CWG      ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                 "
bitfld.long 0x00 20.--23. " ERG      ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19. "           DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
bitfld.long 0x0 14.--15. "  L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
textline "                 "
bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
rgroup.long c15:0x400--0x400
line.long 0x0 "MPUIR,MPU type register"
hexmask.long.byte 0x00 8.--15. 1. " REGNUM   ,Number of regions"
bitfld.long 0x00 0. "           TYPE     ,Type of MPU regions" "Unified,Seperated"
rgroup.long c15:0x500++0x00
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system"
textline "                 "
hexmask.long.byte 0x00 16.--23. 1. " AFFL2    ,Affitnity Level 2"
hexmask.long.byte 0x00 8.--15. 1. "           AFFL1    ,Affitnity Level 1"
hexmask.long.byte 0x00 0.--7. 1. "           AFFL0    ,Affitnity Level 0"
textline "                 "
rgroup.long c15:0x0410++0x00
line.long 0x00 "MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. " IT         ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      FCSE       ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " ACR        ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      TCM        ,TCM and Associated DMA Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " SL         ,Number of Shareability levels implemented" "1,?..."
bitfld.long 0x00 8.--11. "              OS         ,Outermost Shareability domain support" "Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " PMSA       ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  VMSA       ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0510++0x00
line.long 0x00 "MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. " BTB        ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. "   L1TCO      ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " L1UCMO     ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "  L1HCMO     ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " L1UCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "  L1HCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup.long c15:0x0610++0x00
line.long 0x00 "MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. " HAF        ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "  WFI        ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " MBF        ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      UTLBMO     ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " HTLBMO     ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      HL1CMRO    ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " HL1BPCRO   ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  HL1FPCRO   ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c15:0x0710++0x00
line.long 0x00 "MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. " SS         ,Supersection support" "Supported,?..."
bitfld.long 0x00 20.--23. "      CW         ,Coherent walk" "Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " MB         ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " HCMOSW     ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      HCMOMVA    ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup.long c15:0x020++0x00
line.long 0x00 "ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVI       ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "  DEBI       ,Debug Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 16.--19. " CI         ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "  CBI        ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 8.--11. " BI         ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "      BCI        ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 0.--3. " SI         ,Swap Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x120++0x00
line.long 0x00 "ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 28.--31. " JI         ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      INTI       ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " IMMI       ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      ITEI       ,If Then Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " EXTI       ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      E2I        ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " E1I        ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      ENDI       ,Endianness Control Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x220++0x00
line.long 0x00 "ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " RI         ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      PSRI       ,PSR Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " UMI        ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      SMI        ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " MI         ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      II         ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " MHI        ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      LSI        ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x320++0x00
line.long 0x00 "ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 28.--31. " T2E        ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      NOPI       ,True NOP Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " TCI        ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      TBI        ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " SPI        ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      SVCI       ,SVC Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " SIMDI      ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      SI         ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x420++0x00
line.long 0x00 "ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 28.--31. " SWP_FRAC   ,SWAP_frac" "Supported,?..."
bitfld.long 0x00 24.--27. "      PSR_M_I    ,PSR_M Instructions Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " EI         ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      BI         ,Barrier Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " SMII       ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      WBI        ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " WSI        ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      UI         ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0520++0x00
line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
rgroup.long c15:0x0620++0x00
line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
rgroup.long c15:0x0720++0x00
line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
rgroup.long c15:0x010++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "  STATE2 ,Java Extension Interface Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "  STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c15:0x110++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM    ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. "  SE     ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      PM     ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
textline "                 "
rgroup.long c15:0x210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "  TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "      TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "      SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup.long c15:0x310++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long c15:0x02f++0x00
line.long 0x00 "BO1R,Build Options 1 Register"
hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR    ,Default high address for the TCM"
bitfld.long 0x00 1. "                  FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented"
textline "                 "
bitfld.long 0x00 0. " PP_BUS_ECC          ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented"
group.long c15:0x12f++0x00
line.long 0x00 "BO2R,Build Options 2 Register"
bitfld.long 0x00 31. " NUM_CPU             ,Number of CPUs" "1,2"
bitfld.long 0x00 30. "                       LOCK_STEP       ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included"
textline "                 "
bitfld.long 0x00 29. " NO_ICACHE           ,Indicate whether the CPU contains instruction cache" "Yes,No"
bitfld.long 0x00 28. "                     NO_DCACHE       ,Indicate whether the CPU contains data cache" "Yes,No"
textline "                 "
bitfld.long 0x00 26.--27. " ATCM_ES             ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection"
bitfld.long 0x00 23.--25. "  BTCM_ES         ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..."
textline "                 "
bitfld.long 0x00 23. " NO_IE               ,Indicate whether the processor supports big-endian instructions" "Yes,No"
bitfld.long 0x00 22. "                     NO_FPU          ,Indicate whether the CPU contains a floating point unit" "Yes,No"
textline "                 "
bitfld.long 0x00 20.--21. " MPU_REGIONS         ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions"
bitfld.long 0x00 17.--19. "              BREAK_POINTS    ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
textline "                 "
bitfld.long 0x00 14.--16. " WATCH_POINTS        ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "                       NO_A_TCM_INF    ,Indicate whether the CPUs contain ATCM ports" "Yes,No"
textline "                 "
bitfld.long 0x00 12. " NO_B0_TCM_INF       ,Indicate whether the CPUs contain B0TCM ports" "Yes,No"
bitfld.long 0x00 11. "                     NO_B1_TCM_INF   ,Indicate whether the CPUs contain B1TCM ports" "Yes,No"
textline "                 "
bitfld.long 0x00 10. " TCMBUSPARITY        ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes"
bitfld.long 0x00 9. "                     NO_SLAVE        ,Indicate whether the CPU contains an AXI slave port" "Yes,No"
textline "                 "
bitfld.long 0x00 7.--8. " ICACHE_ES           ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC"
bitfld.long 0x00 5.--6. "         DCACHE_ES       ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..."
textline "                 "
bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No"
bitfld.long 0x00 3. "                     AXI_BUS_ECC     ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes"
textline "                 "
bitfld.long 0x00 2. " SL                  ,Indicate whether the processor has been built with split/lock logic" "No,Yes"
bitfld.long 0x00 1. "                     AHB_PP          ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes"
textline "                 "
bitfld.long 0x00 0. " MICRO_SCU           ,Indicate whether the processor contain an ACP interface" "No,Yes"
group.long c15:0x72f++0x00
line.long 0x00 "POR,Pin Options Register"
bitfld.long 0x00 4. " DBGNOCLKSTOP        ,Value of the DBGNOCLKSTOP pin" "Low,High"
bitfld.long 0x00 3. "                    INTSYNCEN       ,Value of the INTSYNCEN pin" "Low,High"
textline "                 "
bitfld.long 0x00 2. " IRQADDRVSYNCEN      ,Value of the IRQADDRVSYNCEN pin" "Low,High"
bitfld.long 0x00 1. "                    SLBTCMSB        ,Value of the SLBTCMSBm pin" "Low,High"
textline "                 "
bitfld.long 0x00 0. " PARITYLEVEL         ,Value of the PARITYLEVEL pin" "Low,High"
tree.end
width 0x8
tree "System Control and Configuration"
group.long c15:0x01++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x0 31. " IE  ,Instruction endianness" "Little,Big"
bitfld.long 0x0 30. "   TE  ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. "    AFE ,Access Flag Enable" "Disable,Enable"
bitfld.long 0x0 28. "  TRE ,TEX remap enable" "Disable,Enable"
bitfld.long 0x0 27. "  NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 25. " EE  ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. "   VE  ,Vector Enable" "Disable,Vectored"
bitfld.long 0x0 21. " FI  ,Fast Interrupts enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 19. " DZ  ,Divide by Zero exception bit" "Disable,Enable"
bitfld.long 0x0 17. "  BR  ,MPU Background region enable" "Disable,Enable"
bitfld.long 0x0 14. "  RR  ,Round-Robin bit" "Random,RRobin"
bitfld.long 0x0 13. "   V   ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline "                 "
bitfld.long 0x0 12. " I   ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. "  Z   ,Branch Prediction Enable" "Disable,Enable"
bitfld.long 0x0 2. "  C   ,Enable data cache" "Disable,Enable"
bitfld.long 0x0 1. "  A   ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. "  M   ,MPU Enable" "Disable,Enable"
textline " "
group.long c15:0x101++0x00
line.long 0x0 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 31. " DICDI     ,Disable Case C dual issue control" "Enable,Disable"
bitfld.long 0x00 30. "    DIB2DI    ,Disable Case B2 dual issue control" "Enable,Disable"
bitfld.long 0x00 29. "    DIB1DI    ,Disable Case B1 dual issue control" "Enable,Disable"
textline "                 "
bitfld.long 0x00 28. " DIADI     ,Disable Case A dual issue control" "Enable,Disable"
bitfld.long 0x00 27. "    B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
bitfld.long 0x00 26. "    B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
textline "                 "
bitfld.long 0x00 25. " ATCMPCEN  ,B1TCM parity or ECC check enable" "Disable,Enable"
bitfld.long 0x00 24. "    AXISCEN   ,AXI slave cache access enable" "Disable,Enable"
bitfld.long 0x00 23. "    AXISCUEN  ,AXI slave cache User mode access enable" "Disable,Enable"
textline "                 "
bitfld.long 0x00 22. " DILSM     ,Disable LIL on load/store multiples" "Enable,Disable"
bitfld.long 0x00 21. "    DEOLP     ,Disable end of loop prediction" "Enable,Disable"
bitfld.long 0x00 20. "    DBHE      ,Disable BH extension" "Enable,Disable"
textline "                 "
bitfld.long 0x00 19. " FRCDIS    ,Fetch rate control disable" "Enable,Disable"
bitfld.long 0x00 17. "    RSDIS     ,Return stack disable" "Enable,Disable"
bitfld.long 0x00 15.--16. "    BP        ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..."
textline "                 "
bitfld.long 0x00 14. " DBWR      ,Disable write_burst on AXI master" "Enable,Disable"
bitfld.long 0x00 13. "    DLFO      ,Disable linefill optimization in the AXI master" "Enable,Disable"
bitfld.long 0x00 12. "    ERPEG     ,Enable random parity error generation" "Disable,Enable"
textline "                 "
bitfld.long 0x00 11. " DNCH      ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable"
bitfld.long 0x00 10. "    FORA      ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced"
bitfld.long 0x00 9. " FWT       ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced"
textline "                 "
bitfld.long 0x00 8. " FDSnS     ,Force D-side to not-shared when MPU is off" "Not forced,Forced"
bitfld.long 0x00 7. " SMOV      ,sMOV disabled" "Enabled,Disabled"
bitfld.long 0x0 6. "   DILS      ,Disable low interrupt latency on all load/store instructions" "Enable,Disable"
textline "                 "
bitfld.long 0x00 3.--5. " CEC       ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..."
textline "                 "
bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable"
bitfld.long 0x00 1. "    B0TCMECEN ,B0TCM external error enable" "Disable,Enable"
bitfld.long 0x00 0. "    ATCMECEN  ,ATCM external error enable" "Disable,Enable"
textline " "
group.long c15:0x0f++0x00
line.long 0x00 "SACTLR,Secondary Auxiliary Control Register"
bitfld.long 0x00 22. " DCHE      ,Disable hard-error support in the caches" "Enable,Disable"
bitfld.long 0x00 21. "    DR2B      ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable"
bitfld.long 0x00 20. "    DF6DI     ,F6 dual issue control" "Enable,Disable"
textline "                 "
bitfld.long 0x00 19. " DF2DI     ,F2 dual issue control" "Enable,Disable"
bitfld.long 0x00 18. "    DDI       ,F1/F3/F4 dual issue control" "Enable,Disable"
bitfld.long 0x00 17. "    DOODPFP   ,Out-of-order Double Precision Floating-point control" "Enable,Disable"
textline "                 "
bitfld.long 0x00 16. " DOOFMACS  ,Out-of-order FMACS control" "Enable,Disable"
bitfld.long 0x00 13. "    IXC       ,Floating-point inexact exception output mask" "Mask,Propagate"
bitfld.long 0x00 12. "  OFC       ,Floating-point overflow exception output mask" "Mask,Propagate"
textline "                 "
bitfld.long 0x00 11. " UFC       ,Floating-point underflow exception output mask" "Mask,Propagate"
bitfld.long 0x00 10. "  IOC       ,Floating-point invalid operation exception output mask" "Mask,Propagate"
bitfld.long 0x00 9. "  DZC       ,Floating-point divide-by-zero exception output mask" "Mask,Propagate"
textline "                 "
bitfld.long 0x00 8. " IDC       ,Floating-point input denormal exception output mask" "Mask,Propagate"
bitfld.long 0x00 3. "  BTCMECC   ,Correction for internal ECC logic on BTCM ports" "Enable,Disable"
bitfld.long 0x00 2. "    ATCMECC   ,Correction for internal ECC logic on ATCM port" "Enable,Disable"
textline "                 "
bitfld.long 0x00 1. " BTCMRMW   ,Enable 64-bit stores on BTCMs" "Disable,Enable"
bitfld.long 0x00 0. "    ATCMRMW   ,Enable 64-bit stores on ATCM" "Disable,Enable"
textline " "
group.long c15:0x201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. " ASEDIS    ,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 30. "        D32DIS    ,Disable use of D16-D31 of the VFP register file" "No,Yes"
textline "                 "
bitfld.long 0x0 26.--27. " CP13      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 24.--25. " CP12      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 22.--23. " CP11      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 20.--21. " CP10      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 18.--19. " CP9       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 16.--17. " CP8       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 14.--15. " CP7       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 12.--13. " CP6       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 10.--11. " CP5       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 8.--9. " CP4       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 6.--7. " CP3       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 4.--5. " CP2       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 2.--3. " CP1       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 0.--1. " CP0       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                      "
group.long c15:0x000b++0x00
line.long 0x00 "SPCR,Slave Port Control Register"
bitfld.long 0x00 1. " PRIV    ,Privilege access only" "User/Privilege,Privilege only"
bitfld.long 0x00 0. "  AXISLEN ,AXI slave port disable" "Enabled,Disabled"
tree.end
width 0x8
tree "MPU Control and Configuration"
group.long c15:0x01++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x0 31. " IE  ,Instruction endianness" "Little,Big"
bitfld.long 0x0 30. "   TE  ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. "    AFE ,Access Flag Enable" "Disable,Enable"
bitfld.long 0x0 28. "  TRE ,TEX remap enable" "Disable,Enable"
bitfld.long 0x0 27. "  NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 25. " EE  ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. "   VE  ,Vector Enable" "Disable,Vectored"
bitfld.long 0x0 21. " FI  ,Fast Interrupts enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 19. " DZ  ,Divide by Zero exception bit" "Disable,Enable"
bitfld.long 0x0 17. "  BR  ,MPU Background region enable" "Disable,Enable"
bitfld.long 0x0 14. "  RR  ,Round-Robin bit" "Random,RRobin"
bitfld.long 0x0 13. "   V   ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline "                 "
bitfld.long 0x0 12. " I   ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. "  Z   ,Branch Prediction Enable" "Disable,Enable"
bitfld.long 0x0 2. "  C   ,Enable data cache" "Disable,Enable"
bitfld.long 0x0 1. "  A   ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. "  M   ,MPU Enable" "Disable,Enable"
textline " "
group.long c15:0x05++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 12. " EXT      ,External Abort Qualifier" "DECERR,SLVERR"
bitfld.long 0x00 11. "            RW       ,Access Caused an Abort Type" "Read,Write"
textline "                 "
bitfld.long 0x00 4.--7. " DOMAIN   ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10.  "               STATUS   ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
group.long c15:0x15++0x00
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22.--23. 20. "                SIDE     ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
textline "                 "
bitfld.long 0x00 21. " REC_ERR  ,Error recoverability indication" "Not recoverable,Recoverable"
bitfld.long 0x00 20. "   SIDE_EXT ,Source of the error" "Internal,External"
textline "                 "
hexmask.long.word 0x00 5.--13. 1. " INDEX    ,Index Value for The Access Giving the Error Register"
group.long c15:0x06++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
textline " "
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. " EXT      ,External Abort Qualifier" "DECERR,SLVERR"
bitfld.long 0x00 0.--3. 10. "            STATUS   ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
group.long c15:0x115++0x00
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22.--23. 20. "                SIDE     ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
textline "                 "
bitfld.long 0x00 21. " REC_ERR  ,Error recoverability indication" "Not recoverable,Recoverable"
bitfld.long 0x00 20. "   SIDE_EXT ,Source of the error" "Internal,External"
textline "                 "
hexmask.long.word 0x00 5.--13. 1. " INDEX    ,Index Value for The Access Giving the Error Register"
group.long c15:0x206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
textline " "
group.long c15:0x0016++0x00
line.long 0x00 "RBAR,Region Base Address Register"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group.long c15:0x0216++0x00
line.long 0x00 "RSER,Region Size and Enable Register"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group.long c15:0x0416++0x00
line.long 0x00 "RACR,Region Access Control Register"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " TYPE  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
group.long c15:0x0026++0x00
line.long 0x00 "MRNR,Memory Region Number Register"
bitfld.long 0x00 0.--3. " REGION  ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
group.long c15:0x010d++0x00
line.long 0x00 "CIDR,Context ID Register"
group.long c15:0x20d++0x00
line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register"
group.long c15:0x30d++0x00
line.long 0x00 "TIDRURO,User read only Thread and Process ID Register"
group.long c15:0x40d++0x00
line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register"
width 0x08
tree "MPU regions"
group c15:0x0016++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RBAR0,Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RSER0,Region Size and Enable Register 0"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RACR0,Region Access Control Register 0"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RBAR1,Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RSER1,Region Size and Enable Register 1"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RACR1,Region Access Control Register 1"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RBAR2,Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RSER2,Region Size and Enable Register 2"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RACR2,Region Access Control Register 2"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RBAR3,Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RSER3,Region Size and Enable Register 3"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RACR3,Region Access Control Register 3"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RBAR4,Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RSER4,Region Size and Enable Register 4"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RACR4,Region Access Control Register 4"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RBAR5,Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RSER5,Region Size and Enable Register 5"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RACR5,Region Access Control Register 5"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RBAR6,Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RSER6,Region Size and Enable Register 6"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RACR6,Region Access Control Register 6"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RBAR7,Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RSER7,Region Size and Enable Register 7"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RACR7,Region Access Control Register 7"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RBAR8,Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RSER8,Region Size and Enable Register 8"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RACR8,Region Access Control Register 8"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RBAR9,Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RSER9,Region Size and Enable Register 9"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RACR9,Region Access Control Register 9"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RBAR10,Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RSER10,Region Size and Enable Register 10"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RACR10,Region Access Control Register 10"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RBAR11,Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RSER11,Region Size and Enable Register 11"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RACR11,Region Access Control Register 11"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RBAR12,Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RSER12,Region Size and Enable Register 12"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RACR12,Region Access Control Register 12"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RBAR13,Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RSER13,Region Size and Enable Register 13"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RACR13,Region Access Control Register 13"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RBAR14,Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RSER14,Region Size and Enable Register 14"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RACR14,Region Access Control Register 14"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RBAR15,Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RSER15,Region Size and Enable Register 15"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RACR15,Region Access Control Register 15"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
tree.end
tree.end
width 0x9
tree "TCM Control and Configuration"
rgroup.long c15:0x200++0x00
line.long 0x00 "TCMTR,TCM Type Register"
bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "         ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7"
group.long c15:0x019++0x00
line.long 0x00 "BTCMRR,BTCM Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address (physical address)"
bitfld.long 0x00 2.--6. "  SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Enable instruction TCM" "Disabled,Enabled"
group.long c15:0x119++0x00
line.long 0x00 "ATCMRR,ATCM Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address (physical address)"
bitfld.long 0x00 2.--6. "  SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Enable instruction TCM" "Disabled,Enabled"
rgroup.long c15:0x29++0x00
line.long 0x00 "TCMSEL,TCM Selection Register"
textline " "
group.long c15:0x10f++0x00
line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address of the interface"
bitfld.long 0x00 2.--6. "  SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Interface enable" "Disabled,Enabled"
group.long c15:0x20f++0x00
line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address of the interface"
bitfld.long 0x00 2.--6. "  SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Interface enable" "Disabled,Enabled"
group.long c15:0x30f++0x00
line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address of the interface"
bitfld.long 0x00 2.--6. "  SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Interface enable" "Disabled,Enabled"
tree.end
width 0xC
tree "Cache Control and Configuration"
rgroup.long c15:0x1100++0x00
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. " LOU      ,Level of Unification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "  LOC       ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
textline "                     "
bitfld.long 0x00 21.--23. " CL8      ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "  CL7       ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 15.--17. " CL6      ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "  CL5       ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 9.--11. " CL4      ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "  CL3       ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 3.--5. " CL2      ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "  CL1       ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7"
rgroup.long c15:0x1700++0x00
line.long 0x00 "AIDR,Auxiliary ID Register"
rgroup.long c15:0x1000++0x00
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT       ,Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. "  WB     ,Write-Back" "Not supported,Supported"
textline "                     "
bitfld.long 0x00 29. " RA       ,Read-Allocate" "Not supported,Supported"
bitfld.long 0x00 28. "  WA     ,Write-Allocate" "Not supported,Supported"
textline "                     "
hexmask.long.word 0x00 13.--27. 1. " NUMSETS  ,Number of sets"
hexmask.long.word 0x00 3.--12. 1. "           ASSOCIATIVITY ,Associativity"
textline "                     "
bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7"
group.long c15:0x2000++0x00
line.long 0x0 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL    ,Cache level to select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "              IND    ,Instruction or data or unified cache to use" "Data/unified,Instruction"
group.long c15:0x03f++0x00
line.long 0x00 "CFLR,Correctable Fault Location Register"
bitfld.long 0x00 26.--29. " WAY      ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--25. "             SIDE   ,Source of the error" "0,1,2,3"
textline "                     "
hexmask.long.word 0x00 5.--13. 1. " INDEX    ,index of the location where the error occurred"
bitfld.long 0x00 0.--1. "           TYPE   ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP"
group.long c15:0x5f++0x00
line.long 0x00 "IADCR,Invalidate All Data Cache Register"
bitfld.long 0x00 30.--31. " WAY      ,Cache way to invalidate or clean" "0,1,2,3"
hexmask.long.byte 0x00 5.--10. 1. "              SET    ,Cache set to invalidate or clean"
group.long c15:0xef++0x00
line.long 0x00 "CSOR,Cache Size Override Register"
bitfld.long 0x00 4.--7. " Dcache   ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
bitfld.long 0x00 0.--3. "       Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
tree.end
width 12.
tree "System Performance Monitor"
group.long c15:0xc9++0x00
line.long 0x00 "PMCR,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "           IDCODE ,Identification code"
bitfld.long 0x00 11.--15. "           N  ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5. "           DP ,Disable PMCCNTR when prohibited" "No,Yes"
textline "                     "
bitfld.long 0x00 4. " X   ,Export enable" "Disabled,Enabled"
bitfld.long 0x00 3. "     D      ,Clock divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "  C  ,Clock counter reset" "No action,Reset"
bitfld.long 0x00 1. "    P  ,Event counter reset" "No action,Reset"
textline "                     "
bitfld.long 0x00 0. " E   ,Enable" "Disabled,Enabled"
group.long c15:0x1c9++0x00
line.long 0x00 "PMCNTENSET,Count Enable Set Register"
eventfld.long 0x00 31. " C   ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,PMN2 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,PMN1 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,PMN0 Enabled / Enable / Disable  counter" "Disabled,Enabled"
group.long c15:0x2c9++0x00
line.long 0x0 "PMCNTENCLR,Count Enable Clear Register"
eventfld.long 0x00 31. " C   ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,PMN2 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,PMN1 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,PMN0 Enabled / Enable / Disable  counter" "Disabled,Enabled"
group.long c15:0x3c9++0x00
line.long 0x0 "PMOVSR,Overflow Flag Status Register"
eventfld.long 0x00 31. " C   ,CCNT overflowed" "No overflow,Overflow"
eventfld.long 0x00  2. "  P2     ,PMN2 overflowed" "No overflow,Overflow"
eventfld.long 0x00  1. "  P1 ,PMN1 overflowed" "No overflow,Overflow"
eventfld.long 0x00  0. "  P0 ,PMN0 overflowed" "No overflow,Overflow"
group.long c15:0x4c9++0x00
line.long 0x0 "PMSWINC,Software Increment Register"
eventfld.long 0x00  2. " P2  ,Increment  PMN2" "No action,Increment"
eventfld.long 0x00  1. "    P1     ,Increment  PMN1" "No action,Increment"
eventfld.long 0x00  0. "    P0 ,Increment  PMN0" "No action,Increment"
group.long c15:0x01d9++0x00
line.long 0x00 "PMXEVTYPER,Event Type Selection Register"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected"
group.long c15:0x02d9++0x00
line.long 0x00 "PMXEVCNTR,Event Count Register"
group.long c15:0x5c9++0x00
line.long 0x00 "PMSELR,Performance Counter Selection Register"
bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..."
group.long c15:0xd9++0x00
line.long 0x00 "PMCCNTR,Cycle Count Register"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x0
line.long 0x00 "ESR0,Event Selection Register 0"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x0
line.long 0x00 "PMCR0,Performance Monitor Count Register 0"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x1
line.long 0x00 "ESR1,Event Selection Register 1"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x1
line.long 0x00 "PMCR1,Performance Monitor Count Register 1"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x2
line.long 0x00 "ESR2,Event Selection Register 2"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x2
line.long 0x00 "PMCR2,Performance Monitor Count Register 2"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0xe9++0x00
line.long 0x00 "PMUSERENR,User Enable Register"
bitfld.long 0x00  0. " EN  ,User mode access to performance monitor and validation registers" "Not allowed,Allowed"
group.long c15:0x1e9++0x00
line.long 0x00 "PMINTENSET,Interrupt Enable Set Register"
eventfld.long 0x00 31. " C   ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,Interrupt on PMN2 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
group.long c15:0x2e9++0x00
line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register"
eventfld.long 0x00 31. " C   ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,Interrupt on PMN2 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
tree "Validation Registers"
group.long c15:0x01f++0x00
line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
group.long c15:0x11f++0x00
line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
group.long c15:0x21f++0x00
line.long 0x00 "RESR,nVAL Reset Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow reset request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
group.long c15:0x31f++0x00
line.long 0x00 "RESR,VAL Debug Request Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow debug request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
group.long c15:0x41f++0x00
line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
group.long c15:0x51f++0x00
line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
group.long c15:0x61f++0x00
line.long 0x00 "RECR,nVAL Reset Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow reset request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
group.long c15:0x71f++0x00
line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow debug request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
tree.end
tree.end
width 11.
width 18.
tree "Debug Registers"
tree "Processor Identifier Registers"
rgroup.long c14:832.++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL       ,Implementer code"
hexmask.long.byte 0x0 20.--23. 0x1 "               SPECREV    ,Variant number"
textline "                           "
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH       ,Architecture"
hexmask.long.word 0x0 4.--15. 0x1 "               PARTNUM    ,Part Number"
textline "                           "
hexmask.long.byte 0x0 0.--3. 0x1 " REV        ,Layout Revision"
rgroup.long c14:833.++0x00
line.long 0x00 "CACHETYPE,Cache Type Register"
bitfld.long 0x00 16.--19. " DMINLINE   ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
bitfld.long 0x00 14.--15. "  L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 0.--3. " IMINLINE   ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
rgroup.long c14:834.++0x00
line.long 0x00 "TCMTR,TCM Type Register"
group.long c14:835.++0x00
line.long 0x00 "AMIDR,Alias of MIDR"
rgroup.long c14:836.++0x00
line.long 0x00 "MPUTR,MPU Type Register"
rgroup.long c14:837.++0x00
line.long 0x00 "MPIDR,Multiprocessor Affinity Register"
group.long c14:838.++0x00
line.long 0x00 "AMIDR0,Alias of MIDR"
group.long c14:839.++0x00
line.long 0x00 "AMIDR1,Alias of MIDR"
rgroup.long c14:840.++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3     ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        STATE2     ,Java Extension Interface Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " STATE1     ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        STATE0     ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c14:841.++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM        ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. "        SE         ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 0.--3. " PM         ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
rgroup.long c14:842.++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM     ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "    TDM_MM     ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " TDM_CB     ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "    CDM_MM     ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " SDM_CB     ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    CDM_CB     ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup.long c14:843.++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long c14:844.++0x00
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
bitfld.long 0x00 28.--31. " IT         ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        FCSE       ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " ACR        ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        TCM        ,TCM and Associated DMA Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " CC_PLEA    ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "    CC_CPUA    ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " PMSA       ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    VMSA       ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c14:845.++0x00
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. " BTB        ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. "     L1TCO      ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " L1UCMO     ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "    L1HCMO     ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " L1UCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "    L1HCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup.long c14:846.++0x00
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
bitfld.long 0x00 28.--31. " HAF        ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "    WFI        ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " MBF        ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        UTLBMO     ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " HTLBMO     ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        HL1CMRO    ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " HL1BPCRO   ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    HL1FPCRO   ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c14:847.++0x00
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
bitfld.long 0x00 4.--7. " HCMOSW     ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        HCMOMVA    ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup.long c14:848.++0x00
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
bitfld.long 0x00 24.--27. " DIVI       ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "    DEBI       ,Debug Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 16.--19. " CI         ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "    CBI        ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 8.--11. " BI         ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "        BCI        ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 0.--3. " AI         ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:849.++0x00
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
bitfld.long 0x00 28.--31. " JI         ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        INTI       ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " IMMI       ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        ITEI       ,If Then Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " EXTI       ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        E2I        ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " E1I        ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        ENDI       ,Endianness Control Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:850.++0x00
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
bitfld.long 0x00 28.--31. " RI         ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        PSRI       ,PSR Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " UMI        ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        SMI        ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " MI         ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        II         ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " MHI        ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        LSI        ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:851.++0x00
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
bitfld.long 0x00 28.--31. " T2E        ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        NOPI       ,True NOP Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " TCI        ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        TBI        ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " SPI        ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        SWII       ,SWI Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " SIMDI      ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        SI         ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:852.++0x00
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
bitfld.long 0x00 20.--23. " EI         ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        BI         ,Barrier Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " SMII       ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        WBI        ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " WSI        ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        UI         ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c14:853.++0x00
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
tree.end
width 15.
tree "Coresight Management Registers"
group.long c14:960.++0x00
line.long 0x00 "DBGITCTRL,Integration Mode Control Register"
bitfld.long 0x00 0. " INTMODE      ,Processor integration mode" "Normal,Integration"
group.long c14:1000.++0x00
line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register"
hexmask.long.byte 0x00 0.--7. 1. " CTS          ,Claim tag set"
group.long c14:1001.++0x00
line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register"
hexmask.long.byte 0x00 0.--7. 1. " CTC          ,Claim tag clear"
wgroup.long c14:1004.++0x00
line.long 0x00 "DBGLAR,Lock Access Register"
rgroup.long c14:1005.++0x00
line.long 0x00 "DBGLSR,Lock Status Register"
bitfld.long 0x00 2. " 32BA         ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes"
textline "                        "
bitfld.long 0x00 1. " LB           ,Lock bit" "Not locked,Locked"
bitfld.long 0x00 0. "              LIB          ,Lock implemented bit" "Not locked,Locked"
rgroup.long c14:1006.++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register"
bitfld.long 0x00 7. " SNDFI        ,Secure non-invasive debug features implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "         SNDFE        ,Secure non-invasive debug features enable" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " SIDFI        ,Secure invasive debug features implemented" "Not implemented,Implemented"
bitfld.long 0x00 4. "         SIDFE        ,Secure invasive debug features enabled" "Disabled,Enabled"
rgroup.long c14:1011.++0x00
line.long 0x00 "DBGDEVTYPE,Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE      ,Subtype"
hexmask.long.byte 0x00 0.--3. 1. "                      MAIN_CLASS   ,Main class"
tree.end
textline "                     "
width 12.
rgroup.long c14:0.++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. " WRP          ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
bitfld.long 0x0 24.--27. "                       BRP          ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
textline "                     "
bitfld.long 0x0 20.--23. " CTX_CMP      ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
hexmask.long.byte 0x0 16.--19. 1. "                      VERSION      ,Debug Architecture Version"
textline "                     "
bitfld.long 0x0 15. " DEVID        ,Debug Device ID" "Low,High"
bitfld.long 0x0 14. "                    NSUHD        ,Secure User halting debug-mode" "Low,High"
textline "                     "
bitfld.long 0x0 13. " PCSR         ,PC Sample register implemented" "Low,High"
bitfld.long 0x0 12. "                    SE           ,Security Extensions implemented" "Low,High"
textline "                     "
hexmask.long.byte 0x0 4.--7. 1. " VARIANT      ,Implementation-defined Variant Number"
hexmask.long.byte 0x0 0.--3. 1. "                      REVISION     ,Implementation-defined Revision Number"
group.long c14:34.++0x0
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register"
bitfld.long 0x00 30. " RXFULL       ,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "                   TXFULL       ,DBGDTRTX Register full" "Empty,Full"
textline "                     "
bitfld.long 0x00 25. " PIPEADV      ,PIPEADV Processor Idle flag" "Not idle,Idle"
bitfld.long 0x00 24. "                INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
textline "                     "
bitfld.long 0x00 20.--21. " EXTDCCMODE   ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
bitfld.long 0x00 19. "            ADADISCARD   ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
bitfld.long 0x00 18. "         NS      ,Non-secure status bit" "Secure,Non-secure"
textline "                     "
bitfld.long 0x00 17. " SPNIDDIS     ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "                     SPIDDIS      ,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "            MDBGEN  ,Monitor debug-mode enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 14. " HDBGEN       ,Halting debug-mode" "Disabled,Enabled"
bitfld.long 0x00 13. "                ITREN        ,Execute ARM instruction enable" "Disabled,Enabled"
bitfld.long 0x00 12. "       UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
textline "                     "
bitfld.long 0x00 11. " INTDIS       ,Interrupt disable" "No,Yes"
bitfld.long 0x00 10. "                     DBGACK       ,Force debug acknowledge" "Normal,Forced"
textline "                     "
bitfld.long 0x00 8. " UND_L        ,Sticky undefined bit" "Not occurred,Occurred"
bitfld.long 0x00 7. "            ADABORT      ,Asynchronous data abort" "Not aborted,Aborted"
bitfld.long 0x00 6. "    SDABORT ,Synchronous data abort" "Not aborted,Aborted"
textline "                     "
bitfld.long 0x00 2.--5. " MOE          ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
bitfld.long 0x00 1. "  RESTARTED    ,Processor restarted" "Pending,Exited"
bitfld.long 0x00 0. "        HALTED  ,Processor halted" "Non-debug,Debug"
group.long c14:0x7++0x0
line.long 0x00 "DBGVCR,Debug Vector Catch register"
bitfld.long 0x00 7. " FIQVCE_S     ,FIQ vector catch in Secure state" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 6. " IRQVCE_S     ,IRQ vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 4. "                DAVCE_S      ,Data Abort vector catch in Secure state" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 3. " PAVCE_S      ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 2. "                SVCVCE_S     ,SVC vector catch in Secure state" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 1. " UIVCE_S      ,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "                RVCE         ,Reset vector catch enable" "Disabled,Enabled"
hgroup.long c14:32.++0x0
hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register"
in
group.long c14:35.++0x00
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
hexmask.long 0x00 0.--31. 1. " HTD          ,Host -> target data"
group.long c14:10.++0x0
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
bitfld.long 0x00 2. " NWT          ,Write through disable" "No,Yes"
bitfld.long 0x00 1. "                     NIL          ,L1 instruction cache line-fills disable" "No,Yes"
textline "                     "
bitfld.long 0x00 0. " NDL          ,L1 data cache line-fills disable" "No,Yes"
wgroup.long c14:33.++0x0
line.long 0x00 "DBGITR,Instruction Transfer Register"
wgroup.long c14:36.++0x0
line.long 0x00 "DBGDRCR,Debug Run Control Register"
bitfld.long 0x00 4. " CMR          ,Cancel memory requests" "Not cancel,Cancel"
bitfld.long 0x00 3. "              CSPA         ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
textline "                     "
bitfld.long 0x00 2. " CSE          ,Clear Sticky Exceptions bits" "No effect,Clear"
bitfld.long 0x00 1. "               RR           ,Restart request" "No effect,Restart"
textline "                     "
bitfld.long 0x00 0. " HR           ,Halt request" "No effect,Halt"
textline "                     "
rgroup.long c14:193.++0x0
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented"
group.long c14:196.++0x0
line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register"
bitfld.long 0x00 2. " HCWR         ,Hold core warm reset" "Not held,Held"
textline "                     "
bitfld.long 0x00 1. " CWRR         ,Reset reguest" "Not requested,Requested"
bitfld.long 0x00 0. "    CORENPDRQ ,Core no powerdown request" "Power-down,Emulate"
rgroup.long c14:197.++0x0
line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register"
bitfld.long 0x00 3. " SR           ,Sticky Reset Status" "Not reset,Reset"
bitfld.long 0x00 2. "        R         ,Reset Status" "No reset,Reset"
textline "                     "
bitfld.long 0x00 1. " SPD          ,Sticky Power-down Status" "Not reset,Reset"
bitfld.long 0x00 0. "        PU        ,Power-up Status" "Powered down,Powered up"
tree.end
width 7.
tree "Breakpoint Registers"
group.long c14:64.++0x0
line.long 0x00 "BVR0,Breakpoint Value 0 Register"
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
group.long c14:80.++0x0
line.long 0x00 "BCR0,Breakpoint Control 0 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:65.++0x0
line.long 0x00 "BVR1,Breakpoint Value 1 Register"
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
group.long c14:81.++0x0
line.long 0x00 "BCR1,Breakpoint Control 1 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:66.++0x0
line.long 0x00 "BVR2,Breakpoint Value 2 Register"
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
group.long c14:82.++0x0
line.long 0x00 "BCR2,Breakpoint Control 2 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:67.++0x0
line.long 0x00 "BVR3,Breakpoint Value 3 Register"
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
group.long c14:83.++0x0
line.long 0x00 "BCR3,Breakpoint Control 3 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:68.++0x0
line.long 0x00 "BVR4,Breakpoint Value 4 Register"
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
group.long c14:84.++0x0
line.long 0x00 "BCR4,Breakpoint Control 4 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:69.++0x0
line.long 0x00 "BVR5,Breakpoint Value 5 Register"
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
group.long c14:85.++0x0
line.long 0x00 "BCR5,Breakpoint Control 5 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:70.++0x0
line.long 0x00 "BVR6,Breakpoint Value 6 Register"
hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6"
group.long c14:86.++0x0
line.long 0x00 "BCR6,Breakpoint Control 6 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:71.++0x0
line.long 0x00 "BVR7,Breakpoint Value 7 Register"
hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7"
group.long c14:87.++0x0
line.long 0x00 "BCR7,Breakpoint Control 7 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
tree.end
tree "Watchpoint Control Registers"
group.long c14:96.++0x0
line.long 0x00 "WVR0,Watchpoint Value 0 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:112.++0x0
line.long 0x00 "WCR0,Watchpoint Control 0 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:97.++0x0
line.long 0x00 "WVR1,Watchpoint Value 1 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:113.++0x0
line.long 0x00 "WCR1,Watchpoint Control 1 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:98.++0x0
line.long 0x00 "WVR2,Watchpoint Value 2 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:114.++0x0
line.long 0x00 "WCR2,Watchpoint Control 2 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:99.++0x0
line.long 0x00 "WVR3,Watchpoint Value 3 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:115.++0x0
line.long 0x00 "WCR3,Watchpoint Control 3 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:100.++0x0
line.long 0x00 "WVR4,Watchpoint Value 4 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:116.++0x0
line.long 0x00 "WCR4,Watchpoint Control 4 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:101.++0x0
line.long 0x00 "WVR5,Watchpoint Value 5 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:117.++0x0
line.long 0x00 "WCR5,Watchpoint Control 5 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:102.++0x0
line.long 0x00 "WVR6,Watchpoint Value 6 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:118.++0x0
line.long 0x00 "WCR6,Watchpoint Control 6 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:103.++0x0
line.long 0x00 "WVR7,Watchpoint Value 7 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:119.++0x0
line.long 0x00 "WCR7,Watchpoint Control 7 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:6.++0x0
line.long 0x00 "WFAR ,Watchpoint Fault Address Register"
hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction"
tree.end
width 11.
AUTOINDENT.POP
tree.end
elif (CORENAME()=="CORTEXM4F")
tree.close "Core Registers (Cortex-M4F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 9. " DISFPCA        ,Disables lazy stacking of floating point context" "No,Yes"
bitfld.long 0x00 8. "                   DISOOFP        ,Disables floating point instructions completing" "No,Yes"
bitfld.long 0x00 2. "              DISFOLD         ,Disables folding of IT instructions" "No,Yes"
textline "                     "
bitfld.long 0x00 1. " DISDEFWBUF     ,Disables write buffer use during default memory map accesses" "No,Yes"
bitfld.long 0x00 0. "                   DISMCYCINT     ,Disables interruption of multi-cycle instructions" "No,Yes"
group.long 0x10++0x0B
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x00 16. " COUNTFLAG      ,Counter Flag" "Not counted,Counted"
bitfld.long 0x00 2. "           CLKSOURCE      ,SysTick clock source" "External,Core"
bitfld.long 0x00 1. "         TICKINT         ,SysTick Handler" "No SysTick,SysTick"
textline "                     "
bitfld.long 0x00 0. " ENABLE         ,Counter Enable" "Disabled,Enabled"
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD         ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF          ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "       SKEW           ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "          TENMS           ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER    ,Implementer Code"
bitfld.long 0x00 20.--23. "                    VARIANT        ,Indicates processor revision" "Revision 0,?..."
bitfld.long 0x00 16.--19. "       ARCHITECTURE    ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
hexmask.long.word 0x00 4.--15. 1. " PARTNO         ,Indicates part number"
bitfld.long 0x00 0.--3. "                  REVISION       ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET     ,Set Pending NMI Bit" "Inactive,Active"
bitfld.long 0x00 28. "              PENDSVSET      ,Set Pending pendSV Bit" "Not pending,Pending"
bitfld.long 0x00 27. "      PENDSVCLR       ,Removes the pending status of the PendSV exception" "No effect,Removed"
textline "                     "
bitfld.long 0x00 26. " PENDSTSET      ,Set Pending SysTick Bit" "Not pending,Pending"
bitfld.long 0x00 25. "           PENDSTCLR      ,Clear Pending SysTick Bit" "No effect,Removed"
bitfld.long 0x00 23. "        ISRPREEMPT      ,Use Only at Debug Time" "Not active,Active"
textline "                     "
bitfld.long 0x00 22. " ISRPENDING     ,Indicates whether an external interrupt" "Not pending,Pending"
hexmask.long.word 0x00 12.--20. 1. "           VECTPENDING    ,Pending ISR Number Field"
bitfld.long 0x00 11. "             RETTOBASE       ,Interrupt Exception" "Active,Not active"
textline "                     "
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE     ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF         ,Vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEY        ,Register Key"
rbitfld.long 0x08 15. "                  ENDIANESS      ,Data endianness Bit" "Little,Big"
bitfld.long 0x08 8.--10. "           PRIGROUP        ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
textline "                     "
bitfld.long 0x08 2. " SYSRESETREQ    ,System Reset Request" "Not requested,Requested"
bitfld.long 0x08 1. "         VECTCLRACTIVE  ,Clear Active Vector Bit" "No effect,Clear"
bitfld.long 0x08 0. "        VECTRESET       ,System Reset" "No effect,Reset"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND      ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 2. "            SLEEPDEEP      ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
bitfld.long 0x0C 1. "   SLEEPONEXIT     ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration Control Register"
bitfld.long 0x10 18. " BP             ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. "              IC             ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. "         DC              ,Cache enable bit" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 9. " STKALIGN       ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
bitfld.long 0x10 8. "  BFHFNMIGN      ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
bitfld.long 0x10 4. "         DIV_0_TRP       ,Trap Divide by Zero" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 3. " UNALIGN_TRP    ,Trap for Unaligned Access" "Disabled,Enabled"
bitfld.long 0x10 1. "              USERSETMPEND   ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
bitfld.long 0x10 0. "          NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7          ,Priority of System Handler 7"
hexmask.long.byte 0x14 16.--23. 1. "                    PRI_6          ,Priority of system handler 6(UsageFault)"
hexmask.long.byte 0x14 8.--15. 1. "               PRI_5           ,Priority of system handler 5(BusFault)"
textline "                     "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4          ,Priority of system handler 4(MemManage)"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11         ,Priority of system handler 11(SVCall)"
hexmask.long.byte 0x18 16.--23. 1. "                    PRI_10         ,Priority of System Handler 10"
hexmask.long.byte 0x18 8.--15. 1. "               PRI_9           ,Priority of System Handler 9"
textline "                     "
hexmask.long.byte 0x18 0.--7. 1. " PRI_8          ,Priority of System Handler 8"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15         ,Priority of System Handler 15(SysTick)"
hexmask.long.byte 0x1C 16.--23. 1. "                    PRI_14         ,Priority of System Handler 14(PendSV)"
hexmask.long.byte 0x1C 8.--15. 1. "               PRI_13          ,Priority of System Handler 13"
textline "                     "
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12         ,Priority of System Handler 12(DebugMonitor)"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 18. " USGFAULTENA    ,Enable UsageFault" "Disabled,Enabled"
bitfld.long 0x20 17. "              BUSFAULTENA    ,Enable BusFault" "Disabled,Enabled"
bitfld.long 0x20 16. "         MEMFAULTENA     ,Enable MemManage fault" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 15. " SVCALLPENDED   ,SVCall is pending" "Not pending,Pending"
bitfld.long 0x20 14. "           BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
bitfld.long 0x20 13. "      MEMFAULTPENDED  ,MemManage is pending" "Not pending,Pending"
textline "                     "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
bitfld.long 0x20 11. "           SYSTICKACT     ,SysTick is Active" "Not active,Active"
bitfld.long 0x20 10. "       PENDSVACT       ,PendSV is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 8. " MONITORACT     ,Monitor is Active" "Not active,Active"
bitfld.long 0x20 7. "            SVCALLACT      ,SVCall is Active" "Not active,Active"
bitfld.long 0x20 3. "       USGFAULTACT     ,UsageFault is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 1. " BUSFAULTACT    ,BusFault is Active" "Not active,Active"
bitfld.long 0x20 0. "            MEMFAULTACT    ,MemManage is Active" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. "       MMARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. "             MLSPERR        ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. "     MSTKERR         ,tacking Access Violations" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x00 3. " MUNSTKERR      ,Unstack Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. "          DACCVIOL       ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. "     IACCVIOL        ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "       BFARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. "             LSPERR         ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. "     STKERR          ,Derived bus fault(exception entry)" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 3. " UNSTKERR       ,Derived bus fault(exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. "          IMPRECISERR    ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. "     PRECISERR       ,Precise data access error" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 0. " IBUSERR        ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "USAFAULT,Usage Fault Status Register"
bitfld.word 0x00 9. "     DIVBYZERO      ,Divide by zero error" "No error,Error"
bitfld.word 0x00 8. "              UNALIGNED      ,Unaligned access error" "No error,Error"
bitfld.word 0x00 3. "         NOCP            ,A coprocessor access error" "No error,Error"
textline "                     "
bitfld.word 0x00 2. " INVPC          ,An integrity check error" "No error,Error"
bitfld.word 0x00 1. "              INVSTATE       ,Invalid Combination of EPSR and Instruction" "No error,Error"
bitfld.word 0x00 0. "         UNDEFINSTR      ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x07
line.long 0x00 "HFSR,Hard Fault Status Register"
bitfld.long 0x00 31. " DEBUGEVT       ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. "          FORCED         ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
bitfld.long 0x00 1. "     VECTTBL         ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
line.long 0x04 "DFSR,Debug Fault Status Register"
bitfld.long 0x04 4. " EXTERNAL       ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
bitfld.long 0x04 3. "          VCATCH         ,Vector Catch Flag" "Not occurred,Occurred"
bitfld.long 0x04 2. "     DWTTRAP         ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
textline "                     "
bitfld.long 0x04 1. " BKPT           ,BKPT Flag" "Not executed,Executed"
bitfld.long 0x04 0. "          HALTED         ,Indicates a debug event generated by either" "Not requested,Requested"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 22.--23. " CP11           ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 20.--21. "       CP10           ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 14.--15. "  CP7             ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 12.--13. " CP6            ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 10.--11. "       CP5            ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 8.--9. "  CP4             ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 6.--7. " CP3            ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 4.--5. "       CP2            ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 2.--3. "  CP1             ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 0.--1. " CP0            ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Trigger Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID          ,Indicates the interrupt to be triggered"
width 10.
tree "Feature Registers"
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,Thumb instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "              STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " DBGMOD    ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
hgroup.long 0xD4C++0x03
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
bitfld.long 0x00 16.--19. "          TCMSUP         ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "Level 1,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "          PMSASUP        ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
hgroup.long 0xD54++0x03
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD60++0x13
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "          DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "          BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x04 20.--23. "          IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x04 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x04 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x08 24.--27. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x08 20.--23. "   MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x08 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
textline "                   "
bitfld.long 0x08 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
bitfld.long 0x08 8.--11. "          MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x08 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x0C 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x0C 20.--23. "          THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x0C 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x0C 8.--11. "          SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x0C 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
textline "                   "
bitfld.long 0x0C 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x10 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
bitfld.long 0x10 20.--23. "          SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x10 16.--19. "        BARRIER   ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x10 4.--7. "          WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
bitfld.long 0x10 0.--3. "        UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
tree.end
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0C "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 16.--23. " IREGION    ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 8.--15. "               DREGION   ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "                    SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "         HFNMIENA  ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "          ENABLE   ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
textline "                        "
textline "                        "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
rgroup.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
tree "Interrupt Enable Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x100++0x7
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x100++0x0B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x100++0x0F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x100++0x13
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x100++0x17
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x100++0x1B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x100++0x1F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x100++0x1F
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
tree "Interrupt Pending Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x200++0x07
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x200++0x0B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x200++0x0F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x200++0x13
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x200++0x17
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x200++0x1B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x200++0x1F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x200++0x1F
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
tree "Interrupt Active Bit Registers"
width 9.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
rgroup.long 0x300++0x07
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
rgroup.long 0x300++0x0B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
rgroup.long 0x300++0x0F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
rgroup.long 0x300++0x13
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
rgroup.long 0x300++0x17
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
rgroup.long 0x300++0x1B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
rgroup.long 0x300++0x1F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
line.long 0x1c "ACTIVE8,Active Bit Register 8"
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 13. "  ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 7. "  ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 1. "  ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x300++0x1F
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
endif
tree.end
tree "Interrupt Priority Registers"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x400++0x3F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x400++0x5F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x400++0x7F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x400++0x9F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x400++0xBF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x400++0xDF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x400++0xEF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28 ,Interrupt 28 Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32 ,Interrupt 32 Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36 ,Interrupt 36 Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40 ,Interrupt 40 Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44 ,Interrupt 44 Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48 ,Interrupt 48 Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52 ,Interrupt 52 Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56 ,Interrupt 56 Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60 ,Interrupt 60 Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64 ,Interrupt 64 Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68 ,Interrupt 68 Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72 ,Interrupt 72 Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76 ,Interrupt 76 Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80 ,Interrupt 80 Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84 ,Interrupt 84 Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88 ,Interrupt 88 Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92 ,Interrupt 92 Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96 ,Interrupt 96 Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
line.long 0xE0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0xE0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0xE0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0xE0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0xE4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0xE4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0xE4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0xE4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0xE8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0xE8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0xE8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0xE8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xEC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xEC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xEC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xEC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
else
hgroup.long 0x400++0xEF
hide.long 0x0 "IPR0,Interrupt Priority Register"
hide.long 0x4 "IPR1,Interrupt Priority Register"
hide.long 0x8 "IPR2,Interrupt Priority Register"
hide.long 0xC "IPR3,Interrupt Priority Register"
hide.long 0x10 "IPR4,Interrupt Priority Register"
hide.long 0x14 "IPR5,Interrupt Priority Register"
hide.long 0x18 "IPR6,Interrupt Priority Register"
hide.long 0x1C "IPR7,Interrupt Priority Register"
hide.long 0x20 "IPR8,Interrupt Priority Register"
hide.long 0x24 "IPR9,Interrupt Priority Register"
hide.long 0x28 "IPR10,Interrupt Priority Register"
hide.long 0x2C "IPR11,Interrupt Priority Register"
hide.long 0x30 "IPR12,Interrupt Priority Register"
hide.long 0x34 "IPR13,Interrupt Priority Register"
hide.long 0x38 "IPR14,Interrupt Priority Register"
hide.long 0x3C "IPR15,Interrupt Priority Register"
hide.long 0x40 "IPR16,Interrupt Priority Register"
hide.long 0x44 "IPR17,Interrupt Priority Register"
hide.long 0x48 "IPR18,Interrupt Priority Register"
hide.long 0x4C "IPR19,Interrupt Priority Register"
hide.long 0x50 "IPR20,Interrupt Priority Register"
hide.long 0x54 "IPR21,Interrupt Priority Register"
hide.long 0x58 "IPR22,Interrupt Priority Register"
hide.long 0x5C "IPR23,Interrupt Priority Register"
hide.long 0x60 "IPR24,Interrupt Priority Register"
hide.long 0x64 "IPR25,Interrupt Priority Register"
hide.long 0x68 "IPR26,Interrupt Priority Register"
hide.long 0x6C "IPR27,Interrupt Priority Register"
hide.long 0x70 "IPR28,Interrupt Priority Register"
hide.long 0x74 "IPR29,Interrupt Priority Register"
hide.long 0x78 "IPR30,Interrupt Priority Register"
hide.long 0x7C "IPR31,Interrupt Priority Register"
hide.long 0x80 "IPR32,Interrupt Priority Register"
hide.long 0x84 "IPR33,Interrupt Priority Register"
hide.long 0x88 "IPR34,Interrupt Priority Register"
hide.long 0x8C "IPR35,Interrupt Priority Register"
hide.long 0x90 "IPR36,Interrupt Priority Register"
hide.long 0x94 "IPR37,Interrupt Priority Register"
hide.long 0x98 "IPR38,Interrupt Priority Register"
hide.long 0x9C "IPR39,Interrupt Priority Register"
hide.long 0xA0 "IPR40,Interrupt Priority Register"
hide.long 0xA4 "IPR41,Interrupt Priority Register"
hide.long 0xA8 "IPR42,Interrupt Priority Register"
hide.long 0xAC "IPR43,Interrupt Priority Register"
hide.long 0xB0 "IPR44,Interrupt Priority Register"
hide.long 0xB4 "IPR45,Interrupt Priority Register"
hide.long 0xB8 "IPR46,Interrupt Priority Register"
hide.long 0xBC "IPR47,Interrupt Priority Register"
hide.long 0xC0 "IPR48,Interrupt Priority Register"
hide.long 0xC4 "IPR49,Interrupt Priority Register"
hide.long 0xC8 "IPR50,Interrupt Priority Register"
hide.long 0xCC "IPR51,Interrupt Priority Register"
hide.long 0xD0 "IPR52,Interrupt Priority Register"
hide.long 0xD4 "IPR53,Interrupt Priority Register"
hide.long 0xD8 "IPR54,Interrupt Priority Register"
hide.long 0xDC "IPR55,Interrupt Priority Register"
hide.long 0xE0 "IPR56,Interrupt Priority Register"
hide.long 0xE4 "IPR57,Interrupt Priority Register"
hide.long 0xE8 "IPR58,Interrupt Priority Register"
hide.long 0xEC "IPR59,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif CORENAME()=="CORTEXM4F"
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN        ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. "                      LSPEN    ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 8. "       MONRDY  ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 6. " BFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. "                      MMRDY    ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
bitfld.long 0x00 4. "       HFRDY   ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 3. " THREAD       ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 1. "                       USER     ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. "   LSPACT  ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS      ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP          ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. "                 DN       ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. "  FZ      ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
textline "                 "
bitfld.long 0x08 22.--23. " RMODE        ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x07
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD     ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 24.--27. "                 SRTERR   ,Indicates the hardware support for FP short vectors" "Not supported,?..."
bitfld.long 0x00 20.--23. "  SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
textline "                 "
bitfld.long 0x00 16.--19. " DIV          ,Indicates the hardware support for FP divide operations" ",Supported,?..."
bitfld.long 0x00 12.--15. "                     FPEXTRP  ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
bitfld.long 0x00 8.--11. "  DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " SNGLPREC     ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. "                     A_SIMD   ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. "                     FP_HPFP  ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
textline "                 "
bitfld.long 0x04 4.--7. " D_NAN        ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. "               FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 7.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL     ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. "  VCATCH     ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. "  DWTTRAP    ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT         ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. "  HALTED     ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR       ,Register Read/Write" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. "          REGSEL     ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. "              MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 10.
group.long 0x00++0x07
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV     ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. "     NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
bitfld.long 0x00 1. "  KEY   ,Key Field" "Low,High"
bitfld.long 0x00 0. "      ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
textline ""
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x04 29. " RMPSPT  ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
hexmask.long.tbyte 0x04 5.--28. 0x20 "               REMAP ,Remap Base Address Field"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0xB
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 15.
group.long 0x00++0x1B
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP     ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 27. "             NOTRCPKT   ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 26. "  NOEXTTRIG   ,Shows whether the implementation includes external match signals" "Supported,Not supported"
textline "                        "
rbitfld.long 0x00 25. " NOCYCCNT    ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
rbitfld.long 0x00 24. "  NOPRFCNT   ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 22. "  CYCEVTENA   ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 21. " FOLDEVTENA  ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. "       LSUEVTENA  ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. "       SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 18. " EXCEVTENA   ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. "       CPIEVTENA  ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. "       EXCTRCENA   ,Enables generation of exception trace" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "       SYNCTAP    ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. "     CYCTAP      ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline "                        "
bitfld.long 0x00 5.--8. " POSTINIT    ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "             POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "             CYCCNTENA   ,Enables CYCCNT" "Disabled,Enabled"
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
line.long 0x08 "DWT_CPICNT,CPI Count Register"
hexmask.long.byte 0x08 0.--7. 1. " CPICNT      ,The base CPI counter"
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT      ,The exception overhead counter"
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT    ,Sleep Counter"
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT      ,Load-store counter"
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT     ,Folded-instruction counter"
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline "                        "
group.long 0x20++0x07
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
else
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x30)++0x07
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x40)++0x07
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x50)++0x07
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
endif
endif
AUTOINDENT.ON center tree
base ad:0x00
sif (cpuis("AM62*X"))
tree "A53_RS_BW_LIMITER0_REGS"
base ad:0x30403000
rgroup.long 0x00++0x07
line.long 0x00 "REGS_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x00 30.--31. "SCHEME,PID scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,PID bu identifier" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,PID function identifier"
bitfld.long 0x00 11.--15. "RTL_VER,PID RTL version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,PID custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR_REV,PID Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "REGS_CTRL,This register controls the overall behavior of the rate limiter module"
bitfld.long 0x04 4. "REGION_FILTER_EN,Enable the region filter which will only apply the bandwith and transaction limits to the configured address regions" "0,1"
bitfld.long 0x04 3. "WR_TXN_ENABLE,Enable limiting maximum outstanding write transactions" "0,1"
bitfld.long 0x04 2. "RD_TXN_ENABLE,Enable limiting maximum outstanding read transactions" "0,1"
bitfld.long 0x04 1. "WR_BW_ENABLE,Enable write bandwidth limiting" "0,1"
bitfld.long 0x04 0. "RD_BW_ENABLE,Enable read bandwidth limiting" "0,1"
group.long 0x100++0x0F
line.long 0x00 "REGS_RD_BW_CIR,Read Bandwidth Committed Information Rate"
line.long 0x04 "REGS_RD_BW_PIR,Read Bandwidth Peak Information Rate"
line.long 0x08 "REGS_RD_BW_BURST_OFFSET,Read Bandwidth Burst Offset"
hexmask.long.word 0x08 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity"
line.long 0x0C "REGS_RD_BW_INFO,Read Bandwidth State machine information"
bitfld.long 0x0C 0.--1. "COLOR,Read Bandwidth three-color marker output from rategen submodule" "0,1,2,3"
group.long 0x120++0x1B
line.long 0x00 "REGS_RD_BW_STATS,Read Bandwidth Statistics Control Register"
hexmask.long.word 0x00 16.--31. 1. "WINDOW,Statistics window size"
rbitfld.long 0x00 9. "OVERFLOW,Statistics overflow error" "0,1"
bitfld.long 0x00 8. "CLR,Clear statistics data" "0,1"
bitfld.long 0x00 0. "EN,Enable read bandwidth statistics" "0,1"
line.long 0x04 "REGS_RD_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR"
line.long 0x08 "REGS_RD_BW_WINDOWS_CNT,Read Bandwidth Statistics - Window Count"
line.long 0x0C "REGS_RD_BW_CIR_CNT,Read Bandwidth Statistics - CIR Count"
line.long 0x10 "REGS_RD_BW_PIR_CNT,Read Bandwidth Statistics - PIR Count"
line.long 0x14 "REGS_RD_BW_THRSHLD_CNT,Read Bandwidth Statistics - Threshold Count"
line.long 0x18 "REGS_RD_BYTES_MAX,The maximum number of bytes seen in a single statitsics window"
group.long 0x300++0x03
line.long 0x00 "REGS_RD_TXN,The maximum number of outstanding read transactions the rate limiter will allow"
hexmask.long.word 0x00 0.--15. 1. "LIMIT,The maximum number of outstanding read transactions allowed"
rgroup.long 0x30C++0x03
line.long 0x00 "REGS_RD_TXN_INFO,Read Transaction State machine information"
hexmask.long.byte 0x00 0.--6. 1. "OCC,Read transaction scoreboard occupancy"
group.long 0x320++0x1F
line.long 0x00 "REGS_RD_TXN_STATS,Read Transaction Stats Control Register"
hexmask.long.word 0x00 16.--31. 1. "WINDOW,Statistics window size"
rbitfld.long 0x00 9. "OVERFLOW,Statistics overflow error" "0,1"
bitfld.long 0x00 8. "CLR,Clear statistics data" "0,1"
bitfld.long 0x00 0. "EN,Enable read transaction statistics" "0,1"
line.long 0x04 "REGS_RD_TXN_STATS_THRSHLD,A statistics threshold separate from the read transaction limit"
hexmask.long.word 0x04 0.--15. 1. "THRESHOLD,Read transaction statistics threshold"
line.long 0x08 "REGS_RD_TXN_WINDOWS_CNT,Read Transaction Statistics - Window Count"
line.long 0x0C "REGS_RD_TXN_LMT_CNT,Read Transaction Statistics - number of windows in which the outstanding transaction limit was reached"
line.long 0x10 "REGS_RD_TXN_THRSHLD_CNT,Read Transaction Statistics - number of windows in which the statistics threshold was reached"
line.long 0x14 "REGS_RD_TXN_LIMIT_TOTAL,Read Transaction Statistics - Cycles at Outstanding Read Transactions Limit"
line.long 0x18 "REGS_RD_TXN_THRSHLD_TOTAL,Read Transaction Statistics - Cycles at the Statistics Threshold"
line.long 0x1C "REGS_RD_TXN_MAX,Read Transaction Statistics - Max Observed Outstanding Read Transactions"
hexmask.long.word 0x1C 0.--15. 1. "VAL,The maximum outstanding read transactions at any point in time regardless of the programmed limit"
tree.end
tree "A53_WS_BW_LIMITER1_REGS"
base ad:0x30402000
rgroup.long 0x00++0x07
line.long 0x00 "REGS_PID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x00 30.--31. "SCHEME,PID scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,PID bu identifier" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,PID function identifier"
bitfld.long 0x00 11.--15. "RTL_VER,PID RTL version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_REV,PID Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,PID custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR_REV,PID Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "REGS_CTRL,This register controls the overall behavior of the rate limiter module"
bitfld.long 0x04 4. "REGION_FILTER_EN,Enable the region filter which will only apply the bandwith and transaction limits to the configured address regions" "0,1"
bitfld.long 0x04 3. "WR_TXN_ENABLE,Enable limiting maximum outstanding write transactions" "0,1"
bitfld.long 0x04 2. "RD_TXN_ENABLE,Enable limiting maximum outstanding read transactions" "0,1"
bitfld.long 0x04 1. "WR_BW_ENABLE,Enable write bandwidth limiting" "0,1"
bitfld.long 0x04 0. "RD_BW_ENABLE,Enable read bandwidth limiting" "0,1"
group.long 0x200++0x0F
line.long 0x00 "REGS_WR_BW_CIR,Write Bandwidth Committed Information Rate"
line.long 0x04 "REGS_WR_BW_PIR,Write Bandwidth Peak Information Rate"
line.long 0x08 "REGS_WR_BW_BURST_OFFSET,Write Bandwidth Burst Offset"
hexmask.long.word 0x08 0.--15. 1. "OFFSET,Burst Offset - the number of bytes before the Committed Information Rate is applied at startup or after a period of inactivity"
line.long 0x0C "REGS_WR_BW_INFO,Write Bandwidth State machine information"
bitfld.long 0x0C 0.--1. "COLOR,Write Bandwidth three-color marker output from rategen submodule" "0,1,2,3"
group.long 0x220++0x1B
line.long 0x00 "REGS_WR_BW_STATS,Write Bandwidth Statistics Control Register"
hexmask.long.word 0x00 16.--31. 1. "WINDOW,Statistics window size"
rbitfld.long 0x00 9. "OVERFLOW,Statistics overflow error" "0,1"
bitfld.long 0x00 8. "CLR,Clear statistics data" "0,1"
bitfld.long 0x00 0. "EN,Enable write bandwidth statistics" "0,1"
line.long 0x04 "REGS_WR_BW_STATS_THRSHLD,A statistics threshold separate from the CIR and PIR"
line.long 0x08 "REGS_WR_BW_WINDOWS_CNT,Write Bandwidth Statistics - Window Count"
line.long 0x0C "REGS_WR_BW_CIR_CNT,Write Bandwidth Statistics - CIR Count"
line.long 0x10 "REGS_WR_BW_PIR_CNT,Write Bandwidth Statistics - PIR Count"
line.long 0x14 "REGS_WR_BW_THRSHLD_CNT,Write Bandwidth Statistics - Threshold Count"
line.long 0x18 "REGS_WR_BYTES_MAX,The maximum number of bytes seen in a single statitsics window"
group.long 0x400++0x03
line.long 0x00 "REGS_WR_TXN,The maximum number of outstanding write transactions the rate limiter will allow"
hexmask.long.word 0x00 0.--15. 1. "LIMIT,The maximum number of outstanding write transactions allowed"
rgroup.long 0x40C++0x03
line.long 0x00 "REGS_WR_TXN_INFO,Write Transaction State machine information"
hexmask.long.byte 0x00 0.--6. 1. "OCC,Write transaction scoreboard occupancy"
group.long 0x420++0x1F
line.long 0x00 "REGS_WR_TXN_STATS,Write Transaction Stats Control Register"
hexmask.long.word 0x00 16.--31. 1. "WINDOW,Statistics window size"
rbitfld.long 0x00 9. "OVERFLOW,Statistics overflow error" "0,1"
bitfld.long 0x00 8. "CLR,Clear statistics data" "0,1"
bitfld.long 0x00 0. "EN,Enable write transaction statistics" "0,1"
line.long 0x04 "REGS_WR_TXN_STATS_THRSHLD,A statistics threshold separate from the write transaction limit"
hexmask.long.word 0x04 0.--15. 1. "THRESHOLD,Write transaction statistics threshold"
line.long 0x08 "REGS_WR_TXN_WINDOWS_CNT,Write Transaction Statistics - Window Count"
line.long 0x0C "REGS_WR_TXN_LMT_CNT,Write Transaction Statistics - number of windows in which the outstanding transaction limit was reached"
line.long 0x10 "REGS_WR_TXN_THRSHLD_CNT,Write Transaction Statistics - number of windows in which the statistics threshold was reached"
line.long 0x14 "REGS_WR_TXN_LIMIT_TOTAL,Write Transaction Statistics - Cycles at Outstanding Write Transactions Limit"
line.long 0x18 "REGS_WR_TXN_THRSHLD_TOTAL,Write Transaction Statistics - Cycles at the Statistics Threshold"
line.long 0x1C "REGS_WR_TXN_MAX,Write Transaction Statistics - Max Observed Outstanding Write Transactions"
hexmask.long.word 0x1C 0.--15. 1. "VAL,The maximum outstanding write transactions at any point in time regardless of the programmed limit"
tree.end
tree "A53SS0_CORE0_CTI"
base ad:0x730020000
group.long 0x00++0x03
line.long 0x00 "APBADDR_CTI_CPU0_CTICONTROL,CTI Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_CTICONTROL_31_1,Reserved RES0"
bitfld.long 0x00 0. "GLBEN,Enables or disables the CTI mapping functions" "0,1"
group.long 0x10++0x2F
line.long 0x00 "APBADDR_CTI_CPU0_CTIINTACK,CTI Output Trigger Acknowledge Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "ACK_N,Can be used to create soft acknowledges for output triggers"
line.long 0x04 "APBADDR_CTI_CPU0_CTIAPPSET,CTI Application Trigger Set Register"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "CTIAPPSETX,Application trigger <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU0_CTIAPPCLEAR,CTI Application Trigger Clear Register"
hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x08 0.--3. "CTIAPPCLEARX,Application trigger <x> disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_CTI_CPU0_CTIAPPPULSE,CTI Application Pulse Register"
hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x0C 0.--3. "CTIAPPPULSEX,Generate event pulse on ECT channel <x>" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU0_CTIINEN0,CTI Input Trigger to Output Channel Enable Register 0"
hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x10 0.--3. "INENX,Input trigger 0 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_CTI_CPU0_CTIINEN1,CTI Input Trigger to Output Channel Enable Register 1"
hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x14 0.--3. "INENX,Input trigger 1 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_CTI_CPU0_CTIINEN2,CTI Input Trigger to Output Channel Enable Register 2"
hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x18 0.--3. "INENX,Input trigger 2 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "APBADDR_CTI_CPU0_CTIINEN3,CTI Input Trigger to Output Channel Enable Register 3"
hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x1C 0.--3. "INENX,Input trigger 3 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "APBADDR_CTI_CPU0_CTIINEN4,CTI Input Trigger to Output Channel Enable Register 4"
hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x20 0.--3. "INENX,Input trigger 4 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "APBADDR_CTI_CPU0_CTIINEN5,CTI Input Trigger to Output Channel Enable Register 5"
hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x24 0.--3. "INENX,Input trigger 5 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "APBADDR_CTI_CPU0_CTIINEN6,CTI Input Trigger to Output Channel Enable Register 6"
hexmask.long 0x28 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x28 0.--3. "INENX,Input trigger 6 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "APBADDR_CTI_CPU0_CTIINEN7,CTI Input Trigger to Output Channel Enable Register 7"
hexmask.long 0x2C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x2C 0.--3. "INENX,Input trigger 7 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0++0x1F
line.long 0x00 "APBADDR_CTI_CPU0_CTIOUTEN0,CTI Input Channel to Output Trigger Enable Register 0"
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--3. "OUTENX,Input channel <x> to output trigger 0 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_CTI_CPU0_CTIOUTEN1,CTI Input Channel to Output Trigger Enable Register 1"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "OUTENX,Input channel <x> to output trigger 1 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU0_CTIOUTEN2,CTI Input Channel to Output Trigger Enable Register 2"
hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x08 0.--3. "OUTENX,Input channel <x> to output trigger 2 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_CTI_CPU0_CTIOUTEN3,CTI Input Channel to Output Trigger Enable Register 3"
hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x0C 0.--3. "OUTENX,Input channel <x> to output trigger 3 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU0_CTIOUTEN4,CTI Input Channel to Output Trigger Enable Register 4"
hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x10 0.--3. "OUTENX,Input channel <x> to output trigger 4 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_CTI_CPU0_CTIOUTEN5,CTI Input Channel to Output Trigger Enable Register 5"
hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x14 0.--3. "OUTENX,Input channel <x> to output trigger 5 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_CTI_CPU0_CTIOUTEN6,CTI Input Channel to Output Trigger Enable Register 6"
hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x18 0.--3. "OUTENX,Input channel <x> to output trigger 6 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "APBADDR_CTI_CPU0_CTIOUTEN7,CTI Input Channel to Output Trigger Enable Register 7"
hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x1C 0.--3. "OUTENX,Input channel <x> to output trigger 7 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x130++0x17
line.long 0x00 "APBADDR_CTI_CPU0_CTITRIGINSTATUS,CTI Trigger In Status Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "TRINN,Provides the status of the trigger inputs"
line.long 0x04 "APBADDR_CTI_CPU0_CTITRIGOUTSTATUS,CTI Trigger Out Status Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x04 0.--7. 1. "TROUTN,Provides the status of the trigger outputs"
line.long 0x08 "APBADDR_CTI_CPU0_CTICHINSTATUS,CTI Channel In Status Register"
hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x08 0.--3. "CHINN,Provides the raw status of the ECT channel inputs to the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_CTI_CPU0_CTICHOUTSTATUS,CTI Channel Out Status Register"
hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x0C 0.--3. "CHOUTN,Provides the status of the ECT channel outputs from the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU0_CTIGATE,CTI Channel Gate Enable Register"
hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x10 0.--3. "GATEX,Determines whether events on channels propagate through the CTM to other ECT components or from the CTM into the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_CTI_CPU0_ASICCTL,CTI External Multiplexor Control register"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_ASICCTL_31_8,Reserved RES0"
hexmask.long.byte 0x14 0.--7. 1. "ASICCTL,IMPLEMENTATION DEFINED ASIC control"
group.long 0xF00++0x03
line.long 0x00 "APBADDR_CTI_CPU0_CTIITCTRL,CTI Integration mode Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_CTIITCTRL_31_1,Reserved RES0"
bitfld.long 0x00 0. "IME,Integration mode enable" "0,1"
group.long 0xFA0++0x33
line.long 0x00 "APBADDR_CTI_CPU0_CTICLAIMSET,CTI Claim Set"
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--3. "CLAIMX,CLAIM tag set bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_CTI_CPU0_CTICLAIMCLR,CTI Claim Clear"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "CLAIMX,Clear CLAIM tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU0_CTIDEVAFF0,CTI Device Affinity Register 0"
line.long 0x0C "APBADDR_CTI_CPU0_CTIDEVAFF1,CTI Device Affinity Register 1"
line.long 0x10 "APBADDR_CTI_CPU0_CTILAR,CTI Lock Access Register"
line.long 0x14 "APBADDR_CTI_CPU0_CTILSR,CTI Lock Status Register"
hexmask.long 0x14 3.--31. 1. "RES0_CTILSR_31_3,Reserved RES0"
bitfld.long 0x14 2. "NTT,Not thirty-two bit access required" "0,1"
bitfld.long 0x14 1. "SLK,Software lock status for this component" "0,1"
newline
bitfld.long 0x14 0. "SLI,Software lock implemented" "0,1"
line.long 0x18 "APBADDR_CTI_CPU0_CTIAUTHSTATUS,CTI Authentication Status Register"
hexmask.long 0x18 4.--31. 1. "RES0_CTIAUTHSTATUS_31_4,Reserved RES0"
bitfld.long 0x18 2.--3. "NSNID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SNID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSNID" "0,1,2,3"
bitfld.long 0x18 0.--1. "NSID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSID" "0,1,2,3"
line.long 0x1C "APBADDR_CTI_CPU0_CTIDEVARCH,CTI Device Architecture Register"
hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A" "0,1"
bitfld.long 0x1C 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
line.long 0x20 "APBADDR_CTI_CPU0_CTIDEVID2,CTI Device ID Register 2"
line.long 0x24 "APBADDR_CTI_CPU0_CTIDEVID1,CTI Device ID Register 1"
line.long 0x28 "APBADDR_CTI_CPU0_CTIDEVID,CTI Device ID Register 0"
bitfld.long 0x28 26.--31. "RES0_CTIDEVID_31_26,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x28 24.--25. "INOUT,Input/output options" "0,1,2,3"
bitfld.long 0x28 22.--23. "RES0_CTIDEVID_23_22,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x28 16.--21. "NUMCHAN,Number of ECT channels implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x28 14.--15. "RES0_CTIDEVID_15_14,Reserved RES0" "0,1,2,3"
bitfld.long 0x28 8.--13. "NUMTRIG,Number of triggers implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x28 5.--7. "RES0_CTIDEVID_7_5,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x28 0.--4. "EXTMUXNUM,Maximum number of external triggers available for multiplexing into the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x2C "APBADDR_CTI_CPU0_CTIDEVTYPE,CTI Device Type Register"
hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_CTIDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x2C 4.--7. "SUB,Subtype" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 0.--3. "MAJOR,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "APBADDR_CTI_CPU0_CTIPIDR4,CTI Peripheral Identification Register 4"
hexmask.long.tbyte 0x30 8.--31. 1. "RES0_CTIPIDR4_31_8,Reserved RES0"
bitfld.long 0x30 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 0.--3. "DES_2,Designer JEP106 continuation code least significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
group.long ($2+0xFD4)++0x03
line.long 0x00 "APBADDR_CTI_CPU0_CTIPIDR$1,CTI Peripheral Identification Register 5"
repeat.end
group.long 0xFE0++0x1F
line.long 0x00 "APBADDR_CTI_CPU0_CTIPIDR0,CTI Peripheral Identification Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_CTIPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number least significant byte"
line.long 0x04 "APBADDR_CTI_CPU0_CTIPIDR1,CTI Peripheral Identification Register 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_CTIPIDR1_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "DES_0,Designer least significant nibble of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "PART_1,Part number most significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU0_CTIPIDR2,CTI Peripheral Identification Register 2"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_CTIPIDR2_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "REVISION,Part major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3. "JEDEC,RAO" "0,1"
newline
bitfld.long 0x08 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x0C "APBADDR_CTI_CPU0_CTIPIDR3,CTI Peripheral Identification Register 3"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_CTIPIDR3_31_8,Reserved RES0"
bitfld.long 0x0C 4.--7. "REVAND,Part minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU0_CTICIDR0,CTI Component Identification Register 0"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_CTICIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x14 "APBADDR_CTI_CPU0_CTICIDR1,CTI Component Identification Register 1"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_CTICIDR1_31_8,Reserved RES0"
bitfld.long 0x14 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_CTI_CPU0_CTICIDR2,CTI Component Identification Register 2"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_CTICIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x1C "APBADDR_CTI_CPU0_CTICIDR3,CTI Component Identification Register 3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_CTICIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_CORE0_DBG"
base ad:0x730010000
group.long 0x20++0x07
line.long 0x00 "APBADDR_DBG_CPU0_EDESR,External Debug Event Status Register"
hexmask.long 0x00 3.--31. 1. "RES0_EDESR_31_3,Reserved RES0"
bitfld.long 0x00 2. "SS,Halting step debug event pending" "0,1"
newline
bitfld.long 0x00 1. "RC,Reset catch debug event pending" "0,1"
bitfld.long 0x00 0. "OSUC,OS unlock debug event pending" "0,1"
line.long 0x04 "APBADDR_DBG_CPU0_EDECR,External Debug Execution Control Register"
hexmask.long 0x04 3.--31. 1. "RES0_EDECR_31_3,Reserved RES0"
bitfld.long 0x04 2. "SS,Halting step enable" "0,1"
newline
bitfld.long 0x04 1. "RCE,Reset catch enable" "0,1"
bitfld.long 0x04 0. "OSUCE,OS unlock catch enabled" "0,1"
group.long 0x30++0x07
line.long 0x00 "APBADDR_DBG_CPU0_EDWAR_31_0,External Debug Watchpoint Address Register (low word)"
line.long 0x04 "APBADDR_DBG_CPU0_EDWAR_63_32,External Debug Watchpoint Address Register (high word)"
group.long 0x80++0x1B
line.long 0x00 "APBADDR_DBG_CPU0_DBGDTRRX_EL0,Debug Data Transfer Register Receive"
line.long 0x04 "APBADDR_DBG_CPU0_EDITR,External Debug Instruction Transfer Register"
line.long 0x08 "APBADDR_DBG_CPU0_EDSCR,External Debug Status and Control Register"
bitfld.long 0x08 31. "RES0_EDSCR_31_31,Reserved RES0" "0,1"
bitfld.long 0x08 30. "RXFULL,DTRRX full" "0,1"
newline
bitfld.long 0x08 29. "TXFULL,DTRTX full" "0,1"
bitfld.long 0x08 28. "ITO,EDITR overrun" "0,1"
newline
bitfld.long 0x08 27. "RXO,DTRRX overrun" "0,1"
bitfld.long 0x08 26. "TXU,DTRTX underrun" "0,1"
newline
bitfld.long 0x08 25. "PIPEADV,Pipeline advance" "0,1"
bitfld.long 0x08 24. "ITE,ITR empty" "0,1"
newline
bitfld.long 0x08 22.--23. "INTDIS,Interrupt disable" "0,1,2,3"
bitfld.long 0x08 21. "TDA,Trap debug registers accesses" "0,1"
newline
bitfld.long 0x08 20. "MA,Memory access mode" "0,1"
bitfld.long 0x08 19. "RES0_EDSCR_19_19,Reserved RES0" "0,1"
newline
bitfld.long 0x08 18. "NS,Non-secure status" "0,1"
bitfld.long 0x08 17. "RES0_EDSCR_17_17,Reserved RES0" "0,1"
newline
bitfld.long 0x08 16. "SDD,Secure debug disabled" "0,1"
bitfld.long 0x08 15. "RES0_EDSCR_15_15,Reserved RES0" "0,1"
newline
bitfld.long 0x08 14. "HDE,Halting debug mode enable" "0,1"
bitfld.long 0x08 10.--13. "RW,Exception level register-width status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 8.--9. "EL,Exception level" "0,1,2,3"
bitfld.long 0x08 7. "A,System Error interrupt pending" "0,1"
newline
bitfld.long 0x08 6. "ERR,Cumulative error flag" "0,1"
bitfld.long 0x08 0.--5. "STATUS,Debug status flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "APBADDR_DBG_CPU0_DBGDTRTX_EL0,Debug Data Transfer Register Transmit"
line.long 0x10 "APBADDR_DBG_CPU0_EDRCR,External Debug Reserve Control Register"
hexmask.long 0x10 5.--31. 1. "RES0_EDRCR_31_5,Reserved RES0"
bitfld.long 0x10 4. "CBRRQ,Allow imprecise entry to Debug state" "0,1"
newline
bitfld.long 0x10 3. "CSPA,Clear Sticky Pipeline Advance" "0,1"
bitfld.long 0x10 2. "CSE,Clear Sticky Error" "0,1"
newline
bitfld.long 0x10 0.--1. "RES0_EDRCR_1_0,Reserved RES0" "0,1,2,3"
line.long 0x14 "APBADDR_DBG_CPU0_EDACR,External Debug Auxiliary Control Register"
line.long 0x18 "APBADDR_DBG_CPU0_EDECCR,External Debug Exception Catch Control Register"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDECCR_31_8,Reserved RES0"
bitfld.long 0x18 4.--7. "NSE,Coarse-grained Non-secure exception catch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 0.--3. "SE,Coarse-grained Secure exception catch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0++0x0F
line.long 0x00 "APBADDR_DBG_CPU0_EDPCSR_31_0,External Debug Program Counter Sample Register (low word)"
line.long 0x04 "APBADDR_DBG_CPU0_EDCIDSR,External Debug Context ID Sample Register"
line.long 0x08 "APBADDR_DBG_CPU0_EDVIDSR,External Debug Virtual Context Sample Register"
bitfld.long 0x08 31. "NS,Non-secure state sample" "0,1"
bitfld.long 0x08 30. "E2,Exception level 2 status sample" "0,1"
newline
bitfld.long 0x08 29. "E3,Exception level 3 status sample" "0,1"
bitfld.long 0x08 28. "HV,EDPCSR high half valid" "0,1"
newline
hexmask.long.tbyte 0x08 8.--27. 1. "RES0_EDVIDSR_27_8,Reserved RES0"
hexmask.long.byte 0x08 0.--7. 1. "VMID,VMID sample"
line.long 0x0C "APBADDR_DBG_CPU0_EDPCSR_63_32,External Debug Program Counter Sample Register (high word)"
group.long 0x300++0x03
line.long 0x00 "APBADDR_DBG_CPU0_OSLAR_EL1,OS Lock Access Register"
hexmask.long 0x00 1.--31. 1. "RES0_OSLAR_EL1_31_1,Reserved RES0"
bitfld.long 0x00 0. "OSLK,On writes to OSLAR_EL1 bit[0] is copied to the OS lock.Use EDPRSR.OSLK to check the current status of the lock" "0,1"
group.long 0x310++0x07
line.long 0x00 "APBADDR_DBG_CPU0_EDPRCR,External Debug Power/Reset Control Register"
hexmask.long 0x00 4.--31. 1. "RES0_EDPRCR_31_4,Reserved RES0"
bitfld.long 0x00 3. "COREPURQ,Core powerup request" "0,1"
newline
bitfld.long 0x00 2. "RES0_EDPRCR_2_2,Reserved RES0" "0,1"
bitfld.long 0x00 1. "CWRR,Warm reset request" "0,1"
newline
bitfld.long 0x00 0. "CORENPDRQ,Core no powerdown request" "0,1"
line.long 0x04 "APBADDR_DBG_CPU0_EDPRSR,External Debug Processor Status Register"
hexmask.long.tbyte 0x04 12.--31. 1. "RES0_EDPRSR_31_12,Reserved RES0"
bitfld.long 0x04 11. "SDR,Sticky debug restart" "0,1"
newline
bitfld.long 0x04 10. "SPMAD,Sticky EPMAD error" "0,1"
bitfld.long 0x04 9. "EPMAD,External performance monitors access disable status" "0,1"
newline
bitfld.long 0x04 8. "SDAD,Sticky EDAD error" "0,1"
bitfld.long 0x04 7. "EDAD,External debug access disable status" "0,1"
newline
bitfld.long 0x04 6. "DLK,OS Double Lock status bit" "0,1"
bitfld.long 0x04 5. "OSLK,OS lock status bit" "0,1"
newline
bitfld.long 0x04 4. "HALTED,Halted status bit" "0,1"
bitfld.long 0x04 3. "SR,Sticky core reset status bit" "0,1"
newline
bitfld.long 0x04 2. "R,Core reset status bit" "0,1"
bitfld.long 0x04 1. "SPD,Sticky core power-down status bit.This bit is set to 1 on Cold reset to indicate the state of the debug registers has been lost" "0,1"
newline
bitfld.long 0x04 0. "PU,Core power-up status bit" "0,1"
group.long 0x400++0x0B
line.long 0x00 "APBADDR_DBG_CPU0_DBGBVR0_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU0_DBGBVR0_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU0_DBGBCR0_EL1,Debug Breakpoint Control Register 0"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR0_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR0_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR0_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x410++0x0B
line.long 0x00 "APBADDR_DBG_CPU0_DBGBVR1_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU0_DBGBVR1_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU0_DBGBCR1_EL1,Debug Breakpoint Control Register 1"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR1_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR1_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR1_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x420++0x0B
line.long 0x00 "APBADDR_DBG_CPU0_DBGBVR2_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU0_DBGBVR2_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU0_DBGBCR2_EL1,Debug Breakpoint Control Register 2"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR2_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR2_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR2_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x430++0x0B
line.long 0x00 "APBADDR_DBG_CPU0_DBGBVR3_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU0_DBGBVR3_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU0_DBGBCR3_EL1,Debug Breakpoint Control Register 3"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR3_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR3_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR3_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x440++0x0B
line.long 0x00 "APBADDR_DBG_CPU0_DBGBVR4_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU0_DBGBVR4_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU0_DBGBCR4_EL1,Debug Breakpoint Control Register 4"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR4_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR4_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR4_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x450++0x0B
line.long 0x00 "APBADDR_DBG_CPU0_DBGBVR5_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU0_DBGBVR5_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU0_DBGBCR5_EL1,Debug Breakpoint Control Register 5"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR5_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR5_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR5_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x800++0x0B
line.long 0x00 "APBADDR_DBG_CPU0_DBGWVR0_EL1_31_0,Debug Watchpoint Value Register 0"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR0_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU0_DBGWVR0_EL1_63_32,Debug Watchpoint Extended Value Register 0"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU0_DBGWCR0_EL1,Debug Watchpoint Control Register 0"
bitfld.long 0x08 29.--31. "RES0_DBGWCR0_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 21.--23. "RES0_DBGWCR0_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
newline
bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0x810++0x0B
line.long 0x00 "APBADDR_DBG_CPU0_DBGWVR1_EL1_31_0,Debug Watchpoint Value Register 1"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR1_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU0_DBGWVR1_EL1_63_32,Debug Watchpoint Extended Value Register 1"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU0_DBGWCR1_EL1,Debug Watchpoint Control Register 1"
bitfld.long 0x08 29.--31. "RES0_DBGWCR1_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 21.--23. "RES0_DBGWCR1_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
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bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
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bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
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bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
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bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0x820++0x0B
line.long 0x00 "APBADDR_DBG_CPU0_DBGWVR2_EL1_31_0,Debug Watchpoint Value Register 2"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR2_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU0_DBGWVR2_EL1_63_32,Debug Watchpoint Extended Value Register 2"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU0_DBGWCR2_EL1,Debug Watchpoint Control Register 2"
bitfld.long 0x08 29.--31. "RES0_DBGWCR2_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 21.--23. "RES0_DBGWCR2_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
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bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
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bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
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bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
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bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0x830++0x0B
line.long 0x00 "APBADDR_DBG_CPU0_DBGWVR3_EL1_31_0,Debug Watchpoint Value Register 3"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR3_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU0_DBGWVR3_EL1_63_32,Debug Watchpoint Extended Value Register 3"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU0_DBGWCR3_EL1,Debug Watchpoint Control Register 3"
bitfld.long 0x08 29.--31. "RES0_DBGWCR3_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 21.--23. "RES0_DBGWCR3_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
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bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
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bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
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bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
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bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0xD00++0x03
line.long 0x00 "APBADDR_DBG_CPU0_MIDR_EL1,Main ID Register"
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,The Implementer code"
bitfld.long 0x00 20.--23. "VARIANT,An IMPLEMENTATION DEFINED variant number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "ARCHITECTURE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 4.--15. 1. "PARTNUM,An IMPLEMENTATION DEFINED primary part number for the device"
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bitfld.long 0x00 0.--3. "REVISION,An IMPLEMENTATION DEFINED revision number for the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD20++0x3F
line.long 0x00 "APBADDR_DBG_CPU0_ID_AA64PFR0_EL1_31_0,Processor Feature Register 0 (low word)"
bitfld.long 0x00 28.--31. "RES0_ID_AA64PFR0_EL1_31_0_31_28,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "GIC,GIC system register interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "ADVSIMD,Advanced SIMD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "FP,Floating-point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "EL3,EL3 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "EL2,EL2 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "EL1,EL1 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "EL0,EL0 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_DBG_CPU0_ID_AA64PFR0_EL1_63_32,Processor Feature Register 0 (high word)"
line.long 0x08 "APBADDR_DBG_CPU0_ID_AA64DFR0_EL1_31_0,Debug Feature Register 0 (low word)"
bitfld.long 0x08 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 24.--27. "RES0_ID_AA64DFR0_EL1_31_0_27_24,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "WRPS,Number of watchpoints minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 16.--19. "RES0_ID_AA64DFR0_EL1_31_0_19_16,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 12.--15. "BRPS,Number of breakpoints minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 8.--11. "PMUVER,Performance Monitors extension version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4.--7. "TRACEVER,Trace extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--3. "DEBUGVER,Debug architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_DBG_CPU0_ID_AA64DFR0_EL1_63_32,Debug Feature Register 0 (high word)"
line.long 0x10 "APBADDR_DBG_CPU0_ID_AA64ISAR0_EL1_31_0,Instruction Set Attribute Register 0 (low word)"
hexmask.long.word 0x10 20.--31. 1. "RES0_ID_AA64ISAR0_EL1_31_0_31_20,Reserved RES0"
bitfld.long 0x10 16.--19. "CRC32,CRC32 instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 12.--15. "SHA2,SHA2 instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 8.--11. "SHA1,SHA1 instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 4.--7. "AES,AES instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 0.--3. "RES0_ID_AA64ISAR0_EL1_31_0_3_0,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_DBG_CPU0_ID_AA64ISAR0_EL1_63_32,Instruction Set Attribute Register 0 (high word)"
line.long 0x18 "APBADDR_DBG_CPU0_ID_AA64MMFR0_EL1_31_0,Memory Model Feature Register 0 (low word)"
bitfld.long 0x18 28.--31. "TGRAN4,Support for 4 Kbyte memory translation granule size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 24.--27. "TGRAN64,Support for 64 Kbyte memory translation granule size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 20.--23. "TGRAN16,Support for 16 Kbyte memory translation granule size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 16.--19. "BIGENDEL0,Mixed-endian support at EL0 only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 8.--11. "BIGEND,Mixed-endian configuration support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 4.--7. "ASIDBITS,Number of ASID bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 0.--3. "PARANGE,Physical Address range supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "APBADDR_DBG_CPU0_ID_AA64MMFR0_EL1_63_32,Memory Model Feature Register 0 (high word)"
line.long 0x20 "APBADDR_DBG_CPU0_ID_AA64PFR1_EL1_31_0,Processor Feature Register 1 (low word)"
line.long 0x24 "APBADDR_DBG_CPU0_ID_AA64PFR1_EL1_63_32,Processor Feature Register 1 (high word)"
line.long 0x28 "APBADDR_DBG_CPU0_ID_AA64DFR1_EL1_31_0,Auxiliary Feature Register 1 (low word)"
line.long 0x2C "APBADDR_DBG_CPU0_ID_AA64DFR1_EL1_63_32,Auxiliary Feature Register 1 (high word)"
line.long 0x30 "APBADDR_DBG_CPU0_ID_AA64ISAR1_EL1_31_0,Instruction Set Attribute Register 1 (low word)"
line.long 0x34 "APBADDR_DBG_CPU0_ID_AA64ISAR1_EL1_63_32,Instruction Set Attribute Register 1 (high word)"
line.long 0x38 "APBADDR_DBG_CPU0_ID_AA64MMFR1_EL1_31_0,Memory Model Feature Register 1 (low word)"
line.long 0x3C "APBADDR_DBG_CPU0_ID_AA64MMFR1_EL1_63_32,Memory Model Feature Register 1 (high word)"
group.long 0xF00++0x03
line.long 0x00 "APBADDR_DBG_CPU0_EDITCTRL,External Debug Integration mode Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_EDITCTRL_31_1,Reserved RES0"
bitfld.long 0x00 0. "IME,Integration mode enable" "0,1"
group.long 0xFA0++0x33
line.long 0x00 "APBADDR_DBG_CPU0_DBGCLAIMSET_EL1,Debug Claim Tag Set Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_DBGCLAIMSET_EL1_31_8,Reserved RAZ/SBZ"
hexmask.long.byte 0x00 0.--7. 1. "CLAIM,Claim set bits"
line.long 0x04 "APBADDR_DBG_CPU0_DBGCLAIMCLR_EL1,Debug Claim Tag Clear Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_DBGCLAIMCLR_EL1_31_8,Reserved RAZ/SBZ"
hexmask.long.byte 0x04 0.--7. 1. "CLAIM,Claim clear bits"
line.long 0x08 "APBADDR_DBG_CPU0_EDDEVAFF0,External Debug Device Affinity Register 0"
line.long 0x0C "APBADDR_DBG_CPU0_EDDEVAFF1,External Debug Device Affinity Register 1"
line.long 0x10 "APBADDR_DBG_CPU0_EDLAR,External Debug Lock Access Register"
line.long 0x14 "APBADDR_DBG_CPU0_EDLSR,External Debug Lock Status Register"
hexmask.long 0x14 3.--31. 1. "RES0_EDLSR_31_3,Reserved RES0"
bitfld.long 0x14 2. "NTT,Not thirty-two bit access required" "0,1"
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bitfld.long 0x14 1. "SLK,Software lock status for this component" "0,1"
bitfld.long 0x14 0. "SLI,Software lock implemented" "0,1"
line.long 0x18 "APBADDR_DBG_CPU0_DBGAUTHSTATUS_EL1,Debug Authentication Status register"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_DBGAUTHSTATUS_EL1_31_8,Reserved RES0"
bitfld.long 0x18 6.--7. "SNID,Secure non-invasive debug" "0,1,2,3"
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bitfld.long 0x18 4.--5. "SID,Secure invasive debug" "0,1,2,3"
bitfld.long 0x18 2.--3. "NSNID,Non-secure non-invasive debug" "0,1,2,3"
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bitfld.long 0x18 0.--1. "NSID,Non-secure invasive debug" "0,1,2,3"
line.long 0x1C "APBADDR_DBG_CPU0_EDDEVARCH,External Debug Device Architecture Register"
hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A" "0,1"
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bitfld.long 0x1C 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
line.long 0x20 "APBADDR_DBG_CPU0_EDDEVID2,External Debug Device ID Register 2"
line.long 0x24 "APBADDR_DBG_CPU0_EDDEVID1,External Debug Device ID Register 1"
hexmask.long 0x24 4.--31. 1. "RES0_EDDEVID1_31_4,Reserved RES0"
bitfld.long 0x24 0.--3. "PCSROFFSET,This field indicates the offset applied to PC samples returned by reads of EDPCSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "APBADDR_DBG_CPU0_EDDEVID,External Debug Device ID Register 0"
bitfld.long 0x28 28.--31. "RES0_EDDEVID_31_28,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 24.--27. "AUXREGS,Indicates support for Auxiliary registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.tbyte 0x28 4.--23. 1. "RES0_EDDEVID_23_4,Reserved RES0"
bitfld.long 0x28 0.--3. "PCSAMPLE,Indicates the level of Sample-based profiling support using external debug registers 40 through 43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "APBADDR_DBG_CPU0_EDDEVTYPE,External Debug Device Type Register"
hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_EDDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x2C 4.--7. "SUB,Subtype" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 0.--3. "MAJOR,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "APBADDR_DBG_CPU0_EDPIDR4,External Debug Peripheral Identification Register 4"
hexmask.long.tbyte 0x30 8.--31. 1. "RES0_EDPIDR4_31_8,Reserved RES0"
bitfld.long 0x30 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 0.--3. "DES_2,Designer JEP106 continuation code least significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFE0++0x1F
line.long 0x00 "APBADDR_DBG_CPU0_EDPIDR0,External Debug Peripheral Identification Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_EDPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number least significant byte"
line.long 0x04 "APBADDR_DBG_CPU0_EDPIDR1,External Debug Peripheral Identification Register 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_EDPIDR1_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "DES_0,Designer least significant nibble of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--3. "PART_1,Part number most significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_DBG_CPU0_EDPIDR2,External Debug Peripheral Identification Register 2"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_EDPIDR2_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "REVISION,Part major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 3. "JEDEC,RAO" "0,1"
bitfld.long 0x08 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x0C "APBADDR_DBG_CPU0_EDPIDR3,External Debug Peripheral Identification Register 3"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_EDPIDR3_31_8,Reserved RES0"
bitfld.long 0x0C 4.--7. "REVAND,Part minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_DBG_CPU0_EDCIDR0,External Debug Component Identification Register 0"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_EDCIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x14 "APBADDR_DBG_CPU0_EDCIDR1,External Debug Component Identification Register 1"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_EDCIDR1_31_8,Reserved RES0"
bitfld.long 0x14 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_DBG_CPU0_EDCIDR2,External Debug Component Identification Register 2"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDCIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x1C "APBADDR_DBG_CPU0_EDCIDR3,External Debug Component Identification Register 3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_EDCIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_CORE0_ECC_AGGR"
base ad:0x718400
rgroup.long 0x00++0x03
line.long 0x00 "ECC_AGGR_CORE0_REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "ECC_AGGR_CORE0_REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
newline
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ECC_AGGR_CORE0_REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ECC_AGGR_CORE0_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "ECC_AGGR_CORE0_REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_CORE0_REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 26. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 25. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 24. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 23. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 22. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 21. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 20. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 19. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 18. "CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 17. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 16. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 15. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 14. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 13. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 12. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 11. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 10. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 9. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 8. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 7. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 6. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 5. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 4. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 3. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 2. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 1. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 0. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ECC_AGGR_CORE0_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 26. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 25. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 24. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 23. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 22. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 21. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 20. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 19. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 18. "CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 17. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 16. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 15. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 14. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 13. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 12. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 11. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 10. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 9. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 8. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 7. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 6. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 5. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 4. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 3. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 2. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 1. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 0. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ECC_AGGR_CORE0_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 26. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 25. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 24. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 23. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 22. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 21. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 20. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 19. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 18. "CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 17. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 16. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 15. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 14. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 13. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 12. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 11. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 10. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 9. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 8. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 7. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 6. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 5. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 4. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 3. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 2. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 0. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ECC_AGGR_CORE0_REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_CORE0_REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 26. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 25. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 24. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 23. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 22. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 21. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 20. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 19. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 18. "CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 17. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 16. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 14. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 13. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 12. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 10. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 8. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 6. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 4. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 2. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ECC_AGGR_CORE0_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 26. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 25. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 24. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 23. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 22. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 21. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 20. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 18. "CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 16. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 14. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 12. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 10. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 8. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 6. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 4. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 2. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 0. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ECC_AGGR_CORE0_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 26. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 25. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 24. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 23. "CPU0_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 22. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 21. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 20. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU0_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 18. "CPU0_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 16. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 14. "CPU0_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 12. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 10. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 8. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 6. "CPU0_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 4. "CPU0_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 2. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 0. "CPU0_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ECC_AGGR_CORE0_REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ECC_AGGR_CORE0_REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ECC_AGGR_CORE0_REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ECC_AGGR_CORE0_REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "A53SS0_CORE0_ETM"
base ad:0x730040000
group.long 0x04++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCPRGCTLR,Programming Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_TRCPRGCTLR_31_1,Reserved RES0"
bitfld.long 0x00 0. "EN,Trace unit enable bit" "0,1"
group.long 0x0C++0x07
line.long 0x00 "APBADDR_ETM_CPU0_TRCSTATR,Status Register"
hexmask.long 0x00 2.--31. 1. "RES0_TRCSTATR_31_2,Reserved RES0"
bitfld.long 0x00 1. "PMSTABLE,Programmer's model stable bit: 0 The programmer's model is not stable" "0,1"
bitfld.long 0x00 0. "IDLE,Idle status bit: 0 The trace unit is not idle" "0,1"
line.long 0x04 "APBADDR_ETM_CPU0_TRCCONFIGR,Trace Configuration Register"
hexmask.long.word 0x04 18.--31. 1. "RES0_TRCCONFIGR_31_18,Reserved RES0"
bitfld.long 0x04 17. "DV,Data value tracing bit: 0 Data value tracing is disabled" "0,1"
bitfld.long 0x04 16. "DA,Data address tracing bit: 0 Data address tracing is disabled" "0,1"
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bitfld.long 0x04 15. "RES0_TRCCONFIGR_15_15,Reserved RES0" "0,1"
bitfld.long 0x04 13.--14. "QE,Q element enable field: 00 Q elements are disabled" "0,1,2,3"
bitfld.long 0x04 12. "RS,Return stack enable bit" "0,1"
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bitfld.long 0x04 11. "TS,Global timestamp tracing bit: 0 Global timestamp tracing is disabled" "0,1"
bitfld.long 0x04 8.--10. "COND,Conditional instruction tracing bit" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "VMID,VMID tracing bit: 0 VMID tracing is disabled" "0,1"
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bitfld.long 0x04 6. "CID,Context ID tracing bit: 0 Context ID tracing is disabled" "0,1"
bitfld.long 0x04 5. "RES0_TRCCONFIGR_5_5,Reserved RES0" "0,1"
bitfld.long 0x04 4. "CCI,Cycle counting instruction trace bit: 0 Cycle counting in the instruction trace is disabled" "0,1"
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bitfld.long 0x04 3. "BB,Branch broadcast mode bit: 0 Branch broadcast mode is disabled" "0,1"
bitfld.long 0x04 1.--2. "INSTP0,Instruction P0 bit" "0,1,2,3"
bitfld.long 0x04 0. "RES1_TRCCONFIGR_0_0,Reserved RES1" "0,1"
group.long 0x18++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCAUXCTLR,Auxiliary Control Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_TRCAUXCTLR_31_8,Reserved RES0"
bitfld.long 0x00 7. "COREIFEN,Keep core interface enabled regardless of trace enable register state" "0,1"
bitfld.long 0x00 6. "RES0_TRCAUXCTLR_6_6,Reserved RES0" "0,1"
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bitfld.long 0x00 5. "AUTHNOFLUSH,Do not flush trace on de-assertion of authentication inputs" "0,1"
bitfld.long 0x00 4. "TSNODELAY,Do not delay timestamp insertion based on FIFO depth" "0,1"
bitfld.long 0x00 3. "SYNCDELAY,Delay periodic synchronization if FIFO is more than half-full" "0,1"
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bitfld.long 0x00 2. "OVFLW,Force an overflow if synchronization is not completed when second synchronization becomes due" "0,1"
bitfld.long 0x00 1. "IDLEACK,Force idle-drain acknowledge high CPU does not wait for trace to drain before entering WFX state" "0,1"
bitfld.long 0x00 0. "AFREADY,Always respond to AFREADY immediately" "0,1"
group.long 0x20++0x07
line.long 0x00 "APBADDR_ETM_CPU0_TRCEVENTCTL0R,Event Control 0 Register"
bitfld.long 0x00 31. "TYPE3,Selects the resource type for trace event 3" "0,1"
bitfld.long 0x00 28.--30. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--27. "SEL3,Selects the resource number based on the value of TYPE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "TYPE2,Selects the resource type for trace event 2" "0,1"
bitfld.long 0x00 20.--22. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "SEL2,Selects the resource number based on the value of TYPE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "TYPE1,Selects the resource type for trace event 1" "0,1"
bitfld.long 0x00 12.--14. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "SEL1,Selects the resource number based on the value of TYPE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "TYPE0,Selects the resource type for trace event 0" "0,1"
bitfld.long 0x00 4.--6. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "SEL0,Selects the resource number based on the value of TYPE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_ETM_CPU0_TRCEVENTCTL1R,Event Control 1 Register"
hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 12. "LPOVERRIDE,Low power state behavior override" "0,1"
bitfld.long 0x04 11. "ATB,ATB trigger enable" "0,1"
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hexmask.long.byte 0x04 4.--10. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "EN,One bit per event to enable generation of an event element in the instruction trace stream when the selected event occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x17
line.long 0x00 "APBADDR_ETM_CPU0_TRCSTALLCTLR,Stall Control Register"
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 8. "ISTALL,Controls if the trace unit can stall the processor when the instruction trace buffer space is less than LEVEL" "0,1"
bitfld.long 0x00 4.--7. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 2.--3. "LEVEL,The field can support 4 monotonic levels from 0b00 to 0b11" "0,1,2,3"
bitfld.long 0x00 0.--1. "RESERVED,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_ETM_CPU0_TRCTSCTLR,Global Timestamp Control Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_TRCTSCTLR_31_8,Reserved RES0"
hexmask.long.byte 0x04 0.--7. 1. "EVENT,An event selector"
line.long 0x08 "APBADDR_ETM_CPU0_TRCSYNCPR,Synchronization Period Register"
hexmask.long 0x08 5.--31. 1. "RES0_TRCSYNCPR_31_5,Reserved RES0"
bitfld.long 0x08 0.--4. "PERIOD,Controls how many bytes of trace the sum of instruction and data that a trace unit can generate before a periodic trace synchronization request occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "APBADDR_ETM_CPU0_TRCCCCTLR,Cycle Count Control Register"
hexmask.long.tbyte 0x0C 12.--31. 1. "RES0_TRCCCCTLR_31_12,Reserved RES0"
hexmask.long.word 0x0C 0.--11. 1. "THRESHOLD,Sets the threshold value for instruction trace cycle counting.The minimum threshold value that can be programmed into THRESHOLD is given in TRCIDR3.CCITMIN.Writing a value of zero might cause UNPREDICTABLE behaviour"
line.long 0x10 "APBADDR_ETM_CPU0_TRCBBCTLR,Branch Broadcast Control Register"
hexmask.long.tbyte 0x10 9.--31. 1. "RES0_TRCBBCTLR_31_9,Reserved RES0"
bitfld.long 0x10 8. "MODE,Mode bit: 0 Exclude mode" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "RANGE,Address range field"
line.long 0x14 "APBADDR_ETM_CPU0_TRCTRACEIDR,Trace ID Register"
hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x14 0.--6. 1. "TRACEID,Trace ID value"
group.long 0x80++0x0B
line.long 0x00 "APBADDR_ETM_CPU0_TRCVICTLR,ViewInst Main Control Register"
hexmask.long.byte 0x00 24.--31. 1. "RES0_TRCVICTLR_31_24,Reserved RES0"
bitfld.long 0x00 20.--23. "EXLEVEL_NS,In Non-secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "EXLEVEL_S,In Secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "RES0_TRCVICTLR_15_12,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "TRCERR,If TRCIDR3.TRCERR==1 this bit controls whether a trace unit must trace a system error exception: 0 The trace unit does not trace a system error exception unless it traces the exception or instruction immediately prior to the system error exception" "0,1"
bitfld.long 0x00 10. "TRCRESET,Controls whether a trace unit must trace a Reset exception: 0 The trace unit does not trace a Reset exception unless it traces the exception or instruction immediately prior to the Reset exception" "0,1"
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bitfld.long 0x00 9. "SSSTATUS,IF TRCIDR4.NUMACPAIRS>0 or TRCIDR.NUMPC>0 this bit returns the status of the start-stop logic: 0 The start-stop logic is in the stopped state" "0,1"
bitfld.long 0x00 8. "RES0_TRCVICTLR_8_8,Reserved RES0" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "EVENT,An event selector"
line.long 0x04 "APBADDR_ETM_CPU0_TRCVIIECTLR,ViewInst Include-Exclude Control Register"
hexmask.long.byte 0x04 24.--31. 1. "RES0_TRCVIIECTLR_31_24,Reserved RES0"
hexmask.long.byte 0x04 16.--23. 1. "EXCLUDE,0 1 The implemented width of the field n is IMPLEMENTATION DEFINED and is set by the value of TRCIDR4.NUMACPAIRS"
hexmask.long.byte 0x04 8.--15. 1. "RES0_TRCVIIECTLR_15_8,Reserved RES0"
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hexmask.long.byte 0x04 0.--7. 1. "INCLUDE,Include range field"
line.long 0x08 "APBADDR_ETM_CPU0_TRCVISSCTLR,ViewInst Start-Stop Control Register"
hexmask.long.word 0x08 16.--31. 1. "STOP,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of stopping trace"
hexmask.long.word 0x08 0.--15. 1. "START,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of starting trace"
group.long 0x100++0x0B
line.long 0x00 "APBADDR_ETM_CPU0_TRCSEQEVR0,Sequencer State Transition Control Registers 0"
hexmask.long.word 0x00 16.--31. 1. "RES0_TRCSEQEVR0_31_16,Reserved RES0"
hexmask.long.byte 0x00 8.--15. 1. "B_N,Backward field"
hexmask.long.byte 0x00 0.--7. 1. "F_N,Forward field"
line.long 0x04 "APBADDR_ETM_CPU0_TRCSEQEVR1,Sequencer State Transition Control Registers 1"
hexmask.long.word 0x04 16.--31. 1. "RES0_TRCSEQEVR1_31_16,Reserved RES0"
hexmask.long.byte 0x04 8.--15. 1. "B_N,Backward field"
hexmask.long.byte 0x04 0.--7. 1. "F_N,Forward field"
line.long 0x08 "APBADDR_ETM_CPU0_TRCSEQEVR2,Sequencer State Transition Control Registers 2"
hexmask.long.word 0x08 16.--31. 1. "RES0_TRCSEQEVR2_31_16,Reserved RES0"
hexmask.long.byte 0x08 8.--15. 1. "B_N,Backward field"
hexmask.long.byte 0x08 0.--7. 1. "F_N,Forward field"
group.long 0x118++0x0B
line.long 0x00 "APBADDR_ETM_CPU0_TRCSEQRSTEVR,Sequencer Reset Control Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_TRCSEQRSTEVR_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "RST,Contains an event number"
line.long 0x04 "APBADDR_ETM_CPU0_TRCSEQSTR,Sequencer State Register"
hexmask.long 0x04 2.--31. 1. "RES0_TRCSEQSTR_31_2,Reserved RES0"
bitfld.long 0x04 0.--1. "STATE,Sets or returns the state of the sequencer: 00 State 0" "0,1,2,3"
line.long 0x08 "APBADDR_ETM_CPU0_TRCEXTINSELR,External Input Select Register"
bitfld.long 0x08 29.--31. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "SEL3,Selects an event from the external input bus for External Input Resource 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 21.--23. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 16.--20. "SEL2,Selects an event from the external input bus for External Input Resource 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 13.--15. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 8.--12. "SEL1,Selects an event from the external input bus for External Input Resource 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 5.--7. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 0.--4. "SEL0,Selects an event from the external input bus for External Input Resource 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x140++0x07
line.long 0x00 "APBADDR_ETM_CPU0_TRCCNTRLDVR0,Counter Reload Value Registers 0"
hexmask.long.word 0x00 16.--31. 1. "RES0_TRCCNTRLDVR0_31_16,Reserved RES0"
hexmask.long.word 0x00 0.--15. 1. "VALUE_N,Contains the reload value for counter <n>"
line.long 0x04 "APBADDR_ETM_CPU0_TRCCNTRLDVR1,Counter Reload Value Registers 1"
hexmask.long.word 0x04 16.--31. 1. "RES0_TRCCNTRLDVR1_31_16,Reserved RES0"
hexmask.long.word 0x04 0.--15. 1. "VALUE_N,Contains the reload value for counter <n>"
group.long 0x150++0x07
line.long 0x00 "APBADDR_ETM_CPU0_TRCCNTCTLR0,Counter Control Register 0"
hexmask.long.word 0x00 18.--31. 1. "RES0_TRCCNTCTLR0_31_18,Reserved RES0"
bitfld.long 0x00 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter <n> decrements when a reload event occurs for counter <n-1>: 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit is RES0" "0,1"
bitfld.long 0x00 16. "RLDSELF_N,Controls whether a reload event occurs for counter <n> when counter <n> reaches zero: 0 The trace unit does not generate a reload event" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter <n>"
hexmask.long.byte 0x00 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter <n> to decrement"
line.long 0x04 "APBADDR_ETM_CPU0_TRCCNTCTLR1,Counter Control Register 1"
hexmask.long.word 0x04 18.--31. 1. "RES0_TRCCNTCTLR1_31_18,Reserved RES0"
bitfld.long 0x04 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter <n> decrements when a reload event occurs for counter <n-1>: 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit is RES0" "0,1"
bitfld.long 0x04 16. "RLDSELF_N,Controls whether a reload event occurs for counter <n> when counter <n> reaches zero: 0 The trace unit does not generate a reload event" "0,1"
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hexmask.long.byte 0x04 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter <n>"
hexmask.long.byte 0x04 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter <n> to decrement"
group.long 0x160++0x07
line.long 0x00 "APBADDR_ETM_CPU0_TRCCNTVR0,Counter Value Registers 0"
hexmask.long.word 0x00 16.--31. 1. "RES0_TRCCNTVR0_31_16,Reserved RES0"
hexmask.long.word 0x00 0.--15. 1. "VALUE_N,Contains the count value of counter <n>"
line.long 0x04 "APBADDR_ETM_CPU0_TRCCNTVR1,Counter Value Registers 1"
hexmask.long.word 0x04 16.--31. 1. "RES0_TRCCNTVR1_31_16,Reserved RES0"
hexmask.long.word 0x04 0.--15. 1. "VALUE_N,Contains the count value of counter <n>"
group.long 0x180++0x17
line.long 0x00 "APBADDR_ETM_CPU0_TRCIDR8,ID Register 8"
line.long 0x04 "APBADDR_ETM_CPU0_TRCIDR9,ID Register 9"
line.long 0x08 "APBADDR_ETM_CPU0_TRCIDR10,ID Register 10"
line.long 0x0C "APBADDR_ETM_CPU0_TRCIDR11,ID Register 11"
line.long 0x10 "APBADDR_ETM_CPU0_TRCIDR12,ID Register 12"
line.long 0x14 "APBADDR_ETM_CPU0_TRCIDR13,ID Register 13"
group.long 0x1C0++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCIMSPEC0,Implementation Specific Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_TRCIMSPEC0_31_8,Reserved RES0"
bitfld.long 0x00 4.--7. "EN,If SUPPORT is not 0b0000 controls whether the IMPLEMENTATION DEFINED features are enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "SUPPORT,Indicates whether the implementation supports IMPLEMENTATION DEFINED features" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1E0++0x17
line.long 0x00 "APBADDR_ETM_CPU0_TRCIDR0,ID Register 0"
bitfld.long 0x00 30.--31. "RES0_TRCIDR0_31_30,Reserved RES0" "0,1,2,3"
bitfld.long 0x00 29. "COMMOPT,Conditional instruction tracing support bit" "0,1"
bitfld.long 0x00 24.--28. "TSSIZE,Global timestamp size field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 17.--23. 1. "RES0_TRCIDR0_23_17,Reserved RES0"
bitfld.long 0x00 15.--16. "QSUPP,Q element support field" "0,1,2,3"
bitfld.long 0x00 14. "QFILT,Q element filtering support field" "0,1"
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bitfld.long 0x00 12.--13. "CONDTYPE,Conditional tracing field" "0,1,2,3"
bitfld.long 0x00 10.--11. "NUMEVENT,Number of events field" "0,1,2,3"
bitfld.long 0x00 9. "RETSTACK,Return stack bit" "0,1"
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bitfld.long 0x00 8. "RES0_TRCIDR0_8_8,Reserved RES0" "0,1"
bitfld.long 0x00 7. "TRCCCI,Cycle counting instruction bit" "0,1"
bitfld.long 0x00 6. "TRCCOND,Conditional instruction tracing support bit" "0,1"
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bitfld.long 0x00 5. "TRCBB,Branch broadcast tracing support bit" "0,1"
bitfld.long 0x00 3.--4. "TRCDATA,Conditional tracing field" "0,1,2,3"
bitfld.long 0x00 1.--2. "INSTP0,P0 tracing support field" "0,1,2,3"
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bitfld.long 0x00 0. "RES0_TRCIDR0_0_0,Reserved RES0" "0,1"
line.long 0x04 "APBADDR_ETM_CPU0_TRCIDR1,ID Register 1"
hexmask.long.byte 0x04 24.--31. 1. "DESIGNER,Indicates which company designed the trace unit"
hexmask.long.byte 0x04 16.--23. 1. "RES0_TRCIDR1_23_16,Reserved RES0"
bitfld.long 0x04 12.--15. "RES1_TRCIDR1_15_12,Reserved RES1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 8.--11. "TRCARCHMAJ,Indicates the major version of the ETM architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 4.--7. "TRCARCHMIN,Indicates the minor version of the ETM architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "REVISION,Returns an IMPLEMENTATION DEFINED value that identifies the revision of the trace registers and the OS Save and Restore registers.ARM recommends:That the initial implementation sets REVISION==0x0 and the field then increments for any subsequent.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_ETM_CPU0_TRCIDR2,ID Register 2"
bitfld.long 0x08 29.--31. "RES0_TRCIDR2_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 25.--28. "CCSIZE,Indicates the size of the cycle counter in bits minus 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 20.--24. "DVSIZE,Indicates the data value size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 15.--19. "DASIZE,Indicates the data address size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 10.--14. "VMIDSIZE,Indicates the VMID size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 5.--9. "CIDSIZE,Indicates the Context ID size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 0.--4. "IASIZE,Indicates the instruction address size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "APBADDR_ETM_CPU0_TRCIDR3,ID Register 3"
bitfld.long 0x0C 31. "NOOVERFLOW,Indicates if TRCSTALLCTLR.NOOVERFLOW is supported: 0 TRCSTALLCTLR.NOOVERFLOW is not supported or STALLCTL==0" "0,1"
bitfld.long 0x0C 28.--30. "NUMPROC,Indicates the number of processors available for tracing" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 27. "SYSSTALL,Indicates if the implementation can support stall control: 0 The system does not support stall control of the processor" "0,1"
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bitfld.long 0x0C 26. "STALLCTL,Indicates if TRCSTALLCTLR is supported: 0 TRCSTALLCTLR is not supported" "0,1"
bitfld.long 0x0C 25. "SYNCPR,Indicates if an implementation has a fixed synchronization period: 0 TRCSYNCPR is read-write so software can change the synchronization period" "0,1"
bitfld.long 0x0C 24. "TRCERR,Indicates if TRCVICTLR.TRCERR is supported: 0 TRCVICTLR.TRCERR is not supported 1 TRCVICTLR.TRCERR is supported" "0,1"
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bitfld.long 0x0C 20.--23. "EXLEVEL_NS,In Non-secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Non-secure state exception level n is not supported so the corresponding bits in TRCACATRn.EXLEVEL_NS and.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 16.--19. "EXLEVEL_S,In Secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Secure state exception level n is not supported so the corresponding bits in TRCACATRn.EXLEVEL_S and TRCVICTLR.EXLEVEL_S.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 12.--15. "RES0_TRCIDR3_15_12,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x0C 0.--11. 1. "CCITMIN,Indicates the minimum value that can be programmed in TRCCCCTLR.THRESHOLD.When cycle counting in the instruction trace is supported that is TRCIDR0.TRCCCI==1 then the minimum value of this field is 0x001 otherwise it is 0x000"
line.long 0x10 "APBADDR_ETM_CPU0_TRCIDR4,ID Register 4"
bitfld.long 0x10 28.--31. "NUMVMIDC,Indicates the number of VMID comparators that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 24.--27. "NUMCIDC,Indicates the number of Context ID comparators that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 20.--23. "NUMSSCC,Indicates the number of single-shot comparator controls that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "NUMRSPAIR,Indicates the number of resource selection pairs that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 12.--15. "NUMPC,Indicates the number of processor comparator inputs that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 9.--11. "RES0_TRCIDR4_11_9,Reserved RES0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 8. "SUPPDAC,Indicates if the implementation can support data address comparisons: 0 The implementation does not support data address comparisons" "0,1"
bitfld.long 0x10 4.--7. "NUMDVC,Indicates the number of data value comparators that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 0.--3. "NUMACPAIRS,Indicates the number of address comparator pairs that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_ETM_CPU0_TRCIDR5,ID Register 5"
bitfld.long 0x14 31. "REDFUNCNTR,Indicates if the reduced function counter is implemented: 0 The reduced function counter is not supported" "0,1"
bitfld.long 0x14 28.--30. "NUMCNTR,Indicates the number of counters that are available for tracing" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 25.--27. "NUMSEQSTATE,Indicates the number of sequencer states that are implemented" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 24. "RES0_TRCIDR5_24_24,Reserved RES0" "0,1"
bitfld.long 0x14 23. "LPOVERRIDE,Indicates if the implementation can support low-power state override: 0 The implementation does not support low-power state override" "0,1"
bitfld.long 0x14 22. "ATBTRIG,Indicates if the implementation can support ATB triggers: 0 The implementation does not support ATB triggers" "0,1"
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bitfld.long 0x14 16.--21. "TRACEIDSIZE,Indicates the trace ID width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 12.--15. "RES0_TRCIDR5_15_12,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 9.--11. "NUMEXTINSEL,Indicates how many external input select resources are implemented" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x14 0.--8. 1. "NUMEXTIN,Indicates how many external inputs are implemented"
group.long 0x208++0x37
line.long 0x00 "APBADDR_ETM_CPU0_TRCRSCTLR2,Resource Selection Control Registers 2"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCRSCTLR2_31_22,Reserved RES0"
bitfld.long 0x00 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x00 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x00 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x04 "APBADDR_ETM_CPU0_TRCRSCTLR3,Resource Selection Control Registers 3"
hexmask.long.word 0x04 22.--31. 1. "RES0_TRCRSCTLR3_31_22,Reserved RES0"
bitfld.long 0x04 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x04 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x04 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x08 "APBADDR_ETM_CPU0_TRCRSCTLR4,Resource Selection Control Registers 4"
hexmask.long.word 0x08 22.--31. 1. "RES0_TRCRSCTLR4_31_22,Reserved RES0"
bitfld.long 0x08 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x08 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x08 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x08 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x0C "APBADDR_ETM_CPU0_TRCRSCTLR5,Resource Selection Control Registers 5"
hexmask.long.word 0x0C 22.--31. 1. "RES0_TRCRSCTLR5_31_22,Reserved RES0"
bitfld.long 0x0C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x0C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x0C 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x0C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x10 "APBADDR_ETM_CPU0_TRCRSCTLR6,Resource Selection Control Registers 6"
hexmask.long.word 0x10 22.--31. 1. "RES0_TRCRSCTLR6_31_22,Reserved RES0"
bitfld.long 0x10 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x10 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x10 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x10 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x14 "APBADDR_ETM_CPU0_TRCRSCTLR7,Resource Selection Control Registers 7"
hexmask.long.word 0x14 22.--31. 1. "RES0_TRCRSCTLR7_31_22,Reserved RES0"
bitfld.long 0x14 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x14 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x14 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x14 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x18 "APBADDR_ETM_CPU0_TRCRSCTLR8,Resource Selection Control Registers 8"
hexmask.long.word 0x18 22.--31. 1. "RES0_TRCRSCTLR8_31_22,Reserved RES0"
bitfld.long 0x18 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x18 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x18 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x1C "APBADDR_ETM_CPU0_TRCRSCTLR9,Resource Selection Control Registers 9"
hexmask.long.word 0x1C 22.--31. 1. "RES0_TRCRSCTLR9_31_22,Reserved RES0"
bitfld.long 0x1C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x1C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x1C 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x1C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x20 "APBADDR_ETM_CPU0_TRCRSCTLR10,Resource Selection Control Registers 10"
hexmask.long.word 0x20 22.--31. 1. "RES0_TRCRSCTLR10_31_22,Reserved RES0"
bitfld.long 0x20 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x20 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x20 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x20 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x24 "APBADDR_ETM_CPU0_TRCRSCTLR11,Resource Selection Control Registers 11"
hexmask.long.word 0x24 22.--31. 1. "RES0_TRCRSCTLR11_31_22,Reserved RES0"
bitfld.long 0x24 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x24 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x24 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x24 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x28 "APBADDR_ETM_CPU0_TRCRSCTLR12,Resource Selection Control Registers 12"
hexmask.long.word 0x28 22.--31. 1. "RES0_TRCRSCTLR12_31_22,Reserved RES0"
bitfld.long 0x28 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x28 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x28 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x28 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x2C "APBADDR_ETM_CPU0_TRCRSCTLR13,Resource Selection Control Registers 13"
hexmask.long.word 0x2C 22.--31. 1. "RES0_TRCRSCTLR13_31_22,Reserved RES0"
bitfld.long 0x2C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x2C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x2C 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x2C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x30 "APBADDR_ETM_CPU0_TRCRSCTLR14,Resource Selection Control Registers 14"
hexmask.long.word 0x30 22.--31. 1. "RES0_TRCRSCTLR14_31_22,Reserved RES0"
bitfld.long 0x30 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x30 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x30 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x30 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x34 "APBADDR_ETM_CPU0_TRCRSCTLR15,Resource Selection Control Registers 15"
hexmask.long.word 0x34 22.--31. 1. "RES0_TRCRSCTLR15_31_22,Reserved RES0"
bitfld.long 0x34 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x34 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x34 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x34 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
group.long 0x280++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCSSCCR0,Single-Shot Comparator Control Register 0"
hexmask.long.byte 0x00 25.--31. 1. "RES0_TRCSSCCR0_31_25,Reserved RES0"
bitfld.long 0x00 24. "RST,Controls whether the single-shot comparator resource is reset when it fires" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "ARC,Selects one or more address range comparators for single-shot control.Each bit represents an address range comparator pair so bit[n-16] controls the selection of address range comparator pair n-16"
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hexmask.long.word 0x00 0.--15. 1. "SAC,Selects one or more single address comparators for single-shot control.Each bit represents a single address comparator so bit[n] controls the selection of single address comparator n"
group.long 0x2A0++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCSSCSR0,Single-Shot Comparator Status Register 0"
bitfld.long 0x00 31. "STATUS,Single-shot status bit" "0,1"
hexmask.long 0x00 3.--30. 1. "RES0_TRCSSCSR0_30_3,Reserved RES0"
bitfld.long 0x00 2. "DV,Data value comparator support bit" "0,1"
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bitfld.long 0x00 1. "DA,Data address comparator support bit" "0,1"
bitfld.long 0x00 0. "INST,Instruction address comparator support bit" "0,1"
group.long 0x300++0x07
line.long 0x00 "APBADDR_ETM_CPU0_TRCOSLAR,OS Lock Access Register"
hexmask.long 0x00 1.--31. 1. "RES0_TRCOSLAR_31_1,Reserved RES0"
bitfld.long 0x00 0. "LOCK,OS Lock control bit: 0 Unlocks the OS Lock" "0,1"
line.long 0x04 "APBADDR_ETM_CPU0_TRCOSLSR,OS Lock Status Register"
hexmask.long 0x04 4.--31. 1. "RES0_TRCOSLSR_31_4,Reserved RES0"
bitfld.long 0x04 3. "PRESENT,Indicates whether the OS Lock is implemented.This bit is RES1 which indicates that the OS Lock is always implemented" "0,1"
bitfld.long 0x04 2. "BIT32,This bit is RES0 which indicates that software must perform a 32-bit write to update the TRCOSLAR" "0,1"
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bitfld.long 0x04 1. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked" "0,1"
bitfld.long 0x04 0. "RES0_TRCOSLSR_0_0,Reserved RES0" "0,1"
group.long 0x310++0x07
line.long 0x00 "APBADDR_ETM_CPU0_TRCPDCR,Power Down Control Register"
hexmask.long 0x00 4.--31. 1. "RES0_TRCPDCR_31_4,Reserved RES0"
bitfld.long 0x00 3. "PU,Powerup request bit: 0 The system can remove power from the trace unit" "0,1"
bitfld.long 0x00 0.--2. "RES0_TRCPDCR_2_0,Reserved RES0" "0,1,2,3,4,5,6,7"
line.long 0x04 "APBADDR_ETM_CPU0_TRCPDSR,Power Down Status Register"
hexmask.long 0x04 6.--31. 1. "RES0_TRCPDSR_31_6,Reserved RES0"
bitfld.long 0x04 5. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked" "0,1"
bitfld.long 0x04 2.--4. "RES0_TRCPDSR_4_2,Reserved RES0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 1. "STICKYPD,Sticky powerdown status bit" "0,1"
bitfld.long 0x04 0. "POWER,Power status bit: 0 The trace unit core power domain is not powered" "0,1"
group.long 0x400++0x3F
line.long 0x00 "APBADDR_ETM_CPU0_TRCACVR0_31_0,Address Comparator Value Registers 0 (low word)"
line.long 0x04 "APBADDR_ETM_CPU0_TRCACVR0_63_32,Address Comparator Value Registers 0 (high word)"
line.long 0x08 "APBADDR_ETM_CPU0_TRCACVR1_31_0,Address Comparator Value Registers 1 (low word)"
line.long 0x0C "APBADDR_ETM_CPU0_TRCACVR1_63_32,Address Comparator Value Registers 1 (high word)"
line.long 0x10 "APBADDR_ETM_CPU0_TRCACVR2_31_0,Address Comparator Value Registers 2 (low word)"
line.long 0x14 "APBADDR_ETM_CPU0_TRCACVR2_63_32,Address Comparator Value Registers 2 (high word)"
line.long 0x18 "APBADDR_ETM_CPU0_TRCACVR3_31_0,Address Comparator Value Registers 3 (low word)"
line.long 0x1C "APBADDR_ETM_CPU0_TRCACVR3_63_32,Address Comparator Value Registers 3 (high word)"
line.long 0x20 "APBADDR_ETM_CPU0_TRCACVR4_31_0,Address Comparator Value Registers 4 (low word)"
line.long 0x24 "APBADDR_ETM_CPU0_TRCACVR4_63_32,Address Comparator Value Registers 4 (high word)"
line.long 0x28 "APBADDR_ETM_CPU0_TRCACVR5_31_0,Address Comparator Value Registers 5 (low word)"
line.long 0x2C "APBADDR_ETM_CPU0_TRCACVR5_63_32,Address Comparator Value Registers 5 (high word)"
line.long 0x30 "APBADDR_ETM_CPU0_TRCACVR6_31_0,Address Comparator Value Registers 6 (low word)"
line.long 0x34 "APBADDR_ETM_CPU0_TRCACVR6_63_32,Address Comparator Value Registers 6 (high word)"
line.long 0x38 "APBADDR_ETM_CPU0_TRCACVR7_31_0,Address Comparator Value Registers 7 (low word)"
line.long 0x3C "APBADDR_ETM_CPU0_TRCACVR7_63_32,Address Comparator Value Registers 7 (high word)"
group.long 0x480++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCACATR0,Address Comparator Access Type Registers 0"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR0_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
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bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR0_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x488++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCACATR1,Address Comparator Access Type Registers 1"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR1_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
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bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR1_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x490++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCACATR2,Address Comparator Access Type Registers 2"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR2_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
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bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR2_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x498++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCACATR3,Address Comparator Access Type Registers 3"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR3_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
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bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR3_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4A0++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCACATR4,Address Comparator Access Type Registers 4"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR4_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
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bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR4_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4A8++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCACATR5,Address Comparator Access Type Registers 5"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR5_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
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bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR5_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4B0++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCACATR6,Address Comparator Access Type Registers 6"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR6_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
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bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR6_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4B8++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCACATR7,Address Comparator Access Type Registers 7"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR7_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
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bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR7_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x600++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCCIDCVR0,Context ID Comparator Value Register 0"
group.long 0x640++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCVMIDCVR0,VMID Comparator Value Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "VALUE,Contains a VMID value"
group.long 0x680++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCCIDCCTLR0,Context ID Comparator Control Register 0"
group.long 0xEE4++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCITATBIDR,Integration ATB Identification Register"
hexmask.long 0x00 7.--31. 1. "RES0_TRCITATBIDR_31_7,Reserved RES0"
hexmask.long.byte 0x00 0.--6. 1. "ID,Drives the ATIDMn[6:0] output pins"
group.long 0xEEC++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCITIDATAR,Integration Instruction ATB Data Register"
hexmask.long 0x00 5.--31. 1. "RES0_TRCITIDATAR_31_5,Reserved RES0"
bitfld.long 0x00 4. "ATDATAM_31,Drives the ATDATAM[31] output" "0,1"
bitfld.long 0x00 3. "ATDATAM_23,Drives the ATDATAM[23] output" "0,1"
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bitfld.long 0x00 2. "ATDATAM_15,Drives the ATDATAM[15] output" "0,1"
bitfld.long 0x00 1. "ATDATAM_7,Drives the ATDATAM[7] output" "0,1"
bitfld.long 0x00 0. "ATDATAM_0,Drives the ATDATAM[0] output" "0,1"
group.long 0xEF4++0x03
line.long 0x00 "APBADDR_ETM_CPU0_TRCITIATBINR,Integration Instruction ATB In Register"
hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved"
bitfld.long 0x00 1. "AFVALIDM,Returns the value of the AFVALIDMn input pin" "0,1"
bitfld.long 0x00 0. "ATREADYM,Returns the value of the ATREADYMn input pin" "0,1"
group.long 0xEFC++0x07
line.long 0x00 "APBADDR_ETM_CPU0_TRCITIATBOUTR,Integration Instruction ATB Out Register"
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
bitfld.long 0x00 8.--9. "BYTES,Drives the ATBYTESMn[1:0] output pins" "0,1,2,3"
bitfld.long 0x00 2.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 1. "AFREADY,Drives the AFREADYMn output pin" "0,1"
bitfld.long 0x00 0. "ATVALID,Drives the ATVALIDMn output pin" "0,1"
line.long 0x04 "APBADDR_ETM_CPU0_TRCITCTRL,Integration Mode Control Register"
hexmask.long 0x04 1.--31. 1. "RES0_TRCITCTRL_31_1,Reserved RES0"
bitfld.long 0x04 0. "ITEN,Integration mode enable bit: 0 The trace unit is not in integration mode" "0,1"
group.long 0xFA0++0x1F
line.long 0x00 "APBADDR_ETM_CPU0_TRCCLAIMSET,Claim Tag Set Register"
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--3. "SET,Sets bits in the claim tag and determines the number of claim tag bits implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_ETM_CPU0_TRCCLAIMCLR,Claim Tag Clear Register"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "CLR,Clears bits in the claim tag and determines the current value of the claim tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_ETM_CPU0_TRCDEVAFF0,Device Affinity Register 0"
line.long 0x0C "APBADDR_ETM_CPU0_TRCDEVAFF1,Device Affinity Register 1"
line.long 0x10 "APBADDR_ETM_CPU0_TRCLAR,Software Lock Access Register"
line.long 0x14 "APBADDR_ETM_CPU0_TRCLSR,Software Lock Status Register"
hexmask.long 0x14 3.--31. 1. "RES0_TRCLSR_31_3,Reserved RES0"
bitfld.long 0x14 2. "NTT,Not thirty-two bit access required" "0,1"
bitfld.long 0x14 1. "SLK,Software lock status for this component" "0,1"
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bitfld.long 0x14 0. "SLI,Software lock implemented" "0,1"
line.long 0x18 "APBADDR_ETM_CPU0_TRCAUTHSTATUS,Authentication Status Register"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCAUTHSTATUS_31_8,Reserved RES0"
bitfld.long 0x18 6.--7. "SNID,Indicates whether the system enables the trace unit to support Secure non-invasive debug: 00 The trace unit does not implement support for Secure non-invasive debug" "0,1,2,3"
bitfld.long 0x18 4.--5. "SID,Indicates whether the trace unit supports Secure invasive debug: 00 The trace unit does not support Secure invasive debug" "0,1,2,3"
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bitfld.long 0x18 2.--3. "NSNID,Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: 00 The trace unit does not implement support for Non-secure non-invasive debug" "0,1,2,3"
bitfld.long 0x18 0.--1. "NSID,Indicates whether the trace unit supports Non-secure invasive debug: 00 The trace unit does not support Non-secure invasive debug" "0,1,2,3"
line.long 0x1C "APBADDR_ETM_CPU0_TRCDEVARCH,Device Architecture Register"
hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is RAO" "0,1"
bitfld.long 0x1C 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
group.long 0xFC8++0x37
line.long 0x00 "APBADDR_ETM_CPU0_TRCDEVID,Device ID Register"
line.long 0x04 "APBADDR_ETM_CPU0_TRCDEVTYPE,Device Type Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_TRCDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "SUB,Returns 0x1 to indicate that the ETM generates processor trace.All other values are reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "MAIN,Returns 0x3 to indicate that the ETM is a trace source.All other values are reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_ETM_CPU0_TRCPIDR4,Peripheral Identification Register 4"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_TRCPIDR4_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--3. "DES_2,Designer JEP106 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_ETM_CPU0_TRCPIDR5,Peripheral Identification Register 5"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_TRCPIDR5_31_8,Reserved RES0"
hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,RES0 reserved for future use"
line.long 0x10 "APBADDR_ETM_CPU0_TRCPIDR6,Peripheral Identification Register 6"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_TRCPIDR6_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "RESERVED,RES0 reserved for future use"
line.long 0x14 "APBADDR_ETM_CPU0_TRCPIDR7,Peripheral Identification Register 7"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_TRCPIDR7_31_8,Reserved RES0"
hexmask.long.byte 0x14 0.--7. 1. "RESERVED,RES0 reserved for future use"
line.long 0x18 "APBADDR_ETM_CPU0_TRCPIDR0,Peripheral Identification Register 0"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PART_0,Part number bits[7:0]"
line.long 0x1C "APBADDR_ETM_CPU0_TRCPIDR1,Peripheral Identification Register 1"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_TRCPIDR1_31_8,Reserved RES0"
bitfld.long 0x1C 4.--7. "DES_0,Designer bits[3:0] of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "PART_1,Part number bits[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "APBADDR_ETM_CPU0_TRCPIDR2,Peripheral Identification Register 2"
hexmask.long.tbyte 0x20 8.--31. 1. "RES0_TRCPIDR2_31_8,Reserved RES0"
bitfld.long 0x20 4.--7. "REVISION,The IMPLEMENTATION DEFINED revision number for the ETM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 3. "JEDEC,RAO" "0,1"
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bitfld.long 0x20 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x24 "APBADDR_ETM_CPU0_TRCPIDR3,Peripheral Identification Register 3"
hexmask.long.tbyte 0x24 8.--31. 1. "RES0_TRCPIDR3_31_8,Reserved RES0"
bitfld.long 0x24 4.--7. "REVAND,The IMPLEMENTATION DEFINED manufacturing revision number for the implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "APBADDR_ETM_CPU0_TRCCIDR0,Component Identification Register 0"
hexmask.long.tbyte 0x28 8.--31. 1. "RES0_TRCCIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x28 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x2C "APBADDR_ETM_CPU0_TRCCIDR1,Component Identification Register 1"
hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_TRCCIDR1_31_8,Reserved RES0"
bitfld.long 0x2C 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "APBADDR_ETM_CPU0_TRCCIDR2,Component Identification Register 2"
hexmask.long.tbyte 0x30 8.--31. 1. "RES0_TRCCIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x30 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x34 "APBADDR_ETM_CPU0_TRCCIDR3,Component Identification Register 3"
hexmask.long.tbyte 0x34 8.--31. 1. "RES0_TRCCIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x34 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_CORE0_PMU"
base ad:0x730030000
group.long 0x00++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMEVCNTR0_EL0,Performance Monitors Event Count Register 0"
group.long 0x08++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMEVCNTR1_EL0,Performance Monitors Event Count Register 1"
group.long 0x10++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMEVCNTR2_EL0,Performance Monitors Event Count Register 2"
group.long 0x18++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMEVCNTR3_EL0,Performance Monitors Event Count Register 3"
group.long 0x20++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMEVCNTR4_EL0,Performance Monitors Event Count Register 4"
group.long 0x28++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMEVCNTR5_EL0,Performance Monitors Event Count Register 5"
group.long 0xF8++0x07
line.long 0x00 "APBADDR_PMU_CPU0_PMCCNTR_EL0_31_0,Performance Monitors Cycle Counter (low word)"
line.long 0x04 "APBADDR_PMU_CPU0_PMCCNTR_EL0_63_32,Performance Monitors Cycle Counter (high word)"
group.long 0x400++0x17
line.long 0x00 "APBADDR_PMU_CPU0_PMEVTYPER0_EL0,Performance Monitors Event Type Register 0"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x00 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x00 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x00 10.--25. 1. "RES0_PMEVTYPER0_EL0_25_10,Reserved RES0"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x04 "APBADDR_PMU_CPU0_PMEVTYPER1_EL0,Performance Monitors Event Type Register 1"
bitfld.long 0x04 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x04 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x04 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x04 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x04 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x04 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x04 10.--25. 1. "RES0_PMEVTYPER1_EL0_25_10,Reserved RES0"
hexmask.long.word 0x04 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x08 "APBADDR_PMU_CPU0_PMEVTYPER2_EL0,Performance Monitors Event Type Register 2"
bitfld.long 0x08 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x08 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x08 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x08 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x08 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x08 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x08 10.--25. 1. "RES0_PMEVTYPER2_EL0_25_10,Reserved RES0"
hexmask.long.word 0x08 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x0C "APBADDR_PMU_CPU0_PMEVTYPER3_EL0,Performance Monitors Event Type Register 3"
bitfld.long 0x0C 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x0C 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x0C 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x0C 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x0C 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x0C 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x0C 10.--25. 1. "RES0_PMEVTYPER3_EL0_25_10,Reserved RES0"
hexmask.long.word 0x0C 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x10 "APBADDR_PMU_CPU0_PMEVTYPER4_EL0,Performance Monitors Event Type Register 4"
bitfld.long 0x10 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x10 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x10 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x10 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x10 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x10 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x10 10.--25. 1. "RES0_PMEVTYPER4_EL0_25_10,Reserved RES0"
hexmask.long.word 0x10 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x14 "APBADDR_PMU_CPU0_PMEVTYPER5_EL0,Performance Monitors Event Type Register 5"
bitfld.long 0x14 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x14 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x14 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x14 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x14 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x14 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x14 10.--25. 1. "RES0_PMEVTYPER5_EL0_25_10,Reserved RES0"
hexmask.long.word 0x14 0.--9. 1. "EVTCOUNT,Event to count"
group.long 0x47C++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMCCFILTR_EL0,Performance Monitors Cycle Counter Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x00 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x00 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long 0x00 0.--25. 1. "RES0_PMCCFILTR_EL0_25_0,Reserved RES0"
group.long 0xC00++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMCNTENSET_EL0,Performance Monitors Count Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 enable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter enable bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xC20++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMCNTENCLR_EL0,Performance Monitors Count Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 disable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter disable bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xC40++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMINTENSET_EL1,Performance Monitors Interrupt Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow interrupt request enable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow interrupt request enable bit for PMEVCNTR<x>_EL0.N is the value in PMCR_EL0.N"
group.long 0xC60++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMINTENCLR_EL1,Performance Monitors Interrupt Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow interrupt request disable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow interrupt request disable bit for PMEVCNTR<x>_EL0.N is the value in PMCR_EL0.N"
group.long 0xC80++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow clear bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xCA0++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMSWINC_EL0,Performance Monitors Software Increment Register"
hexmask.long 0x00 6.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--5. "P_X,Event counter software increment bit for PMEVCNTR<x>" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xCC0++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMOVSSET_EL0,Performance Monitors Overflow Flag Status Set Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow set bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xE00++0x07
line.long 0x00 "APBADDR_PMU_CPU0_PMCFGR,Performance Monitors Configuration Register"
hexmask.long.word 0x00 20.--31. 1. "RES0_PMCFGR_31_20,Reserved RES0"
bitfld.long 0x00 19. "UEN,User-mode Enable Register supported" "0,1"
bitfld.long 0x00 18. "WT,This feature is not supported so this bit is RES0" "0,1"
newline
bitfld.long 0x00 17. "NA,This feature is not supported so this bit is RES0" "0,1"
bitfld.long 0x00 16. "EX,Export supported" "0,1"
bitfld.long 0x00 15. "CCD,Cycle counter has prescale" "0,1"
newline
bitfld.long 0x00 14. "CC,Dedicated cycle counter [counter 31] supported" "0,1"
bitfld.long 0x00 8.--13. "SIZE,Size of counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 0.--7. 1. "N,Number of counters implemented in addition to the cycle counter PMCCNTR_EL0"
line.long 0x04 "APBADDR_PMU_CPU0_PMCR_EL0,Performance Monitors Control Register"
hexmask.long.tbyte 0x04 11.--31. 1. "RES0_PMCR_EL0_31_11,Reserved RAZ/WI"
bitfld.long 0x04 7.--10. "RES0_PMCR_EL0_10_7,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "LC,Long cycle counter enable" "0,1"
newline
bitfld.long 0x04 5. "DP,Disable cycle counter when event counting is prohibited" "0,1"
bitfld.long 0x04 4. "X,Enable export of events in an IMPLEMENTATION DEFINED event stream" "0,1"
bitfld.long 0x04 3. "D,Clock divider" "0,1"
newline
bitfld.long 0x04 2. "C,Cycle counter reset" "0,1"
bitfld.long 0x04 1. "P,Event counter reset" "0,1"
bitfld.long 0x04 0. "E,Enable" "0,1"
group.long 0xE20++0x07
line.long 0x00 "APBADDR_PMU_CPU0_PMCEID0_EL0,Performance Monitors Common Event Identification Register 0"
line.long 0x04 "APBADDR_PMU_CPU0_PMCEID1_EL0,Performance Monitors Common Event Identification Register 1"
hexmask.long 0x04 1.--31. 1. "RES0_PMCEID1_EL0_31_1,Reserved RES0"
bitfld.long 0x04 0. "CE_32,Common architectural and microarchitectural feature events that can be counted by the PMU event counters.For the bit described in the following table the event is implemented if the bit is set to 1 or not implemented if the bit is set to.." "0,1"
group.long 0xF00++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMITCTRL,Performance Monitors Integration mode Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_PMITCTRL_31_1,Reserved RES0"
bitfld.long 0x00 0. "IME,Integration mode enable" "0,1"
group.long 0xFA8++0x17
line.long 0x00 "APBADDR_PMU_CPU0_PMDEVAFF0,Performance Monitors Device Affinity Register 0"
line.long 0x04 "APBADDR_PMU_CPU0_PMDEVAFF1,Performance Monitors Device Affinity Register 1"
line.long 0x08 "APBADDR_PMU_CPU0_PMLAR,Performance Monitors Lock Access Register"
line.long 0x0C "APBADDR_PMU_CPU0_PMLSR,Performance Monitors Lock Status Register"
hexmask.long 0x0C 3.--31. 1. "RES0_PMLSR_31_3,Reserved RES0"
bitfld.long 0x0C 2. "NTT,Not thirty-two bit access required" "0,1"
bitfld.long 0x0C 1. "SLK,Software lock status for this component" "0,1"
newline
bitfld.long 0x0C 0. "SLI,Software lock implemented" "0,1"
line.long 0x10 "APBADDR_PMU_CPU0_PMAUTHSTATUS,Performance Monitors Authentication Status Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_PMAUTHSTATUS_31_8,Reserved RES0"
bitfld.long 0x10 6.--7. "SNID,Holds the same value as DBGAUTHSTATUS_EL1.SNID" "0,1,2,3"
bitfld.long 0x10 4.--5. "RES0_PMAUTHSTATUS_5_4,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x10 2.--3. "NSNID,Holds the same value as DBGAUTHSTATUS_EL1.NSNID" "0,1,2,3"
bitfld.long 0x10 0.--1. "RES0_PMAUTHSTATUS_1_0,Reserved RES0" "0,1,2,3"
line.long 0x14 "APBADDR_PMU_CPU0_PMDEVARCH,Performance Monitors Device Architecture Register"
hexmask.long.word 0x14 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x14 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A" "0,1"
bitfld.long 0x14 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x14 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
group.long 0xFCC++0x07
line.long 0x00 "APBADDR_PMU_CPU0_PMDEVTYPE,Performance Monitors Device Type Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_PMDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x00 4.--7. "SUB,Subtype" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "MAJOR,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_PMU_CPU0_PMPIDR4,Performance Monitors Peripheral Identification Register 4"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_PMPIDR4_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "DES_2,Designer JEP106 continuation code least significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
group.long ($2+0xFD4)++0x03
line.long 0x00 "APBADDR_PMU_CPU0_PMPIDR$1,Performance Monitors Peripheral Identification Register 5"
repeat.end
group.long 0xFE0++0x1F
line.long 0x00 "APBADDR_PMU_CPU0_PMPIDR0,Performance Monitors Peripheral Identification Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_PMPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number least significant byte"
line.long 0x04 "APBADDR_PMU_CPU0_PMPIDR1,Performance Monitors Peripheral Identification Register 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_PMPIDR1_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "DES_0,Designer least significant nibble of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "PART_1,Part number most significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_PMU_CPU0_PMPIDR2,Performance Monitors Peripheral Identification Register 2"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_PMPIDR2_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "REVISION,Part major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3. "JEDEC,RAO" "0,1"
newline
bitfld.long 0x08 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x0C "APBADDR_PMU_CPU0_PMPIDR3,Performance Monitors Peripheral Identification Register 3"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_PMPIDR3_31_8,Reserved RES0"
bitfld.long 0x0C 4.--7. "REVAND,Part minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_PMU_CPU0_PMCIDR0,Performance Monitors Component Identification Register 0"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_PMCIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x14 "APBADDR_PMU_CPU0_PMCIDR1,Performance Monitors Component Identification Register 1"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_PMCIDR1_31_8,Reserved RES0"
bitfld.long 0x14 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_PMU_CPU0_PMCIDR2,Performance Monitors Component Identification Register 2"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_PMCIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x1C "APBADDR_PMU_CPU0_PMCIDR3,Performance Monitors Component Identification Register 3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_PMCIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_CORE1_CTI"
base ad:0x730140000
group.long 0x00++0x03
line.long 0x00 "APBADDR_CTI_CPU1_CTICONTROL,CTI Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_CTICONTROL_31_1,Reserved RES0"
bitfld.long 0x00 0. "GLBEN,Enables or disables the CTI mapping functions" "0,1"
group.long 0x10++0x2F
line.long 0x00 "APBADDR_CTI_CPU1_CTIINTACK,CTI Output Trigger Acknowledge Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "ACK_N,Can be used to create soft acknowledges for output triggers"
line.long 0x04 "APBADDR_CTI_CPU1_CTIAPPSET,CTI Application Trigger Set Register"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "CTIAPPSETX,Application trigger <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU1_CTIAPPCLEAR,CTI Application Trigger Clear Register"
hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x08 0.--3. "CTIAPPCLEARX,Application trigger <x> disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_CTI_CPU1_CTIAPPPULSE,CTI Application Pulse Register"
hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x0C 0.--3. "CTIAPPPULSEX,Generate event pulse on ECT channel <x>" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU1_CTIINEN0,CTI Input Trigger to Output Channel Enable Register 0"
hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x10 0.--3. "INENX,Input trigger 0 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_CTI_CPU1_CTIINEN1,CTI Input Trigger to Output Channel Enable Register 1"
hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x14 0.--3. "INENX,Input trigger 1 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_CTI_CPU1_CTIINEN2,CTI Input Trigger to Output Channel Enable Register 2"
hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x18 0.--3. "INENX,Input trigger 2 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "APBADDR_CTI_CPU1_CTIINEN3,CTI Input Trigger to Output Channel Enable Register 3"
hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x1C 0.--3. "INENX,Input trigger 3 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "APBADDR_CTI_CPU1_CTIINEN4,CTI Input Trigger to Output Channel Enable Register 4"
hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x20 0.--3. "INENX,Input trigger 4 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "APBADDR_CTI_CPU1_CTIINEN5,CTI Input Trigger to Output Channel Enable Register 5"
hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x24 0.--3. "INENX,Input trigger 5 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "APBADDR_CTI_CPU1_CTIINEN6,CTI Input Trigger to Output Channel Enable Register 6"
hexmask.long 0x28 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x28 0.--3. "INENX,Input trigger 6 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "APBADDR_CTI_CPU1_CTIINEN7,CTI Input Trigger to Output Channel Enable Register 7"
hexmask.long 0x2C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x2C 0.--3. "INENX,Input trigger 7 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0++0x1F
line.long 0x00 "APBADDR_CTI_CPU1_CTIOUTEN0,CTI Input Channel to Output Trigger Enable Register 0"
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--3. "OUTENX,Input channel <x> to output trigger 0 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_CTI_CPU1_CTIOUTEN1,CTI Input Channel to Output Trigger Enable Register 1"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "OUTENX,Input channel <x> to output trigger 1 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU1_CTIOUTEN2,CTI Input Channel to Output Trigger Enable Register 2"
hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x08 0.--3. "OUTENX,Input channel <x> to output trigger 2 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_CTI_CPU1_CTIOUTEN3,CTI Input Channel to Output Trigger Enable Register 3"
hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x0C 0.--3. "OUTENX,Input channel <x> to output trigger 3 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU1_CTIOUTEN4,CTI Input Channel to Output Trigger Enable Register 4"
hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x10 0.--3. "OUTENX,Input channel <x> to output trigger 4 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_CTI_CPU1_CTIOUTEN5,CTI Input Channel to Output Trigger Enable Register 5"
hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x14 0.--3. "OUTENX,Input channel <x> to output trigger 5 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_CTI_CPU1_CTIOUTEN6,CTI Input Channel to Output Trigger Enable Register 6"
hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x18 0.--3. "OUTENX,Input channel <x> to output trigger 6 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "APBADDR_CTI_CPU1_CTIOUTEN7,CTI Input Channel to Output Trigger Enable Register 7"
hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x1C 0.--3. "OUTENX,Input channel <x> to output trigger 7 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x130++0x17
line.long 0x00 "APBADDR_CTI_CPU1_CTITRIGINSTATUS,CTI Trigger In Status Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "TRINN,Provides the status of the trigger inputs"
line.long 0x04 "APBADDR_CTI_CPU1_CTITRIGOUTSTATUS,CTI Trigger Out Status Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x04 0.--7. 1. "TROUTN,Provides the status of the trigger outputs"
line.long 0x08 "APBADDR_CTI_CPU1_CTICHINSTATUS,CTI Channel In Status Register"
hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x08 0.--3. "CHINN,Provides the raw status of the ECT channel inputs to the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_CTI_CPU1_CTICHOUTSTATUS,CTI Channel Out Status Register"
hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x0C 0.--3. "CHOUTN,Provides the status of the ECT channel outputs from the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU1_CTIGATE,CTI Channel Gate Enable Register"
hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x10 0.--3. "GATEX,Determines whether events on channels propagate through the CTM to other ECT components or from the CTM into the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_CTI_CPU1_ASICCTL,CTI External Multiplexor Control register"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_ASICCTL_31_8,Reserved RES0"
hexmask.long.byte 0x14 0.--7. 1. "ASICCTL,IMPLEMENTATION DEFINED ASIC control"
group.long 0xF00++0x03
line.long 0x00 "APBADDR_CTI_CPU1_CTIITCTRL,CTI Integration mode Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_CTIITCTRL_31_1,Reserved RES0"
bitfld.long 0x00 0. "IME,Integration mode enable" "0,1"
group.long 0xFA0++0x33
line.long 0x00 "APBADDR_CTI_CPU1_CTICLAIMSET,CTI Claim Set"
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--3. "CLAIMX,CLAIM tag set bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_CTI_CPU1_CTICLAIMCLR,CTI Claim Clear"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "CLAIMX,Clear CLAIM tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU1_CTIDEVAFF0,CTI Device Affinity Register 0"
line.long 0x0C "APBADDR_CTI_CPU1_CTIDEVAFF1,CTI Device Affinity Register 1"
line.long 0x10 "APBADDR_CTI_CPU1_CTILAR,CTI Lock Access Register"
line.long 0x14 "APBADDR_CTI_CPU1_CTILSR,CTI Lock Status Register"
hexmask.long 0x14 3.--31. 1. "RES0_CTILSR_31_3,Reserved RES0"
bitfld.long 0x14 2. "NTT,Not thirty-two bit access required" "0,1"
bitfld.long 0x14 1. "SLK,Software lock status for this component" "0,1"
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bitfld.long 0x14 0. "SLI,Software lock implemented" "0,1"
line.long 0x18 "APBADDR_CTI_CPU1_CTIAUTHSTATUS,CTI Authentication Status Register"
hexmask.long 0x18 4.--31. 1. "RES0_CTIAUTHSTATUS_31_4,Reserved RES0"
bitfld.long 0x18 2.--3. "NSNID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SNID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSNID" "0,1,2,3"
bitfld.long 0x18 0.--1. "NSID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSID" "0,1,2,3"
line.long 0x1C "APBADDR_CTI_CPU1_CTIDEVARCH,CTI Device Architecture Register"
hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A" "0,1"
bitfld.long 0x1C 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
line.long 0x20 "APBADDR_CTI_CPU1_CTIDEVID2,CTI Device ID Register 2"
line.long 0x24 "APBADDR_CTI_CPU1_CTIDEVID1,CTI Device ID Register 1"
line.long 0x28 "APBADDR_CTI_CPU1_CTIDEVID,CTI Device ID Register 0"
bitfld.long 0x28 26.--31. "RES0_CTIDEVID_31_26,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x28 24.--25. "INOUT,Input/output options" "0,1,2,3"
bitfld.long 0x28 22.--23. "RES0_CTIDEVID_23_22,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x28 16.--21. "NUMCHAN,Number of ECT channels implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x28 14.--15. "RES0_CTIDEVID_15_14,Reserved RES0" "0,1,2,3"
bitfld.long 0x28 8.--13. "NUMTRIG,Number of triggers implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x28 5.--7. "RES0_CTIDEVID_7_5,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x28 0.--4. "EXTMUXNUM,Maximum number of external triggers available for multiplexing into the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x2C "APBADDR_CTI_CPU1_CTIDEVTYPE,CTI Device Type Register"
hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_CTIDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x2C 4.--7. "SUB,Subtype" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 0.--3. "MAJOR,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "APBADDR_CTI_CPU1_CTIPIDR4,CTI Peripheral Identification Register 4"
hexmask.long.tbyte 0x30 8.--31. 1. "RES0_CTIPIDR4_31_8,Reserved RES0"
bitfld.long 0x30 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 0.--3. "DES_2,Designer JEP106 continuation code least significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
group.long ($2+0xFD4)++0x03
line.long 0x00 "APBADDR_CTI_CPU1_CTIPIDR$1,CTI Peripheral Identification Register 5"
repeat.end
group.long 0xFE0++0x1F
line.long 0x00 "APBADDR_CTI_CPU1_CTIPIDR0,CTI Peripheral Identification Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_CTIPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number least significant byte"
line.long 0x04 "APBADDR_CTI_CPU1_CTIPIDR1,CTI Peripheral Identification Register 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_CTIPIDR1_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "DES_0,Designer least significant nibble of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "PART_1,Part number most significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU1_CTIPIDR2,CTI Peripheral Identification Register 2"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_CTIPIDR2_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "REVISION,Part major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3. "JEDEC,RAO" "0,1"
newline
bitfld.long 0x08 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x0C "APBADDR_CTI_CPU1_CTIPIDR3,CTI Peripheral Identification Register 3"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_CTIPIDR3_31_8,Reserved RES0"
bitfld.long 0x0C 4.--7. "REVAND,Part minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU1_CTICIDR0,CTI Component Identification Register 0"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_CTICIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x14 "APBADDR_CTI_CPU1_CTICIDR1,CTI Component Identification Register 1"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_CTICIDR1_31_8,Reserved RES0"
bitfld.long 0x14 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_CTI_CPU1_CTICIDR2,CTI Component Identification Register 2"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_CTICIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x1C "APBADDR_CTI_CPU1_CTICIDR3,CTI Component Identification Register 3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_CTICIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_CORE1_DBG"
base ad:0x730110000
group.long 0x20++0x07
line.long 0x00 "APBADDR_DBG_CPU1_EDESR,External Debug Event Status Register"
hexmask.long 0x00 3.--31. 1. "RES0_EDESR_31_3,Reserved RES0"
bitfld.long 0x00 2. "SS,Halting step debug event pending" "0,1"
newline
bitfld.long 0x00 1. "RC,Reset catch debug event pending" "0,1"
bitfld.long 0x00 0. "OSUC,OS unlock debug event pending" "0,1"
line.long 0x04 "APBADDR_DBG_CPU1_EDECR,External Debug Execution Control Register"
hexmask.long 0x04 3.--31. 1. "RES0_EDECR_31_3,Reserved RES0"
bitfld.long 0x04 2. "SS,Halting step enable" "0,1"
newline
bitfld.long 0x04 1. "RCE,Reset catch enable" "0,1"
bitfld.long 0x04 0. "OSUCE,OS unlock catch enabled" "0,1"
group.long 0x30++0x07
line.long 0x00 "APBADDR_DBG_CPU1_EDWAR_31_0,External Debug Watchpoint Address Register (low word)"
line.long 0x04 "APBADDR_DBG_CPU1_EDWAR_63_32,External Debug Watchpoint Address Register (high word)"
group.long 0x80++0x1B
line.long 0x00 "APBADDR_DBG_CPU1_DBGDTRRX_EL0,Debug Data Transfer Register Receive"
line.long 0x04 "APBADDR_DBG_CPU1_EDITR,External Debug Instruction Transfer Register"
line.long 0x08 "APBADDR_DBG_CPU1_EDSCR,External Debug Status and Control Register"
bitfld.long 0x08 31. "RES0_EDSCR_31_31,Reserved RES0" "0,1"
bitfld.long 0x08 30. "RXFULL,DTRRX full" "0,1"
newline
bitfld.long 0x08 29. "TXFULL,DTRTX full" "0,1"
bitfld.long 0x08 28. "ITO,EDITR overrun" "0,1"
newline
bitfld.long 0x08 27. "RXO,DTRRX overrun" "0,1"
bitfld.long 0x08 26. "TXU,DTRTX underrun" "0,1"
newline
bitfld.long 0x08 25. "PIPEADV,Pipeline advance" "0,1"
bitfld.long 0x08 24. "ITE,ITR empty" "0,1"
newline
bitfld.long 0x08 22.--23. "INTDIS,Interrupt disable" "0,1,2,3"
bitfld.long 0x08 21. "TDA,Trap debug registers accesses" "0,1"
newline
bitfld.long 0x08 20. "MA,Memory access mode" "0,1"
bitfld.long 0x08 19. "RES0_EDSCR_19_19,Reserved RES0" "0,1"
newline
bitfld.long 0x08 18. "NS,Non-secure status" "0,1"
bitfld.long 0x08 17. "RES0_EDSCR_17_17,Reserved RES0" "0,1"
newline
bitfld.long 0x08 16. "SDD,Secure debug disabled" "0,1"
bitfld.long 0x08 15. "RES0_EDSCR_15_15,Reserved RES0" "0,1"
newline
bitfld.long 0x08 14. "HDE,Halting debug mode enable" "0,1"
bitfld.long 0x08 10.--13. "RW,Exception level register-width status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 8.--9. "EL,Exception level" "0,1,2,3"
bitfld.long 0x08 7. "A,System Error interrupt pending" "0,1"
newline
bitfld.long 0x08 6. "ERR,Cumulative error flag" "0,1"
bitfld.long 0x08 0.--5. "STATUS,Debug status flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "APBADDR_DBG_CPU1_DBGDTRTX_EL0,Debug Data Transfer Register Transmit"
line.long 0x10 "APBADDR_DBG_CPU1_EDRCR,External Debug Reserve Control Register"
hexmask.long 0x10 5.--31. 1. "RES0_EDRCR_31_5,Reserved RES0"
bitfld.long 0x10 4. "CBRRQ,Allow imprecise entry to Debug state" "0,1"
newline
bitfld.long 0x10 3. "CSPA,Clear Sticky Pipeline Advance" "0,1"
bitfld.long 0x10 2. "CSE,Clear Sticky Error" "0,1"
newline
bitfld.long 0x10 0.--1. "RES0_EDRCR_1_0,Reserved RES0" "0,1,2,3"
line.long 0x14 "APBADDR_DBG_CPU1_EDACR,External Debug Auxiliary Control Register"
line.long 0x18 "APBADDR_DBG_CPU1_EDECCR,External Debug Exception Catch Control Register"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDECCR_31_8,Reserved RES0"
bitfld.long 0x18 4.--7. "NSE,Coarse-grained Non-secure exception catch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 0.--3. "SE,Coarse-grained Secure exception catch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0++0x0F
line.long 0x00 "APBADDR_DBG_CPU1_EDPCSR_31_0,External Debug Program Counter Sample Register (low word)"
line.long 0x04 "APBADDR_DBG_CPU1_EDCIDSR,External Debug Context ID Sample Register"
line.long 0x08 "APBADDR_DBG_CPU1_EDVIDSR,External Debug Virtual Context Sample Register"
bitfld.long 0x08 31. "NS,Non-secure state sample" "0,1"
bitfld.long 0x08 30. "E2,Exception level 2 status sample" "0,1"
newline
bitfld.long 0x08 29. "E3,Exception level 3 status sample" "0,1"
bitfld.long 0x08 28. "HV,EDPCSR high half valid" "0,1"
newline
hexmask.long.tbyte 0x08 8.--27. 1. "RES0_EDVIDSR_27_8,Reserved RES0"
hexmask.long.byte 0x08 0.--7. 1. "VMID,VMID sample"
line.long 0x0C "APBADDR_DBG_CPU1_EDPCSR_63_32,External Debug Program Counter Sample Register (high word)"
group.long 0x300++0x03
line.long 0x00 "APBADDR_DBG_CPU1_OSLAR_EL1,OS Lock Access Register"
hexmask.long 0x00 1.--31. 1. "RES0_OSLAR_EL1_31_1,Reserved RES0"
bitfld.long 0x00 0. "OSLK,On writes to OSLAR_EL1 bit[0] is copied to the OS lock.Use EDPRSR.OSLK to check the current status of the lock" "0,1"
group.long 0x310++0x07
line.long 0x00 "APBADDR_DBG_CPU1_EDPRCR,External Debug Power/Reset Control Register"
hexmask.long 0x00 4.--31. 1. "RES0_EDPRCR_31_4,Reserved RES0"
bitfld.long 0x00 3. "COREPURQ,Core powerup request" "0,1"
newline
bitfld.long 0x00 2. "RES0_EDPRCR_2_2,Reserved RES0" "0,1"
bitfld.long 0x00 1. "CWRR,Warm reset request" "0,1"
newline
bitfld.long 0x00 0. "CORENPDRQ,Core no powerdown request" "0,1"
line.long 0x04 "APBADDR_DBG_CPU1_EDPRSR,External Debug Processor Status Register"
hexmask.long.tbyte 0x04 12.--31. 1. "RES0_EDPRSR_31_12,Reserved RES0"
bitfld.long 0x04 11. "SDR,Sticky debug restart" "0,1"
newline
bitfld.long 0x04 10. "SPMAD,Sticky EPMAD error" "0,1"
bitfld.long 0x04 9. "EPMAD,External performance monitors access disable status" "0,1"
newline
bitfld.long 0x04 8. "SDAD,Sticky EDAD error" "0,1"
bitfld.long 0x04 7. "EDAD,External debug access disable status" "0,1"
newline
bitfld.long 0x04 6. "DLK,OS Double Lock status bit" "0,1"
bitfld.long 0x04 5. "OSLK,OS lock status bit" "0,1"
newline
bitfld.long 0x04 4. "HALTED,Halted status bit" "0,1"
bitfld.long 0x04 3. "SR,Sticky core reset status bit" "0,1"
newline
bitfld.long 0x04 2. "R,Core reset status bit" "0,1"
bitfld.long 0x04 1. "SPD,Sticky core power-down status bit.This bit is set to 1 on Cold reset to indicate the state of the debug registers has been lost" "0,1"
newline
bitfld.long 0x04 0. "PU,Core power-up status bit" "0,1"
group.long 0x400++0x0B
line.long 0x00 "APBADDR_DBG_CPU1_DBGBVR0_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU1_DBGBVR0_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU1_DBGBCR0_EL1,Debug Breakpoint Control Register 0"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR0_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR0_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR0_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x410++0x0B
line.long 0x00 "APBADDR_DBG_CPU1_DBGBVR1_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU1_DBGBVR1_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU1_DBGBCR1_EL1,Debug Breakpoint Control Register 1"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR1_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR1_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR1_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x420++0x0B
line.long 0x00 "APBADDR_DBG_CPU1_DBGBVR2_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU1_DBGBVR2_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU1_DBGBCR2_EL1,Debug Breakpoint Control Register 2"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR2_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR2_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR2_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x430++0x0B
line.long 0x00 "APBADDR_DBG_CPU1_DBGBVR3_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU1_DBGBVR3_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU1_DBGBCR3_EL1,Debug Breakpoint Control Register 3"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR3_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR3_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR3_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x440++0x0B
line.long 0x00 "APBADDR_DBG_CPU1_DBGBVR4_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU1_DBGBVR4_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU1_DBGBCR4_EL1,Debug Breakpoint Control Register 4"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR4_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR4_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR4_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x450++0x0B
line.long 0x00 "APBADDR_DBG_CPU1_DBGBVR5_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU1_DBGBVR5_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU1_DBGBCR5_EL1,Debug Breakpoint Control Register 5"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR5_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR5_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR5_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x800++0x0B
line.long 0x00 "APBADDR_DBG_CPU1_DBGWVR0_EL1_31_0,Debug Watchpoint Value Register 0"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR0_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU1_DBGWVR0_EL1_63_32,Debug Watchpoint Extended Value Register 0"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU1_DBGWCR0_EL1,Debug Watchpoint Control Register 0"
bitfld.long 0x08 29.--31. "RES0_DBGWCR0_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 21.--23. "RES0_DBGWCR0_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
newline
bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0x810++0x0B
line.long 0x00 "APBADDR_DBG_CPU1_DBGWVR1_EL1_31_0,Debug Watchpoint Value Register 1"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR1_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU1_DBGWVR1_EL1_63_32,Debug Watchpoint Extended Value Register 1"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU1_DBGWCR1_EL1,Debug Watchpoint Control Register 1"
bitfld.long 0x08 29.--31. "RES0_DBGWCR1_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 21.--23. "RES0_DBGWCR1_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
newline
bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0x820++0x0B
line.long 0x00 "APBADDR_DBG_CPU1_DBGWVR2_EL1_31_0,Debug Watchpoint Value Register 2"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR2_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU1_DBGWVR2_EL1_63_32,Debug Watchpoint Extended Value Register 2"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU1_DBGWCR2_EL1,Debug Watchpoint Control Register 2"
bitfld.long 0x08 29.--31. "RES0_DBGWCR2_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 21.--23. "RES0_DBGWCR2_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
newline
bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0x830++0x0B
line.long 0x00 "APBADDR_DBG_CPU1_DBGWVR3_EL1_31_0,Debug Watchpoint Value Register 3"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR3_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU1_DBGWVR3_EL1_63_32,Debug Watchpoint Extended Value Register 3"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU1_DBGWCR3_EL1,Debug Watchpoint Control Register 3"
bitfld.long 0x08 29.--31. "RES0_DBGWCR3_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 21.--23. "RES0_DBGWCR3_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
newline
bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0xD00++0x03
line.long 0x00 "APBADDR_DBG_CPU1_MIDR_EL1,Main ID Register"
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,The Implementer code"
bitfld.long 0x00 20.--23. "VARIANT,An IMPLEMENTATION DEFINED variant number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "ARCHITECTURE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 4.--15. 1. "PARTNUM,An IMPLEMENTATION DEFINED primary part number for the device"
newline
bitfld.long 0x00 0.--3. "REVISION,An IMPLEMENTATION DEFINED revision number for the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD20++0x3F
line.long 0x00 "APBADDR_DBG_CPU1_ID_AA64PFR0_EL1_31_0,Processor Feature Register 0 (low word)"
bitfld.long 0x00 28.--31. "RES0_ID_AA64PFR0_EL1_31_0_31_28,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "GIC,GIC system register interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "ADVSIMD,Advanced SIMD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "FP,Floating-point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "EL3,EL3 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "EL2,EL2 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "EL1,EL1 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "EL0,EL0 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_DBG_CPU1_ID_AA64PFR0_EL1_63_32,Processor Feature Register 0 (high word)"
line.long 0x08 "APBADDR_DBG_CPU1_ID_AA64DFR0_EL1_31_0,Debug Feature Register 0 (low word)"
bitfld.long 0x08 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 24.--27. "RES0_ID_AA64DFR0_EL1_31_0_27_24,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "WRPS,Number of watchpoints minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 16.--19. "RES0_ID_AA64DFR0_EL1_31_0_19_16,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 12.--15. "BRPS,Number of breakpoints minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 8.--11. "PMUVER,Performance Monitors extension version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4.--7. "TRACEVER,Trace extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--3. "DEBUGVER,Debug architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_DBG_CPU1_ID_AA64DFR0_EL1_63_32,Debug Feature Register 0 (high word)"
line.long 0x10 "APBADDR_DBG_CPU1_ID_AA64ISAR0_EL1_31_0,Instruction Set Attribute Register 0 (low word)"
hexmask.long.word 0x10 20.--31. 1. "RES0_ID_AA64ISAR0_EL1_31_0_31_20,Reserved RES0"
bitfld.long 0x10 16.--19. "CRC32,CRC32 instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 12.--15. "SHA2,SHA2 instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 8.--11. "SHA1,SHA1 instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 4.--7. "AES,AES instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 0.--3. "RES0_ID_AA64ISAR0_EL1_31_0_3_0,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_DBG_CPU1_ID_AA64ISAR0_EL1_63_32,Instruction Set Attribute Register 0 (high word)"
line.long 0x18 "APBADDR_DBG_CPU1_ID_AA64MMFR0_EL1_31_0,Memory Model Feature Register 0 (low word)"
bitfld.long 0x18 28.--31. "TGRAN4,Support for 4 Kbyte memory translation granule size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 24.--27. "TGRAN64,Support for 64 Kbyte memory translation granule size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 20.--23. "TGRAN16,Support for 16 Kbyte memory translation granule size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 16.--19. "BIGENDEL0,Mixed-endian support at EL0 only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 8.--11. "BIGEND,Mixed-endian configuration support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 4.--7. "ASIDBITS,Number of ASID bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 0.--3. "PARANGE,Physical Address range supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "APBADDR_DBG_CPU1_ID_AA64MMFR0_EL1_63_32,Memory Model Feature Register 0 (high word)"
line.long 0x20 "APBADDR_DBG_CPU1_ID_AA64PFR1_EL1_31_0,Processor Feature Register 1 (low word)"
line.long 0x24 "APBADDR_DBG_CPU1_ID_AA64PFR1_EL1_63_32,Processor Feature Register 1 (high word)"
line.long 0x28 "APBADDR_DBG_CPU1_ID_AA64DFR1_EL1_31_0,Auxiliary Feature Register 1 (low word)"
line.long 0x2C "APBADDR_DBG_CPU1_ID_AA64DFR1_EL1_63_32,Auxiliary Feature Register 1 (high word)"
line.long 0x30 "APBADDR_DBG_CPU1_ID_AA64ISAR1_EL1_31_0,Instruction Set Attribute Register 1 (low word)"
line.long 0x34 "APBADDR_DBG_CPU1_ID_AA64ISAR1_EL1_63_32,Instruction Set Attribute Register 1 (high word)"
line.long 0x38 "APBADDR_DBG_CPU1_ID_AA64MMFR1_EL1_31_0,Memory Model Feature Register 1 (low word)"
line.long 0x3C "APBADDR_DBG_CPU1_ID_AA64MMFR1_EL1_63_32,Memory Model Feature Register 1 (high word)"
group.long 0xF00++0x03
line.long 0x00 "APBADDR_DBG_CPU1_EDITCTRL,External Debug Integration mode Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_EDITCTRL_31_1,Reserved RES0"
bitfld.long 0x00 0. "IME,Integration mode enable" "0,1"
group.long 0xFA0++0x33
line.long 0x00 "APBADDR_DBG_CPU1_DBGCLAIMSET_EL1,Debug Claim Tag Set Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_DBGCLAIMSET_EL1_31_8,Reserved RAZ/SBZ"
hexmask.long.byte 0x00 0.--7. 1. "CLAIM,Claim set bits"
line.long 0x04 "APBADDR_DBG_CPU1_DBGCLAIMCLR_EL1,Debug Claim Tag Clear Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_DBGCLAIMCLR_EL1_31_8,Reserved RAZ/SBZ"
hexmask.long.byte 0x04 0.--7. 1. "CLAIM,Claim clear bits"
line.long 0x08 "APBADDR_DBG_CPU1_EDDEVAFF0,External Debug Device Affinity Register 0"
line.long 0x0C "APBADDR_DBG_CPU1_EDDEVAFF1,External Debug Device Affinity Register 1"
line.long 0x10 "APBADDR_DBG_CPU1_EDLAR,External Debug Lock Access Register"
line.long 0x14 "APBADDR_DBG_CPU1_EDLSR,External Debug Lock Status Register"
hexmask.long 0x14 3.--31. 1. "RES0_EDLSR_31_3,Reserved RES0"
bitfld.long 0x14 2. "NTT,Not thirty-two bit access required" "0,1"
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bitfld.long 0x14 1. "SLK,Software lock status for this component" "0,1"
bitfld.long 0x14 0. "SLI,Software lock implemented" "0,1"
line.long 0x18 "APBADDR_DBG_CPU1_DBGAUTHSTATUS_EL1,Debug Authentication Status register"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_DBGAUTHSTATUS_EL1_31_8,Reserved RES0"
bitfld.long 0x18 6.--7. "SNID,Secure non-invasive debug" "0,1,2,3"
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bitfld.long 0x18 4.--5. "SID,Secure invasive debug" "0,1,2,3"
bitfld.long 0x18 2.--3. "NSNID,Non-secure non-invasive debug" "0,1,2,3"
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bitfld.long 0x18 0.--1. "NSID,Non-secure invasive debug" "0,1,2,3"
line.long 0x1C "APBADDR_DBG_CPU1_EDDEVARCH,External Debug Device Architecture Register"
hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A" "0,1"
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bitfld.long 0x1C 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
line.long 0x20 "APBADDR_DBG_CPU1_EDDEVID2,External Debug Device ID Register 2"
line.long 0x24 "APBADDR_DBG_CPU1_EDDEVID1,External Debug Device ID Register 1"
hexmask.long 0x24 4.--31. 1. "RES0_EDDEVID1_31_4,Reserved RES0"
bitfld.long 0x24 0.--3. "PCSROFFSET,This field indicates the offset applied to PC samples returned by reads of EDPCSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "APBADDR_DBG_CPU1_EDDEVID,External Debug Device ID Register 0"
bitfld.long 0x28 28.--31. "RES0_EDDEVID_31_28,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 24.--27. "AUXREGS,Indicates support for Auxiliary registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.tbyte 0x28 4.--23. 1. "RES0_EDDEVID_23_4,Reserved RES0"
bitfld.long 0x28 0.--3. "PCSAMPLE,Indicates the level of Sample-based profiling support using external debug registers 40 through 43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "APBADDR_DBG_CPU1_EDDEVTYPE,External Debug Device Type Register"
hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_EDDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x2C 4.--7. "SUB,Subtype" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 0.--3. "MAJOR,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "APBADDR_DBG_CPU1_EDPIDR4,External Debug Peripheral Identification Register 4"
hexmask.long.tbyte 0x30 8.--31. 1. "RES0_EDPIDR4_31_8,Reserved RES0"
bitfld.long 0x30 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 0.--3. "DES_2,Designer JEP106 continuation code least significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFE0++0x1F
line.long 0x00 "APBADDR_DBG_CPU1_EDPIDR0,External Debug Peripheral Identification Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_EDPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number least significant byte"
line.long 0x04 "APBADDR_DBG_CPU1_EDPIDR1,External Debug Peripheral Identification Register 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_EDPIDR1_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "DES_0,Designer least significant nibble of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. "PART_1,Part number most significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_DBG_CPU1_EDPIDR2,External Debug Peripheral Identification Register 2"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_EDPIDR2_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "REVISION,Part major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 3. "JEDEC,RAO" "0,1"
bitfld.long 0x08 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x0C "APBADDR_DBG_CPU1_EDPIDR3,External Debug Peripheral Identification Register 3"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_EDPIDR3_31_8,Reserved RES0"
bitfld.long 0x0C 4.--7. "REVAND,Part minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_DBG_CPU1_EDCIDR0,External Debug Component Identification Register 0"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_EDCIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x14 "APBADDR_DBG_CPU1_EDCIDR1,External Debug Component Identification Register 1"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_EDCIDR1_31_8,Reserved RES0"
bitfld.long 0x14 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_DBG_CPU1_EDCIDR2,External Debug Component Identification Register 2"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDCIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x1C "APBADDR_DBG_CPU1_EDCIDR3,External Debug Component Identification Register 3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_EDCIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_CORE1_ECC_AGGR"
base ad:0x718800
rgroup.long 0x00++0x03
line.long 0x00 "ECC_AGGR_CORE1_REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
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bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
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bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "ECC_AGGR_CORE1_REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
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hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
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bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
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hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ECC_AGGR_CORE1_REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ECC_AGGR_CORE1_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "ECC_AGGR_CORE1_REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_CORE1_REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 26. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 25. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 24. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 23. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 22. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 21. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 20. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 19. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 18. "CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 17. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 16. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 15. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 14. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 13. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 12. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 11. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 10. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 9. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 8. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 7. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 6. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 5. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 4. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 3. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 2. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 1. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 0. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ECC_AGGR_CORE1_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 26. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 25. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 24. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 23. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 22. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 21. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 20. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 19. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 18. "CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 17. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 16. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 15. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 14. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 13. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 12. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 11. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 10. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 9. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 8. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 7. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 6. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 5. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 4. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 3. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 2. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 1. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 0. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ECC_AGGR_CORE1_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 26. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 25. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 24. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 23. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 22. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 21. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 20. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 19. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 18. "CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 17. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 16. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 15. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 14. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 13. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 12. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 11. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 10. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 9. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 8. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 7. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 6. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 5. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 4. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 3. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 2. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 1. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 0. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ECC_AGGR_CORE1_REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_CORE1_REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 26. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 25. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 24. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 23. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 22. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 21. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 20. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 19. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 18. "CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 17. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 16. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 15. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 14. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 13. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 12. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 11. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 10. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 9. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 8. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 7. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 6. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 5. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 4. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 3. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 2. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 1. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 0. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ECC_AGGR_CORE1_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 26. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 25. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 24. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 23. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 22. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 21. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 20. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 19. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 18. "CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 17. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 16. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 15. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 14. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 13. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 12. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 11. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 10. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 9. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 8. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 7. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 6. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 5. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 4. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 3. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 2. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 1. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 0. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ECC_AGGR_CORE1_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 26. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 25. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 24. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 23. "CPU1_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 22. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 21. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 20. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 19. "CPU1_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 18. "CPU1_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 17. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 16. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 15. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 14. "CPU1_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 13. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 12. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 11. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 10. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 9. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 8. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 7. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 6. "CPU1_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 5. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 4. "CPU1_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 3. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 2. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 1. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 0. "CPU1_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ECC_AGGR_CORE1_REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
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bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ECC_AGGR_CORE1_REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
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bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ECC_AGGR_CORE1_REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
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bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ECC_AGGR_CORE1_REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
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bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "A53SS0_CORE1_ETM"
base ad:0x730130000
group.long 0x04++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCPRGCTLR,Programming Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_TRCPRGCTLR_31_1,Reserved RES0"
bitfld.long 0x00 0. "EN,Trace unit enable bit" "0,1"
group.long 0x0C++0x07
line.long 0x00 "APBADDR_ETM_CPU1_TRCSTATR,Status Register"
hexmask.long 0x00 2.--31. 1. "RES0_TRCSTATR_31_2,Reserved RES0"
bitfld.long 0x00 1. "PMSTABLE,Programmer's model stable bit: 0 The programmer's model is not stable" "0,1"
bitfld.long 0x00 0. "IDLE,Idle status bit: 0 The trace unit is not idle" "0,1"
line.long 0x04 "APBADDR_ETM_CPU1_TRCCONFIGR,Trace Configuration Register"
hexmask.long.word 0x04 18.--31. 1. "RES0_TRCCONFIGR_31_18,Reserved RES0"
bitfld.long 0x04 17. "DV,Data value tracing bit: 0 Data value tracing is disabled" "0,1"
bitfld.long 0x04 16. "DA,Data address tracing bit: 0 Data address tracing is disabled" "0,1"
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bitfld.long 0x04 15. "RES0_TRCCONFIGR_15_15,Reserved RES0" "0,1"
bitfld.long 0x04 13.--14. "QE,Q element enable field: 00 Q elements are disabled" "0,1,2,3"
bitfld.long 0x04 12. "RS,Return stack enable bit" "0,1"
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bitfld.long 0x04 11. "TS,Global timestamp tracing bit: 0 Global timestamp tracing is disabled" "0,1"
bitfld.long 0x04 8.--10. "COND,Conditional instruction tracing bit" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "VMID,VMID tracing bit: 0 VMID tracing is disabled" "0,1"
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bitfld.long 0x04 6. "CID,Context ID tracing bit: 0 Context ID tracing is disabled" "0,1"
bitfld.long 0x04 5. "RES0_TRCCONFIGR_5_5,Reserved RES0" "0,1"
bitfld.long 0x04 4. "CCI,Cycle counting instruction trace bit: 0 Cycle counting in the instruction trace is disabled" "0,1"
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bitfld.long 0x04 3. "BB,Branch broadcast mode bit: 0 Branch broadcast mode is disabled" "0,1"
bitfld.long 0x04 1.--2. "INSTP0,Instruction P0 bit" "0,1,2,3"
bitfld.long 0x04 0. "RES1_TRCCONFIGR_0_0,Reserved RES1" "0,1"
group.long 0x18++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCAUXCTLR,Auxiliary Control Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_TRCAUXCTLR_31_8,Reserved RES0"
bitfld.long 0x00 7. "COREIFEN,Keep core interface enabled regardless of trace enable register state" "0,1"
bitfld.long 0x00 6. "RES0_TRCAUXCTLR_6_6,Reserved RES0" "0,1"
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bitfld.long 0x00 5. "AUTHNOFLUSH,Do not flush trace on de-assertion of authentication inputs" "0,1"
bitfld.long 0x00 4. "TSNODELAY,Do not delay timestamp insertion based on FIFO depth" "0,1"
bitfld.long 0x00 3. "SYNCDELAY,Delay periodic synchronization if FIFO is more than half-full" "0,1"
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bitfld.long 0x00 2. "OVFLW,Force an overflow if synchronization is not completed when second synchronization becomes due" "0,1"
bitfld.long 0x00 1. "IDLEACK,Force idle-drain acknowledge high CPU does not wait for trace to drain before entering WFX state" "0,1"
bitfld.long 0x00 0. "AFREADY,Always respond to AFREADY immediately" "0,1"
group.long 0x20++0x07
line.long 0x00 "APBADDR_ETM_CPU1_TRCEVENTCTL0R,Event Control 0 Register"
bitfld.long 0x00 31. "TYPE3,Selects the resource type for trace event 3" "0,1"
bitfld.long 0x00 28.--30. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--27. "SEL3,Selects the resource number based on the value of TYPE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "TYPE2,Selects the resource type for trace event 2" "0,1"
bitfld.long 0x00 20.--22. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "SEL2,Selects the resource number based on the value of TYPE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "TYPE1,Selects the resource type for trace event 1" "0,1"
bitfld.long 0x00 12.--14. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "SEL1,Selects the resource number based on the value of TYPE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "TYPE0,Selects the resource type for trace event 0" "0,1"
bitfld.long 0x00 4.--6. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "SEL0,Selects the resource number based on the value of TYPE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_ETM_CPU1_TRCEVENTCTL1R,Event Control 1 Register"
hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 12. "LPOVERRIDE,Low power state behavior override" "0,1"
bitfld.long 0x04 11. "ATB,ATB trigger enable" "0,1"
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hexmask.long.byte 0x04 4.--10. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "EN,One bit per event to enable generation of an event element in the instruction trace stream when the selected event occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x17
line.long 0x00 "APBADDR_ETM_CPU1_TRCSTALLCTLR,Stall Control Register"
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 8. "ISTALL,Controls if the trace unit can stall the processor when the instruction trace buffer space is less than LEVEL" "0,1"
bitfld.long 0x00 4.--7. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 2.--3. "LEVEL,The field can support 4 monotonic levels from 0b00 to 0b11" "0,1,2,3"
bitfld.long 0x00 0.--1. "RESERVED,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_ETM_CPU1_TRCTSCTLR,Global Timestamp Control Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_TRCTSCTLR_31_8,Reserved RES0"
hexmask.long.byte 0x04 0.--7. 1. "EVENT,An event selector"
line.long 0x08 "APBADDR_ETM_CPU1_TRCSYNCPR,Synchronization Period Register"
hexmask.long 0x08 5.--31. 1. "RES0_TRCSYNCPR_31_5,Reserved RES0"
bitfld.long 0x08 0.--4. "PERIOD,Controls how many bytes of trace the sum of instruction and data that a trace unit can generate before a periodic trace synchronization request occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "APBADDR_ETM_CPU1_TRCCCCTLR,Cycle Count Control Register"
hexmask.long.tbyte 0x0C 12.--31. 1. "RES0_TRCCCCTLR_31_12,Reserved RES0"
hexmask.long.word 0x0C 0.--11. 1. "THRESHOLD,Sets the threshold value for instruction trace cycle counting.The minimum threshold value that can be programmed into THRESHOLD is given in TRCIDR3.CCITMIN.Writing a value of zero might cause UNPREDICTABLE behaviour"
line.long 0x10 "APBADDR_ETM_CPU1_TRCBBCTLR,Branch Broadcast Control Register"
hexmask.long.tbyte 0x10 9.--31. 1. "RES0_TRCBBCTLR_31_9,Reserved RES0"
bitfld.long 0x10 8. "MODE,Mode bit: 0 Exclude mode" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "RANGE,Address range field"
line.long 0x14 "APBADDR_ETM_CPU1_TRCTRACEIDR,Trace ID Register"
hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x14 0.--6. 1. "TRACEID,Trace ID value"
group.long 0x80++0x0B
line.long 0x00 "APBADDR_ETM_CPU1_TRCVICTLR,ViewInst Main Control Register"
hexmask.long.byte 0x00 24.--31. 1. "RES0_TRCVICTLR_31_24,Reserved RES0"
bitfld.long 0x00 20.--23. "EXLEVEL_NS,In Non-secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "EXLEVEL_S,In Secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "RES0_TRCVICTLR_15_12,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "TRCERR,If TRCIDR3.TRCERR==1 this bit controls whether a trace unit must trace a system error exception: 0 The trace unit does not trace a system error exception unless it traces the exception or instruction immediately prior to the system error exception" "0,1"
bitfld.long 0x00 10. "TRCRESET,Controls whether a trace unit must trace a Reset exception: 0 The trace unit does not trace a Reset exception unless it traces the exception or instruction immediately prior to the Reset exception" "0,1"
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bitfld.long 0x00 9. "SSSTATUS,IF TRCIDR4.NUMACPAIRS>0 or TRCIDR.NUMPC>0 this bit returns the status of the start-stop logic: 0 The start-stop logic is in the stopped state" "0,1"
bitfld.long 0x00 8. "RES0_TRCVICTLR_8_8,Reserved RES0" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "EVENT,An event selector"
line.long 0x04 "APBADDR_ETM_CPU1_TRCVIIECTLR,ViewInst Include-Exclude Control Register"
hexmask.long.byte 0x04 24.--31. 1. "RES0_TRCVIIECTLR_31_24,Reserved RES0"
hexmask.long.byte 0x04 16.--23. 1. "EXCLUDE,0 1 The implemented width of the field n is IMPLEMENTATION DEFINED and is set by the value of TRCIDR4.NUMACPAIRS"
hexmask.long.byte 0x04 8.--15. 1. "RES0_TRCVIIECTLR_15_8,Reserved RES0"
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hexmask.long.byte 0x04 0.--7. 1. "INCLUDE,Include range field"
line.long 0x08 "APBADDR_ETM_CPU1_TRCVISSCTLR,ViewInst Start-Stop Control Register"
hexmask.long.word 0x08 16.--31. 1. "STOP,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of stopping trace"
hexmask.long.word 0x08 0.--15. 1. "START,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of starting trace"
group.long 0x100++0x0B
line.long 0x00 "APBADDR_ETM_CPU1_TRCSEQEVR0,Sequencer State Transition Control Registers 0"
hexmask.long.word 0x00 16.--31. 1. "RES0_TRCSEQEVR0_31_16,Reserved RES0"
hexmask.long.byte 0x00 8.--15. 1. "B_N,Backward field"
hexmask.long.byte 0x00 0.--7. 1. "F_N,Forward field"
line.long 0x04 "APBADDR_ETM_CPU1_TRCSEQEVR1,Sequencer State Transition Control Registers 1"
hexmask.long.word 0x04 16.--31. 1. "RES0_TRCSEQEVR1_31_16,Reserved RES0"
hexmask.long.byte 0x04 8.--15. 1. "B_N,Backward field"
hexmask.long.byte 0x04 0.--7. 1. "F_N,Forward field"
line.long 0x08 "APBADDR_ETM_CPU1_TRCSEQEVR2,Sequencer State Transition Control Registers 2"
hexmask.long.word 0x08 16.--31. 1. "RES0_TRCSEQEVR2_31_16,Reserved RES0"
hexmask.long.byte 0x08 8.--15. 1. "B_N,Backward field"
hexmask.long.byte 0x08 0.--7. 1. "F_N,Forward field"
group.long 0x118++0x0B
line.long 0x00 "APBADDR_ETM_CPU1_TRCSEQRSTEVR,Sequencer Reset Control Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_TRCSEQRSTEVR_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "RST,Contains an event number"
line.long 0x04 "APBADDR_ETM_CPU1_TRCSEQSTR,Sequencer State Register"
hexmask.long 0x04 2.--31. 1. "RES0_TRCSEQSTR_31_2,Reserved RES0"
bitfld.long 0x04 0.--1. "STATE,Sets or returns the state of the sequencer: 00 State 0" "0,1,2,3"
line.long 0x08 "APBADDR_ETM_CPU1_TRCEXTINSELR,External Input Select Register"
bitfld.long 0x08 29.--31. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "SEL3,Selects an event from the external input bus for External Input Resource 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 21.--23. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 16.--20. "SEL2,Selects an event from the external input bus for External Input Resource 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 13.--15. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 8.--12. "SEL1,Selects an event from the external input bus for External Input Resource 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 5.--7. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 0.--4. "SEL0,Selects an event from the external input bus for External Input Resource 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x140++0x07
line.long 0x00 "APBADDR_ETM_CPU1_TRCCNTRLDVR0,Counter Reload Value Registers 0"
hexmask.long.word 0x00 16.--31. 1. "RES0_TRCCNTRLDVR0_31_16,Reserved RES0"
hexmask.long.word 0x00 0.--15. 1. "VALUE_N,Contains the reload value for counter <n>"
line.long 0x04 "APBADDR_ETM_CPU1_TRCCNTRLDVR1,Counter Reload Value Registers 1"
hexmask.long.word 0x04 16.--31. 1. "RES0_TRCCNTRLDVR1_31_16,Reserved RES0"
hexmask.long.word 0x04 0.--15. 1. "VALUE_N,Contains the reload value for counter <n>"
group.long 0x150++0x07
line.long 0x00 "APBADDR_ETM_CPU1_TRCCNTCTLR0,Counter Control Register 0"
hexmask.long.word 0x00 18.--31. 1. "RES0_TRCCNTCTLR0_31_18,Reserved RES0"
bitfld.long 0x00 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter <n> decrements when a reload event occurs for counter <n-1>: 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit is RES0" "0,1"
bitfld.long 0x00 16. "RLDSELF_N,Controls whether a reload event occurs for counter <n> when counter <n> reaches zero: 0 The trace unit does not generate a reload event" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter <n>"
hexmask.long.byte 0x00 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter <n> to decrement"
line.long 0x04 "APBADDR_ETM_CPU1_TRCCNTCTLR1,Counter Control Register 1"
hexmask.long.word 0x04 18.--31. 1. "RES0_TRCCNTCTLR1_31_18,Reserved RES0"
bitfld.long 0x04 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter <n> decrements when a reload event occurs for counter <n-1>: 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit is RES0" "0,1"
bitfld.long 0x04 16. "RLDSELF_N,Controls whether a reload event occurs for counter <n> when counter <n> reaches zero: 0 The trace unit does not generate a reload event" "0,1"
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hexmask.long.byte 0x04 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter <n>"
hexmask.long.byte 0x04 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter <n> to decrement"
group.long 0x160++0x07
line.long 0x00 "APBADDR_ETM_CPU1_TRCCNTVR0,Counter Value Registers 0"
hexmask.long.word 0x00 16.--31. 1. "RES0_TRCCNTVR0_31_16,Reserved RES0"
hexmask.long.word 0x00 0.--15. 1. "VALUE_N,Contains the count value of counter <n>"
line.long 0x04 "APBADDR_ETM_CPU1_TRCCNTVR1,Counter Value Registers 1"
hexmask.long.word 0x04 16.--31. 1. "RES0_TRCCNTVR1_31_16,Reserved RES0"
hexmask.long.word 0x04 0.--15. 1. "VALUE_N,Contains the count value of counter <n>"
group.long 0x180++0x17
line.long 0x00 "APBADDR_ETM_CPU1_TRCIDR8,ID Register 8"
line.long 0x04 "APBADDR_ETM_CPU1_TRCIDR9,ID Register 9"
line.long 0x08 "APBADDR_ETM_CPU1_TRCIDR10,ID Register 10"
line.long 0x0C "APBADDR_ETM_CPU1_TRCIDR11,ID Register 11"
line.long 0x10 "APBADDR_ETM_CPU1_TRCIDR12,ID Register 12"
line.long 0x14 "APBADDR_ETM_CPU1_TRCIDR13,ID Register 13"
group.long 0x1C0++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCIMSPEC0,Implementation Specific Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_TRCIMSPEC0_31_8,Reserved RES0"
bitfld.long 0x00 4.--7. "EN,If SUPPORT is not 0b0000 controls whether the IMPLEMENTATION DEFINED features are enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "SUPPORT,Indicates whether the implementation supports IMPLEMENTATION DEFINED features" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1E0++0x17
line.long 0x00 "APBADDR_ETM_CPU1_TRCIDR0,ID Register 0"
bitfld.long 0x00 30.--31. "RES0_TRCIDR0_31_30,Reserved RES0" "0,1,2,3"
bitfld.long 0x00 29. "COMMOPT,Conditional instruction tracing support bit" "0,1"
bitfld.long 0x00 24.--28. "TSSIZE,Global timestamp size field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 17.--23. 1. "RES0_TRCIDR0_23_17,Reserved RES0"
bitfld.long 0x00 15.--16. "QSUPP,Q element support field" "0,1,2,3"
bitfld.long 0x00 14. "QFILT,Q element filtering support field" "0,1"
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bitfld.long 0x00 12.--13. "CONDTYPE,Conditional tracing field" "0,1,2,3"
bitfld.long 0x00 10.--11. "NUMEVENT,Number of events field" "0,1,2,3"
bitfld.long 0x00 9. "RETSTACK,Return stack bit" "0,1"
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bitfld.long 0x00 8. "RES0_TRCIDR0_8_8,Reserved RES0" "0,1"
bitfld.long 0x00 7. "TRCCCI,Cycle counting instruction bit" "0,1"
bitfld.long 0x00 6. "TRCCOND,Conditional instruction tracing support bit" "0,1"
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bitfld.long 0x00 5. "TRCBB,Branch broadcast tracing support bit" "0,1"
bitfld.long 0x00 3.--4. "TRCDATA,Conditional tracing field" "0,1,2,3"
bitfld.long 0x00 1.--2. "INSTP0,P0 tracing support field" "0,1,2,3"
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bitfld.long 0x00 0. "RES0_TRCIDR0_0_0,Reserved RES0" "0,1"
line.long 0x04 "APBADDR_ETM_CPU1_TRCIDR1,ID Register 1"
hexmask.long.byte 0x04 24.--31. 1. "DESIGNER,Indicates which company designed the trace unit"
hexmask.long.byte 0x04 16.--23. 1. "RES0_TRCIDR1_23_16,Reserved RES0"
bitfld.long 0x04 12.--15. "RES1_TRCIDR1_15_12,Reserved RES1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 8.--11. "TRCARCHMAJ,Indicates the major version of the ETM architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 4.--7. "TRCARCHMIN,Indicates the minor version of the ETM architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "REVISION,Returns an IMPLEMENTATION DEFINED value that identifies the revision of the trace registers and the OS Save and Restore registers.ARM recommends:That the initial implementation sets REVISION==0x0 and the field then increments for any subsequent.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_ETM_CPU1_TRCIDR2,ID Register 2"
bitfld.long 0x08 29.--31. "RES0_TRCIDR2_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 25.--28. "CCSIZE,Indicates the size of the cycle counter in bits minus 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 20.--24. "DVSIZE,Indicates the data value size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 15.--19. "DASIZE,Indicates the data address size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 10.--14. "VMIDSIZE,Indicates the VMID size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 5.--9. "CIDSIZE,Indicates the Context ID size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 0.--4. "IASIZE,Indicates the instruction address size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "APBADDR_ETM_CPU1_TRCIDR3,ID Register 3"
bitfld.long 0x0C 31. "NOOVERFLOW,Indicates if TRCSTALLCTLR.NOOVERFLOW is supported: 0 TRCSTALLCTLR.NOOVERFLOW is not supported or STALLCTL==0" "0,1"
bitfld.long 0x0C 28.--30. "NUMPROC,Indicates the number of processors available for tracing" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 27. "SYSSTALL,Indicates if the implementation can support stall control: 0 The system does not support stall control of the processor" "0,1"
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bitfld.long 0x0C 26. "STALLCTL,Indicates if TRCSTALLCTLR is supported: 0 TRCSTALLCTLR is not supported" "0,1"
bitfld.long 0x0C 25. "SYNCPR,Indicates if an implementation has a fixed synchronization period: 0 TRCSYNCPR is read-write so software can change the synchronization period" "0,1"
bitfld.long 0x0C 24. "TRCERR,Indicates if TRCVICTLR.TRCERR is supported: 0 TRCVICTLR.TRCERR is not supported 1 TRCVICTLR.TRCERR is supported" "0,1"
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bitfld.long 0x0C 20.--23. "EXLEVEL_NS,In Non-secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Non-secure state exception level n is not supported so the corresponding bits in TRCACATRn.EXLEVEL_NS and.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 16.--19. "EXLEVEL_S,In Secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Secure state exception level n is not supported so the corresponding bits in TRCACATRn.EXLEVEL_S and TRCVICTLR.EXLEVEL_S.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 12.--15. "RES0_TRCIDR3_15_12,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x0C 0.--11. 1. "CCITMIN,Indicates the minimum value that can be programmed in TRCCCCTLR.THRESHOLD.When cycle counting in the instruction trace is supported that is TRCIDR0.TRCCCI==1 then the minimum value of this field is 0x001 otherwise it is 0x000"
line.long 0x10 "APBADDR_ETM_CPU1_TRCIDR4,ID Register 4"
bitfld.long 0x10 28.--31. "NUMVMIDC,Indicates the number of VMID comparators that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 24.--27. "NUMCIDC,Indicates the number of Context ID comparators that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 20.--23. "NUMSSCC,Indicates the number of single-shot comparator controls that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "NUMRSPAIR,Indicates the number of resource selection pairs that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 12.--15. "NUMPC,Indicates the number of processor comparator inputs that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 9.--11. "RES0_TRCIDR4_11_9,Reserved RES0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 8. "SUPPDAC,Indicates if the implementation can support data address comparisons: 0 The implementation does not support data address comparisons" "0,1"
bitfld.long 0x10 4.--7. "NUMDVC,Indicates the number of data value comparators that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 0.--3. "NUMACPAIRS,Indicates the number of address comparator pairs that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_ETM_CPU1_TRCIDR5,ID Register 5"
bitfld.long 0x14 31. "REDFUNCNTR,Indicates if the reduced function counter is implemented: 0 The reduced function counter is not supported" "0,1"
bitfld.long 0x14 28.--30. "NUMCNTR,Indicates the number of counters that are available for tracing" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 25.--27. "NUMSEQSTATE,Indicates the number of sequencer states that are implemented" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 24. "RES0_TRCIDR5_24_24,Reserved RES0" "0,1"
bitfld.long 0x14 23. "LPOVERRIDE,Indicates if the implementation can support low-power state override: 0 The implementation does not support low-power state override" "0,1"
bitfld.long 0x14 22. "ATBTRIG,Indicates if the implementation can support ATB triggers: 0 The implementation does not support ATB triggers" "0,1"
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bitfld.long 0x14 16.--21. "TRACEIDSIZE,Indicates the trace ID width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 12.--15. "RES0_TRCIDR5_15_12,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 9.--11. "NUMEXTINSEL,Indicates how many external input select resources are implemented" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x14 0.--8. 1. "NUMEXTIN,Indicates how many external inputs are implemented"
group.long 0x208++0x37
line.long 0x00 "APBADDR_ETM_CPU1_TRCRSCTLR2,Resource Selection Control Registers 2"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCRSCTLR2_31_22,Reserved RES0"
bitfld.long 0x00 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x00 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x00 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x04 "APBADDR_ETM_CPU1_TRCRSCTLR3,Resource Selection Control Registers 3"
hexmask.long.word 0x04 22.--31. 1. "RES0_TRCRSCTLR3_31_22,Reserved RES0"
bitfld.long 0x04 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x04 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x04 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x08 "APBADDR_ETM_CPU1_TRCRSCTLR4,Resource Selection Control Registers 4"
hexmask.long.word 0x08 22.--31. 1. "RES0_TRCRSCTLR4_31_22,Reserved RES0"
bitfld.long 0x08 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x08 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x08 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x08 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x0C "APBADDR_ETM_CPU1_TRCRSCTLR5,Resource Selection Control Registers 5"
hexmask.long.word 0x0C 22.--31. 1. "RES0_TRCRSCTLR5_31_22,Reserved RES0"
bitfld.long 0x0C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x0C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x0C 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x0C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x10 "APBADDR_ETM_CPU1_TRCRSCTLR6,Resource Selection Control Registers 6"
hexmask.long.word 0x10 22.--31. 1. "RES0_TRCRSCTLR6_31_22,Reserved RES0"
bitfld.long 0x10 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x10 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x10 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x10 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x14 "APBADDR_ETM_CPU1_TRCRSCTLR7,Resource Selection Control Registers 7"
hexmask.long.word 0x14 22.--31. 1. "RES0_TRCRSCTLR7_31_22,Reserved RES0"
bitfld.long 0x14 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x14 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x14 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x14 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x18 "APBADDR_ETM_CPU1_TRCRSCTLR8,Resource Selection Control Registers 8"
hexmask.long.word 0x18 22.--31. 1. "RES0_TRCRSCTLR8_31_22,Reserved RES0"
bitfld.long 0x18 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x18 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x18 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x1C "APBADDR_ETM_CPU1_TRCRSCTLR9,Resource Selection Control Registers 9"
hexmask.long.word 0x1C 22.--31. 1. "RES0_TRCRSCTLR9_31_22,Reserved RES0"
bitfld.long 0x1C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x1C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x1C 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x1C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x20 "APBADDR_ETM_CPU1_TRCRSCTLR10,Resource Selection Control Registers 10"
hexmask.long.word 0x20 22.--31. 1. "RES0_TRCRSCTLR10_31_22,Reserved RES0"
bitfld.long 0x20 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x20 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x20 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x20 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x24 "APBADDR_ETM_CPU1_TRCRSCTLR11,Resource Selection Control Registers 11"
hexmask.long.word 0x24 22.--31. 1. "RES0_TRCRSCTLR11_31_22,Reserved RES0"
bitfld.long 0x24 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x24 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x24 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x24 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x28 "APBADDR_ETM_CPU1_TRCRSCTLR12,Resource Selection Control Registers 12"
hexmask.long.word 0x28 22.--31. 1. "RES0_TRCRSCTLR12_31_22,Reserved RES0"
bitfld.long 0x28 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x28 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x28 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x28 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x2C "APBADDR_ETM_CPU1_TRCRSCTLR13,Resource Selection Control Registers 13"
hexmask.long.word 0x2C 22.--31. 1. "RES0_TRCRSCTLR13_31_22,Reserved RES0"
bitfld.long 0x2C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x2C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x2C 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x2C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x30 "APBADDR_ETM_CPU1_TRCRSCTLR14,Resource Selection Control Registers 14"
hexmask.long.word 0x30 22.--31. 1. "RES0_TRCRSCTLR14_31_22,Reserved RES0"
bitfld.long 0x30 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x30 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x30 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x30 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x34 "APBADDR_ETM_CPU1_TRCRSCTLR15,Resource Selection Control Registers 15"
hexmask.long.word 0x34 22.--31. 1. "RES0_TRCRSCTLR15_31_22,Reserved RES0"
bitfld.long 0x34 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x34 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x34 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x34 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
group.long 0x280++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCSSCCR0,Single-Shot Comparator Control Register 0"
hexmask.long.byte 0x00 25.--31. 1. "RES0_TRCSSCCR0_31_25,Reserved RES0"
bitfld.long 0x00 24. "RST,Controls whether the single-shot comparator resource is reset when it fires" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "ARC,Selects one or more address range comparators for single-shot control.Each bit represents an address range comparator pair so bit[n-16] controls the selection of address range comparator pair n-16"
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hexmask.long.word 0x00 0.--15. 1. "SAC,Selects one or more single address comparators for single-shot control.Each bit represents a single address comparator so bit[n] controls the selection of single address comparator n"
group.long 0x2A0++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCSSCSR0,Single-Shot Comparator Status Register 0"
bitfld.long 0x00 31. "STATUS,Single-shot status bit" "0,1"
hexmask.long 0x00 3.--30. 1. "RES0_TRCSSCSR0_30_3,Reserved RES0"
bitfld.long 0x00 2. "DV,Data value comparator support bit" "0,1"
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bitfld.long 0x00 1. "DA,Data address comparator support bit" "0,1"
bitfld.long 0x00 0. "INST,Instruction address comparator support bit" "0,1"
group.long 0x300++0x07
line.long 0x00 "APBADDR_ETM_CPU1_TRCOSLAR,OS Lock Access Register"
hexmask.long 0x00 1.--31. 1. "RES0_TRCOSLAR_31_1,Reserved RES0"
bitfld.long 0x00 0. "LOCK,OS Lock control bit: 0 Unlocks the OS Lock" "0,1"
line.long 0x04 "APBADDR_ETM_CPU1_TRCOSLSR,OS Lock Status Register"
hexmask.long 0x04 4.--31. 1. "RES0_TRCOSLSR_31_4,Reserved RES0"
bitfld.long 0x04 3. "PRESENT,Indicates whether the OS Lock is implemented.This bit is RES1 which indicates that the OS Lock is always implemented" "0,1"
bitfld.long 0x04 2. "BIT32,This bit is RES0 which indicates that software must perform a 32-bit write to update the TRCOSLAR" "0,1"
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bitfld.long 0x04 1. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked" "0,1"
bitfld.long 0x04 0. "RES0_TRCOSLSR_0_0,Reserved RES0" "0,1"
group.long 0x310++0x07
line.long 0x00 "APBADDR_ETM_CPU1_TRCPDCR,Power Down Control Register"
hexmask.long 0x00 4.--31. 1. "RES0_TRCPDCR_31_4,Reserved RES0"
bitfld.long 0x00 3. "PU,Powerup request bit: 0 The system can remove power from the trace unit" "0,1"
bitfld.long 0x00 0.--2. "RES0_TRCPDCR_2_0,Reserved RES0" "0,1,2,3,4,5,6,7"
line.long 0x04 "APBADDR_ETM_CPU1_TRCPDSR,Power Down Status Register"
hexmask.long 0x04 6.--31. 1. "RES0_TRCPDSR_31_6,Reserved RES0"
bitfld.long 0x04 5. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked" "0,1"
bitfld.long 0x04 2.--4. "RES0_TRCPDSR_4_2,Reserved RES0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 1. "STICKYPD,Sticky powerdown status bit" "0,1"
bitfld.long 0x04 0. "POWER,Power status bit: 0 The trace unit core power domain is not powered" "0,1"
group.long 0x400++0x3F
line.long 0x00 "APBADDR_ETM_CPU1_TRCACVR0_31_0,Address Comparator Value Registers 0 (low word)"
line.long 0x04 "APBADDR_ETM_CPU1_TRCACVR0_63_32,Address Comparator Value Registers 0 (high word)"
line.long 0x08 "APBADDR_ETM_CPU1_TRCACVR1_31_0,Address Comparator Value Registers 1 (low word)"
line.long 0x0C "APBADDR_ETM_CPU1_TRCACVR1_63_32,Address Comparator Value Registers 1 (high word)"
line.long 0x10 "APBADDR_ETM_CPU1_TRCACVR2_31_0,Address Comparator Value Registers 2 (low word)"
line.long 0x14 "APBADDR_ETM_CPU1_TRCACVR2_63_32,Address Comparator Value Registers 2 (high word)"
line.long 0x18 "APBADDR_ETM_CPU1_TRCACVR3_31_0,Address Comparator Value Registers 3 (low word)"
line.long 0x1C "APBADDR_ETM_CPU1_TRCACVR3_63_32,Address Comparator Value Registers 3 (high word)"
line.long 0x20 "APBADDR_ETM_CPU1_TRCACVR4_31_0,Address Comparator Value Registers 4 (low word)"
line.long 0x24 "APBADDR_ETM_CPU1_TRCACVR4_63_32,Address Comparator Value Registers 4 (high word)"
line.long 0x28 "APBADDR_ETM_CPU1_TRCACVR5_31_0,Address Comparator Value Registers 5 (low word)"
line.long 0x2C "APBADDR_ETM_CPU1_TRCACVR5_63_32,Address Comparator Value Registers 5 (high word)"
line.long 0x30 "APBADDR_ETM_CPU1_TRCACVR6_31_0,Address Comparator Value Registers 6 (low word)"
line.long 0x34 "APBADDR_ETM_CPU1_TRCACVR6_63_32,Address Comparator Value Registers 6 (high word)"
line.long 0x38 "APBADDR_ETM_CPU1_TRCACVR7_31_0,Address Comparator Value Registers 7 (low word)"
line.long 0x3C "APBADDR_ETM_CPU1_TRCACVR7_63_32,Address Comparator Value Registers 7 (high word)"
group.long 0x480++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCACATR0,Address Comparator Access Type Registers 0"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR0_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR0_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x488++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCACATR1,Address Comparator Access Type Registers 1"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR1_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR1_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x490++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCACATR2,Address Comparator Access Type Registers 2"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR2_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR2_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x498++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCACATR3,Address Comparator Access Type Registers 3"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR3_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR3_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4A0++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCACATR4,Address Comparator Access Type Registers 4"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR4_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR4_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4A8++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCACATR5,Address Comparator Access Type Registers 5"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR5_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR5_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4B0++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCACATR6,Address Comparator Access Type Registers 6"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR6_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR6_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4B8++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCACATR7,Address Comparator Access Type Registers 7"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR7_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR7_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x600++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCCIDCVR0,Context ID Comparator Value Register 0"
group.long 0x640++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCVMIDCVR0,VMID Comparator Value Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "VALUE,Contains a VMID value"
group.long 0x680++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCCIDCCTLR0,Context ID Comparator Control Register 0"
group.long 0xEE4++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCITATBIDR,Integration ATB Identification Register"
hexmask.long 0x00 7.--31. 1. "RES0_TRCITATBIDR_31_7,Reserved RES0"
hexmask.long.byte 0x00 0.--6. 1. "ID,Drives the ATIDMn[6:0] output pins"
group.long 0xEEC++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCITIDATAR,Integration Instruction ATB Data Register"
hexmask.long 0x00 5.--31. 1. "RES0_TRCITIDATAR_31_5,Reserved RES0"
bitfld.long 0x00 4. "ATDATAM_31,Drives the ATDATAM[31] output" "0,1"
bitfld.long 0x00 3. "ATDATAM_23,Drives the ATDATAM[23] output" "0,1"
newline
bitfld.long 0x00 2. "ATDATAM_15,Drives the ATDATAM[15] output" "0,1"
bitfld.long 0x00 1. "ATDATAM_7,Drives the ATDATAM[7] output" "0,1"
bitfld.long 0x00 0. "ATDATAM_0,Drives the ATDATAM[0] output" "0,1"
group.long 0xEF4++0x03
line.long 0x00 "APBADDR_ETM_CPU1_TRCITIATBINR,Integration Instruction ATB In Register"
hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved"
bitfld.long 0x00 1. "AFVALIDM,Returns the value of the AFVALIDMn input pin" "0,1"
bitfld.long 0x00 0. "ATREADYM,Returns the value of the ATREADYMn input pin" "0,1"
group.long 0xEFC++0x07
line.long 0x00 "APBADDR_ETM_CPU1_TRCITIATBOUTR,Integration Instruction ATB Out Register"
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
bitfld.long 0x00 8.--9. "BYTES,Drives the ATBYTESMn[1:0] output pins" "0,1,2,3"
bitfld.long 0x00 2.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 1. "AFREADY,Drives the AFREADYMn output pin" "0,1"
bitfld.long 0x00 0. "ATVALID,Drives the ATVALIDMn output pin" "0,1"
line.long 0x04 "APBADDR_ETM_CPU1_TRCITCTRL,Integration Mode Control Register"
hexmask.long 0x04 1.--31. 1. "RES0_TRCITCTRL_31_1,Reserved RES0"
bitfld.long 0x04 0. "ITEN,Integration mode enable bit: 0 The trace unit is not in integration mode" "0,1"
group.long 0xFA0++0x1F
line.long 0x00 "APBADDR_ETM_CPU1_TRCCLAIMSET,Claim Tag Set Register"
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--3. "SET,Sets bits in the claim tag and determines the number of claim tag bits implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_ETM_CPU1_TRCCLAIMCLR,Claim Tag Clear Register"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "CLR,Clears bits in the claim tag and determines the current value of the claim tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_ETM_CPU1_TRCDEVAFF0,Device Affinity Register 0"
line.long 0x0C "APBADDR_ETM_CPU1_TRCDEVAFF1,Device Affinity Register 1"
line.long 0x10 "APBADDR_ETM_CPU1_TRCLAR,Software Lock Access Register"
line.long 0x14 "APBADDR_ETM_CPU1_TRCLSR,Software Lock Status Register"
hexmask.long 0x14 3.--31. 1. "RES0_TRCLSR_31_3,Reserved RES0"
bitfld.long 0x14 2. "NTT,Not thirty-two bit access required" "0,1"
bitfld.long 0x14 1. "SLK,Software lock status for this component" "0,1"
newline
bitfld.long 0x14 0. "SLI,Software lock implemented" "0,1"
line.long 0x18 "APBADDR_ETM_CPU1_TRCAUTHSTATUS,Authentication Status Register"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCAUTHSTATUS_31_8,Reserved RES0"
bitfld.long 0x18 6.--7. "SNID,Indicates whether the system enables the trace unit to support Secure non-invasive debug: 00 The trace unit does not implement support for Secure non-invasive debug" "0,1,2,3"
bitfld.long 0x18 4.--5. "SID,Indicates whether the trace unit supports Secure invasive debug: 00 The trace unit does not support Secure invasive debug" "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "NSNID,Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: 00 The trace unit does not implement support for Non-secure non-invasive debug" "0,1,2,3"
bitfld.long 0x18 0.--1. "NSID,Indicates whether the trace unit supports Non-secure invasive debug: 00 The trace unit does not support Non-secure invasive debug" "0,1,2,3"
line.long 0x1C "APBADDR_ETM_CPU1_TRCDEVARCH,Device Architecture Register"
hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is RAO" "0,1"
bitfld.long 0x1C 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
group.long 0xFC8++0x37
line.long 0x00 "APBADDR_ETM_CPU1_TRCDEVID,Device ID Register"
line.long 0x04 "APBADDR_ETM_CPU1_TRCDEVTYPE,Device Type Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_TRCDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "SUB,Returns 0x1 to indicate that the ETM generates processor trace.All other values are reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "MAIN,Returns 0x3 to indicate that the ETM is a trace source.All other values are reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_ETM_CPU1_TRCPIDR4,Peripheral Identification Register 4"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_TRCPIDR4_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--3. "DES_2,Designer JEP106 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_ETM_CPU1_TRCPIDR5,Peripheral Identification Register 5"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_TRCPIDR5_31_8,Reserved RES0"
hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,RES0 reserved for future use"
line.long 0x10 "APBADDR_ETM_CPU1_TRCPIDR6,Peripheral Identification Register 6"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_TRCPIDR6_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "RESERVED,RES0 reserved for future use"
line.long 0x14 "APBADDR_ETM_CPU1_TRCPIDR7,Peripheral Identification Register 7"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_TRCPIDR7_31_8,Reserved RES0"
hexmask.long.byte 0x14 0.--7. 1. "RESERVED,RES0 reserved for future use"
line.long 0x18 "APBADDR_ETM_CPU1_TRCPIDR0,Peripheral Identification Register 0"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PART_0,Part number bits[7:0]"
line.long 0x1C "APBADDR_ETM_CPU1_TRCPIDR1,Peripheral Identification Register 1"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_TRCPIDR1_31_8,Reserved RES0"
bitfld.long 0x1C 4.--7. "DES_0,Designer bits[3:0] of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "PART_1,Part number bits[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "APBADDR_ETM_CPU1_TRCPIDR2,Peripheral Identification Register 2"
hexmask.long.tbyte 0x20 8.--31. 1. "RES0_TRCPIDR2_31_8,Reserved RES0"
bitfld.long 0x20 4.--7. "REVISION,The IMPLEMENTATION DEFINED revision number for the ETM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 3. "JEDEC,RAO" "0,1"
newline
bitfld.long 0x20 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x24 "APBADDR_ETM_CPU1_TRCPIDR3,Peripheral Identification Register 3"
hexmask.long.tbyte 0x24 8.--31. 1. "RES0_TRCPIDR3_31_8,Reserved RES0"
bitfld.long 0x24 4.--7. "REVAND,The IMPLEMENTATION DEFINED manufacturing revision number for the implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "APBADDR_ETM_CPU1_TRCCIDR0,Component Identification Register 0"
hexmask.long.tbyte 0x28 8.--31. 1. "RES0_TRCCIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x28 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x2C "APBADDR_ETM_CPU1_TRCCIDR1,Component Identification Register 1"
hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_TRCCIDR1_31_8,Reserved RES0"
bitfld.long 0x2C 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "APBADDR_ETM_CPU1_TRCCIDR2,Component Identification Register 2"
hexmask.long.tbyte 0x30 8.--31. 1. "RES0_TRCCIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x30 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x34 "APBADDR_ETM_CPU1_TRCCIDR3,Component Identification Register 3"
hexmask.long.tbyte 0x34 8.--31. 1. "RES0_TRCCIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x34 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_CORE1_PMU"
base ad:0x730120000
group.long 0x00++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMEVCNTR0_EL0,Performance Monitors Event Count Register 0"
group.long 0x08++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMEVCNTR1_EL0,Performance Monitors Event Count Register 1"
group.long 0x10++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMEVCNTR2_EL0,Performance Monitors Event Count Register 2"
group.long 0x18++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMEVCNTR3_EL0,Performance Monitors Event Count Register 3"
group.long 0x20++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMEVCNTR4_EL0,Performance Monitors Event Count Register 4"
group.long 0x28++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMEVCNTR5_EL0,Performance Monitors Event Count Register 5"
group.long 0xF8++0x07
line.long 0x00 "APBADDR_PMU_CPU1_PMCCNTR_EL0_31_0,Performance Monitors Cycle Counter (low word)"
line.long 0x04 "APBADDR_PMU_CPU1_PMCCNTR_EL0_63_32,Performance Monitors Cycle Counter (high word)"
group.long 0x400++0x17
line.long 0x00 "APBADDR_PMU_CPU1_PMEVTYPER0_EL0,Performance Monitors Event Type Register 0"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x00 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x00 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x00 10.--25. 1. "RES0_PMEVTYPER0_EL0_25_10,Reserved RES0"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x04 "APBADDR_PMU_CPU1_PMEVTYPER1_EL0,Performance Monitors Event Type Register 1"
bitfld.long 0x04 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x04 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x04 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x04 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x04 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x04 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x04 10.--25. 1. "RES0_PMEVTYPER1_EL0_25_10,Reserved RES0"
hexmask.long.word 0x04 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x08 "APBADDR_PMU_CPU1_PMEVTYPER2_EL0,Performance Monitors Event Type Register 2"
bitfld.long 0x08 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x08 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x08 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x08 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x08 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x08 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x08 10.--25. 1. "RES0_PMEVTYPER2_EL0_25_10,Reserved RES0"
hexmask.long.word 0x08 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x0C "APBADDR_PMU_CPU1_PMEVTYPER3_EL0,Performance Monitors Event Type Register 3"
bitfld.long 0x0C 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x0C 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x0C 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x0C 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x0C 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x0C 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x0C 10.--25. 1. "RES0_PMEVTYPER3_EL0_25_10,Reserved RES0"
hexmask.long.word 0x0C 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x10 "APBADDR_PMU_CPU1_PMEVTYPER4_EL0,Performance Monitors Event Type Register 4"
bitfld.long 0x10 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x10 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x10 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x10 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x10 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x10 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x10 10.--25. 1. "RES0_PMEVTYPER4_EL0_25_10,Reserved RES0"
hexmask.long.word 0x10 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x14 "APBADDR_PMU_CPU1_PMEVTYPER5_EL0,Performance Monitors Event Type Register 5"
bitfld.long 0x14 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x14 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x14 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x14 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x14 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x14 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x14 10.--25. 1. "RES0_PMEVTYPER5_EL0_25_10,Reserved RES0"
hexmask.long.word 0x14 0.--9. 1. "EVTCOUNT,Event to count"
group.long 0x47C++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMCCFILTR_EL0,Performance Monitors Cycle Counter Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x00 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x00 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long 0x00 0.--25. 1. "RES0_PMCCFILTR_EL0_25_0,Reserved RES0"
group.long 0xC00++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMCNTENSET_EL0,Performance Monitors Count Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 enable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter enable bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xC20++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMCNTENCLR_EL0,Performance Monitors Count Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 disable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter disable bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xC40++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMINTENSET_EL1,Performance Monitors Interrupt Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow interrupt request enable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow interrupt request enable bit for PMEVCNTR<x>_EL0.N is the value in PMCR_EL0.N"
group.long 0xC60++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMINTENCLR_EL1,Performance Monitors Interrupt Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow interrupt request disable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow interrupt request disable bit for PMEVCNTR<x>_EL0.N is the value in PMCR_EL0.N"
group.long 0xC80++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow clear bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xCA0++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMSWINC_EL0,Performance Monitors Software Increment Register"
hexmask.long 0x00 6.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--5. "P_X,Event counter software increment bit for PMEVCNTR<x>" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xCC0++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMOVSSET_EL0,Performance Monitors Overflow Flag Status Set Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow set bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xE00++0x07
line.long 0x00 "APBADDR_PMU_CPU1_PMCFGR,Performance Monitors Configuration Register"
hexmask.long.word 0x00 20.--31. 1. "RES0_PMCFGR_31_20,Reserved RES0"
bitfld.long 0x00 19. "UEN,User-mode Enable Register supported" "0,1"
bitfld.long 0x00 18. "WT,This feature is not supported so this bit is RES0" "0,1"
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bitfld.long 0x00 17. "NA,This feature is not supported so this bit is RES0" "0,1"
bitfld.long 0x00 16. "EX,Export supported" "0,1"
bitfld.long 0x00 15. "CCD,Cycle counter has prescale" "0,1"
newline
bitfld.long 0x00 14. "CC,Dedicated cycle counter [counter 31] supported" "0,1"
bitfld.long 0x00 8.--13. "SIZE,Size of counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 0.--7. 1. "N,Number of counters implemented in addition to the cycle counter PMCCNTR_EL0"
line.long 0x04 "APBADDR_PMU_CPU1_PMCR_EL0,Performance Monitors Control Register"
hexmask.long.tbyte 0x04 11.--31. 1. "RES0_PMCR_EL0_31_11,Reserved RAZ/WI"
bitfld.long 0x04 7.--10. "RES0_PMCR_EL0_10_7,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "LC,Long cycle counter enable" "0,1"
newline
bitfld.long 0x04 5. "DP,Disable cycle counter when event counting is prohibited" "0,1"
bitfld.long 0x04 4. "X,Enable export of events in an IMPLEMENTATION DEFINED event stream" "0,1"
bitfld.long 0x04 3. "D,Clock divider" "0,1"
newline
bitfld.long 0x04 2. "C,Cycle counter reset" "0,1"
bitfld.long 0x04 1. "P,Event counter reset" "0,1"
bitfld.long 0x04 0. "E,Enable" "0,1"
group.long 0xE20++0x07
line.long 0x00 "APBADDR_PMU_CPU1_PMCEID0_EL0,Performance Monitors Common Event Identification Register 0"
line.long 0x04 "APBADDR_PMU_CPU1_PMCEID1_EL0,Performance Monitors Common Event Identification Register 1"
hexmask.long 0x04 1.--31. 1. "RES0_PMCEID1_EL0_31_1,Reserved RES0"
bitfld.long 0x04 0. "CE_32,Common architectural and microarchitectural feature events that can be counted by the PMU event counters.For the bit described in the following table the event is implemented if the bit is set to 1 or not implemented if the bit is set to.." "0,1"
group.long 0xF00++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMITCTRL,Performance Monitors Integration mode Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_PMITCTRL_31_1,Reserved RES0"
bitfld.long 0x00 0. "IME,Integration mode enable" "0,1"
group.long 0xFA8++0x17
line.long 0x00 "APBADDR_PMU_CPU1_PMDEVAFF0,Performance Monitors Device Affinity Register 0"
line.long 0x04 "APBADDR_PMU_CPU1_PMDEVAFF1,Performance Monitors Device Affinity Register 1"
line.long 0x08 "APBADDR_PMU_CPU1_PMLAR,Performance Monitors Lock Access Register"
line.long 0x0C "APBADDR_PMU_CPU1_PMLSR,Performance Monitors Lock Status Register"
hexmask.long 0x0C 3.--31. 1. "RES0_PMLSR_31_3,Reserved RES0"
bitfld.long 0x0C 2. "NTT,Not thirty-two bit access required" "0,1"
bitfld.long 0x0C 1. "SLK,Software lock status for this component" "0,1"
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bitfld.long 0x0C 0. "SLI,Software lock implemented" "0,1"
line.long 0x10 "APBADDR_PMU_CPU1_PMAUTHSTATUS,Performance Monitors Authentication Status Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_PMAUTHSTATUS_31_8,Reserved RES0"
bitfld.long 0x10 6.--7. "SNID,Holds the same value as DBGAUTHSTATUS_EL1.SNID" "0,1,2,3"
bitfld.long 0x10 4.--5. "RES0_PMAUTHSTATUS_5_4,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x10 2.--3. "NSNID,Holds the same value as DBGAUTHSTATUS_EL1.NSNID" "0,1,2,3"
bitfld.long 0x10 0.--1. "RES0_PMAUTHSTATUS_1_0,Reserved RES0" "0,1,2,3"
line.long 0x14 "APBADDR_PMU_CPU1_PMDEVARCH,Performance Monitors Device Architecture Register"
hexmask.long.word 0x14 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x14 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A" "0,1"
bitfld.long 0x14 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x14 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
group.long 0xFCC++0x07
line.long 0x00 "APBADDR_PMU_CPU1_PMDEVTYPE,Performance Monitors Device Type Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_PMDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x00 4.--7. "SUB,Subtype" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "MAJOR,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_PMU_CPU1_PMPIDR4,Performance Monitors Peripheral Identification Register 4"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_PMPIDR4_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "DES_2,Designer JEP106 continuation code least significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
group.long ($2+0xFD4)++0x03
line.long 0x00 "APBADDR_PMU_CPU1_PMPIDR$1,Performance Monitors Peripheral Identification Register 5"
repeat.end
group.long 0xFE0++0x1F
line.long 0x00 "APBADDR_PMU_CPU1_PMPIDR0,Performance Monitors Peripheral Identification Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_PMPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number least significant byte"
line.long 0x04 "APBADDR_PMU_CPU1_PMPIDR1,Performance Monitors Peripheral Identification Register 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_PMPIDR1_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "DES_0,Designer least significant nibble of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "PART_1,Part number most significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_PMU_CPU1_PMPIDR2,Performance Monitors Peripheral Identification Register 2"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_PMPIDR2_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "REVISION,Part major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3. "JEDEC,RAO" "0,1"
newline
bitfld.long 0x08 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x0C "APBADDR_PMU_CPU1_PMPIDR3,Performance Monitors Peripheral Identification Register 3"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_PMPIDR3_31_8,Reserved RES0"
bitfld.long 0x0C 4.--7. "REVAND,Part minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_PMU_CPU1_PMCIDR0,Performance Monitors Component Identification Register 0"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_PMCIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x14 "APBADDR_PMU_CPU1_PMCIDR1,Performance Monitors Component Identification Register 1"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_PMCIDR1_31_8,Reserved RES0"
bitfld.long 0x14 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_PMU_CPU1_PMCIDR2,Performance Monitors Component Identification Register 2"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_PMCIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x1C "APBADDR_PMU_CPU1_PMCIDR3,Performance Monitors Component Identification Register 3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_PMCIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_CORE2_CTI"
base ad:0x730240000
group.long 0x00++0x03
line.long 0x00 "APBADDR_CTI_CPU2_CTICONTROL,CTI Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_CTICONTROL_31_1,Reserved RES0"
bitfld.long 0x00 0. "GLBEN,Enables or disables the CTI mapping functions" "0,1"
group.long 0x10++0x2F
line.long 0x00 "APBADDR_CTI_CPU2_CTIINTACK,CTI Output Trigger Acknowledge Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "ACK_N,Can be used to create soft acknowledges for output triggers"
line.long 0x04 "APBADDR_CTI_CPU2_CTIAPPSET,CTI Application Trigger Set Register"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "CTIAPPSETX,Application trigger <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU2_CTIAPPCLEAR,CTI Application Trigger Clear Register"
hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x08 0.--3. "CTIAPPCLEARX,Application trigger <x> disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_CTI_CPU2_CTIAPPPULSE,CTI Application Pulse Register"
hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x0C 0.--3. "CTIAPPPULSEX,Generate event pulse on ECT channel <x>" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU2_CTIINEN0,CTI Input Trigger to Output Channel Enable Register 0"
hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x10 0.--3. "INENX,Input trigger 0 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_CTI_CPU2_CTIINEN1,CTI Input Trigger to Output Channel Enable Register 1"
hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x14 0.--3. "INENX,Input trigger 1 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_CTI_CPU2_CTIINEN2,CTI Input Trigger to Output Channel Enable Register 2"
hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x18 0.--3. "INENX,Input trigger 2 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "APBADDR_CTI_CPU2_CTIINEN3,CTI Input Trigger to Output Channel Enable Register 3"
hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x1C 0.--3. "INENX,Input trigger 3 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "APBADDR_CTI_CPU2_CTIINEN4,CTI Input Trigger to Output Channel Enable Register 4"
hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x20 0.--3. "INENX,Input trigger 4 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "APBADDR_CTI_CPU2_CTIINEN5,CTI Input Trigger to Output Channel Enable Register 5"
hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x24 0.--3. "INENX,Input trigger 5 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "APBADDR_CTI_CPU2_CTIINEN6,CTI Input Trigger to Output Channel Enable Register 6"
hexmask.long 0x28 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x28 0.--3. "INENX,Input trigger 6 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "APBADDR_CTI_CPU2_CTIINEN7,CTI Input Trigger to Output Channel Enable Register 7"
hexmask.long 0x2C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x2C 0.--3. "INENX,Input trigger 7 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0++0x1F
line.long 0x00 "APBADDR_CTI_CPU2_CTIOUTEN0,CTI Input Channel to Output Trigger Enable Register 0"
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--3. "OUTENX,Input channel <x> to output trigger 0 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_CTI_CPU2_CTIOUTEN1,CTI Input Channel to Output Trigger Enable Register 1"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "OUTENX,Input channel <x> to output trigger 1 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU2_CTIOUTEN2,CTI Input Channel to Output Trigger Enable Register 2"
hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x08 0.--3. "OUTENX,Input channel <x> to output trigger 2 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_CTI_CPU2_CTIOUTEN3,CTI Input Channel to Output Trigger Enable Register 3"
hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x0C 0.--3. "OUTENX,Input channel <x> to output trigger 3 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU2_CTIOUTEN4,CTI Input Channel to Output Trigger Enable Register 4"
hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x10 0.--3. "OUTENX,Input channel <x> to output trigger 4 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_CTI_CPU2_CTIOUTEN5,CTI Input Channel to Output Trigger Enable Register 5"
hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x14 0.--3. "OUTENX,Input channel <x> to output trigger 5 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_CTI_CPU2_CTIOUTEN6,CTI Input Channel to Output Trigger Enable Register 6"
hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x18 0.--3. "OUTENX,Input channel <x> to output trigger 6 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "APBADDR_CTI_CPU2_CTIOUTEN7,CTI Input Channel to Output Trigger Enable Register 7"
hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x1C 0.--3. "OUTENX,Input channel <x> to output trigger 7 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x130++0x17
line.long 0x00 "APBADDR_CTI_CPU2_CTITRIGINSTATUS,CTI Trigger In Status Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "TRINN,Provides the status of the trigger inputs"
line.long 0x04 "APBADDR_CTI_CPU2_CTITRIGOUTSTATUS,CTI Trigger Out Status Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x04 0.--7. 1. "TROUTN,Provides the status of the trigger outputs"
line.long 0x08 "APBADDR_CTI_CPU2_CTICHINSTATUS,CTI Channel In Status Register"
hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x08 0.--3. "CHINN,Provides the raw status of the ECT channel inputs to the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_CTI_CPU2_CTICHOUTSTATUS,CTI Channel Out Status Register"
hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x0C 0.--3. "CHOUTN,Provides the status of the ECT channel outputs from the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU2_CTIGATE,CTI Channel Gate Enable Register"
hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x10 0.--3. "GATEX,Determines whether events on channels propagate through the CTM to other ECT components or from the CTM into the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_CTI_CPU2_ASICCTL,CTI External Multiplexor Control register"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_ASICCTL_31_8,Reserved RES0"
hexmask.long.byte 0x14 0.--7. 1. "ASICCTL,IMPLEMENTATION DEFINED ASIC control"
group.long 0xF00++0x03
line.long 0x00 "APBADDR_CTI_CPU2_CTIITCTRL,CTI Integration mode Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_CTIITCTRL_31_1,Reserved RES0"
bitfld.long 0x00 0. "IME,Integration mode enable" "0,1"
group.long 0xFA0++0x33
line.long 0x00 "APBADDR_CTI_CPU2_CTICLAIMSET,CTI Claim Set"
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--3. "CLAIMX,CLAIM tag set bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_CTI_CPU2_CTICLAIMCLR,CTI Claim Clear"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "CLAIMX,Clear CLAIM tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU2_CTIDEVAFF0,CTI Device Affinity Register 0"
line.long 0x0C "APBADDR_CTI_CPU2_CTIDEVAFF1,CTI Device Affinity Register 1"
line.long 0x10 "APBADDR_CTI_CPU2_CTILAR,CTI Lock Access Register"
line.long 0x14 "APBADDR_CTI_CPU2_CTILSR,CTI Lock Status Register"
hexmask.long 0x14 3.--31. 1. "RES0_CTILSR_31_3,Reserved RES0"
bitfld.long 0x14 2. "NTT,Not thirty-two bit access required" "0,1"
bitfld.long 0x14 1. "SLK,Software lock status for this component" "0,1"
newline
bitfld.long 0x14 0. "SLI,Software lock implemented" "0,1"
line.long 0x18 "APBADDR_CTI_CPU2_CTIAUTHSTATUS,CTI Authentication Status Register"
hexmask.long 0x18 4.--31. 1. "RES0_CTIAUTHSTATUS_31_4,Reserved RES0"
bitfld.long 0x18 2.--3. "NSNID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SNID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSNID" "0,1,2,3"
bitfld.long 0x18 0.--1. "NSID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSID" "0,1,2,3"
line.long 0x1C "APBADDR_CTI_CPU2_CTIDEVARCH,CTI Device Architecture Register"
hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A" "0,1"
bitfld.long 0x1C 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
line.long 0x20 "APBADDR_CTI_CPU2_CTIDEVID2,CTI Device ID Register 2"
line.long 0x24 "APBADDR_CTI_CPU2_CTIDEVID1,CTI Device ID Register 1"
line.long 0x28 "APBADDR_CTI_CPU2_CTIDEVID,CTI Device ID Register 0"
bitfld.long 0x28 26.--31. "RES0_CTIDEVID_31_26,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x28 24.--25. "INOUT,Input/output options" "0,1,2,3"
bitfld.long 0x28 22.--23. "RES0_CTIDEVID_23_22,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x28 16.--21. "NUMCHAN,Number of ECT channels implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x28 14.--15. "RES0_CTIDEVID_15_14,Reserved RES0" "0,1,2,3"
bitfld.long 0x28 8.--13. "NUMTRIG,Number of triggers implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x28 5.--7. "RES0_CTIDEVID_7_5,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x28 0.--4. "EXTMUXNUM,Maximum number of external triggers available for multiplexing into the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x2C "APBADDR_CTI_CPU2_CTIDEVTYPE,CTI Device Type Register"
hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_CTIDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x2C 4.--7. "SUB,Subtype" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 0.--3. "MAJOR,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "APBADDR_CTI_CPU2_CTIPIDR4,CTI Peripheral Identification Register 4"
hexmask.long.tbyte 0x30 8.--31. 1. "RES0_CTIPIDR4_31_8,Reserved RES0"
bitfld.long 0x30 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 0.--3. "DES_2,Designer JEP106 continuation code least significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
group.long ($2+0xFD4)++0x03
line.long 0x00 "APBADDR_CTI_CPU2_CTIPIDR$1,CTI Peripheral Identification Register 5"
repeat.end
group.long 0xFE0++0x1F
line.long 0x00 "APBADDR_CTI_CPU2_CTIPIDR0,CTI Peripheral Identification Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_CTIPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number least significant byte"
line.long 0x04 "APBADDR_CTI_CPU2_CTIPIDR1,CTI Peripheral Identification Register 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_CTIPIDR1_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "DES_0,Designer least significant nibble of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "PART_1,Part number most significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU2_CTIPIDR2,CTI Peripheral Identification Register 2"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_CTIPIDR2_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "REVISION,Part major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3. "JEDEC,RAO" "0,1"
newline
bitfld.long 0x08 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x0C "APBADDR_CTI_CPU2_CTIPIDR3,CTI Peripheral Identification Register 3"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_CTIPIDR3_31_8,Reserved RES0"
bitfld.long 0x0C 4.--7. "REVAND,Part minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU2_CTICIDR0,CTI Component Identification Register 0"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_CTICIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x14 "APBADDR_CTI_CPU2_CTICIDR1,CTI Component Identification Register 1"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_CTICIDR1_31_8,Reserved RES0"
bitfld.long 0x14 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_CTI_CPU2_CTICIDR2,CTI Component Identification Register 2"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_CTICIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x1C "APBADDR_CTI_CPU2_CTICIDR3,CTI Component Identification Register 3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_CTICIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_CORE2_DBG"
base ad:0x730210000
group.long 0x20++0x07
line.long 0x00 "APBADDR_DBG_CPU2_EDESR,External Debug Event Status Register"
hexmask.long 0x00 3.--31. 1. "RES0_EDESR_31_3,Reserved RES0"
bitfld.long 0x00 2. "SS,Halting step debug event pending" "0,1"
newline
bitfld.long 0x00 1. "RC,Reset catch debug event pending" "0,1"
bitfld.long 0x00 0. "OSUC,OS unlock debug event pending" "0,1"
line.long 0x04 "APBADDR_DBG_CPU2_EDECR,External Debug Execution Control Register"
hexmask.long 0x04 3.--31. 1. "RES0_EDECR_31_3,Reserved RES0"
bitfld.long 0x04 2. "SS,Halting step enable" "0,1"
newline
bitfld.long 0x04 1. "RCE,Reset catch enable" "0,1"
bitfld.long 0x04 0. "OSUCE,OS unlock catch enabled" "0,1"
group.long 0x30++0x07
line.long 0x00 "APBADDR_DBG_CPU2_EDWAR_31_0,External Debug Watchpoint Address Register (low word)"
line.long 0x04 "APBADDR_DBG_CPU2_EDWAR_63_32,External Debug Watchpoint Address Register (high word)"
group.long 0x80++0x1B
line.long 0x00 "APBADDR_DBG_CPU2_DBGDTRRX_EL0,Debug Data Transfer Register Receive"
line.long 0x04 "APBADDR_DBG_CPU2_EDITR,External Debug Instruction Transfer Register"
line.long 0x08 "APBADDR_DBG_CPU2_EDSCR,External Debug Status and Control Register"
bitfld.long 0x08 31. "RES0_EDSCR_31_31,Reserved RES0" "0,1"
bitfld.long 0x08 30. "RXFULL,DTRRX full" "0,1"
newline
bitfld.long 0x08 29. "TXFULL,DTRTX full" "0,1"
bitfld.long 0x08 28. "ITO,EDITR overrun" "0,1"
newline
bitfld.long 0x08 27. "RXO,DTRRX overrun" "0,1"
bitfld.long 0x08 26. "TXU,DTRTX underrun" "0,1"
newline
bitfld.long 0x08 25. "PIPEADV,Pipeline advance" "0,1"
bitfld.long 0x08 24. "ITE,ITR empty" "0,1"
newline
bitfld.long 0x08 22.--23. "INTDIS,Interrupt disable" "0,1,2,3"
bitfld.long 0x08 21. "TDA,Trap debug registers accesses" "0,1"
newline
bitfld.long 0x08 20. "MA,Memory access mode" "0,1"
bitfld.long 0x08 19. "RES0_EDSCR_19_19,Reserved RES0" "0,1"
newline
bitfld.long 0x08 18. "NS,Non-secure status" "0,1"
bitfld.long 0x08 17. "RES0_EDSCR_17_17,Reserved RES0" "0,1"
newline
bitfld.long 0x08 16. "SDD,Secure debug disabled" "0,1"
bitfld.long 0x08 15. "RES0_EDSCR_15_15,Reserved RES0" "0,1"
newline
bitfld.long 0x08 14. "HDE,Halting debug mode enable" "0,1"
bitfld.long 0x08 10.--13. "RW,Exception level register-width status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 8.--9. "EL,Exception level" "0,1,2,3"
bitfld.long 0x08 7. "A,System Error interrupt pending" "0,1"
newline
bitfld.long 0x08 6. "ERR,Cumulative error flag" "0,1"
bitfld.long 0x08 0.--5. "STATUS,Debug status flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "APBADDR_DBG_CPU2_DBGDTRTX_EL0,Debug Data Transfer Register Transmit"
line.long 0x10 "APBADDR_DBG_CPU2_EDRCR,External Debug Reserve Control Register"
hexmask.long 0x10 5.--31. 1. "RES0_EDRCR_31_5,Reserved RES0"
bitfld.long 0x10 4. "CBRRQ,Allow imprecise entry to Debug state" "0,1"
newline
bitfld.long 0x10 3. "CSPA,Clear Sticky Pipeline Advance" "0,1"
bitfld.long 0x10 2. "CSE,Clear Sticky Error" "0,1"
newline
bitfld.long 0x10 0.--1. "RES0_EDRCR_1_0,Reserved RES0" "0,1,2,3"
line.long 0x14 "APBADDR_DBG_CPU2_EDACR,External Debug Auxiliary Control Register"
line.long 0x18 "APBADDR_DBG_CPU2_EDECCR,External Debug Exception Catch Control Register"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDECCR_31_8,Reserved RES0"
bitfld.long 0x18 4.--7. "NSE,Coarse-grained Non-secure exception catch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 0.--3. "SE,Coarse-grained Secure exception catch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0++0x0F
line.long 0x00 "APBADDR_DBG_CPU2_EDPCSR_31_0,External Debug Program Counter Sample Register (low word)"
line.long 0x04 "APBADDR_DBG_CPU2_EDCIDSR,External Debug Context ID Sample Register"
line.long 0x08 "APBADDR_DBG_CPU2_EDVIDSR,External Debug Virtual Context Sample Register"
bitfld.long 0x08 31. "NS,Non-secure state sample" "0,1"
bitfld.long 0x08 30. "E2,Exception level 2 status sample" "0,1"
newline
bitfld.long 0x08 29. "E3,Exception level 3 status sample" "0,1"
bitfld.long 0x08 28. "HV,EDPCSR high half valid" "0,1"
newline
hexmask.long.tbyte 0x08 8.--27. 1. "RES0_EDVIDSR_27_8,Reserved RES0"
hexmask.long.byte 0x08 0.--7. 1. "VMID,VMID sample"
line.long 0x0C "APBADDR_DBG_CPU2_EDPCSR_63_32,External Debug Program Counter Sample Register (high word)"
group.long 0x300++0x03
line.long 0x00 "APBADDR_DBG_CPU2_OSLAR_EL1,OS Lock Access Register"
hexmask.long 0x00 1.--31. 1. "RES0_OSLAR_EL1_31_1,Reserved RES0"
bitfld.long 0x00 0. "OSLK,On writes to OSLAR_EL1 bit[0] is copied to the OS lock.Use EDPRSR.OSLK to check the current status of the lock" "0,1"
group.long 0x310++0x07
line.long 0x00 "APBADDR_DBG_CPU2_EDPRCR,External Debug Power/Reset Control Register"
hexmask.long 0x00 4.--31. 1. "RES0_EDPRCR_31_4,Reserved RES0"
bitfld.long 0x00 3. "COREPURQ,Core powerup request" "0,1"
newline
bitfld.long 0x00 2. "RES0_EDPRCR_2_2,Reserved RES0" "0,1"
bitfld.long 0x00 1. "CWRR,Warm reset request" "0,1"
newline
bitfld.long 0x00 0. "CORENPDRQ,Core no powerdown request" "0,1"
line.long 0x04 "APBADDR_DBG_CPU2_EDPRSR,External Debug Processor Status Register"
hexmask.long.tbyte 0x04 12.--31. 1. "RES0_EDPRSR_31_12,Reserved RES0"
bitfld.long 0x04 11. "SDR,Sticky debug restart" "0,1"
newline
bitfld.long 0x04 10. "SPMAD,Sticky EPMAD error" "0,1"
bitfld.long 0x04 9. "EPMAD,External performance monitors access disable status" "0,1"
newline
bitfld.long 0x04 8. "SDAD,Sticky EDAD error" "0,1"
bitfld.long 0x04 7. "EDAD,External debug access disable status" "0,1"
newline
bitfld.long 0x04 6. "DLK,OS Double Lock status bit" "0,1"
bitfld.long 0x04 5. "OSLK,OS lock status bit" "0,1"
newline
bitfld.long 0x04 4. "HALTED,Halted status bit" "0,1"
bitfld.long 0x04 3. "SR,Sticky core reset status bit" "0,1"
newline
bitfld.long 0x04 2. "R,Core reset status bit" "0,1"
bitfld.long 0x04 1. "SPD,Sticky core power-down status bit.This bit is set to 1 on Cold reset to indicate the state of the debug registers has been lost" "0,1"
newline
bitfld.long 0x04 0. "PU,Core power-up status bit" "0,1"
group.long 0x400++0x0B
line.long 0x00 "APBADDR_DBG_CPU2_DBGBVR0_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU2_DBGBVR0_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU2_DBGBCR0_EL1,Debug Breakpoint Control Register 0"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR0_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR0_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR0_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x410++0x0B
line.long 0x00 "APBADDR_DBG_CPU2_DBGBVR1_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU2_DBGBVR1_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU2_DBGBCR1_EL1,Debug Breakpoint Control Register 1"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR1_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR1_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR1_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x420++0x0B
line.long 0x00 "APBADDR_DBG_CPU2_DBGBVR2_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU2_DBGBVR2_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU2_DBGBCR2_EL1,Debug Breakpoint Control Register 2"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR2_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR2_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR2_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x430++0x0B
line.long 0x00 "APBADDR_DBG_CPU2_DBGBVR3_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU2_DBGBVR3_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU2_DBGBCR3_EL1,Debug Breakpoint Control Register 3"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR3_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR3_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR3_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x440++0x0B
line.long 0x00 "APBADDR_DBG_CPU2_DBGBVR4_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU2_DBGBVR4_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU2_DBGBCR4_EL1,Debug Breakpoint Control Register 4"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR4_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
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bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR4_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR4_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x450++0x0B
line.long 0x00 "APBADDR_DBG_CPU2_DBGBVR5_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU2_DBGBVR5_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU2_DBGBCR5_EL1,Debug Breakpoint Control Register 5"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR5_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
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bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR5_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR5_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x800++0x0B
line.long 0x00 "APBADDR_DBG_CPU2_DBGWVR0_EL1_31_0,Debug Watchpoint Value Register 0"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR0_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU2_DBGWVR0_EL1_63_32,Debug Watchpoint Extended Value Register 0"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU2_DBGWCR0_EL1,Debug Watchpoint Control Register 0"
bitfld.long 0x08 29.--31. "RES0_DBGWCR0_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 21.--23. "RES0_DBGWCR0_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
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bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
newline
bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0x810++0x0B
line.long 0x00 "APBADDR_DBG_CPU2_DBGWVR1_EL1_31_0,Debug Watchpoint Value Register 1"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR1_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU2_DBGWVR1_EL1_63_32,Debug Watchpoint Extended Value Register 1"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU2_DBGWCR1_EL1,Debug Watchpoint Control Register 1"
bitfld.long 0x08 29.--31. "RES0_DBGWCR1_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 21.--23. "RES0_DBGWCR1_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
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bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
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bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
newline
bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0x820++0x0B
line.long 0x00 "APBADDR_DBG_CPU2_DBGWVR2_EL1_31_0,Debug Watchpoint Value Register 2"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR2_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU2_DBGWVR2_EL1_63_32,Debug Watchpoint Extended Value Register 2"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU2_DBGWCR2_EL1,Debug Watchpoint Control Register 2"
bitfld.long 0x08 29.--31. "RES0_DBGWCR2_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 21.--23. "RES0_DBGWCR2_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
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bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
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bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
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bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0x830++0x0B
line.long 0x00 "APBADDR_DBG_CPU2_DBGWVR3_EL1_31_0,Debug Watchpoint Value Register 3"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR3_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU2_DBGWVR3_EL1_63_32,Debug Watchpoint Extended Value Register 3"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU2_DBGWCR3_EL1,Debug Watchpoint Control Register 3"
bitfld.long 0x08 29.--31. "RES0_DBGWCR3_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 21.--23. "RES0_DBGWCR3_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
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bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
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bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
newline
bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0xD00++0x03
line.long 0x00 "APBADDR_DBG_CPU2_MIDR_EL1,Main ID Register"
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,The Implementer code"
bitfld.long 0x00 20.--23. "VARIANT,An IMPLEMENTATION DEFINED variant number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "ARCHITECTURE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 4.--15. 1. "PARTNUM,An IMPLEMENTATION DEFINED primary part number for the device"
newline
bitfld.long 0x00 0.--3. "REVISION,An IMPLEMENTATION DEFINED revision number for the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD20++0x3F
line.long 0x00 "APBADDR_DBG_CPU2_ID_AA64PFR0_EL1_31_0,Processor Feature Register 0 (low word)"
bitfld.long 0x00 28.--31. "RES0_ID_AA64PFR0_EL1_31_0_31_28,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "GIC,GIC system register interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "ADVSIMD,Advanced SIMD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "FP,Floating-point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "EL3,EL3 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "EL2,EL2 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "EL1,EL1 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "EL0,EL0 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_DBG_CPU2_ID_AA64PFR0_EL1_63_32,Processor Feature Register 0 (high word)"
line.long 0x08 "APBADDR_DBG_CPU2_ID_AA64DFR0_EL1_31_0,Debug Feature Register 0 (low word)"
bitfld.long 0x08 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 24.--27. "RES0_ID_AA64DFR0_EL1_31_0_27_24,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "WRPS,Number of watchpoints minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 16.--19. "RES0_ID_AA64DFR0_EL1_31_0_19_16,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 12.--15. "BRPS,Number of breakpoints minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 8.--11. "PMUVER,Performance Monitors extension version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 4.--7. "TRACEVER,Trace extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--3. "DEBUGVER,Debug architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_DBG_CPU2_ID_AA64DFR0_EL1_63_32,Debug Feature Register 0 (high word)"
line.long 0x10 "APBADDR_DBG_CPU2_ID_AA64ISAR0_EL1_31_0,Instruction Set Attribute Register 0 (low word)"
hexmask.long.word 0x10 20.--31. 1. "RES0_ID_AA64ISAR0_EL1_31_0_31_20,Reserved RES0"
bitfld.long 0x10 16.--19. "CRC32,CRC32 instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 12.--15. "SHA2,SHA2 instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 8.--11. "SHA1,SHA1 instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 4.--7. "AES,AES instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 0.--3. "RES0_ID_AA64ISAR0_EL1_31_0_3_0,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_DBG_CPU2_ID_AA64ISAR0_EL1_63_32,Instruction Set Attribute Register 0 (high word)"
line.long 0x18 "APBADDR_DBG_CPU2_ID_AA64MMFR0_EL1_31_0,Memory Model Feature Register 0 (low word)"
bitfld.long 0x18 28.--31. "TGRAN4,Support for 4 Kbyte memory translation granule size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 24.--27. "TGRAN64,Support for 64 Kbyte memory translation granule size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 20.--23. "TGRAN16,Support for 16 Kbyte memory translation granule size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 16.--19. "BIGENDEL0,Mixed-endian support at EL0 only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 8.--11. "BIGEND,Mixed-endian configuration support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 4.--7. "ASIDBITS,Number of ASID bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 0.--3. "PARANGE,Physical Address range supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "APBADDR_DBG_CPU2_ID_AA64MMFR0_EL1_63_32,Memory Model Feature Register 0 (high word)"
line.long 0x20 "APBADDR_DBG_CPU2_ID_AA64PFR1_EL1_31_0,Processor Feature Register 1 (low word)"
line.long 0x24 "APBADDR_DBG_CPU2_ID_AA64PFR1_EL1_63_32,Processor Feature Register 1 (high word)"
line.long 0x28 "APBADDR_DBG_CPU2_ID_AA64DFR1_EL1_31_0,Auxiliary Feature Register 1 (low word)"
line.long 0x2C "APBADDR_DBG_CPU2_ID_AA64DFR1_EL1_63_32,Auxiliary Feature Register 1 (high word)"
line.long 0x30 "APBADDR_DBG_CPU2_ID_AA64ISAR1_EL1_31_0,Instruction Set Attribute Register 1 (low word)"
line.long 0x34 "APBADDR_DBG_CPU2_ID_AA64ISAR1_EL1_63_32,Instruction Set Attribute Register 1 (high word)"
line.long 0x38 "APBADDR_DBG_CPU2_ID_AA64MMFR1_EL1_31_0,Memory Model Feature Register 1 (low word)"
line.long 0x3C "APBADDR_DBG_CPU2_ID_AA64MMFR1_EL1_63_32,Memory Model Feature Register 1 (high word)"
group.long 0xF00++0x03
line.long 0x00 "APBADDR_DBG_CPU2_EDITCTRL,External Debug Integration mode Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_EDITCTRL_31_1,Reserved RES0"
bitfld.long 0x00 0. "IME,Integration mode enable" "0,1"
group.long 0xFA0++0x33
line.long 0x00 "APBADDR_DBG_CPU2_DBGCLAIMSET_EL1,Debug Claim Tag Set Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_DBGCLAIMSET_EL1_31_8,Reserved RAZ/SBZ"
hexmask.long.byte 0x00 0.--7. 1. "CLAIM,Claim set bits"
line.long 0x04 "APBADDR_DBG_CPU2_DBGCLAIMCLR_EL1,Debug Claim Tag Clear Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_DBGCLAIMCLR_EL1_31_8,Reserved RAZ/SBZ"
hexmask.long.byte 0x04 0.--7. 1. "CLAIM,Claim clear bits"
line.long 0x08 "APBADDR_DBG_CPU2_EDDEVAFF0,External Debug Device Affinity Register 0"
line.long 0x0C "APBADDR_DBG_CPU2_EDDEVAFF1,External Debug Device Affinity Register 1"
line.long 0x10 "APBADDR_DBG_CPU2_EDLAR,External Debug Lock Access Register"
line.long 0x14 "APBADDR_DBG_CPU2_EDLSR,External Debug Lock Status Register"
hexmask.long 0x14 3.--31. 1. "RES0_EDLSR_31_3,Reserved RES0"
bitfld.long 0x14 2. "NTT,Not thirty-two bit access required" "0,1"
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bitfld.long 0x14 1. "SLK,Software lock status for this component" "0,1"
bitfld.long 0x14 0. "SLI,Software lock implemented" "0,1"
line.long 0x18 "APBADDR_DBG_CPU2_DBGAUTHSTATUS_EL1,Debug Authentication Status register"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_DBGAUTHSTATUS_EL1_31_8,Reserved RES0"
bitfld.long 0x18 6.--7. "SNID,Secure non-invasive debug" "0,1,2,3"
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bitfld.long 0x18 4.--5. "SID,Secure invasive debug" "0,1,2,3"
bitfld.long 0x18 2.--3. "NSNID,Non-secure non-invasive debug" "0,1,2,3"
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bitfld.long 0x18 0.--1. "NSID,Non-secure invasive debug" "0,1,2,3"
line.long 0x1C "APBADDR_DBG_CPU2_EDDEVARCH,External Debug Device Architecture Register"
hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A" "0,1"
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bitfld.long 0x1C 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
line.long 0x20 "APBADDR_DBG_CPU2_EDDEVID2,External Debug Device ID Register 2"
line.long 0x24 "APBADDR_DBG_CPU2_EDDEVID1,External Debug Device ID Register 1"
hexmask.long 0x24 4.--31. 1. "RES0_EDDEVID1_31_4,Reserved RES0"
bitfld.long 0x24 0.--3. "PCSROFFSET,This field indicates the offset applied to PC samples returned by reads of EDPCSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "APBADDR_DBG_CPU2_EDDEVID,External Debug Device ID Register 0"
bitfld.long 0x28 28.--31. "RES0_EDDEVID_31_28,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 24.--27. "AUXREGS,Indicates support for Auxiliary registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.tbyte 0x28 4.--23. 1. "RES0_EDDEVID_23_4,Reserved RES0"
bitfld.long 0x28 0.--3. "PCSAMPLE,Indicates the level of Sample-based profiling support using external debug registers 40 through 43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "APBADDR_DBG_CPU2_EDDEVTYPE,External Debug Device Type Register"
hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_EDDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x2C 4.--7. "SUB,Subtype" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 0.--3. "MAJOR,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "APBADDR_DBG_CPU2_EDPIDR4,External Debug Peripheral Identification Register 4"
hexmask.long.tbyte 0x30 8.--31. 1. "RES0_EDPIDR4_31_8,Reserved RES0"
bitfld.long 0x30 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 0.--3. "DES_2,Designer JEP106 continuation code least significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFE0++0x1F
line.long 0x00 "APBADDR_DBG_CPU2_EDPIDR0,External Debug Peripheral Identification Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_EDPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number least significant byte"
line.long 0x04 "APBADDR_DBG_CPU2_EDPIDR1,External Debug Peripheral Identification Register 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_EDPIDR1_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "DES_0,Designer least significant nibble of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. "PART_1,Part number most significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_DBG_CPU2_EDPIDR2,External Debug Peripheral Identification Register 2"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_EDPIDR2_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "REVISION,Part major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 3. "JEDEC,RAO" "0,1"
bitfld.long 0x08 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x0C "APBADDR_DBG_CPU2_EDPIDR3,External Debug Peripheral Identification Register 3"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_EDPIDR3_31_8,Reserved RES0"
bitfld.long 0x0C 4.--7. "REVAND,Part minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_DBG_CPU2_EDCIDR0,External Debug Component Identification Register 0"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_EDCIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x14 "APBADDR_DBG_CPU2_EDCIDR1,External Debug Component Identification Register 1"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_EDCIDR1_31_8,Reserved RES0"
bitfld.long 0x14 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_DBG_CPU2_EDCIDR2,External Debug Component Identification Register 2"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDCIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x1C "APBADDR_DBG_CPU2_EDCIDR3,External Debug Component Identification Register 3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_EDCIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_CORE2_ECC_AGGR"
base ad:0x718C00
rgroup.long 0x00++0x03
line.long 0x00 "ECC_AGGR_CORE2_REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
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bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
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bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "ECC_AGGR_CORE2_REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
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hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
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bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
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hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ECC_AGGR_CORE2_REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ECC_AGGR_CORE2_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "ECC_AGGR_CORE2_REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_CORE2_REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 26. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 25. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 24. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 23. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 22. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 21. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 20. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 19. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 18. "CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 17. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 16. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 15. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 14. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 13. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 12. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 11. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 10. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 9. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 8. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 7. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 6. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 5. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 4. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 3. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 2. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 1. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 0. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ECC_AGGR_CORE2_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 26. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 25. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 24. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 23. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 22. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 21. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 20. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 19. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 18. "CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 17. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 16. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 15. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 14. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 13. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 12. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 11. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 10. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 9. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 8. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 7. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 6. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 5. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 4. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 3. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 2. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 1. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 0. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ECC_AGGR_CORE2_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 26. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 25. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 24. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 23. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 22. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 21. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 20. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 19. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 18. "CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 17. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 16. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 15. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 14. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 13. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 12. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 11. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 10. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 9. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 8. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 7. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 6. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 5. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 4. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 3. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 2. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 1. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 0. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ECC_AGGR_CORE2_REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_CORE2_REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 26. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 25. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 24. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 23. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 22. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 21. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 20. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 19. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 18. "CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 17. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 16. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 15. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 14. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 13. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 12. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 11. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 10. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 9. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 8. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 7. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 6. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 5. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 4. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 3. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 2. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 1. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 0. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu2_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ECC_AGGR_CORE2_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 26. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 25. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 24. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 23. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 22. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 21. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 20. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 19. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 18. "CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 17. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 16. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 15. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 14. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 13. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 12. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 11. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 10. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 9. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 8. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 7. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 6. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 5. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 4. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 3. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 2. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 1. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 0. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu2_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ECC_AGGR_CORE2_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 26. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 25. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 24. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 23. "CPU2_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 22. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 21. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 20. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 19. "CPU2_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 18. "CPU2_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 17. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 16. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 15. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 14. "CPU2_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 13. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 12. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 11. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 10. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 9. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 8. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 7. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 6. "CPU2_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 5. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 4. "CPU2_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 3. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 2. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 1. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 0. "CPU2_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu2_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ECC_AGGR_CORE2_REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
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bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ECC_AGGR_CORE2_REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
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bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ECC_AGGR_CORE2_REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ECC_AGGR_CORE2_REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "A53SS0_CORE2_ETM"
base ad:0x730230000
group.long 0x04++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCPRGCTLR,Programming Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_TRCPRGCTLR_31_1,Reserved RES0"
bitfld.long 0x00 0. "EN,Trace unit enable bit" "0,1"
group.long 0x0C++0x07
line.long 0x00 "APBADDR_ETM_CPU2_TRCSTATR,Status Register"
hexmask.long 0x00 2.--31. 1. "RES0_TRCSTATR_31_2,Reserved RES0"
bitfld.long 0x00 1. "PMSTABLE,Programmer's model stable bit: 0 The programmer's model is not stable" "0,1"
bitfld.long 0x00 0. "IDLE,Idle status bit: 0 The trace unit is not idle" "0,1"
line.long 0x04 "APBADDR_ETM_CPU2_TRCCONFIGR,Trace Configuration Register"
hexmask.long.word 0x04 18.--31. 1. "RES0_TRCCONFIGR_31_18,Reserved RES0"
bitfld.long 0x04 17. "DV,Data value tracing bit: 0 Data value tracing is disabled" "0,1"
bitfld.long 0x04 16. "DA,Data address tracing bit: 0 Data address tracing is disabled" "0,1"
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bitfld.long 0x04 15. "RES0_TRCCONFIGR_15_15,Reserved RES0" "0,1"
bitfld.long 0x04 13.--14. "QE,Q element enable field: 00 Q elements are disabled" "0,1,2,3"
bitfld.long 0x04 12. "RS,Return stack enable bit" "0,1"
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bitfld.long 0x04 11. "TS,Global timestamp tracing bit: 0 Global timestamp tracing is disabled" "0,1"
bitfld.long 0x04 8.--10. "COND,Conditional instruction tracing bit" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "VMID,VMID tracing bit: 0 VMID tracing is disabled" "0,1"
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bitfld.long 0x04 6. "CID,Context ID tracing bit: 0 Context ID tracing is disabled" "0,1"
bitfld.long 0x04 5. "RES0_TRCCONFIGR_5_5,Reserved RES0" "0,1"
bitfld.long 0x04 4. "CCI,Cycle counting instruction trace bit: 0 Cycle counting in the instruction trace is disabled" "0,1"
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bitfld.long 0x04 3. "BB,Branch broadcast mode bit: 0 Branch broadcast mode is disabled" "0,1"
bitfld.long 0x04 1.--2. "INSTP0,Instruction P0 bit" "0,1,2,3"
bitfld.long 0x04 0. "RES1_TRCCONFIGR_0_0,Reserved RES1" "0,1"
group.long 0x18++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCAUXCTLR,Auxiliary Control Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_TRCAUXCTLR_31_8,Reserved RES0"
bitfld.long 0x00 7. "COREIFEN,Keep core interface enabled regardless of trace enable register state" "0,1"
bitfld.long 0x00 6. "RES0_TRCAUXCTLR_6_6,Reserved RES0" "0,1"
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bitfld.long 0x00 5. "AUTHNOFLUSH,Do not flush trace on de-assertion of authentication inputs" "0,1"
bitfld.long 0x00 4. "TSNODELAY,Do not delay timestamp insertion based on FIFO depth" "0,1"
bitfld.long 0x00 3. "SYNCDELAY,Delay periodic synchronization if FIFO is more than half-full" "0,1"
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bitfld.long 0x00 2. "OVFLW,Force an overflow if synchronization is not completed when second synchronization becomes due" "0,1"
bitfld.long 0x00 1. "IDLEACK,Force idle-drain acknowledge high CPU does not wait for trace to drain before entering WFX state" "0,1"
bitfld.long 0x00 0. "AFREADY,Always respond to AFREADY immediately" "0,1"
group.long 0x20++0x07
line.long 0x00 "APBADDR_ETM_CPU2_TRCEVENTCTL0R,Event Control 0 Register"
bitfld.long 0x00 31. "TYPE3,Selects the resource type for trace event 3" "0,1"
bitfld.long 0x00 28.--30. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--27. "SEL3,Selects the resource number based on the value of TYPE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "TYPE2,Selects the resource type for trace event 2" "0,1"
bitfld.long 0x00 20.--22. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "SEL2,Selects the resource number based on the value of TYPE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "TYPE1,Selects the resource type for trace event 1" "0,1"
bitfld.long 0x00 12.--14. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "SEL1,Selects the resource number based on the value of TYPE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "TYPE0,Selects the resource type for trace event 0" "0,1"
bitfld.long 0x00 4.--6. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "SEL0,Selects the resource number based on the value of TYPE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_ETM_CPU2_TRCEVENTCTL1R,Event Control 1 Register"
hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 12. "LPOVERRIDE,Low power state behavior override" "0,1"
bitfld.long 0x04 11. "ATB,ATB trigger enable" "0,1"
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hexmask.long.byte 0x04 4.--10. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "EN,One bit per event to enable generation of an event element in the instruction trace stream when the selected event occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x17
line.long 0x00 "APBADDR_ETM_CPU2_TRCSTALLCTLR,Stall Control Register"
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 8. "ISTALL,Controls if the trace unit can stall the processor when the instruction trace buffer space is less than LEVEL" "0,1"
bitfld.long 0x00 4.--7. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2.--3. "LEVEL,The field can support 4 monotonic levels from 0b00 to 0b11" "0,1,2,3"
bitfld.long 0x00 0.--1. "RESERVED,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_ETM_CPU2_TRCTSCTLR,Global Timestamp Control Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_TRCTSCTLR_31_8,Reserved RES0"
hexmask.long.byte 0x04 0.--7. 1. "EVENT,An event selector"
line.long 0x08 "APBADDR_ETM_CPU2_TRCSYNCPR,Synchronization Period Register"
hexmask.long 0x08 5.--31. 1. "RES0_TRCSYNCPR_31_5,Reserved RES0"
bitfld.long 0x08 0.--4. "PERIOD,Controls how many bytes of trace the sum of instruction and data that a trace unit can generate before a periodic trace synchronization request occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "APBADDR_ETM_CPU2_TRCCCCTLR,Cycle Count Control Register"
hexmask.long.tbyte 0x0C 12.--31. 1. "RES0_TRCCCCTLR_31_12,Reserved RES0"
hexmask.long.word 0x0C 0.--11. 1. "THRESHOLD,Sets the threshold value for instruction trace cycle counting.The minimum threshold value that can be programmed into THRESHOLD is given in TRCIDR3.CCITMIN.Writing a value of zero might cause UNPREDICTABLE behaviour"
line.long 0x10 "APBADDR_ETM_CPU2_TRCBBCTLR,Branch Broadcast Control Register"
hexmask.long.tbyte 0x10 9.--31. 1. "RES0_TRCBBCTLR_31_9,Reserved RES0"
bitfld.long 0x10 8. "MODE,Mode bit: 0 Exclude mode" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "RANGE,Address range field"
line.long 0x14 "APBADDR_ETM_CPU2_TRCTRACEIDR,Trace ID Register"
hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x14 0.--6. 1. "TRACEID,Trace ID value"
group.long 0x80++0x0B
line.long 0x00 "APBADDR_ETM_CPU2_TRCVICTLR,ViewInst Main Control Register"
hexmask.long.byte 0x00 24.--31. 1. "RES0_TRCVICTLR_31_24,Reserved RES0"
bitfld.long 0x00 20.--23. "EXLEVEL_NS,In Non-secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "EXLEVEL_S,In Secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "RES0_TRCVICTLR_15_12,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "TRCERR,If TRCIDR3.TRCERR==1 this bit controls whether a trace unit must trace a system error exception: 0 The trace unit does not trace a system error exception unless it traces the exception or instruction immediately prior to the system error exception" "0,1"
bitfld.long 0x00 10. "TRCRESET,Controls whether a trace unit must trace a Reset exception: 0 The trace unit does not trace a Reset exception unless it traces the exception or instruction immediately prior to the Reset exception" "0,1"
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bitfld.long 0x00 9. "SSSTATUS,IF TRCIDR4.NUMACPAIRS>0 or TRCIDR.NUMPC>0 this bit returns the status of the start-stop logic: 0 The start-stop logic is in the stopped state" "0,1"
bitfld.long 0x00 8. "RES0_TRCVICTLR_8_8,Reserved RES0" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "EVENT,An event selector"
line.long 0x04 "APBADDR_ETM_CPU2_TRCVIIECTLR,ViewInst Include-Exclude Control Register"
hexmask.long.byte 0x04 24.--31. 1. "RES0_TRCVIIECTLR_31_24,Reserved RES0"
hexmask.long.byte 0x04 16.--23. 1. "EXCLUDE,0 1 The implemented width of the field n is IMPLEMENTATION DEFINED and is set by the value of TRCIDR4.NUMACPAIRS"
hexmask.long.byte 0x04 8.--15. 1. "RES0_TRCVIIECTLR_15_8,Reserved RES0"
newline
hexmask.long.byte 0x04 0.--7. 1. "INCLUDE,Include range field"
line.long 0x08 "APBADDR_ETM_CPU2_TRCVISSCTLR,ViewInst Start-Stop Control Register"
hexmask.long.word 0x08 16.--31. 1. "STOP,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of stopping trace"
hexmask.long.word 0x08 0.--15. 1. "START,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of starting trace"
group.long 0x100++0x0B
line.long 0x00 "APBADDR_ETM_CPU2_TRCSEQEVR0,Sequencer State Transition Control Registers 0"
hexmask.long.word 0x00 16.--31. 1. "RES0_TRCSEQEVR0_31_16,Reserved RES0"
hexmask.long.byte 0x00 8.--15. 1. "B_N,Backward field"
hexmask.long.byte 0x00 0.--7. 1. "F_N,Forward field"
line.long 0x04 "APBADDR_ETM_CPU2_TRCSEQEVR1,Sequencer State Transition Control Registers 1"
hexmask.long.word 0x04 16.--31. 1. "RES0_TRCSEQEVR1_31_16,Reserved RES0"
hexmask.long.byte 0x04 8.--15. 1. "B_N,Backward field"
hexmask.long.byte 0x04 0.--7. 1. "F_N,Forward field"
line.long 0x08 "APBADDR_ETM_CPU2_TRCSEQEVR2,Sequencer State Transition Control Registers 2"
hexmask.long.word 0x08 16.--31. 1. "RES0_TRCSEQEVR2_31_16,Reserved RES0"
hexmask.long.byte 0x08 8.--15. 1. "B_N,Backward field"
hexmask.long.byte 0x08 0.--7. 1. "F_N,Forward field"
group.long 0x118++0x0B
line.long 0x00 "APBADDR_ETM_CPU2_TRCSEQRSTEVR,Sequencer Reset Control Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_TRCSEQRSTEVR_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "RST,Contains an event number"
line.long 0x04 "APBADDR_ETM_CPU2_TRCSEQSTR,Sequencer State Register"
hexmask.long 0x04 2.--31. 1. "RES0_TRCSEQSTR_31_2,Reserved RES0"
bitfld.long 0x04 0.--1. "STATE,Sets or returns the state of the sequencer: 00 State 0" "0,1,2,3"
line.long 0x08 "APBADDR_ETM_CPU2_TRCEXTINSELR,External Input Select Register"
bitfld.long 0x08 29.--31. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "SEL3,Selects an event from the external input bus for External Input Resource 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 21.--23. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 16.--20. "SEL2,Selects an event from the external input bus for External Input Resource 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 13.--15. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 8.--12. "SEL1,Selects an event from the external input bus for External Input Resource 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 5.--7. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 0.--4. "SEL0,Selects an event from the external input bus for External Input Resource 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x140++0x07
line.long 0x00 "APBADDR_ETM_CPU2_TRCCNTRLDVR0,Counter Reload Value Registers 0"
hexmask.long.word 0x00 16.--31. 1. "RES0_TRCCNTRLDVR0_31_16,Reserved RES0"
hexmask.long.word 0x00 0.--15. 1. "VALUE_N,Contains the reload value for counter <n>"
line.long 0x04 "APBADDR_ETM_CPU2_TRCCNTRLDVR1,Counter Reload Value Registers 1"
hexmask.long.word 0x04 16.--31. 1. "RES0_TRCCNTRLDVR1_31_16,Reserved RES0"
hexmask.long.word 0x04 0.--15. 1. "VALUE_N,Contains the reload value for counter <n>"
group.long 0x150++0x07
line.long 0x00 "APBADDR_ETM_CPU2_TRCCNTCTLR0,Counter Control Register 0"
hexmask.long.word 0x00 18.--31. 1. "RES0_TRCCNTCTLR0_31_18,Reserved RES0"
bitfld.long 0x00 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter <n> decrements when a reload event occurs for counter <n-1>: 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit is RES0" "0,1"
bitfld.long 0x00 16. "RLDSELF_N,Controls whether a reload event occurs for counter <n> when counter <n> reaches zero: 0 The trace unit does not generate a reload event" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter <n>"
hexmask.long.byte 0x00 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter <n> to decrement"
line.long 0x04 "APBADDR_ETM_CPU2_TRCCNTCTLR1,Counter Control Register 1"
hexmask.long.word 0x04 18.--31. 1. "RES0_TRCCNTCTLR1_31_18,Reserved RES0"
bitfld.long 0x04 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter <n> decrements when a reload event occurs for counter <n-1>: 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit is RES0" "0,1"
bitfld.long 0x04 16. "RLDSELF_N,Controls whether a reload event occurs for counter <n> when counter <n> reaches zero: 0 The trace unit does not generate a reload event" "0,1"
newline
hexmask.long.byte 0x04 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter <n>"
hexmask.long.byte 0x04 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter <n> to decrement"
group.long 0x160++0x07
line.long 0x00 "APBADDR_ETM_CPU2_TRCCNTVR0,Counter Value Registers 0"
hexmask.long.word 0x00 16.--31. 1. "RES0_TRCCNTVR0_31_16,Reserved RES0"
hexmask.long.word 0x00 0.--15. 1. "VALUE_N,Contains the count value of counter <n>"
line.long 0x04 "APBADDR_ETM_CPU2_TRCCNTVR1,Counter Value Registers 1"
hexmask.long.word 0x04 16.--31. 1. "RES0_TRCCNTVR1_31_16,Reserved RES0"
hexmask.long.word 0x04 0.--15. 1. "VALUE_N,Contains the count value of counter <n>"
group.long 0x180++0x17
line.long 0x00 "APBADDR_ETM_CPU2_TRCIDR8,ID Register 8"
line.long 0x04 "APBADDR_ETM_CPU2_TRCIDR9,ID Register 9"
line.long 0x08 "APBADDR_ETM_CPU2_TRCIDR10,ID Register 10"
line.long 0x0C "APBADDR_ETM_CPU2_TRCIDR11,ID Register 11"
line.long 0x10 "APBADDR_ETM_CPU2_TRCIDR12,ID Register 12"
line.long 0x14 "APBADDR_ETM_CPU2_TRCIDR13,ID Register 13"
group.long 0x1C0++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCIMSPEC0,Implementation Specific Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_TRCIMSPEC0_31_8,Reserved RES0"
bitfld.long 0x00 4.--7. "EN,If SUPPORT is not 0b0000 controls whether the IMPLEMENTATION DEFINED features are enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "SUPPORT,Indicates whether the implementation supports IMPLEMENTATION DEFINED features" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1E0++0x17
line.long 0x00 "APBADDR_ETM_CPU2_TRCIDR0,ID Register 0"
bitfld.long 0x00 30.--31. "RES0_TRCIDR0_31_30,Reserved RES0" "0,1,2,3"
bitfld.long 0x00 29. "COMMOPT,Conditional instruction tracing support bit" "0,1"
bitfld.long 0x00 24.--28. "TSSIZE,Global timestamp size field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 17.--23. 1. "RES0_TRCIDR0_23_17,Reserved RES0"
bitfld.long 0x00 15.--16. "QSUPP,Q element support field" "0,1,2,3"
bitfld.long 0x00 14. "QFILT,Q element filtering support field" "0,1"
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bitfld.long 0x00 12.--13. "CONDTYPE,Conditional tracing field" "0,1,2,3"
bitfld.long 0x00 10.--11. "NUMEVENT,Number of events field" "0,1,2,3"
bitfld.long 0x00 9. "RETSTACK,Return stack bit" "0,1"
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bitfld.long 0x00 8. "RES0_TRCIDR0_8_8,Reserved RES0" "0,1"
bitfld.long 0x00 7. "TRCCCI,Cycle counting instruction bit" "0,1"
bitfld.long 0x00 6. "TRCCOND,Conditional instruction tracing support bit" "0,1"
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bitfld.long 0x00 5. "TRCBB,Branch broadcast tracing support bit" "0,1"
bitfld.long 0x00 3.--4. "TRCDATA,Conditional tracing field" "0,1,2,3"
bitfld.long 0x00 1.--2. "INSTP0,P0 tracing support field" "0,1,2,3"
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bitfld.long 0x00 0. "RES0_TRCIDR0_0_0,Reserved RES0" "0,1"
line.long 0x04 "APBADDR_ETM_CPU2_TRCIDR1,ID Register 1"
hexmask.long.byte 0x04 24.--31. 1. "DESIGNER,Indicates which company designed the trace unit"
hexmask.long.byte 0x04 16.--23. 1. "RES0_TRCIDR1_23_16,Reserved RES0"
bitfld.long 0x04 12.--15. "RES1_TRCIDR1_15_12,Reserved RES1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 8.--11. "TRCARCHMAJ,Indicates the major version of the ETM architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 4.--7. "TRCARCHMIN,Indicates the minor version of the ETM architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "REVISION,Returns an IMPLEMENTATION DEFINED value that identifies the revision of the trace registers and the OS Save and Restore registers.ARM recommends:That the initial implementation sets REVISION==0x0 and the field then increments for any subsequent.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_ETM_CPU2_TRCIDR2,ID Register 2"
bitfld.long 0x08 29.--31. "RES0_TRCIDR2_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 25.--28. "CCSIZE,Indicates the size of the cycle counter in bits minus 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 20.--24. "DVSIZE,Indicates the data value size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 15.--19. "DASIZE,Indicates the data address size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 10.--14. "VMIDSIZE,Indicates the VMID size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 5.--9. "CIDSIZE,Indicates the Context ID size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 0.--4. "IASIZE,Indicates the instruction address size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "APBADDR_ETM_CPU2_TRCIDR3,ID Register 3"
bitfld.long 0x0C 31. "NOOVERFLOW,Indicates if TRCSTALLCTLR.NOOVERFLOW is supported: 0 TRCSTALLCTLR.NOOVERFLOW is not supported or STALLCTL==0" "0,1"
bitfld.long 0x0C 28.--30. "NUMPROC,Indicates the number of processors available for tracing" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 27. "SYSSTALL,Indicates if the implementation can support stall control: 0 The system does not support stall control of the processor" "0,1"
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bitfld.long 0x0C 26. "STALLCTL,Indicates if TRCSTALLCTLR is supported: 0 TRCSTALLCTLR is not supported" "0,1"
bitfld.long 0x0C 25. "SYNCPR,Indicates if an implementation has a fixed synchronization period: 0 TRCSYNCPR is read-write so software can change the synchronization period" "0,1"
bitfld.long 0x0C 24. "TRCERR,Indicates if TRCVICTLR.TRCERR is supported: 0 TRCVICTLR.TRCERR is not supported 1 TRCVICTLR.TRCERR is supported" "0,1"
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bitfld.long 0x0C 20.--23. "EXLEVEL_NS,In Non-secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Non-secure state exception level n is not supported so the corresponding bits in TRCACATRn.EXLEVEL_NS and.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 16.--19. "EXLEVEL_S,In Secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Secure state exception level n is not supported so the corresponding bits in TRCACATRn.EXLEVEL_S and TRCVICTLR.EXLEVEL_S.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 12.--15. "RES0_TRCIDR3_15_12,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x0C 0.--11. 1. "CCITMIN,Indicates the minimum value that can be programmed in TRCCCCTLR.THRESHOLD.When cycle counting in the instruction trace is supported that is TRCIDR0.TRCCCI==1 then the minimum value of this field is 0x001 otherwise it is 0x000"
line.long 0x10 "APBADDR_ETM_CPU2_TRCIDR4,ID Register 4"
bitfld.long 0x10 28.--31. "NUMVMIDC,Indicates the number of VMID comparators that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 24.--27. "NUMCIDC,Indicates the number of Context ID comparators that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 20.--23. "NUMSSCC,Indicates the number of single-shot comparator controls that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "NUMRSPAIR,Indicates the number of resource selection pairs that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 12.--15. "NUMPC,Indicates the number of processor comparator inputs that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 9.--11. "RES0_TRCIDR4_11_9,Reserved RES0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 8. "SUPPDAC,Indicates if the implementation can support data address comparisons: 0 The implementation does not support data address comparisons" "0,1"
bitfld.long 0x10 4.--7. "NUMDVC,Indicates the number of data value comparators that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 0.--3. "NUMACPAIRS,Indicates the number of address comparator pairs that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_ETM_CPU2_TRCIDR5,ID Register 5"
bitfld.long 0x14 31. "REDFUNCNTR,Indicates if the reduced function counter is implemented: 0 The reduced function counter is not supported" "0,1"
bitfld.long 0x14 28.--30. "NUMCNTR,Indicates the number of counters that are available for tracing" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 25.--27. "NUMSEQSTATE,Indicates the number of sequencer states that are implemented" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 24. "RES0_TRCIDR5_24_24,Reserved RES0" "0,1"
bitfld.long 0x14 23. "LPOVERRIDE,Indicates if the implementation can support low-power state override: 0 The implementation does not support low-power state override" "0,1"
bitfld.long 0x14 22. "ATBTRIG,Indicates if the implementation can support ATB triggers: 0 The implementation does not support ATB triggers" "0,1"
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bitfld.long 0x14 16.--21. "TRACEIDSIZE,Indicates the trace ID width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 12.--15. "RES0_TRCIDR5_15_12,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 9.--11. "NUMEXTINSEL,Indicates how many external input select resources are implemented" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x14 0.--8. 1. "NUMEXTIN,Indicates how many external inputs are implemented"
group.long 0x208++0x37
line.long 0x00 "APBADDR_ETM_CPU2_TRCRSCTLR2,Resource Selection Control Registers 2"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCRSCTLR2_31_22,Reserved RES0"
bitfld.long 0x00 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x00 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x00 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x04 "APBADDR_ETM_CPU2_TRCRSCTLR3,Resource Selection Control Registers 3"
hexmask.long.word 0x04 22.--31. 1. "RES0_TRCRSCTLR3_31_22,Reserved RES0"
bitfld.long 0x04 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x04 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x04 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x08 "APBADDR_ETM_CPU2_TRCRSCTLR4,Resource Selection Control Registers 4"
hexmask.long.word 0x08 22.--31. 1. "RES0_TRCRSCTLR4_31_22,Reserved RES0"
bitfld.long 0x08 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x08 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x08 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x08 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x0C "APBADDR_ETM_CPU2_TRCRSCTLR5,Resource Selection Control Registers 5"
hexmask.long.word 0x0C 22.--31. 1. "RES0_TRCRSCTLR5_31_22,Reserved RES0"
bitfld.long 0x0C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x0C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x0C 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x0C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x10 "APBADDR_ETM_CPU2_TRCRSCTLR6,Resource Selection Control Registers 6"
hexmask.long.word 0x10 22.--31. 1. "RES0_TRCRSCTLR6_31_22,Reserved RES0"
bitfld.long 0x10 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x10 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x10 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x10 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x14 "APBADDR_ETM_CPU2_TRCRSCTLR7,Resource Selection Control Registers 7"
hexmask.long.word 0x14 22.--31. 1. "RES0_TRCRSCTLR7_31_22,Reserved RES0"
bitfld.long 0x14 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x14 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x14 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x14 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x18 "APBADDR_ETM_CPU2_TRCRSCTLR8,Resource Selection Control Registers 8"
hexmask.long.word 0x18 22.--31. 1. "RES0_TRCRSCTLR8_31_22,Reserved RES0"
bitfld.long 0x18 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x18 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x18 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x1C "APBADDR_ETM_CPU2_TRCRSCTLR9,Resource Selection Control Registers 9"
hexmask.long.word 0x1C 22.--31. 1. "RES0_TRCRSCTLR9_31_22,Reserved RES0"
bitfld.long 0x1C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x1C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x1C 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x1C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x20 "APBADDR_ETM_CPU2_TRCRSCTLR10,Resource Selection Control Registers 10"
hexmask.long.word 0x20 22.--31. 1. "RES0_TRCRSCTLR10_31_22,Reserved RES0"
bitfld.long 0x20 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x20 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x20 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x20 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x24 "APBADDR_ETM_CPU2_TRCRSCTLR11,Resource Selection Control Registers 11"
hexmask.long.word 0x24 22.--31. 1. "RES0_TRCRSCTLR11_31_22,Reserved RES0"
bitfld.long 0x24 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x24 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x24 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x24 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x28 "APBADDR_ETM_CPU2_TRCRSCTLR12,Resource Selection Control Registers 12"
hexmask.long.word 0x28 22.--31. 1. "RES0_TRCRSCTLR12_31_22,Reserved RES0"
bitfld.long 0x28 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x28 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x28 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x28 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x2C "APBADDR_ETM_CPU2_TRCRSCTLR13,Resource Selection Control Registers 13"
hexmask.long.word 0x2C 22.--31. 1. "RES0_TRCRSCTLR13_31_22,Reserved RES0"
bitfld.long 0x2C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x2C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x2C 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x2C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x30 "APBADDR_ETM_CPU2_TRCRSCTLR14,Resource Selection Control Registers 14"
hexmask.long.word 0x30 22.--31. 1. "RES0_TRCRSCTLR14_31_22,Reserved RES0"
bitfld.long 0x30 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x30 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x30 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x30 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x34 "APBADDR_ETM_CPU2_TRCRSCTLR15,Resource Selection Control Registers 15"
hexmask.long.word 0x34 22.--31. 1. "RES0_TRCRSCTLR15_31_22,Reserved RES0"
bitfld.long 0x34 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x34 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x34 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x34 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
group.long 0x280++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCSSCCR0,Single-Shot Comparator Control Register 0"
hexmask.long.byte 0x00 25.--31. 1. "RES0_TRCSSCCR0_31_25,Reserved RES0"
bitfld.long 0x00 24. "RST,Controls whether the single-shot comparator resource is reset when it fires" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "ARC,Selects one or more address range comparators for single-shot control.Each bit represents an address range comparator pair so bit[n-16] controls the selection of address range comparator pair n-16"
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hexmask.long.word 0x00 0.--15. 1. "SAC,Selects one or more single address comparators for single-shot control.Each bit represents a single address comparator so bit[n] controls the selection of single address comparator n"
group.long 0x2A0++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCSSCSR0,Single-Shot Comparator Status Register 0"
bitfld.long 0x00 31. "STATUS,Single-shot status bit" "0,1"
hexmask.long 0x00 3.--30. 1. "RES0_TRCSSCSR0_30_3,Reserved RES0"
bitfld.long 0x00 2. "DV,Data value comparator support bit" "0,1"
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bitfld.long 0x00 1. "DA,Data address comparator support bit" "0,1"
bitfld.long 0x00 0. "INST,Instruction address comparator support bit" "0,1"
group.long 0x300++0x07
line.long 0x00 "APBADDR_ETM_CPU2_TRCOSLAR,OS Lock Access Register"
hexmask.long 0x00 1.--31. 1. "RES0_TRCOSLAR_31_1,Reserved RES0"
bitfld.long 0x00 0. "LOCK,OS Lock control bit: 0 Unlocks the OS Lock" "0,1"
line.long 0x04 "APBADDR_ETM_CPU2_TRCOSLSR,OS Lock Status Register"
hexmask.long 0x04 4.--31. 1. "RES0_TRCOSLSR_31_4,Reserved RES0"
bitfld.long 0x04 3. "PRESENT,Indicates whether the OS Lock is implemented.This bit is RES1 which indicates that the OS Lock is always implemented" "0,1"
bitfld.long 0x04 2. "BIT32,This bit is RES0 which indicates that software must perform a 32-bit write to update the TRCOSLAR" "0,1"
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bitfld.long 0x04 1. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked" "0,1"
bitfld.long 0x04 0. "RES0_TRCOSLSR_0_0,Reserved RES0" "0,1"
group.long 0x310++0x07
line.long 0x00 "APBADDR_ETM_CPU2_TRCPDCR,Power Down Control Register"
hexmask.long 0x00 4.--31. 1. "RES0_TRCPDCR_31_4,Reserved RES0"
bitfld.long 0x00 3. "PU,Powerup request bit: 0 The system can remove power from the trace unit" "0,1"
bitfld.long 0x00 0.--2. "RES0_TRCPDCR_2_0,Reserved RES0" "0,1,2,3,4,5,6,7"
line.long 0x04 "APBADDR_ETM_CPU2_TRCPDSR,Power Down Status Register"
hexmask.long 0x04 6.--31. 1. "RES0_TRCPDSR_31_6,Reserved RES0"
bitfld.long 0x04 5. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked" "0,1"
bitfld.long 0x04 2.--4. "RES0_TRCPDSR_4_2,Reserved RES0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 1. "STICKYPD,Sticky powerdown status bit" "0,1"
bitfld.long 0x04 0. "POWER,Power status bit: 0 The trace unit core power domain is not powered" "0,1"
group.long 0x400++0x3F
line.long 0x00 "APBADDR_ETM_CPU2_TRCACVR0_31_0,Address Comparator Value Registers 0 (low word)"
line.long 0x04 "APBADDR_ETM_CPU2_TRCACVR0_63_32,Address Comparator Value Registers 0 (high word)"
line.long 0x08 "APBADDR_ETM_CPU2_TRCACVR1_31_0,Address Comparator Value Registers 1 (low word)"
line.long 0x0C "APBADDR_ETM_CPU2_TRCACVR1_63_32,Address Comparator Value Registers 1 (high word)"
line.long 0x10 "APBADDR_ETM_CPU2_TRCACVR2_31_0,Address Comparator Value Registers 2 (low word)"
line.long 0x14 "APBADDR_ETM_CPU2_TRCACVR2_63_32,Address Comparator Value Registers 2 (high word)"
line.long 0x18 "APBADDR_ETM_CPU2_TRCACVR3_31_0,Address Comparator Value Registers 3 (low word)"
line.long 0x1C "APBADDR_ETM_CPU2_TRCACVR3_63_32,Address Comparator Value Registers 3 (high word)"
line.long 0x20 "APBADDR_ETM_CPU2_TRCACVR4_31_0,Address Comparator Value Registers 4 (low word)"
line.long 0x24 "APBADDR_ETM_CPU2_TRCACVR4_63_32,Address Comparator Value Registers 4 (high word)"
line.long 0x28 "APBADDR_ETM_CPU2_TRCACVR5_31_0,Address Comparator Value Registers 5 (low word)"
line.long 0x2C "APBADDR_ETM_CPU2_TRCACVR5_63_32,Address Comparator Value Registers 5 (high word)"
line.long 0x30 "APBADDR_ETM_CPU2_TRCACVR6_31_0,Address Comparator Value Registers 6 (low word)"
line.long 0x34 "APBADDR_ETM_CPU2_TRCACVR6_63_32,Address Comparator Value Registers 6 (high word)"
line.long 0x38 "APBADDR_ETM_CPU2_TRCACVR7_31_0,Address Comparator Value Registers 7 (low word)"
line.long 0x3C "APBADDR_ETM_CPU2_TRCACVR7_63_32,Address Comparator Value Registers 7 (high word)"
group.long 0x480++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCACATR0,Address Comparator Access Type Registers 0"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR0_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR0_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x488++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCACATR1,Address Comparator Access Type Registers 1"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR1_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR1_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x490++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCACATR2,Address Comparator Access Type Registers 2"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR2_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR2_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x498++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCACATR3,Address Comparator Access Type Registers 3"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR3_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR3_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4A0++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCACATR4,Address Comparator Access Type Registers 4"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR4_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR4_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4A8++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCACATR5,Address Comparator Access Type Registers 5"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR5_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR5_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4B0++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCACATR6,Address Comparator Access Type Registers 6"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR6_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR6_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4B8++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCACATR7,Address Comparator Access Type Registers 7"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR7_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR7_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x600++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCCIDCVR0,Context ID Comparator Value Register 0"
group.long 0x640++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCVMIDCVR0,VMID Comparator Value Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "VALUE,Contains a VMID value"
group.long 0x680++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCCIDCCTLR0,Context ID Comparator Control Register 0"
group.long 0xEE4++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCITATBIDR,Integration ATB Identification Register"
hexmask.long 0x00 7.--31. 1. "RES0_TRCITATBIDR_31_7,Reserved RES0"
hexmask.long.byte 0x00 0.--6. 1. "ID,Drives the ATIDMn[6:0] output pins"
group.long 0xEEC++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCITIDATAR,Integration Instruction ATB Data Register"
hexmask.long 0x00 5.--31. 1. "RES0_TRCITIDATAR_31_5,Reserved RES0"
bitfld.long 0x00 4. "ATDATAM_31,Drives the ATDATAM[31] output" "0,1"
bitfld.long 0x00 3. "ATDATAM_23,Drives the ATDATAM[23] output" "0,1"
newline
bitfld.long 0x00 2. "ATDATAM_15,Drives the ATDATAM[15] output" "0,1"
bitfld.long 0x00 1. "ATDATAM_7,Drives the ATDATAM[7] output" "0,1"
bitfld.long 0x00 0. "ATDATAM_0,Drives the ATDATAM[0] output" "0,1"
group.long 0xEF4++0x03
line.long 0x00 "APBADDR_ETM_CPU2_TRCITIATBINR,Integration Instruction ATB In Register"
hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved"
bitfld.long 0x00 1. "AFVALIDM,Returns the value of the AFVALIDMn input pin" "0,1"
bitfld.long 0x00 0. "ATREADYM,Returns the value of the ATREADYMn input pin" "0,1"
group.long 0xEFC++0x07
line.long 0x00 "APBADDR_ETM_CPU2_TRCITIATBOUTR,Integration Instruction ATB Out Register"
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
bitfld.long 0x00 8.--9. "BYTES,Drives the ATBYTESMn[1:0] output pins" "0,1,2,3"
bitfld.long 0x00 2.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 1. "AFREADY,Drives the AFREADYMn output pin" "0,1"
bitfld.long 0x00 0. "ATVALID,Drives the ATVALIDMn output pin" "0,1"
line.long 0x04 "APBADDR_ETM_CPU2_TRCITCTRL,Integration Mode Control Register"
hexmask.long 0x04 1.--31. 1. "RES0_TRCITCTRL_31_1,Reserved RES0"
bitfld.long 0x04 0. "ITEN,Integration mode enable bit: 0 The trace unit is not in integration mode" "0,1"
group.long 0xFA0++0x1F
line.long 0x00 "APBADDR_ETM_CPU2_TRCCLAIMSET,Claim Tag Set Register"
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--3. "SET,Sets bits in the claim tag and determines the number of claim tag bits implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_ETM_CPU2_TRCCLAIMCLR,Claim Tag Clear Register"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "CLR,Clears bits in the claim tag and determines the current value of the claim tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_ETM_CPU2_TRCDEVAFF0,Device Affinity Register 0"
line.long 0x0C "APBADDR_ETM_CPU2_TRCDEVAFF1,Device Affinity Register 1"
line.long 0x10 "APBADDR_ETM_CPU2_TRCLAR,Software Lock Access Register"
line.long 0x14 "APBADDR_ETM_CPU2_TRCLSR,Software Lock Status Register"
hexmask.long 0x14 3.--31. 1. "RES0_TRCLSR_31_3,Reserved RES0"
bitfld.long 0x14 2. "NTT,Not thirty-two bit access required" "0,1"
bitfld.long 0x14 1. "SLK,Software lock status for this component" "0,1"
newline
bitfld.long 0x14 0. "SLI,Software lock implemented" "0,1"
line.long 0x18 "APBADDR_ETM_CPU2_TRCAUTHSTATUS,Authentication Status Register"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCAUTHSTATUS_31_8,Reserved RES0"
bitfld.long 0x18 6.--7. "SNID,Indicates whether the system enables the trace unit to support Secure non-invasive debug: 00 The trace unit does not implement support for Secure non-invasive debug" "0,1,2,3"
bitfld.long 0x18 4.--5. "SID,Indicates whether the trace unit supports Secure invasive debug: 00 The trace unit does not support Secure invasive debug" "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "NSNID,Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: 00 The trace unit does not implement support for Non-secure non-invasive debug" "0,1,2,3"
bitfld.long 0x18 0.--1. "NSID,Indicates whether the trace unit supports Non-secure invasive debug: 00 The trace unit does not support Non-secure invasive debug" "0,1,2,3"
line.long 0x1C "APBADDR_ETM_CPU2_TRCDEVARCH,Device Architecture Register"
hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is RAO" "0,1"
bitfld.long 0x1C 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
group.long 0xFC8++0x37
line.long 0x00 "APBADDR_ETM_CPU2_TRCDEVID,Device ID Register"
line.long 0x04 "APBADDR_ETM_CPU2_TRCDEVTYPE,Device Type Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_TRCDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "SUB,Returns 0x1 to indicate that the ETM generates processor trace.All other values are reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "MAIN,Returns 0x3 to indicate that the ETM is a trace source.All other values are reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_ETM_CPU2_TRCPIDR4,Peripheral Identification Register 4"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_TRCPIDR4_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--3. "DES_2,Designer JEP106 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_ETM_CPU2_TRCPIDR5,Peripheral Identification Register 5"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_TRCPIDR5_31_8,Reserved RES0"
hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,RES0 reserved for future use"
line.long 0x10 "APBADDR_ETM_CPU2_TRCPIDR6,Peripheral Identification Register 6"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_TRCPIDR6_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "RESERVED,RES0 reserved for future use"
line.long 0x14 "APBADDR_ETM_CPU2_TRCPIDR7,Peripheral Identification Register 7"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_TRCPIDR7_31_8,Reserved RES0"
hexmask.long.byte 0x14 0.--7. 1. "RESERVED,RES0 reserved for future use"
line.long 0x18 "APBADDR_ETM_CPU2_TRCPIDR0,Peripheral Identification Register 0"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PART_0,Part number bits[7:0]"
line.long 0x1C "APBADDR_ETM_CPU2_TRCPIDR1,Peripheral Identification Register 1"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_TRCPIDR1_31_8,Reserved RES0"
bitfld.long 0x1C 4.--7. "DES_0,Designer bits[3:0] of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "PART_1,Part number bits[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "APBADDR_ETM_CPU2_TRCPIDR2,Peripheral Identification Register 2"
hexmask.long.tbyte 0x20 8.--31. 1. "RES0_TRCPIDR2_31_8,Reserved RES0"
bitfld.long 0x20 4.--7. "REVISION,The IMPLEMENTATION DEFINED revision number for the ETM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 3. "JEDEC,RAO" "0,1"
newline
bitfld.long 0x20 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x24 "APBADDR_ETM_CPU2_TRCPIDR3,Peripheral Identification Register 3"
hexmask.long.tbyte 0x24 8.--31. 1. "RES0_TRCPIDR3_31_8,Reserved RES0"
bitfld.long 0x24 4.--7. "REVAND,The IMPLEMENTATION DEFINED manufacturing revision number for the implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "APBADDR_ETM_CPU2_TRCCIDR0,Component Identification Register 0"
hexmask.long.tbyte 0x28 8.--31. 1. "RES0_TRCCIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x28 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x2C "APBADDR_ETM_CPU2_TRCCIDR1,Component Identification Register 1"
hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_TRCCIDR1_31_8,Reserved RES0"
bitfld.long 0x2C 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "APBADDR_ETM_CPU2_TRCCIDR2,Component Identification Register 2"
hexmask.long.tbyte 0x30 8.--31. 1. "RES0_TRCCIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x30 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x34 "APBADDR_ETM_CPU2_TRCCIDR3,Component Identification Register 3"
hexmask.long.tbyte 0x34 8.--31. 1. "RES0_TRCCIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x34 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_CORE2_PMU"
base ad:0x730220000
group.long 0x00++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMEVCNTR0_EL0,Performance Monitors Event Count Register 0"
group.long 0x08++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMEVCNTR1_EL0,Performance Monitors Event Count Register 1"
group.long 0x10++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMEVCNTR2_EL0,Performance Monitors Event Count Register 2"
group.long 0x18++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMEVCNTR3_EL0,Performance Monitors Event Count Register 3"
group.long 0x20++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMEVCNTR4_EL0,Performance Monitors Event Count Register 4"
group.long 0x28++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMEVCNTR5_EL0,Performance Monitors Event Count Register 5"
group.long 0xF8++0x07
line.long 0x00 "APBADDR_PMU_CPU2_PMCCNTR_EL0_31_0,Performance Monitors Cycle Counter (low word)"
line.long 0x04 "APBADDR_PMU_CPU2_PMCCNTR_EL0_63_32,Performance Monitors Cycle Counter (high word)"
group.long 0x400++0x17
line.long 0x00 "APBADDR_PMU_CPU2_PMEVTYPER0_EL0,Performance Monitors Event Type Register 0"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x00 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x00 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x00 10.--25. 1. "RES0_PMEVTYPER0_EL0_25_10,Reserved RES0"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x04 "APBADDR_PMU_CPU2_PMEVTYPER1_EL0,Performance Monitors Event Type Register 1"
bitfld.long 0x04 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x04 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x04 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x04 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x04 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x04 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x04 10.--25. 1. "RES0_PMEVTYPER1_EL0_25_10,Reserved RES0"
hexmask.long.word 0x04 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x08 "APBADDR_PMU_CPU2_PMEVTYPER2_EL0,Performance Monitors Event Type Register 2"
bitfld.long 0x08 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x08 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x08 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x08 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x08 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x08 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x08 10.--25. 1. "RES0_PMEVTYPER2_EL0_25_10,Reserved RES0"
hexmask.long.word 0x08 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x0C "APBADDR_PMU_CPU2_PMEVTYPER3_EL0,Performance Monitors Event Type Register 3"
bitfld.long 0x0C 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x0C 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x0C 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x0C 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x0C 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x0C 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x0C 10.--25. 1. "RES0_PMEVTYPER3_EL0_25_10,Reserved RES0"
hexmask.long.word 0x0C 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x10 "APBADDR_PMU_CPU2_PMEVTYPER4_EL0,Performance Monitors Event Type Register 4"
bitfld.long 0x10 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x10 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x10 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x10 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x10 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x10 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x10 10.--25. 1. "RES0_PMEVTYPER4_EL0_25_10,Reserved RES0"
hexmask.long.word 0x10 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x14 "APBADDR_PMU_CPU2_PMEVTYPER5_EL0,Performance Monitors Event Type Register 5"
bitfld.long 0x14 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x14 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x14 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x14 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x14 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x14 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x14 10.--25. 1. "RES0_PMEVTYPER5_EL0_25_10,Reserved RES0"
hexmask.long.word 0x14 0.--9. 1. "EVTCOUNT,Event to count"
group.long 0x47C++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMCCFILTR_EL0,Performance Monitors Cycle Counter Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x00 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x00 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long 0x00 0.--25. 1. "RES0_PMCCFILTR_EL0_25_0,Reserved RES0"
group.long 0xC00++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMCNTENSET_EL0,Performance Monitors Count Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 enable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter enable bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xC20++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMCNTENCLR_EL0,Performance Monitors Count Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 disable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter disable bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xC40++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMINTENSET_EL1,Performance Monitors Interrupt Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow interrupt request enable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow interrupt request enable bit for PMEVCNTR<x>_EL0.N is the value in PMCR_EL0.N"
group.long 0xC60++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMINTENCLR_EL1,Performance Monitors Interrupt Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow interrupt request disable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow interrupt request disable bit for PMEVCNTR<x>_EL0.N is the value in PMCR_EL0.N"
group.long 0xC80++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow clear bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xCA0++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMSWINC_EL0,Performance Monitors Software Increment Register"
hexmask.long 0x00 6.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--5. "P_X,Event counter software increment bit for PMEVCNTR<x>" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xCC0++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMOVSSET_EL0,Performance Monitors Overflow Flag Status Set Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow set bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xE00++0x07
line.long 0x00 "APBADDR_PMU_CPU2_PMCFGR,Performance Monitors Configuration Register"
hexmask.long.word 0x00 20.--31. 1. "RES0_PMCFGR_31_20,Reserved RES0"
bitfld.long 0x00 19. "UEN,User-mode Enable Register supported" "0,1"
bitfld.long 0x00 18. "WT,This feature is not supported so this bit is RES0" "0,1"
newline
bitfld.long 0x00 17. "NA,This feature is not supported so this bit is RES0" "0,1"
bitfld.long 0x00 16. "EX,Export supported" "0,1"
bitfld.long 0x00 15. "CCD,Cycle counter has prescale" "0,1"
newline
bitfld.long 0x00 14. "CC,Dedicated cycle counter [counter 31] supported" "0,1"
bitfld.long 0x00 8.--13. "SIZE,Size of counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 0.--7. 1. "N,Number of counters implemented in addition to the cycle counter PMCCNTR_EL0"
line.long 0x04 "APBADDR_PMU_CPU2_PMCR_EL0,Performance Monitors Control Register"
hexmask.long.tbyte 0x04 11.--31. 1. "RES0_PMCR_EL0_31_11,Reserved RAZ/WI"
bitfld.long 0x04 7.--10. "RES0_PMCR_EL0_10_7,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "LC,Long cycle counter enable" "0,1"
newline
bitfld.long 0x04 5. "DP,Disable cycle counter when event counting is prohibited" "0,1"
bitfld.long 0x04 4. "X,Enable export of events in an IMPLEMENTATION DEFINED event stream" "0,1"
bitfld.long 0x04 3. "D,Clock divider" "0,1"
newline
bitfld.long 0x04 2. "C,Cycle counter reset" "0,1"
bitfld.long 0x04 1. "P,Event counter reset" "0,1"
bitfld.long 0x04 0. "E,Enable" "0,1"
group.long 0xE20++0x07
line.long 0x00 "APBADDR_PMU_CPU2_PMCEID0_EL0,Performance Monitors Common Event Identification Register 0"
line.long 0x04 "APBADDR_PMU_CPU2_PMCEID1_EL0,Performance Monitors Common Event Identification Register 1"
hexmask.long 0x04 1.--31. 1. "RES0_PMCEID1_EL0_31_1,Reserved RES0"
bitfld.long 0x04 0. "CE_32,Common architectural and microarchitectural feature events that can be counted by the PMU event counters.For the bit described in the following table the event is implemented if the bit is set to 1 or not implemented if the bit is set to.." "0,1"
group.long 0xF00++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMITCTRL,Performance Monitors Integration mode Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_PMITCTRL_31_1,Reserved RES0"
bitfld.long 0x00 0. "IME,Integration mode enable" "0,1"
group.long 0xFA8++0x17
line.long 0x00 "APBADDR_PMU_CPU2_PMDEVAFF0,Performance Monitors Device Affinity Register 0"
line.long 0x04 "APBADDR_PMU_CPU2_PMDEVAFF1,Performance Monitors Device Affinity Register 1"
line.long 0x08 "APBADDR_PMU_CPU2_PMLAR,Performance Monitors Lock Access Register"
line.long 0x0C "APBADDR_PMU_CPU2_PMLSR,Performance Monitors Lock Status Register"
hexmask.long 0x0C 3.--31. 1. "RES0_PMLSR_31_3,Reserved RES0"
bitfld.long 0x0C 2. "NTT,Not thirty-two bit access required" "0,1"
bitfld.long 0x0C 1. "SLK,Software lock status for this component" "0,1"
newline
bitfld.long 0x0C 0. "SLI,Software lock implemented" "0,1"
line.long 0x10 "APBADDR_PMU_CPU2_PMAUTHSTATUS,Performance Monitors Authentication Status Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_PMAUTHSTATUS_31_8,Reserved RES0"
bitfld.long 0x10 6.--7. "SNID,Holds the same value as DBGAUTHSTATUS_EL1.SNID" "0,1,2,3"
bitfld.long 0x10 4.--5. "RES0_PMAUTHSTATUS_5_4,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x10 2.--3. "NSNID,Holds the same value as DBGAUTHSTATUS_EL1.NSNID" "0,1,2,3"
bitfld.long 0x10 0.--1. "RES0_PMAUTHSTATUS_1_0,Reserved RES0" "0,1,2,3"
line.long 0x14 "APBADDR_PMU_CPU2_PMDEVARCH,Performance Monitors Device Architecture Register"
hexmask.long.word 0x14 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x14 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A" "0,1"
bitfld.long 0x14 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x14 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
group.long 0xFCC++0x07
line.long 0x00 "APBADDR_PMU_CPU2_PMDEVTYPE,Performance Monitors Device Type Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_PMDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x00 4.--7. "SUB,Subtype" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "MAJOR,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_PMU_CPU2_PMPIDR4,Performance Monitors Peripheral Identification Register 4"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_PMPIDR4_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "DES_2,Designer JEP106 continuation code least significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
group.long ($2+0xFD4)++0x03
line.long 0x00 "APBADDR_PMU_CPU2_PMPIDR$1,Performance Monitors Peripheral Identification Register 5"
repeat.end
group.long 0xFE0++0x1F
line.long 0x00 "APBADDR_PMU_CPU2_PMPIDR0,Performance Monitors Peripheral Identification Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_PMPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number least significant byte"
line.long 0x04 "APBADDR_PMU_CPU2_PMPIDR1,Performance Monitors Peripheral Identification Register 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_PMPIDR1_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "DES_0,Designer least significant nibble of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "PART_1,Part number most significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_PMU_CPU2_PMPIDR2,Performance Monitors Peripheral Identification Register 2"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_PMPIDR2_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "REVISION,Part major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3. "JEDEC,RAO" "0,1"
newline
bitfld.long 0x08 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x0C "APBADDR_PMU_CPU2_PMPIDR3,Performance Monitors Peripheral Identification Register 3"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_PMPIDR3_31_8,Reserved RES0"
bitfld.long 0x0C 4.--7. "REVAND,Part minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_PMU_CPU2_PMCIDR0,Performance Monitors Component Identification Register 0"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_PMCIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x14 "APBADDR_PMU_CPU2_PMCIDR1,Performance Monitors Component Identification Register 1"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_PMCIDR1_31_8,Reserved RES0"
bitfld.long 0x14 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_PMU_CPU2_PMCIDR2,Performance Monitors Component Identification Register 2"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_PMCIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x1C "APBADDR_PMU_CPU2_PMCIDR3,Performance Monitors Component Identification Register 3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_PMCIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_CORE3_CTI"
base ad:0x730340000
group.long 0x00++0x03
line.long 0x00 "APBADDR_CTI_CPU3_CTICONTROL,CTI Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_CTICONTROL_31_1,Reserved RES0"
bitfld.long 0x00 0. "GLBEN,Enables or disables the CTI mapping functions" "0,1"
group.long 0x10++0x2F
line.long 0x00 "APBADDR_CTI_CPU3_CTIINTACK,CTI Output Trigger Acknowledge Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "ACK_N,Can be used to create soft acknowledges for output triggers"
line.long 0x04 "APBADDR_CTI_CPU3_CTIAPPSET,CTI Application Trigger Set Register"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "CTIAPPSETX,Application trigger <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU3_CTIAPPCLEAR,CTI Application Trigger Clear Register"
hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x08 0.--3. "CTIAPPCLEARX,Application trigger <x> disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_CTI_CPU3_CTIAPPPULSE,CTI Application Pulse Register"
hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x0C 0.--3. "CTIAPPPULSEX,Generate event pulse on ECT channel <x>" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU3_CTIINEN0,CTI Input Trigger to Output Channel Enable Register 0"
hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x10 0.--3. "INENX,Input trigger 0 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_CTI_CPU3_CTIINEN1,CTI Input Trigger to Output Channel Enable Register 1"
hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x14 0.--3. "INENX,Input trigger 1 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_CTI_CPU3_CTIINEN2,CTI Input Trigger to Output Channel Enable Register 2"
hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x18 0.--3. "INENX,Input trigger 2 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "APBADDR_CTI_CPU3_CTIINEN3,CTI Input Trigger to Output Channel Enable Register 3"
hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x1C 0.--3. "INENX,Input trigger 3 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "APBADDR_CTI_CPU3_CTIINEN4,CTI Input Trigger to Output Channel Enable Register 4"
hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x20 0.--3. "INENX,Input trigger 4 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "APBADDR_CTI_CPU3_CTIINEN5,CTI Input Trigger to Output Channel Enable Register 5"
hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x24 0.--3. "INENX,Input trigger 5 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "APBADDR_CTI_CPU3_CTIINEN6,CTI Input Trigger to Output Channel Enable Register 6"
hexmask.long 0x28 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x28 0.--3. "INENX,Input trigger 6 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "APBADDR_CTI_CPU3_CTIINEN7,CTI Input Trigger to Output Channel Enable Register 7"
hexmask.long 0x2C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x2C 0.--3. "INENX,Input trigger 7 to output channel <x> enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0++0x1F
line.long 0x00 "APBADDR_CTI_CPU3_CTIOUTEN0,CTI Input Channel to Output Trigger Enable Register 0"
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--3. "OUTENX,Input channel <x> to output trigger 0 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_CTI_CPU3_CTIOUTEN1,CTI Input Channel to Output Trigger Enable Register 1"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "OUTENX,Input channel <x> to output trigger 1 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU3_CTIOUTEN2,CTI Input Channel to Output Trigger Enable Register 2"
hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x08 0.--3. "OUTENX,Input channel <x> to output trigger 2 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_CTI_CPU3_CTIOUTEN3,CTI Input Channel to Output Trigger Enable Register 3"
hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x0C 0.--3. "OUTENX,Input channel <x> to output trigger 3 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU3_CTIOUTEN4,CTI Input Channel to Output Trigger Enable Register 4"
hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x10 0.--3. "OUTENX,Input channel <x> to output trigger 4 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_CTI_CPU3_CTIOUTEN5,CTI Input Channel to Output Trigger Enable Register 5"
hexmask.long 0x14 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x14 0.--3. "OUTENX,Input channel <x> to output trigger 5 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_CTI_CPU3_CTIOUTEN6,CTI Input Channel to Output Trigger Enable Register 6"
hexmask.long 0x18 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x18 0.--3. "OUTENX,Input channel <x> to output trigger 6 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "APBADDR_CTI_CPU3_CTIOUTEN7,CTI Input Channel to Output Trigger Enable Register 7"
hexmask.long 0x1C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x1C 0.--3. "OUTENX,Input channel <x> to output trigger 7 enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x130++0x17
line.long 0x00 "APBADDR_CTI_CPU3_CTITRIGINSTATUS,CTI Trigger In Status Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "TRINN,Provides the status of the trigger inputs"
line.long 0x04 "APBADDR_CTI_CPU3_CTITRIGOUTSTATUS,CTI Trigger Out Status Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x04 0.--7. 1. "TROUTN,Provides the status of the trigger outputs"
line.long 0x08 "APBADDR_CTI_CPU3_CTICHINSTATUS,CTI Channel In Status Register"
hexmask.long 0x08 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x08 0.--3. "CHINN,Provides the raw status of the ECT channel inputs to the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_CTI_CPU3_CTICHOUTSTATUS,CTI Channel Out Status Register"
hexmask.long 0x0C 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x0C 0.--3. "CHOUTN,Provides the status of the ECT channel outputs from the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU3_CTIGATE,CTI Channel Gate Enable Register"
hexmask.long 0x10 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x10 0.--3. "GATEX,Determines whether events on channels propagate through the CTM to other ECT components or from the CTM into the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_CTI_CPU3_ASICCTL,CTI External Multiplexor Control register"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_ASICCTL_31_8,Reserved RES0"
hexmask.long.byte 0x14 0.--7. 1. "ASICCTL,IMPLEMENTATION DEFINED ASIC control"
group.long 0xF00++0x03
line.long 0x00 "APBADDR_CTI_CPU3_CTIITCTRL,CTI Integration mode Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_CTIITCTRL_31_1,Reserved RES0"
bitfld.long 0x00 0. "IME,Integration mode enable" "0,1"
group.long 0xFA0++0x33
line.long 0x00 "APBADDR_CTI_CPU3_CTICLAIMSET,CTI Claim Set"
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--3. "CLAIMX,CLAIM tag set bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_CTI_CPU3_CTICLAIMCLR,CTI Claim Clear"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "CLAIMX,Clear CLAIM tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU3_CTIDEVAFF0,CTI Device Affinity Register 0"
line.long 0x0C "APBADDR_CTI_CPU3_CTIDEVAFF1,CTI Device Affinity Register 1"
line.long 0x10 "APBADDR_CTI_CPU3_CTILAR,CTI Lock Access Register"
line.long 0x14 "APBADDR_CTI_CPU3_CTILSR,CTI Lock Status Register"
hexmask.long 0x14 3.--31. 1. "RES0_CTILSR_31_3,Reserved RES0"
bitfld.long 0x14 2. "NTT,Not thirty-two bit access required" "0,1"
bitfld.long 0x14 1. "SLK,Software lock status for this component" "0,1"
newline
bitfld.long 0x14 0. "SLI,Software lock implemented" "0,1"
line.long 0x18 "APBADDR_CTI_CPU3_CTIAUTHSTATUS,CTI Authentication Status Register"
hexmask.long 0x18 4.--31. 1. "RES0_CTIAUTHSTATUS_31_4,Reserved RES0"
bitfld.long 0x18 2.--3. "NSNID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SNID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSNID" "0,1,2,3"
bitfld.long 0x18 0.--1. "NSID,If EL3 is not implemented and the processor is Secure holds the same value as DBGAUTHSTATUS_EL1.SID.Otherwise holds the same value as DBGAUTHSTATUS_EL1.NSID" "0,1,2,3"
line.long 0x1C "APBADDR_CTI_CPU3_CTIDEVARCH,CTI Device Architecture Register"
hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A" "0,1"
bitfld.long 0x1C 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
line.long 0x20 "APBADDR_CTI_CPU3_CTIDEVID2,CTI Device ID Register 2"
line.long 0x24 "APBADDR_CTI_CPU3_CTIDEVID1,CTI Device ID Register 1"
line.long 0x28 "APBADDR_CTI_CPU3_CTIDEVID,CTI Device ID Register 0"
bitfld.long 0x28 26.--31. "RES0_CTIDEVID_31_26,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x28 24.--25. "INOUT,Input/output options" "0,1,2,3"
bitfld.long 0x28 22.--23. "RES0_CTIDEVID_23_22,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x28 16.--21. "NUMCHAN,Number of ECT channels implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x28 14.--15. "RES0_CTIDEVID_15_14,Reserved RES0" "0,1,2,3"
bitfld.long 0x28 8.--13. "NUMTRIG,Number of triggers implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x28 5.--7. "RES0_CTIDEVID_7_5,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x28 0.--4. "EXTMUXNUM,Maximum number of external triggers available for multiplexing into the CTI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x2C "APBADDR_CTI_CPU3_CTIDEVTYPE,CTI Device Type Register"
hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_CTIDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x2C 4.--7. "SUB,Subtype" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 0.--3. "MAJOR,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "APBADDR_CTI_CPU3_CTIPIDR4,CTI Peripheral Identification Register 4"
hexmask.long.tbyte 0x30 8.--31. 1. "RES0_CTIPIDR4_31_8,Reserved RES0"
bitfld.long 0x30 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 0.--3. "DES_2,Designer JEP106 continuation code least significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
group.long ($2+0xFD4)++0x03
line.long 0x00 "APBADDR_CTI_CPU3_CTIPIDR$1,CTI Peripheral Identification Register 5"
repeat.end
group.long 0xFE0++0x1F
line.long 0x00 "APBADDR_CTI_CPU3_CTIPIDR0,CTI Peripheral Identification Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_CTIPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number least significant byte"
line.long 0x04 "APBADDR_CTI_CPU3_CTIPIDR1,CTI Peripheral Identification Register 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_CTIPIDR1_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "DES_0,Designer least significant nibble of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "PART_1,Part number most significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_CTI_CPU3_CTIPIDR2,CTI Peripheral Identification Register 2"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_CTIPIDR2_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "REVISION,Part major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3. "JEDEC,RAO" "0,1"
newline
bitfld.long 0x08 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x0C "APBADDR_CTI_CPU3_CTIPIDR3,CTI Peripheral Identification Register 3"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_CTIPIDR3_31_8,Reserved RES0"
bitfld.long 0x0C 4.--7. "REVAND,Part minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_CTI_CPU3_CTICIDR0,CTI Component Identification Register 0"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_CTICIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x14 "APBADDR_CTI_CPU3_CTICIDR1,CTI Component Identification Register 1"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_CTICIDR1_31_8,Reserved RES0"
bitfld.long 0x14 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_CTI_CPU3_CTICIDR2,CTI Component Identification Register 2"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_CTICIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x1C "APBADDR_CTI_CPU3_CTICIDR3,CTI Component Identification Register 3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_CTICIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_CORE3_DBG"
base ad:0x730310000
group.long 0x20++0x07
line.long 0x00 "APBADDR_DBG_CPU3_EDESR,External Debug Event Status Register"
hexmask.long 0x00 3.--31. 1. "RES0_EDESR_31_3,Reserved RES0"
bitfld.long 0x00 2. "SS,Halting step debug event pending" "0,1"
newline
bitfld.long 0x00 1. "RC,Reset catch debug event pending" "0,1"
bitfld.long 0x00 0. "OSUC,OS unlock debug event pending" "0,1"
line.long 0x04 "APBADDR_DBG_CPU3_EDECR,External Debug Execution Control Register"
hexmask.long 0x04 3.--31. 1. "RES0_EDECR_31_3,Reserved RES0"
bitfld.long 0x04 2. "SS,Halting step enable" "0,1"
newline
bitfld.long 0x04 1. "RCE,Reset catch enable" "0,1"
bitfld.long 0x04 0. "OSUCE,OS unlock catch enabled" "0,1"
group.long 0x30++0x07
line.long 0x00 "APBADDR_DBG_CPU3_EDWAR_31_0,External Debug Watchpoint Address Register (low word)"
line.long 0x04 "APBADDR_DBG_CPU3_EDWAR_63_32,External Debug Watchpoint Address Register (high word)"
group.long 0x80++0x1B
line.long 0x00 "APBADDR_DBG_CPU3_DBGDTRRX_EL0,Debug Data Transfer Register Receive"
line.long 0x04 "APBADDR_DBG_CPU3_EDITR,External Debug Instruction Transfer Register"
line.long 0x08 "APBADDR_DBG_CPU3_EDSCR,External Debug Status and Control Register"
bitfld.long 0x08 31. "RES0_EDSCR_31_31,Reserved RES0" "0,1"
bitfld.long 0x08 30. "RXFULL,DTRRX full" "0,1"
newline
bitfld.long 0x08 29. "TXFULL,DTRTX full" "0,1"
bitfld.long 0x08 28. "ITO,EDITR overrun" "0,1"
newline
bitfld.long 0x08 27. "RXO,DTRRX overrun" "0,1"
bitfld.long 0x08 26. "TXU,DTRTX underrun" "0,1"
newline
bitfld.long 0x08 25. "PIPEADV,Pipeline advance" "0,1"
bitfld.long 0x08 24. "ITE,ITR empty" "0,1"
newline
bitfld.long 0x08 22.--23. "INTDIS,Interrupt disable" "0,1,2,3"
bitfld.long 0x08 21. "TDA,Trap debug registers accesses" "0,1"
newline
bitfld.long 0x08 20. "MA,Memory access mode" "0,1"
bitfld.long 0x08 19. "RES0_EDSCR_19_19,Reserved RES0" "0,1"
newline
bitfld.long 0x08 18. "NS,Non-secure status" "0,1"
bitfld.long 0x08 17. "RES0_EDSCR_17_17,Reserved RES0" "0,1"
newline
bitfld.long 0x08 16. "SDD,Secure debug disabled" "0,1"
bitfld.long 0x08 15. "RES0_EDSCR_15_15,Reserved RES0" "0,1"
newline
bitfld.long 0x08 14. "HDE,Halting debug mode enable" "0,1"
bitfld.long 0x08 10.--13. "RW,Exception level register-width status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 8.--9. "EL,Exception level" "0,1,2,3"
bitfld.long 0x08 7. "A,System Error interrupt pending" "0,1"
newline
bitfld.long 0x08 6. "ERR,Cumulative error flag" "0,1"
bitfld.long 0x08 0.--5. "STATUS,Debug status flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "APBADDR_DBG_CPU3_DBGDTRTX_EL0,Debug Data Transfer Register Transmit"
line.long 0x10 "APBADDR_DBG_CPU3_EDRCR,External Debug Reserve Control Register"
hexmask.long 0x10 5.--31. 1. "RES0_EDRCR_31_5,Reserved RES0"
bitfld.long 0x10 4. "CBRRQ,Allow imprecise entry to Debug state" "0,1"
newline
bitfld.long 0x10 3. "CSPA,Clear Sticky Pipeline Advance" "0,1"
bitfld.long 0x10 2. "CSE,Clear Sticky Error" "0,1"
newline
bitfld.long 0x10 0.--1. "RES0_EDRCR_1_0,Reserved RES0" "0,1,2,3"
line.long 0x14 "APBADDR_DBG_CPU3_EDACR,External Debug Auxiliary Control Register"
line.long 0x18 "APBADDR_DBG_CPU3_EDECCR,External Debug Exception Catch Control Register"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDECCR_31_8,Reserved RES0"
bitfld.long 0x18 4.--7. "NSE,Coarse-grained Non-secure exception catch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 0.--3. "SE,Coarse-grained Secure exception catch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xA0++0x0F
line.long 0x00 "APBADDR_DBG_CPU3_EDPCSR_31_0,External Debug Program Counter Sample Register (low word)"
line.long 0x04 "APBADDR_DBG_CPU3_EDCIDSR,External Debug Context ID Sample Register"
line.long 0x08 "APBADDR_DBG_CPU3_EDVIDSR,External Debug Virtual Context Sample Register"
bitfld.long 0x08 31. "NS,Non-secure state sample" "0,1"
bitfld.long 0x08 30. "E2,Exception level 2 status sample" "0,1"
newline
bitfld.long 0x08 29. "E3,Exception level 3 status sample" "0,1"
bitfld.long 0x08 28. "HV,EDPCSR high half valid" "0,1"
newline
hexmask.long.tbyte 0x08 8.--27. 1. "RES0_EDVIDSR_27_8,Reserved RES0"
hexmask.long.byte 0x08 0.--7. 1. "VMID,VMID sample"
line.long 0x0C "APBADDR_DBG_CPU3_EDPCSR_63_32,External Debug Program Counter Sample Register (high word)"
group.long 0x300++0x03
line.long 0x00 "APBADDR_DBG_CPU3_OSLAR_EL1,OS Lock Access Register"
hexmask.long 0x00 1.--31. 1. "RES0_OSLAR_EL1_31_1,Reserved RES0"
bitfld.long 0x00 0. "OSLK,On writes to OSLAR_EL1 bit[0] is copied to the OS lock.Use EDPRSR.OSLK to check the current status of the lock" "0,1"
group.long 0x310++0x07
line.long 0x00 "APBADDR_DBG_CPU3_EDPRCR,External Debug Power/Reset Control Register"
hexmask.long 0x00 4.--31. 1. "RES0_EDPRCR_31_4,Reserved RES0"
bitfld.long 0x00 3. "COREPURQ,Core powerup request" "0,1"
newline
bitfld.long 0x00 2. "RES0_EDPRCR_2_2,Reserved RES0" "0,1"
bitfld.long 0x00 1. "CWRR,Warm reset request" "0,1"
newline
bitfld.long 0x00 0. "CORENPDRQ,Core no powerdown request" "0,1"
line.long 0x04 "APBADDR_DBG_CPU3_EDPRSR,External Debug Processor Status Register"
hexmask.long.tbyte 0x04 12.--31. 1. "RES0_EDPRSR_31_12,Reserved RES0"
bitfld.long 0x04 11. "SDR,Sticky debug restart" "0,1"
newline
bitfld.long 0x04 10. "SPMAD,Sticky EPMAD error" "0,1"
bitfld.long 0x04 9. "EPMAD,External performance monitors access disable status" "0,1"
newline
bitfld.long 0x04 8. "SDAD,Sticky EDAD error" "0,1"
bitfld.long 0x04 7. "EDAD,External debug access disable status" "0,1"
newline
bitfld.long 0x04 6. "DLK,OS Double Lock status bit" "0,1"
bitfld.long 0x04 5. "OSLK,OS lock status bit" "0,1"
newline
bitfld.long 0x04 4. "HALTED,Halted status bit" "0,1"
bitfld.long 0x04 3. "SR,Sticky core reset status bit" "0,1"
newline
bitfld.long 0x04 2. "R,Core reset status bit" "0,1"
bitfld.long 0x04 1. "SPD,Sticky core power-down status bit.This bit is set to 1 on Cold reset to indicate the state of the debug registers has been lost" "0,1"
newline
bitfld.long 0x04 0. "PU,Core power-up status bit" "0,1"
group.long 0x400++0x0B
line.long 0x00 "APBADDR_DBG_CPU3_DBGBVR0_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU3_DBGBVR0_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU3_DBGBCR0_EL1,Debug Breakpoint Control Register 0"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR0_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR0_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR0_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x410++0x0B
line.long 0x00 "APBADDR_DBG_CPU3_DBGBVR1_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU3_DBGBVR1_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU3_DBGBCR1_EL1,Debug Breakpoint Control Register 1"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR1_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR1_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR1_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x420++0x0B
line.long 0x00 "APBADDR_DBG_CPU3_DBGBVR2_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU3_DBGBVR2_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU3_DBGBCR2_EL1,Debug Breakpoint Control Register 2"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR2_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR2_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR2_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x430++0x0B
line.long 0x00 "APBADDR_DBG_CPU3_DBGBVR3_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU3_DBGBVR3_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU3_DBGBCR3_EL1,Debug Breakpoint Control Register 3"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR3_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR3_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR3_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x440++0x0B
line.long 0x00 "APBADDR_DBG_CPU3_DBGBVR4_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU3_DBGBVR4_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU3_DBGBCR4_EL1,Debug Breakpoint Control Register 4"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR4_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR4_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR4_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x450++0x0B
line.long 0x00 "APBADDR_DBG_CPU3_DBGBVR5_EL1_31_0,Debug Breakpoint Value Registers"
line.long 0x04 "APBADDR_DBG_CPU3_DBGBVR5_EL1_63_32,Debug Breakpoint Extended Value Registers"
line.long 0x08 "APBADDR_DBG_CPU3_DBGBCR5_EL1,Debug Breakpoint Control Register 5"
hexmask.long.byte 0x08 24.--31. 1. "RES0_DBGBCR5_EL1_31_24,Reserved RES0"
bitfld.long 0x08 20.--23. "BT,Breakpoint Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
bitfld.long 0x08 9.--12. "RES0_DBGBCR5_EL1_12_9,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 5.--8. "BAS,Byte address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3.--4. "RES0_DBGBCR5_EL1_4_3,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x08 1.--2. "PMC,Privilege mode control" "0,1,2,3"
bitfld.long 0x08 0. "E,Enable breakpoint DBGBVR<n>_EL1" "0,1"
group.long 0x800++0x0B
line.long 0x00 "APBADDR_DBG_CPU3_DBGWVR0_EL1_31_0,Debug Watchpoint Value Register 0"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR0_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU3_DBGWVR0_EL1_63_32,Debug Watchpoint Extended Value Register 0"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU3_DBGWCR0_EL1,Debug Watchpoint Control Register 0"
bitfld.long 0x08 29.--31. "RES0_DBGWCR0_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 21.--23. "RES0_DBGWCR0_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
newline
bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0x810++0x0B
line.long 0x00 "APBADDR_DBG_CPU3_DBGWVR1_EL1_31_0,Debug Watchpoint Value Register 1"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR1_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU3_DBGWVR1_EL1_63_32,Debug Watchpoint Extended Value Register 1"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU3_DBGWCR1_EL1,Debug Watchpoint Control Register 1"
bitfld.long 0x08 29.--31. "RES0_DBGWCR1_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 21.--23. "RES0_DBGWCR1_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
newline
bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0x820++0x0B
line.long 0x00 "APBADDR_DBG_CPU3_DBGWVR2_EL1_31_0,Debug Watchpoint Value Register 2"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR2_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU3_DBGWVR2_EL1_63_32,Debug Watchpoint Extended Value Register 2"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU3_DBGWCR2_EL1,Debug Watchpoint Control Register 2"
bitfld.long 0x08 29.--31. "RES0_DBGWCR2_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 21.--23. "RES0_DBGWCR2_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
newline
bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
newline
bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
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bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
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bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0x830++0x0B
line.long 0x00 "APBADDR_DBG_CPU3_DBGWVR3_EL1_31_0,Debug Watchpoint Value Register 3"
hexmask.long 0x00 2.--31. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
bitfld.long 0x00 0.--1. "RES0_DBGWVR3_EL1_31_0_1_0,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_DBG_CPU3_DBGWVR3_EL1_63_32,Debug Watchpoint Extended Value Register 3"
hexmask.long.word 0x04 17.--31. 1. "RESS,Reserved Sign extended"
hexmask.long.tbyte 0x04 0.--16. 1. "VA,Bits[48:2] of the address value for comparison.ARM deprecates setting DBGWVR<n>_EL1[2] == 1"
line.long 0x08 "APBADDR_DBG_CPU3_DBGWCR3_EL1,Debug Watchpoint Control Register 3"
bitfld.long 0x08 29.--31. "RES0_DBGWCR3_EL1_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "MASK,Address mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 21.--23. "RES0_DBGWCR3_EL1_23_21,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 20. "WT,Watchpoint type" "0,1"
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bitfld.long 0x08 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 14.--15. "SSC,Security state control" "0,1,2,3"
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bitfld.long 0x08 13. "HMC,Higher mode control" "0,1"
hexmask.long.byte 0x08 5.--12. 1. "BAS,Byte address select"
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bitfld.long 0x08 3.--4. "LSC,Load/store control" "0,1,2,3"
bitfld.long 0x08 1.--2. "PAC,Privilege of access control" "0,1,2,3"
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bitfld.long 0x08 0. "E,Enable watchpoint n" "0,1"
group.long 0xD00++0x03
line.long 0x00 "APBADDR_DBG_CPU3_MIDR_EL1,Main ID Register"
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,The Implementer code"
bitfld.long 0x00 20.--23. "VARIANT,An IMPLEMENTATION DEFINED variant number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "ARCHITECTURE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 4.--15. 1. "PARTNUM,An IMPLEMENTATION DEFINED primary part number for the device"
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bitfld.long 0x00 0.--3. "REVISION,An IMPLEMENTATION DEFINED revision number for the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD20++0x3F
line.long 0x00 "APBADDR_DBG_CPU3_ID_AA64PFR0_EL1_31_0,Processor Feature Register 0 (low word)"
bitfld.long 0x00 28.--31. "RES0_ID_AA64PFR0_EL1_31_0_31_28,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "GIC,GIC system register interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "ADVSIMD,Advanced SIMD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "FP,Floating-point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "EL3,EL3 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "EL2,EL2 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "EL1,EL1 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "EL0,EL0 exception level handling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_DBG_CPU3_ID_AA64PFR0_EL1_63_32,Processor Feature Register 0 (high word)"
line.long 0x08 "APBADDR_DBG_CPU3_ID_AA64DFR0_EL1_31_0,Debug Feature Register 0 (low word)"
bitfld.long 0x08 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 24.--27. "RES0_ID_AA64DFR0_EL1_31_0_27_24,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "WRPS,Number of watchpoints minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 16.--19. "RES0_ID_AA64DFR0_EL1_31_0_19_16,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 12.--15. "BRPS,Number of breakpoints minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 8.--11. "PMUVER,Performance Monitors extension version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4.--7. "TRACEVER,Trace extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--3. "DEBUGVER,Debug architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_DBG_CPU3_ID_AA64DFR0_EL1_63_32,Debug Feature Register 0 (high word)"
line.long 0x10 "APBADDR_DBG_CPU3_ID_AA64ISAR0_EL1_31_0,Instruction Set Attribute Register 0 (low word)"
hexmask.long.word 0x10 20.--31. 1. "RES0_ID_AA64ISAR0_EL1_31_0_31_20,Reserved RES0"
bitfld.long 0x10 16.--19. "CRC32,CRC32 instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 12.--15. "SHA2,SHA2 instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 8.--11. "SHA1,SHA1 instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 4.--7. "AES,AES instructions in AArch64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 0.--3. "RES0_ID_AA64ISAR0_EL1_31_0_3_0,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_DBG_CPU3_ID_AA64ISAR0_EL1_63_32,Instruction Set Attribute Register 0 (high word)"
line.long 0x18 "APBADDR_DBG_CPU3_ID_AA64MMFR0_EL1_31_0,Memory Model Feature Register 0 (low word)"
bitfld.long 0x18 28.--31. "TGRAN4,Support for 4 Kbyte memory translation granule size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 24.--27. "TGRAN64,Support for 64 Kbyte memory translation granule size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 20.--23. "TGRAN16,Support for 16 Kbyte memory translation granule size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 16.--19. "BIGENDEL0,Mixed-endian support at EL0 only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 8.--11. "BIGEND,Mixed-endian configuration support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 4.--7. "ASIDBITS,Number of ASID bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 0.--3. "PARANGE,Physical Address range supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "APBADDR_DBG_CPU3_ID_AA64MMFR0_EL1_63_32,Memory Model Feature Register 0 (high word)"
line.long 0x20 "APBADDR_DBG_CPU3_ID_AA64PFR1_EL1_31_0,Processor Feature Register 1 (low word)"
line.long 0x24 "APBADDR_DBG_CPU3_ID_AA64PFR1_EL1_63_32,Processor Feature Register 1 (high word)"
line.long 0x28 "APBADDR_DBG_CPU3_ID_AA64DFR1_EL1_31_0,Auxiliary Feature Register 1 (low word)"
line.long 0x2C "APBADDR_DBG_CPU3_ID_AA64DFR1_EL1_63_32,Auxiliary Feature Register 1 (high word)"
line.long 0x30 "APBADDR_DBG_CPU3_ID_AA64ISAR1_EL1_31_0,Instruction Set Attribute Register 1 (low word)"
line.long 0x34 "APBADDR_DBG_CPU3_ID_AA64ISAR1_EL1_63_32,Instruction Set Attribute Register 1 (high word)"
line.long 0x38 "APBADDR_DBG_CPU3_ID_AA64MMFR1_EL1_31_0,Memory Model Feature Register 1 (low word)"
line.long 0x3C "APBADDR_DBG_CPU3_ID_AA64MMFR1_EL1_63_32,Memory Model Feature Register 1 (high word)"
group.long 0xF00++0x03
line.long 0x00 "APBADDR_DBG_CPU3_EDITCTRL,External Debug Integration mode Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_EDITCTRL_31_1,Reserved RES0"
bitfld.long 0x00 0. "IME,Integration mode enable" "0,1"
group.long 0xFA0++0x33
line.long 0x00 "APBADDR_DBG_CPU3_DBGCLAIMSET_EL1,Debug Claim Tag Set Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_DBGCLAIMSET_EL1_31_8,Reserved RAZ/SBZ"
hexmask.long.byte 0x00 0.--7. 1. "CLAIM,Claim set bits"
line.long 0x04 "APBADDR_DBG_CPU3_DBGCLAIMCLR_EL1,Debug Claim Tag Clear Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_DBGCLAIMCLR_EL1_31_8,Reserved RAZ/SBZ"
hexmask.long.byte 0x04 0.--7. 1. "CLAIM,Claim clear bits"
line.long 0x08 "APBADDR_DBG_CPU3_EDDEVAFF0,External Debug Device Affinity Register 0"
line.long 0x0C "APBADDR_DBG_CPU3_EDDEVAFF1,External Debug Device Affinity Register 1"
line.long 0x10 "APBADDR_DBG_CPU3_EDLAR,External Debug Lock Access Register"
line.long 0x14 "APBADDR_DBG_CPU3_EDLSR,External Debug Lock Status Register"
hexmask.long 0x14 3.--31. 1. "RES0_EDLSR_31_3,Reserved RES0"
bitfld.long 0x14 2. "NTT,Not thirty-two bit access required" "0,1"
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bitfld.long 0x14 1. "SLK,Software lock status for this component" "0,1"
bitfld.long 0x14 0. "SLI,Software lock implemented" "0,1"
line.long 0x18 "APBADDR_DBG_CPU3_DBGAUTHSTATUS_EL1,Debug Authentication Status register"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_DBGAUTHSTATUS_EL1_31_8,Reserved RES0"
bitfld.long 0x18 6.--7. "SNID,Secure non-invasive debug" "0,1,2,3"
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bitfld.long 0x18 4.--5. "SID,Secure invasive debug" "0,1,2,3"
bitfld.long 0x18 2.--3. "NSNID,Non-secure non-invasive debug" "0,1,2,3"
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bitfld.long 0x18 0.--1. "NSID,Non-secure invasive debug" "0,1,2,3"
line.long 0x1C "APBADDR_DBG_CPU3_EDDEVARCH,External Debug Device Architecture Register"
hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A" "0,1"
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bitfld.long 0x1C 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
line.long 0x20 "APBADDR_DBG_CPU3_EDDEVID2,External Debug Device ID Register 2"
line.long 0x24 "APBADDR_DBG_CPU3_EDDEVID1,External Debug Device ID Register 1"
hexmask.long 0x24 4.--31. 1. "RES0_EDDEVID1_31_4,Reserved RES0"
bitfld.long 0x24 0.--3. "PCSROFFSET,This field indicates the offset applied to PC samples returned by reads of EDPCSR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "APBADDR_DBG_CPU3_EDDEVID,External Debug Device ID Register 0"
bitfld.long 0x28 28.--31. "RES0_EDDEVID_31_28,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 24.--27. "AUXREGS,Indicates support for Auxiliary registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.tbyte 0x28 4.--23. 1. "RES0_EDDEVID_23_4,Reserved RES0"
bitfld.long 0x28 0.--3. "PCSAMPLE,Indicates the level of Sample-based profiling support using external debug registers 40 through 43" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "APBADDR_DBG_CPU3_EDDEVTYPE,External Debug Device Type Register"
hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_EDDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x2C 4.--7. "SUB,Subtype" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 0.--3. "MAJOR,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "APBADDR_DBG_CPU3_EDPIDR4,External Debug Peripheral Identification Register 4"
hexmask.long.tbyte 0x30 8.--31. 1. "RES0_EDPIDR4_31_8,Reserved RES0"
bitfld.long 0x30 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 0.--3. "DES_2,Designer JEP106 continuation code least significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFE0++0x1F
line.long 0x00 "APBADDR_DBG_CPU3_EDPIDR0,External Debug Peripheral Identification Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_EDPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number least significant byte"
line.long 0x04 "APBADDR_DBG_CPU3_EDPIDR1,External Debug Peripheral Identification Register 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_EDPIDR1_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "DES_0,Designer least significant nibble of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. "PART_1,Part number most significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_DBG_CPU3_EDPIDR2,External Debug Peripheral Identification Register 2"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_EDPIDR2_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "REVISION,Part major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 3. "JEDEC,RAO" "0,1"
bitfld.long 0x08 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x0C "APBADDR_DBG_CPU3_EDPIDR3,External Debug Peripheral Identification Register 3"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_EDPIDR3_31_8,Reserved RES0"
bitfld.long 0x0C 4.--7. "REVAND,Part minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_DBG_CPU3_EDCIDR0,External Debug Component Identification Register 0"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_EDCIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x14 "APBADDR_DBG_CPU3_EDCIDR1,External Debug Component Identification Register 1"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_EDCIDR1_31_8,Reserved RES0"
bitfld.long 0x14 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_DBG_CPU3_EDCIDR2,External Debug Component Identification Register 2"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_EDCIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x1C "APBADDR_DBG_CPU3_EDCIDR3,External Debug Component Identification Register 3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_EDCIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_CORE3_ECC_AGGR"
base ad:0x719000
rgroup.long 0x00++0x03
line.long 0x00 "ECC_AGGR_CORE3_REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
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bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
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bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "ECC_AGGR_CORE3_REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
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hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ECC_AGGR_CORE3_REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ECC_AGGR_CORE3_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "ECC_AGGR_CORE3_REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_CORE3_REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 26. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 25. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 24. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 23. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 22. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 21. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 20. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 19. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 18. "CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 17. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 16. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 15. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 14. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 13. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 12. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 11. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 10. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 9. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 8. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 7. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 6. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 5. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 4. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 3. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 2. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 1. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 0. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ECC_AGGR_CORE3_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 26. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 25. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 24. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 23. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 22. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 21. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 20. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 19. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 18. "CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 17. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 16. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 15. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 14. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 13. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 12. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 11. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 10. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 9. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 8. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 7. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 6. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 5. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 4. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 3. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 2. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 1. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 0. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ECC_AGGR_CORE3_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 26. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 25. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 24. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 23. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 22. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 21. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 20. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 19. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 18. "CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 17. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 16. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 15. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 14. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 13. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 12. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 11. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 10. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 9. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 8. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 7. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 6. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 5. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 4. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 3. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 2. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 1. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 0. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ECC_AGGR_CORE3_REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_CORE3_REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 26. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 25. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 24. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 23. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 22. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 21. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 20. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 19. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 18. "CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 17. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 16. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 15. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 14. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 13. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 12. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 11. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 10. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 8. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 7. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 6. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 5. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 4. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 2. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 1. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 0. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_PEND,Interrupt Pending Status for cpu3_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ECC_AGGR_CORE3_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 26. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 25. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 24. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 23. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 22. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 21. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 20. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 18. "CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 16. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 14. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 12. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 10. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 8. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 6. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 4. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 2. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 0. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for cpu3_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ECC_AGGR_CORE3_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 26. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 25. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 24. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 23. "CPU3_A53_DUAL_U_L1D_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_l1d_tagram_spram_way0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 22. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 21. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 20. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 19. "CPU3_A53_DUAL_U_TLB_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_tlb_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 18. "CPU3_A53_DUAL_U_DDIRTY_SPRAM_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddirty_spram_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 17. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 16. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 14. "CPU3_A53_DUAL_U_DTAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_dtag_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 13. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank7_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 12. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank6_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 11. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank5_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 10. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank4_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank3_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 8. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 7. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 6. "CPU3_A53_DUAL_U_DDATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_ddata_spram_bank0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 5. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_itag_spram_ram1_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 4. "CPU3_A53_DUAL_U_ITAG_SPRAM_RAM0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_itag_spram_ram0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank1_hi_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 2. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK1_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank1_lo_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 1. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_HI_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank0_hi_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 0. "CPU3_A53_DUAL_U_IDATA_SPRAM_BANK0_LO_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for cpu3_a53_dual_u_idata_spram_bank0_lo_ecc_svbus_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ECC_AGGR_CORE3_REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ECC_AGGR_CORE3_REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ECC_AGGR_CORE3_REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ECC_AGGR_CORE3_REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "A53SS0_CORE3_ETM"
base ad:0x730330000
group.long 0x04++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCPRGCTLR,Programming Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_TRCPRGCTLR_31_1,Reserved RES0"
bitfld.long 0x00 0. "EN,Trace unit enable bit" "0,1"
group.long 0x0C++0x07
line.long 0x00 "APBADDR_ETM_CPU3_TRCSTATR,Status Register"
hexmask.long 0x00 2.--31. 1. "RES0_TRCSTATR_31_2,Reserved RES0"
bitfld.long 0x00 1. "PMSTABLE,Programmer's model stable bit: 0 The programmer's model is not stable" "0,1"
bitfld.long 0x00 0. "IDLE,Idle status bit: 0 The trace unit is not idle" "0,1"
line.long 0x04 "APBADDR_ETM_CPU3_TRCCONFIGR,Trace Configuration Register"
hexmask.long.word 0x04 18.--31. 1. "RES0_TRCCONFIGR_31_18,Reserved RES0"
bitfld.long 0x04 17. "DV,Data value tracing bit: 0 Data value tracing is disabled" "0,1"
bitfld.long 0x04 16. "DA,Data address tracing bit: 0 Data address tracing is disabled" "0,1"
newline
bitfld.long 0x04 15. "RES0_TRCCONFIGR_15_15,Reserved RES0" "0,1"
bitfld.long 0x04 13.--14. "QE,Q element enable field: 00 Q elements are disabled" "0,1,2,3"
bitfld.long 0x04 12. "RS,Return stack enable bit" "0,1"
newline
bitfld.long 0x04 11. "TS,Global timestamp tracing bit: 0 Global timestamp tracing is disabled" "0,1"
bitfld.long 0x04 8.--10. "COND,Conditional instruction tracing bit" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "VMID,VMID tracing bit: 0 VMID tracing is disabled" "0,1"
newline
bitfld.long 0x04 6. "CID,Context ID tracing bit: 0 Context ID tracing is disabled" "0,1"
bitfld.long 0x04 5. "RES0_TRCCONFIGR_5_5,Reserved RES0" "0,1"
bitfld.long 0x04 4. "CCI,Cycle counting instruction trace bit: 0 Cycle counting in the instruction trace is disabled" "0,1"
newline
bitfld.long 0x04 3. "BB,Branch broadcast mode bit: 0 Branch broadcast mode is disabled" "0,1"
bitfld.long 0x04 1.--2. "INSTP0,Instruction P0 bit" "0,1,2,3"
bitfld.long 0x04 0. "RES1_TRCCONFIGR_0_0,Reserved RES1" "0,1"
group.long 0x18++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCAUXCTLR,Auxiliary Control Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_TRCAUXCTLR_31_8,Reserved RES0"
bitfld.long 0x00 7. "COREIFEN,Keep core interface enabled regardless of trace enable register state" "0,1"
bitfld.long 0x00 6. "RES0_TRCAUXCTLR_6_6,Reserved RES0" "0,1"
newline
bitfld.long 0x00 5. "AUTHNOFLUSH,Do not flush trace on de-assertion of authentication inputs" "0,1"
bitfld.long 0x00 4. "TSNODELAY,Do not delay timestamp insertion based on FIFO depth" "0,1"
bitfld.long 0x00 3. "SYNCDELAY,Delay periodic synchronization if FIFO is more than half-full" "0,1"
newline
bitfld.long 0x00 2. "OVFLW,Force an overflow if synchronization is not completed when second synchronization becomes due" "0,1"
bitfld.long 0x00 1. "IDLEACK,Force idle-drain acknowledge high CPU does not wait for trace to drain before entering WFX state" "0,1"
bitfld.long 0x00 0. "AFREADY,Always respond to AFREADY immediately" "0,1"
group.long 0x20++0x07
line.long 0x00 "APBADDR_ETM_CPU3_TRCEVENTCTL0R,Event Control 0 Register"
bitfld.long 0x00 31. "TYPE3,Selects the resource type for trace event 3" "0,1"
bitfld.long 0x00 28.--30. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--27. "SEL3,Selects the resource number based on the value of TYPE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 23. "TYPE2,Selects the resource type for trace event 2" "0,1"
bitfld.long 0x00 20.--22. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "SEL2,Selects the resource number based on the value of TYPE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 15. "TYPE1,Selects the resource type for trace event 1" "0,1"
bitfld.long 0x00 12.--14. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "SEL1,Selects the resource number based on the value of TYPE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "TYPE0,Selects the resource type for trace event 0" "0,1"
bitfld.long 0x00 4.--6. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "SEL0,Selects the resource number based on the value of TYPE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_ETM_CPU3_TRCEVENTCTL1R,Event Control 1 Register"
hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 12. "LPOVERRIDE,Low power state behavior override" "0,1"
bitfld.long 0x04 11. "ATB,ATB trigger enable" "0,1"
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hexmask.long.byte 0x04 4.--10. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "EN,One bit per event to enable generation of an event element in the instruction trace stream when the selected event occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x17
line.long 0x00 "APBADDR_ETM_CPU3_TRCSTALLCTLR,Stall Control Register"
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 8. "ISTALL,Controls if the trace unit can stall the processor when the instruction trace buffer space is less than LEVEL" "0,1"
bitfld.long 0x00 4.--7. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 2.--3. "LEVEL,The field can support 4 monotonic levels from 0b00 to 0b11" "0,1,2,3"
bitfld.long 0x00 0.--1. "RESERVED,Reserved RES0" "0,1,2,3"
line.long 0x04 "APBADDR_ETM_CPU3_TRCTSCTLR,Global Timestamp Control Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_TRCTSCTLR_31_8,Reserved RES0"
hexmask.long.byte 0x04 0.--7. 1. "EVENT,An event selector"
line.long 0x08 "APBADDR_ETM_CPU3_TRCSYNCPR,Synchronization Period Register"
hexmask.long 0x08 5.--31. 1. "RES0_TRCSYNCPR_31_5,Reserved RES0"
bitfld.long 0x08 0.--4. "PERIOD,Controls how many bytes of trace the sum of instruction and data that a trace unit can generate before a periodic trace synchronization request occurs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "APBADDR_ETM_CPU3_TRCCCCTLR,Cycle Count Control Register"
hexmask.long.tbyte 0x0C 12.--31. 1. "RES0_TRCCCCTLR_31_12,Reserved RES0"
hexmask.long.word 0x0C 0.--11. 1. "THRESHOLD,Sets the threshold value for instruction trace cycle counting.The minimum threshold value that can be programmed into THRESHOLD is given in TRCIDR3.CCITMIN.Writing a value of zero might cause UNPREDICTABLE behaviour"
line.long 0x10 "APBADDR_ETM_CPU3_TRCBBCTLR,Branch Broadcast Control Register"
hexmask.long.tbyte 0x10 9.--31. 1. "RES0_TRCBBCTLR_31_9,Reserved RES0"
bitfld.long 0x10 8. "MODE,Mode bit: 0 Exclude mode" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "RANGE,Address range field"
line.long 0x14 "APBADDR_ETM_CPU3_TRCTRACEIDR,Trace ID Register"
hexmask.long 0x14 7.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x14 0.--6. 1. "TRACEID,Trace ID value"
group.long 0x80++0x0B
line.long 0x00 "APBADDR_ETM_CPU3_TRCVICTLR,ViewInst Main Control Register"
hexmask.long.byte 0x00 24.--31. 1. "RES0_TRCVICTLR_31_24,Reserved RES0"
bitfld.long 0x00 20.--23. "EXLEVEL_NS,In Non-secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "EXLEVEL_S,In Secure state each bit controls whether instruction tracing is enabled for the corresponding exception level: 0 The trace unit generates instruction trace in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "RES0_TRCVICTLR_15_12,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "TRCERR,If TRCIDR3.TRCERR==1 this bit controls whether a trace unit must trace a system error exception: 0 The trace unit does not trace a system error exception unless it traces the exception or instruction immediately prior to the system error exception" "0,1"
bitfld.long 0x00 10. "TRCRESET,Controls whether a trace unit must trace a Reset exception: 0 The trace unit does not trace a Reset exception unless it traces the exception or instruction immediately prior to the Reset exception" "0,1"
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bitfld.long 0x00 9. "SSSTATUS,IF TRCIDR4.NUMACPAIRS>0 or TRCIDR.NUMPC>0 this bit returns the status of the start-stop logic: 0 The start-stop logic is in the stopped state" "0,1"
bitfld.long 0x00 8. "RES0_TRCVICTLR_8_8,Reserved RES0" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "EVENT,An event selector"
line.long 0x04 "APBADDR_ETM_CPU3_TRCVIIECTLR,ViewInst Include-Exclude Control Register"
hexmask.long.byte 0x04 24.--31. 1. "RES0_TRCVIIECTLR_31_24,Reserved RES0"
hexmask.long.byte 0x04 16.--23. 1. "EXCLUDE,0 1 The implemented width of the field n is IMPLEMENTATION DEFINED and is set by the value of TRCIDR4.NUMACPAIRS"
hexmask.long.byte 0x04 8.--15. 1. "RES0_TRCVIIECTLR_15_8,Reserved RES0"
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hexmask.long.byte 0x04 0.--7. 1. "INCLUDE,Include range field"
line.long 0x08 "APBADDR_ETM_CPU3_TRCVISSCTLR,ViewInst Start-Stop Control Register"
hexmask.long.word 0x08 16.--31. 1. "STOP,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of stopping trace"
hexmask.long.word 0x08 0.--15. 1. "START,Selects which single address comparators are in use with ViewInst start-stop control for the purpose of starting trace"
group.long 0x100++0x0B
line.long 0x00 "APBADDR_ETM_CPU3_TRCSEQEVR0,Sequencer State Transition Control Registers 0"
hexmask.long.word 0x00 16.--31. 1. "RES0_TRCSEQEVR0_31_16,Reserved RES0"
hexmask.long.byte 0x00 8.--15. 1. "B_N,Backward field"
hexmask.long.byte 0x00 0.--7. 1. "F_N,Forward field"
line.long 0x04 "APBADDR_ETM_CPU3_TRCSEQEVR1,Sequencer State Transition Control Registers 1"
hexmask.long.word 0x04 16.--31. 1. "RES0_TRCSEQEVR1_31_16,Reserved RES0"
hexmask.long.byte 0x04 8.--15. 1. "B_N,Backward field"
hexmask.long.byte 0x04 0.--7. 1. "F_N,Forward field"
line.long 0x08 "APBADDR_ETM_CPU3_TRCSEQEVR2,Sequencer State Transition Control Registers 2"
hexmask.long.word 0x08 16.--31. 1. "RES0_TRCSEQEVR2_31_16,Reserved RES0"
hexmask.long.byte 0x08 8.--15. 1. "B_N,Backward field"
hexmask.long.byte 0x08 0.--7. 1. "F_N,Forward field"
group.long 0x118++0x0B
line.long 0x00 "APBADDR_ETM_CPU3_TRCSEQRSTEVR,Sequencer Reset Control Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_TRCSEQRSTEVR_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "RST,Contains an event number"
line.long 0x04 "APBADDR_ETM_CPU3_TRCSEQSTR,Sequencer State Register"
hexmask.long 0x04 2.--31. 1. "RES0_TRCSEQSTR_31_2,Reserved RES0"
bitfld.long 0x04 0.--1. "STATE,Sets or returns the state of the sequencer: 00 State 0" "0,1,2,3"
line.long 0x08 "APBADDR_ETM_CPU3_TRCEXTINSELR,External Input Select Register"
bitfld.long 0x08 29.--31. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--28. "SEL3,Selects an event from the external input bus for External Input Resource 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 21.--23. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 16.--20. "SEL2,Selects an event from the external input bus for External Input Resource 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 13.--15. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 8.--12. "SEL1,Selects an event from the external input bus for External Input Resource 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 5.--7. "RESERVED,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 0.--4. "SEL0,Selects an event from the external input bus for External Input Resource 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x140++0x07
line.long 0x00 "APBADDR_ETM_CPU3_TRCCNTRLDVR0,Counter Reload Value Registers 0"
hexmask.long.word 0x00 16.--31. 1. "RES0_TRCCNTRLDVR0_31_16,Reserved RES0"
hexmask.long.word 0x00 0.--15. 1. "VALUE_N,Contains the reload value for counter <n>"
line.long 0x04 "APBADDR_ETM_CPU3_TRCCNTRLDVR1,Counter Reload Value Registers 1"
hexmask.long.word 0x04 16.--31. 1. "RES0_TRCCNTRLDVR1_31_16,Reserved RES0"
hexmask.long.word 0x04 0.--15. 1. "VALUE_N,Contains the reload value for counter <n>"
group.long 0x150++0x07
line.long 0x00 "APBADDR_ETM_CPU3_TRCCNTCTLR0,Counter Control Register 0"
hexmask.long.word 0x00 18.--31. 1. "RES0_TRCCNTCTLR0_31_18,Reserved RES0"
bitfld.long 0x00 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter <n> decrements when a reload event occurs for counter <n-1>: 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit is RES0" "0,1"
bitfld.long 0x00 16. "RLDSELF_N,Controls whether a reload event occurs for counter <n> when counter <n> reaches zero: 0 The trace unit does not generate a reload event" "0,1"
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hexmask.long.byte 0x00 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter <n>"
hexmask.long.byte 0x00 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter <n> to decrement"
line.long 0x04 "APBADDR_ETM_CPU3_TRCCNTCTLR1,Counter Control Register 1"
hexmask.long.word 0x04 18.--31. 1. "RES0_TRCCNTCTLR1_31_18,Reserved RES0"
bitfld.long 0x04 17. "CNTCHAIN_N,For TRCCNTCTLR3 and TRCCNTCTLR1 controls whether counter <n> decrements when a reload event occurs for counter <n-1>: 0 1 For TRCCNTCTLR2 and TRCCNTCTLR0 this bit is RES0" "0,1"
bitfld.long 0x04 16. "RLDSELF_N,Controls whether a reload event occurs for counter <n> when counter <n> reaches zero: 0 The trace unit does not generate a reload event" "0,1"
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hexmask.long.byte 0x04 8.--15. 1. "RLDEVENT_N,Selects an event that when it occurs causes a reload event for counter <n>"
hexmask.long.byte 0x04 0.--7. 1. "CNTEVENT_N,Selects an event that when it occurs causes counter <n> to decrement"
group.long 0x160++0x07
line.long 0x00 "APBADDR_ETM_CPU3_TRCCNTVR0,Counter Value Registers 0"
hexmask.long.word 0x00 16.--31. 1. "RES0_TRCCNTVR0_31_16,Reserved RES0"
hexmask.long.word 0x00 0.--15. 1. "VALUE_N,Contains the count value of counter <n>"
line.long 0x04 "APBADDR_ETM_CPU3_TRCCNTVR1,Counter Value Registers 1"
hexmask.long.word 0x04 16.--31. 1. "RES0_TRCCNTVR1_31_16,Reserved RES0"
hexmask.long.word 0x04 0.--15. 1. "VALUE_N,Contains the count value of counter <n>"
group.long 0x180++0x17
line.long 0x00 "APBADDR_ETM_CPU3_TRCIDR8,ID Register 8"
line.long 0x04 "APBADDR_ETM_CPU3_TRCIDR9,ID Register 9"
line.long 0x08 "APBADDR_ETM_CPU3_TRCIDR10,ID Register 10"
line.long 0x0C "APBADDR_ETM_CPU3_TRCIDR11,ID Register 11"
line.long 0x10 "APBADDR_ETM_CPU3_TRCIDR12,ID Register 12"
line.long 0x14 "APBADDR_ETM_CPU3_TRCIDR13,ID Register 13"
group.long 0x1C0++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCIMSPEC0,Implementation Specific Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_TRCIMSPEC0_31_8,Reserved RES0"
bitfld.long 0x00 4.--7. "EN,If SUPPORT is not 0b0000 controls whether the IMPLEMENTATION DEFINED features are enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "SUPPORT,Indicates whether the implementation supports IMPLEMENTATION DEFINED features" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1E0++0x17
line.long 0x00 "APBADDR_ETM_CPU3_TRCIDR0,ID Register 0"
bitfld.long 0x00 30.--31. "RES0_TRCIDR0_31_30,Reserved RES0" "0,1,2,3"
bitfld.long 0x00 29. "COMMOPT,Conditional instruction tracing support bit" "0,1"
bitfld.long 0x00 24.--28. "TSSIZE,Global timestamp size field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 17.--23. 1. "RES0_TRCIDR0_23_17,Reserved RES0"
bitfld.long 0x00 15.--16. "QSUPP,Q element support field" "0,1,2,3"
bitfld.long 0x00 14. "QFILT,Q element filtering support field" "0,1"
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bitfld.long 0x00 12.--13. "CONDTYPE,Conditional tracing field" "0,1,2,3"
bitfld.long 0x00 10.--11. "NUMEVENT,Number of events field" "0,1,2,3"
bitfld.long 0x00 9. "RETSTACK,Return stack bit" "0,1"
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bitfld.long 0x00 8. "RES0_TRCIDR0_8_8,Reserved RES0" "0,1"
bitfld.long 0x00 7. "TRCCCI,Cycle counting instruction bit" "0,1"
bitfld.long 0x00 6. "TRCCOND,Conditional instruction tracing support bit" "0,1"
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bitfld.long 0x00 5. "TRCBB,Branch broadcast tracing support bit" "0,1"
bitfld.long 0x00 3.--4. "TRCDATA,Conditional tracing field" "0,1,2,3"
bitfld.long 0x00 1.--2. "INSTP0,P0 tracing support field" "0,1,2,3"
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bitfld.long 0x00 0. "RES0_TRCIDR0_0_0,Reserved RES0" "0,1"
line.long 0x04 "APBADDR_ETM_CPU3_TRCIDR1,ID Register 1"
hexmask.long.byte 0x04 24.--31. 1. "DESIGNER,Indicates which company designed the trace unit"
hexmask.long.byte 0x04 16.--23. 1. "RES0_TRCIDR1_23_16,Reserved RES0"
bitfld.long 0x04 12.--15. "RES1_TRCIDR1_15_12,Reserved RES1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 8.--11. "TRCARCHMAJ,Indicates the major version of the ETM architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 4.--7. "TRCARCHMIN,Indicates the minor version of the ETM architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "REVISION,Returns an IMPLEMENTATION DEFINED value that identifies the revision of the trace registers and the OS Save and Restore registers.ARM recommends:That the initial implementation sets REVISION==0x0 and the field then increments for any subsequent.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_ETM_CPU3_TRCIDR2,ID Register 2"
bitfld.long 0x08 29.--31. "RES0_TRCIDR2_31_29,Reserved RES0" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 25.--28. "CCSIZE,Indicates the size of the cycle counter in bits minus 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 20.--24. "DVSIZE,Indicates the data value size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 15.--19. "DASIZE,Indicates the data address size in bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 10.--14. "VMIDSIZE,Indicates the VMID size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 5.--9. "CIDSIZE,Indicates the Context ID size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 0.--4. "IASIZE,Indicates the instruction address size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "APBADDR_ETM_CPU3_TRCIDR3,ID Register 3"
bitfld.long 0x0C 31. "NOOVERFLOW,Indicates if TRCSTALLCTLR.NOOVERFLOW is supported: 0 TRCSTALLCTLR.NOOVERFLOW is not supported or STALLCTL==0" "0,1"
bitfld.long 0x0C 28.--30. "NUMPROC,Indicates the number of processors available for tracing" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 27. "SYSSTALL,Indicates if the implementation can support stall control: 0 The system does not support stall control of the processor" "0,1"
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bitfld.long 0x0C 26. "STALLCTL,Indicates if TRCSTALLCTLR is supported: 0 TRCSTALLCTLR is not supported" "0,1"
bitfld.long 0x0C 25. "SYNCPR,Indicates if an implementation has a fixed synchronization period: 0 TRCSYNCPR is read-write so software can change the synchronization period" "0,1"
bitfld.long 0x0C 24. "TRCERR,Indicates if TRCVICTLR.TRCERR is supported: 0 TRCVICTLR.TRCERR is not supported 1 TRCVICTLR.TRCERR is supported" "0,1"
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bitfld.long 0x0C 20.--23. "EXLEVEL_NS,In Non-secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Non-secure state exception level n is not supported so the corresponding bits in TRCACATRn.EXLEVEL_NS and.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 16.--19. "EXLEVEL_S,In Secure state each bit indicates whether instruction tracing is supported for the corresponding exception level: 0 In Secure state exception level n is not supported so the corresponding bits in TRCACATRn.EXLEVEL_S and TRCVICTLR.EXLEVEL_S.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 12.--15. "RES0_TRCIDR3_15_12,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x0C 0.--11. 1. "CCITMIN,Indicates the minimum value that can be programmed in TRCCCCTLR.THRESHOLD.When cycle counting in the instruction trace is supported that is TRCIDR0.TRCCCI==1 then the minimum value of this field is 0x001 otherwise it is 0x000"
line.long 0x10 "APBADDR_ETM_CPU3_TRCIDR4,ID Register 4"
bitfld.long 0x10 28.--31. "NUMVMIDC,Indicates the number of VMID comparators that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 24.--27. "NUMCIDC,Indicates the number of Context ID comparators that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 20.--23. "NUMSSCC,Indicates the number of single-shot comparator controls that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "NUMRSPAIR,Indicates the number of resource selection pairs that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 12.--15. "NUMPC,Indicates the number of processor comparator inputs that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 9.--11. "RES0_TRCIDR4_11_9,Reserved RES0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 8. "SUPPDAC,Indicates if the implementation can support data address comparisons: 0 The implementation does not support data address comparisons" "0,1"
bitfld.long 0x10 4.--7. "NUMDVC,Indicates the number of data value comparators that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 0.--3. "NUMACPAIRS,Indicates the number of address comparator pairs that are available for tracing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "APBADDR_ETM_CPU3_TRCIDR5,ID Register 5"
bitfld.long 0x14 31. "REDFUNCNTR,Indicates if the reduced function counter is implemented: 0 The reduced function counter is not supported" "0,1"
bitfld.long 0x14 28.--30. "NUMCNTR,Indicates the number of counters that are available for tracing" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 25.--27. "NUMSEQSTATE,Indicates the number of sequencer states that are implemented" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 24. "RES0_TRCIDR5_24_24,Reserved RES0" "0,1"
bitfld.long 0x14 23. "LPOVERRIDE,Indicates if the implementation can support low-power state override: 0 The implementation does not support low-power state override" "0,1"
bitfld.long 0x14 22. "ATBTRIG,Indicates if the implementation can support ATB triggers: 0 The implementation does not support ATB triggers" "0,1"
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bitfld.long 0x14 16.--21. "TRACEIDSIZE,Indicates the trace ID width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 12.--15. "RES0_TRCIDR5_15_12,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 9.--11. "NUMEXTINSEL,Indicates how many external input select resources are implemented" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x14 0.--8. 1. "NUMEXTIN,Indicates how many external inputs are implemented"
group.long 0x208++0x37
line.long 0x00 "APBADDR_ETM_CPU3_TRCRSCTLR2,Resource Selection Control Registers 2"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCRSCTLR2_31_22,Reserved RES0"
bitfld.long 0x00 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x00 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x00 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x04 "APBADDR_ETM_CPU3_TRCRSCTLR3,Resource Selection Control Registers 3"
hexmask.long.word 0x04 22.--31. 1. "RES0_TRCRSCTLR3_31_22,Reserved RES0"
bitfld.long 0x04 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x04 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x04 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x08 "APBADDR_ETM_CPU3_TRCRSCTLR4,Resource Selection Control Registers 4"
hexmask.long.word 0x08 22.--31. 1. "RES0_TRCRSCTLR4_31_22,Reserved RES0"
bitfld.long 0x08 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x08 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x08 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x08 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x0C "APBADDR_ETM_CPU3_TRCRSCTLR5,Resource Selection Control Registers 5"
hexmask.long.word 0x0C 22.--31. 1. "RES0_TRCRSCTLR5_31_22,Reserved RES0"
bitfld.long 0x0C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x0C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x0C 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x0C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x10 "APBADDR_ETM_CPU3_TRCRSCTLR6,Resource Selection Control Registers 6"
hexmask.long.word 0x10 22.--31. 1. "RES0_TRCRSCTLR6_31_22,Reserved RES0"
bitfld.long 0x10 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x10 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x10 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x10 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x14 "APBADDR_ETM_CPU3_TRCRSCTLR7,Resource Selection Control Registers 7"
hexmask.long.word 0x14 22.--31. 1. "RES0_TRCRSCTLR7_31_22,Reserved RES0"
bitfld.long 0x14 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x14 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x14 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x14 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x18 "APBADDR_ETM_CPU3_TRCRSCTLR8,Resource Selection Control Registers 8"
hexmask.long.word 0x18 22.--31. 1. "RES0_TRCRSCTLR8_31_22,Reserved RES0"
bitfld.long 0x18 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x18 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x18 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x1C "APBADDR_ETM_CPU3_TRCRSCTLR9,Resource Selection Control Registers 9"
hexmask.long.word 0x1C 22.--31. 1. "RES0_TRCRSCTLR9_31_22,Reserved RES0"
bitfld.long 0x1C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x1C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x1C 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x1C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x20 "APBADDR_ETM_CPU3_TRCRSCTLR10,Resource Selection Control Registers 10"
hexmask.long.word 0x20 22.--31. 1. "RES0_TRCRSCTLR10_31_22,Reserved RES0"
bitfld.long 0x20 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x20 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x20 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x20 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x24 "APBADDR_ETM_CPU3_TRCRSCTLR11,Resource Selection Control Registers 11"
hexmask.long.word 0x24 22.--31. 1. "RES0_TRCRSCTLR11_31_22,Reserved RES0"
bitfld.long 0x24 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x24 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
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bitfld.long 0x24 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x24 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x28 "APBADDR_ETM_CPU3_TRCRSCTLR12,Resource Selection Control Registers 12"
hexmask.long.word 0x28 22.--31. 1. "RES0_TRCRSCTLR12_31_22,Reserved RES0"
bitfld.long 0x28 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x28 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x28 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x28 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x2C "APBADDR_ETM_CPU3_TRCRSCTLR13,Resource Selection Control Registers 13"
hexmask.long.word 0x2C 22.--31. 1. "RES0_TRCRSCTLR13_31_22,Reserved RES0"
bitfld.long 0x2C 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x2C 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x2C 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x2C 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x30 "APBADDR_ETM_CPU3_TRCRSCTLR14,Resource Selection Control Registers 14"
hexmask.long.word 0x30 22.--31. 1. "RES0_TRCRSCTLR14_31_22,Reserved RES0"
bitfld.long 0x30 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x30 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x30 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x30 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
line.long 0x34 "APBADDR_ETM_CPU3_TRCRSCTLR15,Resource Selection Control Registers 15"
hexmask.long.word 0x34 22.--31. 1. "RES0_TRCRSCTLR15_31_22,Reserved RES0"
bitfld.long 0x34 21. "PAIRINV,If n is an even number controls whether the combined result from a resource pair is inverted: 0 The combined result is not inverted" "0,1"
bitfld.long 0x34 20. "INV,Controls whether the resource that GROUP and SELECT selects is inverted: 0 The selected resource is not inverted" "0,1"
newline
bitfld.long 0x34 16.--19. "GROUP,Selects a group of resources" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x34 0.--15. 1. "SELECT,Selects one or more resources from the group that the GROUP field selects"
group.long 0x280++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCSSCCR0,Single-Shot Comparator Control Register 0"
hexmask.long.byte 0x00 25.--31. 1. "RES0_TRCSSCCR0_31_25,Reserved RES0"
bitfld.long 0x00 24. "RST,Controls whether the single-shot comparator resource is reset when it fires" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "ARC,Selects one or more address range comparators for single-shot control.Each bit represents an address range comparator pair so bit[n-16] controls the selection of address range comparator pair n-16"
newline
hexmask.long.word 0x00 0.--15. 1. "SAC,Selects one or more single address comparators for single-shot control.Each bit represents a single address comparator so bit[n] controls the selection of single address comparator n"
group.long 0x2A0++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCSSCSR0,Single-Shot Comparator Status Register 0"
bitfld.long 0x00 31. "STATUS,Single-shot status bit" "0,1"
hexmask.long 0x00 3.--30. 1. "RES0_TRCSSCSR0_30_3,Reserved RES0"
bitfld.long 0x00 2. "DV,Data value comparator support bit" "0,1"
newline
bitfld.long 0x00 1. "DA,Data address comparator support bit" "0,1"
bitfld.long 0x00 0. "INST,Instruction address comparator support bit" "0,1"
group.long 0x300++0x07
line.long 0x00 "APBADDR_ETM_CPU3_TRCOSLAR,OS Lock Access Register"
hexmask.long 0x00 1.--31. 1. "RES0_TRCOSLAR_31_1,Reserved RES0"
bitfld.long 0x00 0. "LOCK,OS Lock control bit: 0 Unlocks the OS Lock" "0,1"
line.long 0x04 "APBADDR_ETM_CPU3_TRCOSLSR,OS Lock Status Register"
hexmask.long 0x04 4.--31. 1. "RES0_TRCOSLSR_31_4,Reserved RES0"
bitfld.long 0x04 3. "PRESENT,Indicates whether the OS Lock is implemented.This bit is RES1 which indicates that the OS Lock is always implemented" "0,1"
bitfld.long 0x04 2. "BIT32,This bit is RES0 which indicates that software must perform a 32-bit write to update the TRCOSLAR" "0,1"
newline
bitfld.long 0x04 1. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked" "0,1"
bitfld.long 0x04 0. "RES0_TRCOSLSR_0_0,Reserved RES0" "0,1"
group.long 0x310++0x07
line.long 0x00 "APBADDR_ETM_CPU3_TRCPDCR,Power Down Control Register"
hexmask.long 0x00 4.--31. 1. "RES0_TRCPDCR_31_4,Reserved RES0"
bitfld.long 0x00 3. "PU,Powerup request bit: 0 The system can remove power from the trace unit" "0,1"
bitfld.long 0x00 0.--2. "RES0_TRCPDCR_2_0,Reserved RES0" "0,1,2,3,4,5,6,7"
line.long 0x04 "APBADDR_ETM_CPU3_TRCPDSR,Power Down Status Register"
hexmask.long 0x04 6.--31. 1. "RES0_TRCPDSR_31_6,Reserved RES0"
bitfld.long 0x04 5. "LOCKED,OS Lock status bit: 0 The OS Lock is unlocked" "0,1"
bitfld.long 0x04 2.--4. "RES0_TRCPDSR_4_2,Reserved RES0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 1. "STICKYPD,Sticky powerdown status bit" "0,1"
bitfld.long 0x04 0. "POWER,Power status bit: 0 The trace unit core power domain is not powered" "0,1"
group.long 0x400++0x3F
line.long 0x00 "APBADDR_ETM_CPU3_TRCACVR0_31_0,Address Comparator Value Registers 0 (low word)"
line.long 0x04 "APBADDR_ETM_CPU3_TRCACVR0_63_32,Address Comparator Value Registers 0 (high word)"
line.long 0x08 "APBADDR_ETM_CPU3_TRCACVR1_31_0,Address Comparator Value Registers 1 (low word)"
line.long 0x0C "APBADDR_ETM_CPU3_TRCACVR1_63_32,Address Comparator Value Registers 1 (high word)"
line.long 0x10 "APBADDR_ETM_CPU3_TRCACVR2_31_0,Address Comparator Value Registers 2 (low word)"
line.long 0x14 "APBADDR_ETM_CPU3_TRCACVR2_63_32,Address Comparator Value Registers 2 (high word)"
line.long 0x18 "APBADDR_ETM_CPU3_TRCACVR3_31_0,Address Comparator Value Registers 3 (low word)"
line.long 0x1C "APBADDR_ETM_CPU3_TRCACVR3_63_32,Address Comparator Value Registers 3 (high word)"
line.long 0x20 "APBADDR_ETM_CPU3_TRCACVR4_31_0,Address Comparator Value Registers 4 (low word)"
line.long 0x24 "APBADDR_ETM_CPU3_TRCACVR4_63_32,Address Comparator Value Registers 4 (high word)"
line.long 0x28 "APBADDR_ETM_CPU3_TRCACVR5_31_0,Address Comparator Value Registers 5 (low word)"
line.long 0x2C "APBADDR_ETM_CPU3_TRCACVR5_63_32,Address Comparator Value Registers 5 (high word)"
line.long 0x30 "APBADDR_ETM_CPU3_TRCACVR6_31_0,Address Comparator Value Registers 6 (low word)"
line.long 0x34 "APBADDR_ETM_CPU3_TRCACVR6_63_32,Address Comparator Value Registers 6 (high word)"
line.long 0x38 "APBADDR_ETM_CPU3_TRCACVR7_31_0,Address Comparator Value Registers 7 (low word)"
line.long 0x3C "APBADDR_ETM_CPU3_TRCACVR7_63_32,Address Comparator Value Registers 7 (high word)"
group.long 0x480++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCACATR0,Address Comparator Access Type Registers 0"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR0_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR0_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x488++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCACATR1,Address Comparator Access Type Registers 1"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR1_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR1_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x490++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCACATR2,Address Comparator Access Type Registers 2"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR2_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR2_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x498++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCACATR3,Address Comparator Access Type Registers 3"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR3_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR3_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4A0++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCACATR4,Address Comparator Access Type Registers 4"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR4_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR4_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4A8++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCACATR5,Address Comparator Access Type Registers 5"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR5_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR5_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4B0++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCACATR6,Address Comparator Access Type Registers 6"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR6_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR6_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x4B8++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCACATR7,Address Comparator Access Type Registers 7"
hexmask.long.word 0x00 22.--31. 1. "RES0_TRCACATR7_31_22,Reserved RES0"
bitfld.long 0x00 21. "DTBM,Controls whether data address comparisons use the data address [63:56] bits: 0 The trace unit ignores the data address [63:56] bits for data address comparisons" "0,1"
bitfld.long 0x00 20. "DATARANGE,Controls whether a data value comparison uses the single address comparator or the address range comparator: 0 The trace unit uses the single address comparator for data value comparisons" "0,1"
newline
bitfld.long 0x00 18.--19. "DATASIZE,Controls the width of the data value comparison: 00 Byte" "0,1,2,3"
bitfld.long 0x00 16.--17. "DATAMATCH,Controls how the trace unit performs a data value comparison: 00 The trace unit does not perform a data value comparison" "0,1,2,3"
bitfld.long 0x00 12.--15. "EXLEVEL_NS,In Non-secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Non-secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "EXLEVEL_S,In Secure state each bit controls whether a comparison can occur for the corresponding exception level: 0 The trace unit can perform a comparison in Secure state for exception level n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "RES0_TRCACATR7_7_7,Reserved RES0" "0,1"
bitfld.long 0x00 4.--6. "CONTEXT,If TRCIDR4.NUMCIDFC > 0 or TRCIDR4.NUMVMIDC > 0 selects a Context ID comparator or VMID comparator: 000 Comparator 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 2.--3. "CONTEXTTYPE,If TRCIDR4.NUMVMIDC>0 and TRCIDR4.NUMCIDC>0 this field controls whether the trace unit performs a Context ID comparison a virtual machine identifier [VMID] comparison or both comparisons: 00 The trace unit does not perform a Context ID or.." "0,1,2,3"
bitfld.long 0x00 0.--1. "TYPE,Controls what type of comparison the trace unit performs: 00 Instruction address" "0,1,2,3"
group.long 0x600++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCCIDCVR0,Context ID Comparator Value Register 0"
group.long 0x640++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCVMIDCVR0,VMID Comparator Value Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "VALUE,Contains a VMID value"
group.long 0x680++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCCIDCCTLR0,Context ID Comparator Control Register 0"
group.long 0xEE4++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCITATBIDR,Integration ATB Identification Register"
hexmask.long 0x00 7.--31. 1. "RES0_TRCITATBIDR_31_7,Reserved RES0"
hexmask.long.byte 0x00 0.--6. 1. "ID,Drives the ATIDMn[6:0] output pins"
group.long 0xEEC++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCITIDATAR,Integration Instruction ATB Data Register"
hexmask.long 0x00 5.--31. 1. "RES0_TRCITIDATAR_31_5,Reserved RES0"
bitfld.long 0x00 4. "ATDATAM_31,Drives the ATDATAM[31] output" "0,1"
bitfld.long 0x00 3. "ATDATAM_23,Drives the ATDATAM[23] output" "0,1"
newline
bitfld.long 0x00 2. "ATDATAM_15,Drives the ATDATAM[15] output" "0,1"
bitfld.long 0x00 1. "ATDATAM_7,Drives the ATDATAM[7] output" "0,1"
bitfld.long 0x00 0. "ATDATAM_0,Drives the ATDATAM[0] output" "0,1"
group.long 0xEF4++0x03
line.long 0x00 "APBADDR_ETM_CPU3_TRCITIATBINR,Integration Instruction ATB In Register"
hexmask.long 0x00 2.--31. 1. "RESERVED,Reserved"
bitfld.long 0x00 1. "AFVALIDM,Returns the value of the AFVALIDMn input pin" "0,1"
bitfld.long 0x00 0. "ATREADYM,Returns the value of the ATREADYMn input pin" "0,1"
group.long 0xEFC++0x07
line.long 0x00 "APBADDR_ETM_CPU3_TRCITIATBOUTR,Integration Instruction ATB Out Register"
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED,Reserved"
bitfld.long 0x00 8.--9. "BYTES,Drives the ATBYTESMn[1:0] output pins" "0,1,2,3"
bitfld.long 0x00 2.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 1. "AFREADY,Drives the AFREADYMn output pin" "0,1"
bitfld.long 0x00 0. "ATVALID,Drives the ATVALIDMn output pin" "0,1"
line.long 0x04 "APBADDR_ETM_CPU3_TRCITCTRL,Integration Mode Control Register"
hexmask.long 0x04 1.--31. 1. "RES0_TRCITCTRL_31_1,Reserved RES0"
bitfld.long 0x04 0. "ITEN,Integration mode enable bit: 0 The trace unit is not in integration mode" "0,1"
group.long 0xFA0++0x1F
line.long 0x00 "APBADDR_ETM_CPU3_TRCCLAIMSET,Claim Tag Set Register"
hexmask.long 0x00 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--3. "SET,Sets bits in the claim tag and determines the number of claim tag bits implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_ETM_CPU3_TRCCLAIMCLR,Claim Tag Clear Register"
hexmask.long 0x04 4.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x04 0.--3. "CLR,Clears bits in the claim tag and determines the current value of the claim tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_ETM_CPU3_TRCDEVAFF0,Device Affinity Register 0"
line.long 0x0C "APBADDR_ETM_CPU3_TRCDEVAFF1,Device Affinity Register 1"
line.long 0x10 "APBADDR_ETM_CPU3_TRCLAR,Software Lock Access Register"
line.long 0x14 "APBADDR_ETM_CPU3_TRCLSR,Software Lock Status Register"
hexmask.long 0x14 3.--31. 1. "RES0_TRCLSR_31_3,Reserved RES0"
bitfld.long 0x14 2. "NTT,Not thirty-two bit access required" "0,1"
bitfld.long 0x14 1. "SLK,Software lock status for this component" "0,1"
newline
bitfld.long 0x14 0. "SLI,Software lock implemented" "0,1"
line.long 0x18 "APBADDR_ETM_CPU3_TRCAUTHSTATUS,Authentication Status Register"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCAUTHSTATUS_31_8,Reserved RES0"
bitfld.long 0x18 6.--7. "SNID,Indicates whether the system enables the trace unit to support Secure non-invasive debug: 00 The trace unit does not implement support for Secure non-invasive debug" "0,1,2,3"
bitfld.long 0x18 4.--5. "SID,Indicates whether the trace unit supports Secure invasive debug: 00 The trace unit does not support Secure invasive debug" "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "NSNID,Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: 00 The trace unit does not implement support for Non-secure non-invasive debug" "0,1,2,3"
bitfld.long 0x18 0.--1. "NSID,Indicates whether the trace unit supports Non-secure invasive debug: 00 The trace unit does not support Non-secure invasive debug" "0,1,2,3"
line.long 0x1C "APBADDR_ETM_CPU3_TRCDEVARCH,Device Architecture Register"
hexmask.long.word 0x1C 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x1C 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is RAO" "0,1"
bitfld.long 0x1C 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x1C 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
group.long 0xFC8++0x37
line.long 0x00 "APBADDR_ETM_CPU3_TRCDEVID,Device ID Register"
line.long 0x04 "APBADDR_ETM_CPU3_TRCDEVTYPE,Device Type Register"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_TRCDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "SUB,Returns 0x1 to indicate that the ETM generates processor trace.All other values are reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "MAIN,Returns 0x3 to indicate that the ETM is a trace source.All other values are reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_ETM_CPU3_TRCPIDR4,Peripheral Identification Register 4"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_TRCPIDR4_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--3. "DES_2,Designer JEP106 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "APBADDR_ETM_CPU3_TRCPIDR5,Peripheral Identification Register 5"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_TRCPIDR5_31_8,Reserved RES0"
hexmask.long.byte 0x0C 0.--7. 1. "RESERVED,RES0 reserved for future use"
line.long 0x10 "APBADDR_ETM_CPU3_TRCPIDR6,Peripheral Identification Register 6"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_TRCPIDR6_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "RESERVED,RES0 reserved for future use"
line.long 0x14 "APBADDR_ETM_CPU3_TRCPIDR7,Peripheral Identification Register 7"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_TRCPIDR7_31_8,Reserved RES0"
hexmask.long.byte 0x14 0.--7. 1. "RESERVED,RES0 reserved for future use"
line.long 0x18 "APBADDR_ETM_CPU3_TRCPIDR0,Peripheral Identification Register 0"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_TRCPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PART_0,Part number bits[7:0]"
line.long 0x1C "APBADDR_ETM_CPU3_TRCPIDR1,Peripheral Identification Register 1"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_TRCPIDR1_31_8,Reserved RES0"
bitfld.long 0x1C 4.--7. "DES_0,Designer bits[3:0] of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "PART_1,Part number bits[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "APBADDR_ETM_CPU3_TRCPIDR2,Peripheral Identification Register 2"
hexmask.long.tbyte 0x20 8.--31. 1. "RES0_TRCPIDR2_31_8,Reserved RES0"
bitfld.long 0x20 4.--7. "REVISION,The IMPLEMENTATION DEFINED revision number for the ETM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 3. "JEDEC,RAO" "0,1"
newline
bitfld.long 0x20 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x24 "APBADDR_ETM_CPU3_TRCPIDR3,Peripheral Identification Register 3"
hexmask.long.tbyte 0x24 8.--31. 1. "RES0_TRCPIDR3_31_8,Reserved RES0"
bitfld.long 0x24 4.--7. "REVAND,The IMPLEMENTATION DEFINED manufacturing revision number for the implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "APBADDR_ETM_CPU3_TRCCIDR0,Component Identification Register 0"
hexmask.long.tbyte 0x28 8.--31. 1. "RES0_TRCCIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x28 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x2C "APBADDR_ETM_CPU3_TRCCIDR1,Component Identification Register 1"
hexmask.long.tbyte 0x2C 8.--31. 1. "RES0_TRCCIDR1_31_8,Reserved RES0"
bitfld.long 0x2C 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "APBADDR_ETM_CPU3_TRCCIDR2,Component Identification Register 2"
hexmask.long.tbyte 0x30 8.--31. 1. "RES0_TRCCIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x30 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x34 "APBADDR_ETM_CPU3_TRCCIDR3,Component Identification Register 3"
hexmask.long.tbyte 0x34 8.--31. 1. "RES0_TRCCIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x34 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_CORE3_PMU"
base ad:0x730320000
group.long 0x00++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMEVCNTR0_EL0,Performance Monitors Event Count Register 0"
group.long 0x08++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMEVCNTR1_EL0,Performance Monitors Event Count Register 1"
group.long 0x10++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMEVCNTR2_EL0,Performance Monitors Event Count Register 2"
group.long 0x18++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMEVCNTR3_EL0,Performance Monitors Event Count Register 3"
group.long 0x20++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMEVCNTR4_EL0,Performance Monitors Event Count Register 4"
group.long 0x28++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMEVCNTR5_EL0,Performance Monitors Event Count Register 5"
group.long 0xF8++0x07
line.long 0x00 "APBADDR_PMU_CPU3_PMCCNTR_EL0_31_0,Performance Monitors Cycle Counter (low word)"
line.long 0x04 "APBADDR_PMU_CPU3_PMCCNTR_EL0_63_32,Performance Monitors Cycle Counter (high word)"
group.long 0x400++0x17
line.long 0x00 "APBADDR_PMU_CPU3_PMEVTYPER0_EL0,Performance Monitors Event Type Register 0"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x00 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x00 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x00 10.--25. 1. "RES0_PMEVTYPER0_EL0_25_10,Reserved RES0"
hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x04 "APBADDR_PMU_CPU3_PMEVTYPER1_EL0,Performance Monitors Event Type Register 1"
bitfld.long 0x04 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x04 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x04 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x04 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x04 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x04 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x04 10.--25. 1. "RES0_PMEVTYPER1_EL0_25_10,Reserved RES0"
hexmask.long.word 0x04 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x08 "APBADDR_PMU_CPU3_PMEVTYPER2_EL0,Performance Monitors Event Type Register 2"
bitfld.long 0x08 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x08 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x08 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x08 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x08 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x08 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x08 10.--25. 1. "RES0_PMEVTYPER2_EL0_25_10,Reserved RES0"
hexmask.long.word 0x08 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x0C "APBADDR_PMU_CPU3_PMEVTYPER3_EL0,Performance Monitors Event Type Register 3"
bitfld.long 0x0C 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x0C 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x0C 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x0C 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x0C 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x0C 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x0C 10.--25. 1. "RES0_PMEVTYPER3_EL0_25_10,Reserved RES0"
hexmask.long.word 0x0C 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x10 "APBADDR_PMU_CPU3_PMEVTYPER4_EL0,Performance Monitors Event Type Register 4"
bitfld.long 0x10 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x10 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x10 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x10 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x10 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x10 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x10 10.--25. 1. "RES0_PMEVTYPER4_EL0_25_10,Reserved RES0"
hexmask.long.word 0x10 0.--9. 1. "EVTCOUNT,Event to count"
line.long 0x14 "APBADDR_PMU_CPU3_PMEVTYPER5_EL0,Performance Monitors Event Type Register 5"
bitfld.long 0x14 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x14 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x14 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x14 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x14 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x14 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long.word 0x14 10.--25. 1. "RES0_PMEVTYPER5_EL0_25_10,Reserved RES0"
hexmask.long.word 0x14 0.--9. 1. "EVTCOUNT,Event to count"
group.long 0x47C++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMCCFILTR_EL0,Performance Monitors Cycle Counter Filter Register"
bitfld.long 0x00 31. "P,EL1 modes filtering bit" "0,1"
bitfld.long 0x00 30. "U,EL0 filtering bit" "0,1"
bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "0,1"
newline
bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "0,1"
bitfld.long 0x00 27. "NSH,Non-secure Hyp modes filtering bit" "0,1"
bitfld.long 0x00 26. "M,Secure EL3 filtering bit" "0,1"
newline
hexmask.long 0x00 0.--25. 1. "RES0_PMCCFILTR_EL0_25_0,Reserved RES0"
group.long 0xC00++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMCNTENSET_EL0,Performance Monitors Count Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 enable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter enable bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xC20++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMCNTENCLR_EL0,Performance Monitors Count Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 disable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter disable bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xC40++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMINTENSET_EL1,Performance Monitors Interrupt Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow interrupt request enable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow interrupt request enable bit for PMEVCNTR<x>_EL0.N is the value in PMCR_EL0.N"
group.long 0xC60++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMINTENCLR_EL1,Performance Monitors Interrupt Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow interrupt request disable bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow interrupt request disable bit for PMEVCNTR<x>_EL0.N is the value in PMCR_EL0.N"
group.long 0xC80++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMOVSCLR_EL0,Performance Monitors Overflow Flag Status Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow clear bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xCA0++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMSWINC_EL0,Performance Monitors Software Increment Register"
hexmask.long 0x00 6.--31. 1. "RESERVED,Reserved RES0"
bitfld.long 0x00 0.--5. "P_X,Event counter software increment bit for PMEVCNTR<x>" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xCC0++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMOVSSET_EL0,Performance Monitors Overflow Flag Status Set Register"
bitfld.long 0x00 31. "C,PMCCNTR_EL0 overflow bit" "0,1"
hexmask.long 0x00 0.--30. 1. "P_X,Event counter overflow set bit for PMEVCNTR<x>.N is the value in PMCR_EL0.N"
group.long 0xE00++0x07
line.long 0x00 "APBADDR_PMU_CPU3_PMCFGR,Performance Monitors Configuration Register"
hexmask.long.word 0x00 20.--31. 1. "RES0_PMCFGR_31_20,Reserved RES0"
bitfld.long 0x00 19. "UEN,User-mode Enable Register supported" "0,1"
bitfld.long 0x00 18. "WT,This feature is not supported so this bit is RES0" "0,1"
newline
bitfld.long 0x00 17. "NA,This feature is not supported so this bit is RES0" "0,1"
bitfld.long 0x00 16. "EX,Export supported" "0,1"
bitfld.long 0x00 15. "CCD,Cycle counter has prescale" "0,1"
newline
bitfld.long 0x00 14. "CC,Dedicated cycle counter [counter 31] supported" "0,1"
bitfld.long 0x00 8.--13. "SIZE,Size of counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 0.--7. 1. "N,Number of counters implemented in addition to the cycle counter PMCCNTR_EL0"
line.long 0x04 "APBADDR_PMU_CPU3_PMCR_EL0,Performance Monitors Control Register"
hexmask.long.tbyte 0x04 11.--31. 1. "RES0_PMCR_EL0_31_11,Reserved RAZ/WI"
bitfld.long 0x04 7.--10. "RES0_PMCR_EL0_10_7,Reserved RES0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 6. "LC,Long cycle counter enable" "0,1"
newline
bitfld.long 0x04 5. "DP,Disable cycle counter when event counting is prohibited" "0,1"
bitfld.long 0x04 4. "X,Enable export of events in an IMPLEMENTATION DEFINED event stream" "0,1"
bitfld.long 0x04 3. "D,Clock divider" "0,1"
newline
bitfld.long 0x04 2. "C,Cycle counter reset" "0,1"
bitfld.long 0x04 1. "P,Event counter reset" "0,1"
bitfld.long 0x04 0. "E,Enable" "0,1"
group.long 0xE20++0x07
line.long 0x00 "APBADDR_PMU_CPU3_PMCEID0_EL0,Performance Monitors Common Event Identification Register 0"
line.long 0x04 "APBADDR_PMU_CPU3_PMCEID1_EL0,Performance Monitors Common Event Identification Register 1"
hexmask.long 0x04 1.--31. 1. "RES0_PMCEID1_EL0_31_1,Reserved RES0"
bitfld.long 0x04 0. "CE_32,Common architectural and microarchitectural feature events that can be counted by the PMU event counters.For the bit described in the following table the event is implemented if the bit is set to 1 or not implemented if the bit is set to.." "0,1"
group.long 0xF00++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMITCTRL,Performance Monitors Integration mode Control Register"
hexmask.long 0x00 1.--31. 1. "RES0_PMITCTRL_31_1,Reserved RES0"
bitfld.long 0x00 0. "IME,Integration mode enable" "0,1"
group.long 0xFA8++0x17
line.long 0x00 "APBADDR_PMU_CPU3_PMDEVAFF0,Performance Monitors Device Affinity Register 0"
line.long 0x04 "APBADDR_PMU_CPU3_PMDEVAFF1,Performance Monitors Device Affinity Register 1"
line.long 0x08 "APBADDR_PMU_CPU3_PMLAR,Performance Monitors Lock Access Register"
line.long 0x0C "APBADDR_PMU_CPU3_PMLSR,Performance Monitors Lock Status Register"
hexmask.long 0x0C 3.--31. 1. "RES0_PMLSR_31_3,Reserved RES0"
bitfld.long 0x0C 2. "NTT,Not thirty-two bit access required" "0,1"
bitfld.long 0x0C 1. "SLK,Software lock status for this component" "0,1"
newline
bitfld.long 0x0C 0. "SLI,Software lock implemented" "0,1"
line.long 0x10 "APBADDR_PMU_CPU3_PMAUTHSTATUS,Performance Monitors Authentication Status Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_PMAUTHSTATUS_31_8,Reserved RES0"
bitfld.long 0x10 6.--7. "SNID,Holds the same value as DBGAUTHSTATUS_EL1.SNID" "0,1,2,3"
bitfld.long 0x10 4.--5. "RES0_PMAUTHSTATUS_5_4,Reserved RES0" "0,1,2,3"
newline
bitfld.long 0x10 2.--3. "NSNID,Holds the same value as DBGAUTHSTATUS_EL1.NSNID" "0,1,2,3"
bitfld.long 0x10 0.--1. "RES0_PMAUTHSTATUS_1_0,Reserved RES0" "0,1,2,3"
line.long 0x14 "APBADDR_PMU_CPU3_PMDEVARCH,Performance Monitors Device Architecture Register"
hexmask.long.word 0x14 21.--31. 1. "ARCHITECT,Defines the architecture of the component"
bitfld.long 0x14 20. "PRESENT,When set to 1 indicates that the DEVARCH is present.This field is 1 in v8-A" "0,1"
bitfld.long 0x14 16.--19. "REVISION,Defines the architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x14 0.--15. 1. "ARCHID,Defines this part to be a v8-A debug component"
group.long 0xFCC++0x07
line.long 0x00 "APBADDR_PMU_CPU3_PMDEVTYPE,Performance Monitors Device Type Register"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_PMDEVTYPE_31_8,Reserved RES0"
bitfld.long 0x00 4.--7. "SUB,Subtype" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "MAJOR,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "APBADDR_PMU_CPU3_PMPIDR4,Performance Monitors Peripheral Identification Register 4"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_PMPIDR4_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "SIZE,Size of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "DES_2,Designer JEP106 continuation code least significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
group.long ($2+0xFD4)++0x03
line.long 0x00 "APBADDR_PMU_CPU3_PMPIDR$1,Performance Monitors Peripheral Identification Register 5"
repeat.end
group.long 0xFE0++0x1F
line.long 0x00 "APBADDR_PMU_CPU3_PMPIDR0,Performance Monitors Peripheral Identification Register 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES0_PMPIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Part number least significant byte"
line.long 0x04 "APBADDR_PMU_CPU3_PMPIDR1,Performance Monitors Peripheral Identification Register 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RES0_PMPIDR1_31_8,Reserved RES0"
bitfld.long 0x04 4.--7. "DES_0,Designer least significant nibble of JEP106 ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "PART_1,Part number most significant nibble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "APBADDR_PMU_CPU3_PMPIDR2,Performance Monitors Peripheral Identification Register 2"
hexmask.long.tbyte 0x08 8.--31. 1. "RES0_PMPIDR2_31_8,Reserved RES0"
bitfld.long 0x08 4.--7. "REVISION,Part major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3. "JEDEC,RAO" "0,1"
newline
bitfld.long 0x08 0.--2. "DES_1,Designer most significant bits of JEP106 ID code" "0,1,2,3,4,5,6,7"
line.long 0x0C "APBADDR_PMU_CPU3_PMPIDR3,Performance Monitors Peripheral Identification Register 3"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES0_PMPIDR3_31_8,Reserved RES0"
bitfld.long 0x0C 4.--7. "REVAND,Part minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "CMOD,Customer modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "APBADDR_PMU_CPU3_PMCIDR0,Performance Monitors Component Identification Register 0"
hexmask.long.tbyte 0x10 8.--31. 1. "RES0_PMCIDR0_31_8,Reserved RES0"
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Preamble"
line.long 0x14 "APBADDR_PMU_CPU3_PMCIDR1,Performance Monitors Component Identification Register 1"
hexmask.long.tbyte 0x14 8.--31. 1. "RES0_PMCIDR1_31_8,Reserved RES0"
bitfld.long 0x14 4.--7. "CLASS,Component class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--3. "PRMBL_1,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "APBADDR_PMU_CPU3_PMCIDR2,Performance Monitors Component Identification Register 2"
hexmask.long.tbyte 0x18 8.--31. 1. "RES0_PMCIDR2_31_8,Reserved RES0"
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Preamble"
line.long 0x1C "APBADDR_PMU_CPU3_PMCIDR3,Performance Monitors Component Identification Register 3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RES0_PMCIDR3_31_8,Reserved RES0"
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Preamble"
tree.end
tree "A53SS0_SS_ECC_AGGR"
base ad:0x718000
rgroup.long 0x00++0x03
line.long 0x00 "ECC_AGGR_COREPAC_REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "ECC_AGGR_COREPAC_REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
newline
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ECC_AGGR_COREPAC_REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ECC_AGGR_COREPAC_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "ECC_AGGR_COREPAC_REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_COREPAC_REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 23. "A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend" "0,1"
bitfld.long 0x04 22. "A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 21. "A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend" "0,1"
bitfld.long 0x04 20. "A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 19. "A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend" "0,1"
bitfld.long 0x04 18. "A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 17. "A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend" "0,1"
bitfld.long 0x04 16. "A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 15. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend" "0,1"
bitfld.long 0x04 14. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 13. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend" "0,1"
bitfld.long 0x04 12. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x04 11. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend" "0,1"
bitfld.long 0x04 10. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 9. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend" "0,1"
bitfld.long 0x04 8. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 7. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend" "0,1"
bitfld.long 0x04 6. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 5. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend" "0,1"
bitfld.long 0x04 4. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 3. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend" "0,1"
bitfld.long 0x04 2. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 1. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend" "0,1"
bitfld.long 0x04 0. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ECC_AGGR_COREPAC_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 23. "A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend" "0,1"
bitfld.long 0x00 22. "A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 21. "A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend" "0,1"
bitfld.long 0x00 20. "A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 19. "A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend" "0,1"
bitfld.long 0x00 18. "A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 17. "A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend" "0,1"
bitfld.long 0x00 16. "A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 15. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend" "0,1"
bitfld.long 0x00 14. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 13. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend" "0,1"
bitfld.long 0x00 12. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 11. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend" "0,1"
bitfld.long 0x00 10. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 9. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend" "0,1"
bitfld.long 0x00 8. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 7. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend" "0,1"
bitfld.long 0x00 6. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 5. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend" "0,1"
bitfld.long 0x00 4. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 3. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend" "0,1"
bitfld.long 0x00 2. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 1. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend" "0,1"
bitfld.long 0x00 0. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ECC_AGGR_COREPAC_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 23. "A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend" "0,1"
bitfld.long 0x00 22. "A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 21. "A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend" "0,1"
bitfld.long 0x00 20. "A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 19. "A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend" "0,1"
bitfld.long 0x00 18. "A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 17. "A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend" "0,1"
bitfld.long 0x00 16. "A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 15. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend" "0,1"
bitfld.long 0x00 14. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 13. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend" "0,1"
bitfld.long 0x00 12. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 11. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend" "0,1"
bitfld.long 0x00 10. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 9. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend" "0,1"
bitfld.long 0x00 8. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 7. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend" "0,1"
bitfld.long 0x00 6. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 5. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend" "0,1"
bitfld.long 0x00 4. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 3. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend" "0,1"
bitfld.long 0x00 2. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 1. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend" "0,1"
bitfld.long 0x00 0. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ECC_AGGR_COREPAC_REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_COREPAC_REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 23. "A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend" "0,1"
bitfld.long 0x04 22. "A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 21. "A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend" "0,1"
bitfld.long 0x04 20. "A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 19. "A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend" "0,1"
bitfld.long 0x04 18. "A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 17. "A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend" "0,1"
bitfld.long 0x04 16. "A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 15. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend" "0,1"
bitfld.long 0x04 14. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 13. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend" "0,1"
bitfld.long 0x04 12. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 11. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend" "0,1"
bitfld.long 0x04 10. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 9. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend" "0,1"
bitfld.long 0x04 8. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 7. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend" "0,1"
bitfld.long 0x04 6. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 5. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend" "0,1"
bitfld.long 0x04 4. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 3. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend" "0,1"
bitfld.long 0x04 2. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend" "0,1"
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bitfld.long 0x04 1. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend" "0,1"
bitfld.long 0x04 0. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_PEND,Interrupt Pending Status for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ECC_AGGR_COREPAC_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 23. "A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend" "0,1"
bitfld.long 0x00 22. "A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 21. "A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend" "0,1"
bitfld.long 0x00 20. "A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 19. "A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend" "0,1"
bitfld.long 0x00 18. "A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 17. "A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend" "0,1"
bitfld.long 0x00 16. "A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 15. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend" "0,1"
bitfld.long 0x00 14. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 13. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend" "0,1"
bitfld.long 0x00 12. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend" "0,1"
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bitfld.long 0x00 11. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend" "0,1"
bitfld.long 0x00 10. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 9. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend" "0,1"
bitfld.long 0x00 8. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 7. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend" "0,1"
bitfld.long 0x00 6. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 5. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend" "0,1"
bitfld.long 0x00 4. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 3. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend" "0,1"
bitfld.long 0x00 2. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 1. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend" "0,1"
bitfld.long 0x00 0. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_SET,Interrupt Enable Set Register for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ECC_AGGR_COREPAC_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 23. "A53_DUAL_U_L2_DATARAM_SPRAM_7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_7_ecc_svbus_pend" "0,1"
bitfld.long 0x00 22. "A53_DUAL_U_L2_DATARAM_SPRAM_6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_6_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 21. "A53_DUAL_U_L2_DATARAM_SPRAM_5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_5_ecc_svbus_pend" "0,1"
bitfld.long 0x00 20. "A53_DUAL_U_L2_DATARAM_SPRAM_4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_4_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 19. "A53_DUAL_U_L2_DATARAM_SPRAM_3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_3_ecc_svbus_pend" "0,1"
bitfld.long 0x00 18. "A53_DUAL_U_L2_DATARAM_SPRAM_2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 17. "A53_DUAL_U_L2_DATARAM_SPRAM_1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_1_ecc_svbus_pend" "0,1"
bitfld.long 0x00 16. "A53_DUAL_U_L2_DATARAM_SPRAM_0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_dataram_spram_0_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 15. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY15_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way15_ecc_svbus_pend" "0,1"
bitfld.long 0x00 14. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY14_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way14_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 13. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY13_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way13_ecc_svbus_pend" "0,1"
bitfld.long 0x00 12. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY12_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way12_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 11. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY11_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way11_ecc_svbus_pend" "0,1"
bitfld.long 0x00 10. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY10_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way10_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 9. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY9_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way9_ecc_svbus_pend" "0,1"
bitfld.long 0x00 8. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY8_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way8_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 7. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY7_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way7_ecc_svbus_pend" "0,1"
bitfld.long 0x00 6. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY6_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way6_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 5. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY5_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way5_ecc_svbus_pend" "0,1"
bitfld.long 0x00 4. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY4_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way4_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 3. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY3_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way3_ecc_svbus_pend" "0,1"
bitfld.long 0x00 2. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY2_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way2_ecc_svbus_pend" "0,1"
newline
bitfld.long 0x00 1. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY1_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way1_ecc_svbus_pend" "0,1"
bitfld.long 0x00 0. "A53_DUAL_U_L2_TAGRAM_SPRAM_WAY0_ECC_SVBUS_ENABLE_CLR,Interrupt Enable Clear Register for a53_dual_u_l2_tagram_spram_way0_ecc_svbus_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ECC_AGGR_COREPAC_REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ECC_AGGR_COREPAC_REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ECC_AGGR_COREPAC_REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ECC_AGGR_COREPAC_REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "A53SS0_SS_ROM"
base ad:0x730000000
hgroup.long 0x00++0x3F
hide.long 0x00 "APBADDR_ROMV8_ROMENTRY0,ROM Table Entry Register 0 (CPU 0 Debug Component)"
hide.long 0x04 "APBADDR_ROMV8_ROMENTRY1,ROM Table Entry Register 1 (CPU 0 CTI Component)"
hide.long 0x08 "APBADDR_ROMV8_ROMENTRY2,ROM Table Entry Register 2 (CPU 0 PMU Component)"
hide.long 0x0C "APBADDR_ROMV8_ROMENTRY3,ROM Table Entry Register 3 (CPU 0 ETM Component)"
hide.long 0x10 "APBADDR_ROMV8_ROMENTRY4,ROM Table Entry Register 4 (CPU 1 Debug Component)"
hide.long 0x14 "APBADDR_ROMV8_ROMENTRY5,ROM Table Entry Register 5 (CPU 1 CTI Component)"
hide.long 0x18 "APBADDR_ROMV8_ROMENTRY6,ROM Table Entry Register 6 (CPU 1 PMU Component)"
hide.long 0x1C "APBADDR_ROMV8_ROMENTRY7,ROM Table Entry Register 7 (CPU 1 ETM Component)"
hide.long 0x20 "APBADDR_ROMV8_ROMENTRY8,ROM Table Entry Register 8 (CPU 2 Debug Component)"
hide.long 0x24 "APBADDR_ROMV8_ROMENTRY9,ROM Table Entry Register 9 (CPU 2 CTI Component)"
hide.long 0x28 "APBADDR_ROMV8_ROMENTRY10,ROM Table Entry Register 10 (CPU 2 PMU Component)"
hide.long 0x2C "APBADDR_ROMV8_ROMENTRY11,ROM Table Entry Register 11 (CPU 2 ETM Component)"
hide.long 0x30 "APBADDR_ROMV8_ROMENTRY12,ROM Table Entry Register 12 (CPU 3 Debug Component)"
hide.long 0x34 "APBADDR_ROMV8_ROMENTRY13,ROM Table Entry Register 13 (CPU 3 CTI Component)"
hide.long 0x38 "APBADDR_ROMV8_ROMENTRY14,ROM Table Entry Register 14 (CPU 3 PMU Component)"
hide.long 0x3C "APBADDR_ROMV8_ROMENTRY15,ROM Table Entry Register 15 (CPU 3 ETM Component)"
hgroup.long 0xFD0++0x2F
hide.long 0x00 "APBADDR_ROMV8_ROM_PERIPHID4_VAL,ROM Peripheral ID 4"
hide.long 0x04 "APBADDR_ROMV8_ROM_PERIPHID5_VAL,ROM Peripheral ID 5"
hide.long 0x08 "APBADDR_ROMV8_ROM_PERIPHID6_VAL,ROM Peripheral ID 6"
hide.long 0x0C "APBADDR_ROMV8_ROM_PERIPHID7_VAL,ROM Peripheral ID 7"
hide.long 0x10 "APBADDR_ROMV8_ROM_PERIPHID0_VAL,ROM Peripheral ID 0"
hide.long 0x14 "APBADDR_ROMV8_ROM_PERIPHID1_VAL,ROM Peripheral ID 1"
hide.long 0x18 "APBADDR_ROMV8_ROM_PERIPHID2_VAL,ROM Peripheral ID 2"
hide.long 0x1C "APBADDR_ROMV8_ROM_PERIPHID3_VAL,ROM Peripheral ID 3"
hide.long 0x20 "APBADDR_ROMV8_ROM_COMPONID0_VAL,ROM Component ID 0"
hide.long 0x24 "APBADDR_ROMV8_ROM_COMPONID1_VAL,ROM Component ID 1"
hide.long 0x28 "APBADDR_ROMV8_ROM_COMPONID2_VAL,ROM Component ID 2"
hide.long 0x2C "APBADDR_ROMV8_ROM_COMPONID3_VAL,ROM Component ID 3"
tree.end
tree "CBASS0_ERR"
base ad:0x3A000000
rgroup.long 0x00++0x07
line.long 0x00 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "CBASS0_FW"
base ad:0x45000000
group.long 0x400++0xFF
line.long 0x00 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Isam62_ddr_wrap_main_0.ddrss region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_ddr_wrap_main_0.ddrss region 0 firewall"
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_ddr_wrap_main_0.ddrss region 0 firewall"
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 0 firewall"
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 0 firewall"
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Isam62_ddr_wrap_main_0.ddrss region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_ddr_wrap_main_0.ddrss region 1 firewall"
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_ddr_wrap_main_0.ddrss region 1 firewall"
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 1 firewall"
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 1 firewall"
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Isam62_ddr_wrap_main_0.ddrss region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_ddr_wrap_main_0.ddrss region 2 firewall"
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_ddr_wrap_main_0.ddrss region 2 firewall"
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 2 firewall"
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 2 firewall"
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Isam62_ddr_wrap_main_0.ddrss region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_ddr_wrap_main_0.ddrss region 3 firewall"
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_ddr_wrap_main_0.ddrss region 3 firewall"
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 3 firewall"
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 3 firewall"
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x80 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Isam62_ddr_wrap_main_0.ddrss region 4 firewall"
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region" "0,1"
bitfld.long 0x80 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 4 firewall"
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x88 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 4 firewall"
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x8C "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 4 firewall"
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x90 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_ddr_wrap_main_0.ddrss region 4 firewall"
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x94 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_ddr_wrap_main_0.ddrss region 4 firewall"
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x98 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 4 firewall"
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x9C "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 4 firewall"
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xA0 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Isam62_ddr_wrap_main_0.ddrss region 5 firewall"
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xA0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 5 firewall"
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xA8 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 5 firewall"
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xAC "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 5 firewall"
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xB0 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_ddr_wrap_main_0.ddrss region 5 firewall"
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xB4 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_ddr_wrap_main_0.ddrss region 5 firewall"
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xB8 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 5 firewall"
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xBC "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 5 firewall"
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xC0 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Isam62_ddr_wrap_main_0.ddrss region 6 firewall"
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xC0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 6 firewall"
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xC8 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 6 firewall"
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xCC "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 6 firewall"
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xD0 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_ddr_wrap_main_0.ddrss region 6 firewall"
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xD4 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_ddr_wrap_main_0.ddrss region 6 firewall"
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xD8 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 6 firewall"
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xDC "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 6 firewall"
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xE0 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Isam62_ddr_wrap_main_0.ddrss region 7 firewall"
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xE0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 7 firewall"
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xE8 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 7 firewall"
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xEC "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Isam62_ddr_wrap_main_0.ddrss region 7 firewall"
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xF0 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_ddr_wrap_main_0.ddrss region 7 firewall"
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xF4 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_ddr_wrap_main_0.ddrss region 7 firewall"
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xF8 "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 7 firewall"
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xFC "FW_REGS_Isam62_ddr_wrap_main_0_ddrss_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_ddr_wrap_main_0.ddrss region 7 firewall"
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
group.long 0x800++0xFF
line.long 0x00 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 0 firewall"
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 0.."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 0.."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 0.."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 1 firewall"
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 1.."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 1.."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 1.."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 2 firewall"
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 2.."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 2.."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 2.."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 3 firewall"
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 3.."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 3.."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 3.."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x80 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 4 firewall"
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region" "0,1"
bitfld.long 0x80 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 4 firewall"
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x88 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 4 firewall"
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x8C "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 4 firewall"
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x90 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 4 firewall"
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x94 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 4.."
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x98 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 4.."
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x9C "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 4.."
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xA0 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 5 firewall"
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xA0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 5 firewall"
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xA8 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 5 firewall"
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xAC "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 5 firewall"
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xB0 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 5 firewall"
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xB4 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 5.."
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xB8 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 5.."
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xBC "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 5.."
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xC0 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 6 firewall"
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xC0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 6 firewall"
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xC8 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 6 firewall"
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xCC "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 6 firewall"
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xD0 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 6 firewall"
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xD4 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 6.."
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xD8 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 6.."
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xDC "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 6.."
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xE0 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 7 firewall"
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xE0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 7 firewall"
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xE8 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 7 firewall"
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xEC "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 7 firewall"
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xF0 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 7 firewall"
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xF4 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 7.."
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xF8 "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 7.."
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xFC "FW_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_acp_w_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_acp_w region 7.."
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
group.long 0xC00++0x7F
line.long 0x00 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall"
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall"
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall"
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 0 firewall"
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall"
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall"
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall"
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 1 firewall"
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall"
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall"
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall"
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 2 firewall"
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall"
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall"
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall"
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_Idebugss_k3_wrap_cv0_main_0_vbusp_cfg_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Idebugss_k3_wrap_cv0_main_0.vbusp_cfg region 3 firewall"
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
group.long 0x2000++0xFF
line.long 0x00 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 0.."
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 0.."
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 0.."
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave.."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 1.."
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 1.."
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 1.."
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave.."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 2.."
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 2.."
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 2.."
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave.."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 3.."
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 3.."
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 3.."
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave.."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x80 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 4 firewall"
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region" "0,1"
bitfld.long 0x80 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 4.."
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x88 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 4.."
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x8C "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 4.."
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x90 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave.."
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x94 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x98 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x9C "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xA0 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 5 firewall"
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xA0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 5.."
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xA8 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 5.."
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xAC "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 5.."
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xB0 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave.."
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xB4 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xB8 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xBC "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xC0 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 6 firewall"
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xC0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 6.."
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xC8 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 6.."
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xCC "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 6.."
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xD0 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave.."
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xD4 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xD8 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xDC "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xE0 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 7 firewall"
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xE0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 7.."
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xE8 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 7.."
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xEC "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0.slv region 7.."
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xF0 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave.."
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xF4 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xF8 "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xFC "FW_REGS_export_am62_main_data_cbass_to_am62_main_misc_peri_cbass_data_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
group.long 0x2400++0x2FF
line.long 0x00 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall"
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall"
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall"
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 0 firewall"
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall"
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall"
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall"
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 1 firewall"
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall"
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall"
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall"
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 2 firewall"
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall"
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall"
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall"
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 3 firewall"
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x80 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall"
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region" "0,1"
bitfld.long 0x80 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall"
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x88 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall"
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x8C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall"
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x90 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall"
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x94 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall"
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x98 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall"
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x9C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 4 firewall"
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xA0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall"
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xA0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall"
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xA8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall"
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xAC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall"
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xB0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall"
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xB4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall"
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xB8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall"
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xBC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 5 firewall"
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xC0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall"
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xC0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall"
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xC8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall"
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xCC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall"
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xD0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall"
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xD4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall"
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xD8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall"
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xDC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 6 firewall"
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xE0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall"
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xE0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall"
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xE8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall"
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xEC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall"
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xF0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall"
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xF4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall"
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xF8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall"
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xFC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 7 firewall"
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x100 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_control,The FW Region 8 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall"
bitfld.long 0x100 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x100 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x100 4. "LOCK,Lock region" "0,1"
bitfld.long 0x100 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x104 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_permission_0,The FW Region 8 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall"
hexmask.long.byte 0x104 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x104 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x104 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x104 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x104 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x104 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x104 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x104 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x104 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x104 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x104 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x104 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x104 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x104 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x104 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x104 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x104 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x108 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_permission_1,The FW Region 8 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall"
hexmask.long.byte 0x108 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x108 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x108 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x108 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x108 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x108 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x108 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x108 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x108 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x108 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x108 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x108 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x108 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x108 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x108 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x108 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x108 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_permission_2,The FW Region 8 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall"
hexmask.long.byte 0x10C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x10C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x10C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x10C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x10C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x10C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x10C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x10C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x10C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x10C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x10C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x10C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x10C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x10C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x10C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x10C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x10C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x110 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_start_address_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall"
hexmask.long.tbyte 0x110 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x110 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x114 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_start_address_h,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall"
hexmask.long.word 0x114 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x118 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_end_address_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall"
hexmask.long.tbyte 0x118 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x118 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x11C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_8_end_address_h,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 8 firewall"
hexmask.long.word 0x11C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x120 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_control,The FW Region 9 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall"
bitfld.long 0x120 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x120 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x120 4. "LOCK,Lock region" "0,1"
bitfld.long 0x120 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x124 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_permission_0,The FW Region 9 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall"
hexmask.long.byte 0x124 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x124 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x124 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x124 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x124 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x124 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x124 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x124 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x124 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x124 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x124 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x124 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x124 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x124 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x124 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x124 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x124 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x128 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_permission_1,The FW Region 9 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall"
hexmask.long.byte 0x128 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x128 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x128 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x128 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x128 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x128 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x128 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x128 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x128 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x128 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x128 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x128 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x128 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x128 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x128 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x128 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x128 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x12C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_permission_2,The FW Region 9 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall"
hexmask.long.byte 0x12C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x12C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x12C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x12C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x12C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x12C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x12C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x12C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x12C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x12C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x12C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x12C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x12C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x12C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x12C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x12C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x12C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x130 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_start_address_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall"
hexmask.long.tbyte 0x130 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x130 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x134 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_start_address_h,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall"
hexmask.long.word 0x134 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x138 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_end_address_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall"
hexmask.long.tbyte 0x138 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x138 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x13C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_9_end_address_h,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 9 firewall"
hexmask.long.word 0x13C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x140 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_control,The FW Region 10 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall"
bitfld.long 0x140 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x140 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x140 4. "LOCK,Lock region" "0,1"
bitfld.long 0x140 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x144 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_permission_0,The FW Region 10 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall"
hexmask.long.byte 0x144 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x144 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x144 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x144 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x144 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x144 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x144 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x144 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x144 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x144 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x144 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x144 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x144 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x144 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x144 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x144 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x144 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x148 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_permission_1,The FW Region 10 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall"
hexmask.long.byte 0x148 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x148 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x148 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x148 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x148 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x148 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x148 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x148 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x148 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x148 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x148 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x148 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x148 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x148 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x148 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x148 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x148 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x14C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_permission_2,The FW Region 10 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall"
hexmask.long.byte 0x14C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x14C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x14C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x14C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x14C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x14C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x14C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x14C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x14C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x14C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x14C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x14C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x14C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x14C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x14C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x14C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x14C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x150 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_start_address_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall"
hexmask.long.tbyte 0x150 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x150 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x154 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_start_address_h,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall"
hexmask.long.word 0x154 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x158 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_end_address_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall"
hexmask.long.tbyte 0x158 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x158 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x15C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_10_end_address_h,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 10 firewall"
hexmask.long.word 0x15C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x160 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_control,The FW Region 11 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall"
bitfld.long 0x160 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x160 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x160 4. "LOCK,Lock region" "0,1"
bitfld.long 0x160 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_permission_0,The FW Region 11 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall"
hexmask.long.byte 0x164 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x164 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x164 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x164 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x164 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x164 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x164 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x164 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x164 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x164 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x164 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x164 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x164 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x164 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x164 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x164 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x164 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x168 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_permission_1,The FW Region 11 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall"
hexmask.long.byte 0x168 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x168 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x168 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x168 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x168 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x168 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x168 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x168 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x168 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x168 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x168 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x168 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x168 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x168 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x168 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x168 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x168 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x16C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_permission_2,The FW Region 11 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall"
hexmask.long.byte 0x16C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x16C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x16C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x16C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x16C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x16C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x16C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x16C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x16C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x16C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x16C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x16C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x16C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x16C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x16C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x16C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x16C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x170 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_start_address_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall"
hexmask.long.tbyte 0x170 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x170 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x174 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_start_address_h,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall"
hexmask.long.word 0x174 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x178 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_end_address_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall"
hexmask.long.tbyte 0x178 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x178 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x17C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_11_end_address_h,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 11 firewall"
hexmask.long.word 0x17C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x180 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_control,The FW Region 12 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall"
bitfld.long 0x180 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x180 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x180 4. "LOCK,Lock region" "0,1"
bitfld.long 0x180 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_permission_0,The FW Region 12 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall"
hexmask.long.byte 0x184 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x184 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x184 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x184 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x184 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x184 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x184 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x184 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x184 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x184 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x184 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x184 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x184 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x184 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x184 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x184 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x184 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x188 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_permission_1,The FW Region 12 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall"
hexmask.long.byte 0x188 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x188 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x188 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x188 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x188 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x188 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x188 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x188 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x188 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x188 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x188 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x188 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x188 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x188 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x188 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x188 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x188 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x18C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_permission_2,The FW Region 12 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall"
hexmask.long.byte 0x18C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x18C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x18C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x18C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x18C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x18C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x18C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x18C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x18C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x18C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x18C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x18C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x18C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x18C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x18C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x18C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x18C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x190 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_start_address_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall"
hexmask.long.tbyte 0x190 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x190 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x194 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_start_address_h,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall"
hexmask.long.word 0x194 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x198 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_end_address_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall"
hexmask.long.tbyte 0x198 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x198 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x19C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_12_end_address_h,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 12 firewall"
hexmask.long.word 0x19C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x1A0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_control,The FW Region 13 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall"
bitfld.long 0x1A0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x1A0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x1A0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x1A0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_permission_0,The FW Region 13 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall"
hexmask.long.byte 0x1A4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1A4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1A4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1A4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1A4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1A8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_permission_1,The FW Region 13 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall"
hexmask.long.byte 0x1A8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1A8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1A8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1A8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1A8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1AC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_permission_2,The FW Region 13 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall"
hexmask.long.byte 0x1AC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1AC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1AC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1AC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1AC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1AC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1B0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_start_address_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall"
hexmask.long.tbyte 0x1B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x1B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x1B4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_start_address_h,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall"
hexmask.long.word 0x1B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x1B8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_end_address_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall"
hexmask.long.tbyte 0x1B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x1B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1BC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_13_end_address_h,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 13 firewall"
hexmask.long.word 0x1BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x1C0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_control,The FW Region 14 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall"
bitfld.long 0x1C0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x1C0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x1C0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x1C0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_permission_0,The FW Region 14 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall"
hexmask.long.byte 0x1C4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1C4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1C4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1C4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1C4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1C8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_permission_1,The FW Region 14 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall"
hexmask.long.byte 0x1C8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1C8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1C8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1C8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1C8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1CC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_permission_2,The FW Region 14 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall"
hexmask.long.byte 0x1CC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1CC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1CC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1CC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1CC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1CC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1D0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_start_address_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall"
hexmask.long.tbyte 0x1D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x1D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x1D4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_start_address_h,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall"
hexmask.long.word 0x1D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x1D8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_end_address_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall"
hexmask.long.tbyte 0x1D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x1D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1DC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_14_end_address_h,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 14 firewall"
hexmask.long.word 0x1DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x1E0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_control,The FW Region 15 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall"
bitfld.long 0x1E0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x1E0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x1E0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x1E0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_permission_0,The FW Region 15 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall"
hexmask.long.byte 0x1E4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1E4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1E4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1E4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1E4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1E8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_permission_1,The FW Region 15 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall"
hexmask.long.byte 0x1E8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1E8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1E8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1E8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1E8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1EC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_permission_2,The FW Region 15 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall"
hexmask.long.byte 0x1EC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1EC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1EC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1EC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1EC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1EC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1F0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_start_address_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall"
hexmask.long.tbyte 0x1F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x1F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x1F4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_start_address_h,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall"
hexmask.long.word 0x1F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x1F8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_end_address_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall"
hexmask.long.tbyte 0x1F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x1F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1FC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_15_end_address_h,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 15 firewall"
hexmask.long.word 0x1FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x200 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_control,The FW Region 16 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall"
bitfld.long 0x200 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x200 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x200 4. "LOCK,Lock region" "0,1"
bitfld.long 0x200 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x204 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_permission_0,The FW Region 16 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall"
hexmask.long.byte 0x204 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x204 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x204 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x204 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x204 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x204 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x204 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x204 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x204 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x204 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x204 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x204 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x204 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x204 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x204 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x204 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x204 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x208 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_permission_1,The FW Region 16 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall"
hexmask.long.byte 0x208 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x208 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x208 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x208 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x208 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x208 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x208 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x208 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x208 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x208 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x208 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x208 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x208 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x208 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x208 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x208 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x208 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x20C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_permission_2,The FW Region 16 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall"
hexmask.long.byte 0x20C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x20C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x20C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x20C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x20C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x20C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x20C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x20C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x20C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x20C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x20C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x20C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x20C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x20C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x20C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x20C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x20C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x210 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_start_address_l,The FW Region 16 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall"
hexmask.long.tbyte 0x210 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x210 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x214 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_start_address_h,The FW Region 16 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall"
hexmask.long.word 0x214 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x218 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_end_address_l,The FW Region 16 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall"
hexmask.long.tbyte 0x218 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x218 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x21C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_16_end_address_h,The FW Region 16 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 16 firewall"
hexmask.long.word 0x21C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x220 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_control,The FW Region 17 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall"
bitfld.long 0x220 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x220 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x220 4. "LOCK,Lock region" "0,1"
bitfld.long 0x220 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x224 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_permission_0,The FW Region 17 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall"
hexmask.long.byte 0x224 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x224 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x224 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x224 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x224 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x224 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x224 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x224 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x224 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x224 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x224 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x224 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x224 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x224 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x224 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x224 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x224 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x228 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_permission_1,The FW Region 17 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall"
hexmask.long.byte 0x228 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x228 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x228 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x228 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x228 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x228 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x228 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x228 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x228 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x228 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x228 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x228 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x228 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x228 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x228 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x228 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x228 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x22C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_permission_2,The FW Region 17 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall"
hexmask.long.byte 0x22C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x22C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x22C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x22C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x22C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x22C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x22C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x22C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x22C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x22C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x22C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x22C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x22C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x22C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x22C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x22C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x22C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x230 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_start_address_l,The FW Region 17 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall"
hexmask.long.tbyte 0x230 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x230 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x234 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_start_address_h,The FW Region 17 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall"
hexmask.long.word 0x234 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x238 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_end_address_l,The FW Region 17 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall"
hexmask.long.tbyte 0x238 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x238 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x23C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_17_end_address_h,The FW Region 17 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 17 firewall"
hexmask.long.word 0x23C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x240 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_control,The FW Region 18 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall"
bitfld.long 0x240 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x240 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x240 4. "LOCK,Lock region" "0,1"
bitfld.long 0x240 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x244 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_permission_0,The FW Region 18 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall"
hexmask.long.byte 0x244 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x244 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x244 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x244 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x244 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x244 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x244 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x244 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x244 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x244 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x244 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x244 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x244 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x244 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x244 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x244 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x244 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x248 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_permission_1,The FW Region 18 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall"
hexmask.long.byte 0x248 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x248 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x248 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x248 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x248 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x248 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x248 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x248 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x248 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x248 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x248 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x248 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x248 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x248 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x248 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x248 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x248 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x24C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_permission_2,The FW Region 18 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall"
hexmask.long.byte 0x24C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x24C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x24C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x250 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_start_address_l,The FW Region 18 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall"
hexmask.long.tbyte 0x250 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x250 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x254 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_start_address_h,The FW Region 18 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall"
hexmask.long.word 0x254 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x258 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_end_address_l,The FW Region 18 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall"
hexmask.long.tbyte 0x258 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x258 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x25C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_18_end_address_h,The FW Region 18 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 18 firewall"
hexmask.long.word 0x25C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x260 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_control,The FW Region 19 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall"
bitfld.long 0x260 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x260 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x260 4. "LOCK,Lock region" "0,1"
bitfld.long 0x260 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x264 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_permission_0,The FW Region 19 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall"
hexmask.long.byte 0x264 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x264 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x264 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x264 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x264 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x264 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x264 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x264 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x264 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x264 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x264 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x264 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x264 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x264 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x264 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x264 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x264 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x268 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_permission_1,The FW Region 19 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall"
hexmask.long.byte 0x268 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x268 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x268 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x268 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x268 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x268 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x268 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x268 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x268 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x268 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x268 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x268 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x268 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x268 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x268 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x268 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x268 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x26C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_permission_2,The FW Region 19 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall"
hexmask.long.byte 0x26C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x26C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x26C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x26C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x26C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x26C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x26C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x26C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x26C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x26C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x26C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x26C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x26C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x26C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x26C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x26C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x26C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x270 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_start_address_l,The FW Region 19 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall"
hexmask.long.tbyte 0x270 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x270 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x274 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_start_address_h,The FW Region 19 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall"
hexmask.long.word 0x274 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x278 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_end_address_l,The FW Region 19 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall"
hexmask.long.tbyte 0x278 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x278 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x27C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_19_end_address_h,The FW Region 19 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 19 firewall"
hexmask.long.word 0x27C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x280 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_control,The FW Region 20 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall"
bitfld.long 0x280 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x280 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x280 4. "LOCK,Lock region" "0,1"
bitfld.long 0x280 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x284 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_permission_0,The FW Region 20 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall"
hexmask.long.byte 0x284 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x284 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x284 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x284 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x284 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x284 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x284 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x284 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x284 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x284 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x284 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x284 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x284 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x284 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x284 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x284 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x284 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x288 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_permission_1,The FW Region 20 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall"
hexmask.long.byte 0x288 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x288 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x288 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x288 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x288 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x288 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x288 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x288 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x288 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x288 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x288 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x288 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x288 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x288 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x288 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x288 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x288 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_permission_2,The FW Region 20 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall"
hexmask.long.byte 0x28C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x28C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x28C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x290 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_start_address_l,The FW Region 20 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall"
hexmask.long.tbyte 0x290 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x290 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x294 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_start_address_h,The FW Region 20 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall"
hexmask.long.word 0x294 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x298 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_end_address_l,The FW Region 20 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall"
hexmask.long.tbyte 0x298 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x298 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x29C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_20_end_address_h,The FW Region 20 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 20 firewall"
hexmask.long.word 0x29C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x2A0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_control,The FW Region 21 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall"
bitfld.long 0x2A0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x2A0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x2A0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x2A0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_permission_0,The FW Region 21 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall"
hexmask.long.byte 0x2A4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2A4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2A4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2A4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2A4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2A4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2A8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_permission_1,The FW Region 21 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall"
hexmask.long.byte 0x2A8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2A8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2A8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2A8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2A8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2A8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2AC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_permission_2,The FW Region 21 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall"
hexmask.long.byte 0x2AC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2AC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2AC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2AC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2AC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2AC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2B0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_start_address_l,The FW Region 21 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall"
hexmask.long.tbyte 0x2B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x2B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x2B4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_start_address_h,The FW Region 21 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall"
hexmask.long.word 0x2B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x2B8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_end_address_l,The FW Region 21 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall"
hexmask.long.tbyte 0x2B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x2B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x2BC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_21_end_address_h,The FW Region 21 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 21 firewall"
hexmask.long.word 0x2BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x2C0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_control,The FW Region 22 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall"
bitfld.long 0x2C0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x2C0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x2C0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x2C0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_permission_0,The FW Region 22 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall"
hexmask.long.byte 0x2C4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_permission_1,The FW Region 22 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall"
hexmask.long.byte 0x2C8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2CC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_permission_2,The FW Region 22 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall"
hexmask.long.byte 0x2CC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2CC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2CC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2CC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2CC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2CC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2D0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_start_address_l,The FW Region 22 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall"
hexmask.long.tbyte 0x2D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x2D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x2D4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_start_address_h,The FW Region 22 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall"
hexmask.long.word 0x2D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x2D8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_end_address_l,The FW Region 22 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall"
hexmask.long.tbyte 0x2D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x2D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x2DC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_22_end_address_h,The FW Region 22 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 22 firewall"
hexmask.long.word 0x2DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x2E0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_control,The FW Region 23 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall"
bitfld.long 0x2E0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x2E0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x2E0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x2E0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_permission_0,The FW Region 23 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall"
hexmask.long.byte 0x2E4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2E4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2E4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2E4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2E4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2E4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2E8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_permission_1,The FW Region 23 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall"
hexmask.long.byte 0x2E8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2E8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2E8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2E8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2E8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2E8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2EC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_permission_2,The FW Region 23 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall"
hexmask.long.byte 0x2EC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2EC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2EC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2EC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2EC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2EC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2F0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_start_address_l,The FW Region 23 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall"
hexmask.long.tbyte 0x2F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x2F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x2F4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_start_address_h,The FW Region 23 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall"
hexmask.long.word 0x2F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x2F8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_end_address_l,The FW Region 23 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall"
hexmask.long.tbyte 0x2F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x2F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x2FC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0_fw_region_23_end_address_h,The FW Region 23 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk2_dma_cfg_l0 region 23 firewall"
hexmask.long.word 0x2FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
group.long 0x2800++0xFF
line.long 0x00 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall"
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall"
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall"
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 0 firewall"
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall"
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall"
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall"
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 1 firewall"
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall"
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall"
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall"
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 2 firewall"
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall"
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall"
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall"
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 3 firewall"
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x80 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall"
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region" "0,1"
bitfld.long 0x80 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall"
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x88 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall"
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x8C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall"
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x90 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall"
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x94 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall"
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x98 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall"
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x9C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 4 firewall"
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xA0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall"
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xA0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall"
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xA8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall"
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xAC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall"
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xB0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall"
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xB4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall"
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xB8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall"
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xBC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 5 firewall"
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xC0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall"
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xC0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall"
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xC8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall"
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xCC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall"
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xD0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall"
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xD4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall"
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xD8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall"
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xDC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 6 firewall"
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xE0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall"
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xE0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall"
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xE8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall"
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xEC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall"
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xF0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall"
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xF4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall"
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xF8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall"
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xFC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_clk4_cfg_l0 region 7 firewall"
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
group.long 0x2C00++0x1FF
line.long 0x00 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall"
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall"
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall"
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 0 firewall"
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall"
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall"
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall"
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 1 firewall"
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall"
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall"
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall"
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 2 firewall"
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall"
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall"
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall"
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 3 firewall"
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x80 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall"
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region" "0,1"
bitfld.long 0x80 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall"
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x88 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall"
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x8C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall"
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x90 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall"
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x94 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall"
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x98 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall"
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x9C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 4 firewall"
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xA0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall"
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xA0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall"
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xA8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall"
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xAC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall"
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xB0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall"
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xB4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall"
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xB8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall"
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xBC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 5 firewall"
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xC0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall"
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xC0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall"
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xC8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall"
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xCC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall"
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xD0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall"
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xD4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall"
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xD8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall"
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xDC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 6 firewall"
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xE0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall"
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xE0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall"
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xE8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall"
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xEC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall"
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xF0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall"
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xF4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall"
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xF8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall"
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xFC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 7 firewall"
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x100 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_control,The FW Region 8 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall"
bitfld.long 0x100 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x100 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x100 4. "LOCK,Lock region" "0,1"
bitfld.long 0x100 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x104 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_permission_0,The FW Region 8 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall"
hexmask.long.byte 0x104 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x104 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x104 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x104 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x104 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x104 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x104 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x104 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x104 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x104 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x104 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x104 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x104 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x104 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x104 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x104 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x104 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x108 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_permission_1,The FW Region 8 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall"
hexmask.long.byte 0x108 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x108 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x108 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x108 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x108 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x108 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x108 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x108 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x108 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x108 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x108 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x108 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x108 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x108 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x108 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x108 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x108 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_permission_2,The FW Region 8 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall"
hexmask.long.byte 0x10C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x10C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x10C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x10C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x10C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x10C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x10C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x10C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x10C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x10C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x10C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x10C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x10C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x10C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x10C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x10C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x10C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x110 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_start_address_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall"
hexmask.long.tbyte 0x110 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x110 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x114 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_start_address_h,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall"
hexmask.long.word 0x114 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x118 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_end_address_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall"
hexmask.long.tbyte 0x118 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x118 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x11C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_8_end_address_h,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 8 firewall"
hexmask.long.word 0x11C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x120 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_control,The FW Region 9 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall"
bitfld.long 0x120 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x120 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x120 4. "LOCK,Lock region" "0,1"
bitfld.long 0x120 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x124 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_permission_0,The FW Region 9 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall"
hexmask.long.byte 0x124 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x124 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x124 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x124 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x124 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x124 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x124 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x124 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x124 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x124 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x124 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x124 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x124 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x124 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x124 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x124 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x124 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x128 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_permission_1,The FW Region 9 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall"
hexmask.long.byte 0x128 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x128 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x128 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x128 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x128 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x128 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x128 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x128 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x128 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x128 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x128 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x128 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x128 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x128 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x128 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x128 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x128 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x12C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_permission_2,The FW Region 9 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall"
hexmask.long.byte 0x12C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x12C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x12C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x12C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x12C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x12C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x12C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x12C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x12C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x12C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x12C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x12C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x12C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x12C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x12C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x12C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x12C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x130 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_start_address_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall"
hexmask.long.tbyte 0x130 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x130 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x134 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_start_address_h,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall"
hexmask.long.word 0x134 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x138 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_end_address_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall"
hexmask.long.tbyte 0x138 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x138 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x13C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_9_end_address_h,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 9 firewall"
hexmask.long.word 0x13C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x140 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_control,The FW Region 10 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall"
bitfld.long 0x140 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x140 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x140 4. "LOCK,Lock region" "0,1"
bitfld.long 0x140 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x144 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_permission_0,The FW Region 10 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall"
hexmask.long.byte 0x144 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x144 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x144 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x144 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x144 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x144 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x144 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x144 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x144 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x144 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x144 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x144 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x144 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x144 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x144 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x144 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x144 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x148 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_permission_1,The FW Region 10 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall"
hexmask.long.byte 0x148 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x148 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x148 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x148 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x148 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x148 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x148 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x148 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x148 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x148 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x148 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x148 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x148 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x148 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x148 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x148 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x148 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x14C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_permission_2,The FW Region 10 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall"
hexmask.long.byte 0x14C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x14C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x14C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x14C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x14C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x14C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x14C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x14C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x14C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x14C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x14C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x14C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x14C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x14C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x14C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x14C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x14C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x150 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_start_address_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall"
hexmask.long.tbyte 0x150 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x150 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x154 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_start_address_h,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall"
hexmask.long.word 0x154 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x158 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_end_address_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall"
hexmask.long.tbyte 0x158 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x158 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x15C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_10_end_address_h,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 10 firewall"
hexmask.long.word 0x15C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x160 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_control,The FW Region 11 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall"
bitfld.long 0x160 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x160 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x160 4. "LOCK,Lock region" "0,1"
bitfld.long 0x160 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_permission_0,The FW Region 11 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall"
hexmask.long.byte 0x164 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x164 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x164 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x164 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x164 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x164 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x164 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x164 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x164 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x164 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x164 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x164 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x164 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x164 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x164 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x164 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x164 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x168 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_permission_1,The FW Region 11 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall"
hexmask.long.byte 0x168 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x168 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x168 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x168 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x168 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x168 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x168 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x168 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x168 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x168 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x168 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x168 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x168 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x168 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x168 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x168 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x168 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x16C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_permission_2,The FW Region 11 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall"
hexmask.long.byte 0x16C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x16C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x16C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x16C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x16C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x16C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x16C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x16C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x16C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x16C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x16C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x16C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x16C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x16C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x16C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x16C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x16C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x170 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_start_address_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall"
hexmask.long.tbyte 0x170 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x170 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x174 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_start_address_h,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall"
hexmask.long.word 0x174 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x178 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_end_address_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall"
hexmask.long.tbyte 0x178 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x178 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x17C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_11_end_address_h,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 11 firewall"
hexmask.long.word 0x17C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x180 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_control,The FW Region 12 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall"
bitfld.long 0x180 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x180 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x180 4. "LOCK,Lock region" "0,1"
bitfld.long 0x180 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_permission_0,The FW Region 12 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall"
hexmask.long.byte 0x184 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x184 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x184 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x184 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x184 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x184 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x184 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x184 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x184 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x184 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x184 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x184 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x184 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x184 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x184 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x184 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x184 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x188 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_permission_1,The FW Region 12 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall"
hexmask.long.byte 0x188 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x188 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x188 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x188 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x188 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x188 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x188 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x188 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x188 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x188 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x188 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x188 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x188 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x188 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x188 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x188 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x188 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x18C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_permission_2,The FW Region 12 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall"
hexmask.long.byte 0x18C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x18C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x18C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x18C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x18C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x18C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x18C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x18C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x18C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x18C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x18C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x18C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x18C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x18C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x18C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x18C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x18C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x190 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_start_address_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall"
hexmask.long.tbyte 0x190 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x190 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x194 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_start_address_h,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall"
hexmask.long.word 0x194 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x198 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_end_address_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall"
hexmask.long.tbyte 0x198 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x198 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x19C "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_12_end_address_h,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 12 firewall"
hexmask.long.word 0x19C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x1A0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_control,The FW Region 13 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall"
bitfld.long 0x1A0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x1A0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x1A0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x1A0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_permission_0,The FW Region 13 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall"
hexmask.long.byte 0x1A4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1A4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1A4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1A4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1A4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1A8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_permission_1,The FW Region 13 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall"
hexmask.long.byte 0x1A8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1A8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1A8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1A8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1A8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1AC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_permission_2,The FW Region 13 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall"
hexmask.long.byte 0x1AC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1AC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1AC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1AC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1AC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1AC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1B0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_start_address_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall"
hexmask.long.tbyte 0x1B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x1B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x1B4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_start_address_h,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall"
hexmask.long.word 0x1B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x1B8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_end_address_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall"
hexmask.long.tbyte 0x1B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x1B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1BC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_13_end_address_h,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 13 firewall"
hexmask.long.word 0x1BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x1C0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_control,The FW Region 14 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall"
bitfld.long 0x1C0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x1C0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x1C0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x1C0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_permission_0,The FW Region 14 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall"
hexmask.long.byte 0x1C4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1C4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1C4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1C4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1C4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1C8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_permission_1,The FW Region 14 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall"
hexmask.long.byte 0x1C8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1C8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1C8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1C8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1C8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1CC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_permission_2,The FW Region 14 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall"
hexmask.long.byte 0x1CC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1CC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1CC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1CC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1CC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1CC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1D0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_start_address_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall"
hexmask.long.tbyte 0x1D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x1D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x1D4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_start_address_h,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall"
hexmask.long.word 0x1D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x1D8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_end_address_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall"
hexmask.long.tbyte 0x1D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x1D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1DC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_14_end_address_h,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 14 firewall"
hexmask.long.word 0x1DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x1E0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_control,The FW Region 15 Control Register defines the control fields for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall"
bitfld.long 0x1E0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x1E0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x1E0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x1E0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_permission_0,The FW Region 15 Permission 0 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall"
hexmask.long.byte 0x1E4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1E4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1E4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1E4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1E4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1E8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_permission_1,The FW Region 15 Permission 1 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall"
hexmask.long.byte 0x1E8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1E8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1E8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1E8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1E8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1EC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_permission_2,The FW Region 15 Permission 2 Register defines the permissions for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall"
hexmask.long.byte 0x1EC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1EC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1EC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1EC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1EC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1EC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1F0 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_start_address_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall"
hexmask.long.tbyte 0x1F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x1F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x1F4 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_start_address_h,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall"
hexmask.long.word 0x1F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x1F8 "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_end_address_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall"
hexmask.long.tbyte 0x1F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x1F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1FC "FW_REGS_br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0_fw_region_15_end_address_h,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_64b_clk2_to_SCRP_32_clk2_misc_l0 region 15 firewall"
hexmask.long.word 0x1FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
tree.end
tree "CBASS0_GLB"
base ad:0x45B08000
rgroup.long 0x00++0x07
line.long 0x00 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "CBASS0_ISC"
base ad:0x45820000
group.long 0x400++0x03
line.long 0x00 "ISC_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x410++0x13
line.long 0x00 "ISC_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r region 0.."
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r region 0.."
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x800++0x03
line.long 0x00 "ISC_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x810++0x13
line.long 0x00 "ISC_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w region 0.."
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w region 0.."
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC00++0x03
line.long 0x00 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC10++0x13
line.long 0x00 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC30++0x13
line.long 0x00 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 1 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 1 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 1 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 1 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 2 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC50++0x13
line.long 0x00 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 2 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 2 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 2 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 2 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 3 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC70++0x13
line.long 0x00 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 3 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 3 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 3 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 3 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 4 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC90++0x13
line.long 0x00 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 4 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 4 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 4 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 4 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 5 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xCB0++0x13
line.long 0x00 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 5 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 5 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 5 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 5 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w region 6 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1000++0x03
line.long 0x00 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1010++0x13
line.long 0x00 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1030++0x13
line.long 0x00 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 1 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 1 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 1 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 1 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 2 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1050++0x13
line.long 0x00 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 2 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 2 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 2 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 2 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 3 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1070++0x13
line.long 0x00 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 3 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 3 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 3 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 3 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_4_control,The ISC Region 4 Control Register defines the control fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 4 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1090++0x13
line.long 0x00 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_4_start_address_l,The ISC Region 4 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 4 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_4_start_address_h,The ISC Region 4 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 4 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_4_end_address_l,The ISC Region 4 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 4 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_4_end_address_h,The ISC Region 4 End Address High Register defines the end address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 4 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_5_control,The ISC Region 5 Control Register defines the control fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 5 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10B0++0x13
line.long 0x00 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_5_start_address_l,The ISC Region 5 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 5 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_5_start_address_h,The ISC Region 5 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 5 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_5_end_address_l,The ISC Region 5 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 5 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_5_end_address_h,The ISC Region 5 End Address High Register defines the end address bits 47 to 32 for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 5 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r region 6 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1400++0x03
line.long 0x00 "ISC_REGS_Ik3_led2vbus_main_0_vbusp_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_led2vbus_main_0.vbusp region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1410++0x13
line.long 0x00 "ISC_REGS_Ik3_led2vbus_main_0_vbusp_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_led2vbus_main_0.vbusp region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_led2vbus_main_0_vbusp_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_led2vbus_main_0.vbusp region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_led2vbus_main_0_vbusp_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_led2vbus_main_0.vbusp region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_led2vbus_main_0_vbusp_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_led2vbus_main_0.vbusp region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_led2vbus_main_0_vbusp_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_led2vbus_main_0.vbusp region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1800++0x03
line.long 0x00 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1810++0x13
line.long 0x00 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmw region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C00++0x03
line.long 0x00 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C10++0x13
line.long 0x00 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmr region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2000++0x03
line.long 0x00 "ISC_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Igic500ss_1_4_main_0.mem_wr_vbusm region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2010++0x13
line.long 0x00 "ISC_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Igic500ss_1_4_main_0.mem_wr_vbusm region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Igic500ss_1_4_main_0.mem_wr_vbusm region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Igic500ss_1_4_main_0.mem_wr_vbusm region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Igic500ss_1_4_main_0.mem_wr_vbusm region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Igic500ss_1_4_main_0.mem_wr_vbusm region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2400++0x03
line.long 0x00 "ISC_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Igic500ss_1_4_main_0.mem_rd_vbusm region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2410++0x13
line.long 0x00 "ISC_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Igic500ss_1_4_main_0.mem_rd_vbusm region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Igic500ss_1_4_main_0.mem_rd_vbusm region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Igic500ss_1_4_main_0.mem_rd_vbusm region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Igic500ss_1_4_main_0.mem_rd_vbusm region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Igic500ss_1_4_main_0.mem_rd_vbusm region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2800++0x03
line.long 0x00 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd8ss_main_0.emmcsdss_rd region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2810++0x13
line.long 0x00 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd8ss_main_0.emmcsdss_rd region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd8ss_main_0.emmcsdss_rd region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd8ss_main_0.emmcsdss_rd region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd8ss_main_0.emmcsdss_rd region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd8ss_main_0.emmcsdss_rd region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C00++0x03
line.long 0x00 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd8ss_main_0.emmcsdss_wr region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C10++0x13
line.long 0x00 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd8ss_main_0.emmcsdss_wr region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd8ss_main_0.emmcsdss_wr region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd8ss_main_0.emmcsdss_wr region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd8ss_main_0.emmcsdss_wr region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd8ss_main_0.emmcsdss_wr region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3000++0x03
line.long 0x00 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3010++0x13
line.long 0x00 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_rd region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_rd region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3400++0x03
line.long 0x00 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3410++0x13
line.long 0x00 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd4ss_main_0.emmcsdss_wr region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd4ss_main_0.emmcsdss_wr region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3800++0x03
line.long 0x00 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd4ss_main_1.emmcsdss_wr region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3810++0x13
line.long 0x00 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd4ss_main_1.emmcsdss_wr region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd4ss_main_1.emmcsdss_wr region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd4ss_main_1.emmcsdss_wr region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd4ss_main_1.emmcsdss_wr region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd4ss_main_1.emmcsdss_wr region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3C00++0x03
line.long 0x00 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iemmcsd4ss_main_1.emmcsdss_rd region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3C10++0x13
line.long 0x00 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iemmcsd4ss_main_1.emmcsdss_rd region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iemmcsd4ss_main_1.emmcsdss_rd region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iemmcsd4ss_main_1.emmcsdss_rd region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iemmcsd4ss_main_1.emmcsdss_rd region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iemmcsd4ss_main_1.emmcsdss_rd region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4000++0x03
line.long 0x00 "ISC_REGS_Iusb2ss_16ffc_main_0_mstw0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iusb2ss_16ffc_main_0.mstw0 region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4010++0x13
line.long 0x00 "ISC_REGS_Iusb2ss_16ffc_main_0_mstw0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb2ss_16ffc_main_0.mstw0 region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Iusb2ss_16ffc_main_0_mstw0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iusb2ss_16ffc_main_0.mstw0 region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Iusb2ss_16ffc_main_0_mstw0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb2ss_16ffc_main_0.mstw0 region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Iusb2ss_16ffc_main_0_mstw0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iusb2ss_16ffc_main_0.mstw0 region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Iusb2ss_16ffc_main_0_mstw0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iusb2ss_16ffc_main_0.mstw0 region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4400++0x03
line.long 0x00 "ISC_REGS_Iusb2ss_16ffc_main_0_mstr0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iusb2ss_16ffc_main_0.mstr0 region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4410++0x13
line.long 0x00 "ISC_REGS_Iusb2ss_16ffc_main_0_mstr0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb2ss_16ffc_main_0.mstr0 region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Iusb2ss_16ffc_main_0_mstr0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iusb2ss_16ffc_main_0.mstr0 region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Iusb2ss_16ffc_main_0_mstr0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb2ss_16ffc_main_0.mstr0 region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Iusb2ss_16ffc_main_0_mstr0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iusb2ss_16ffc_main_0.mstr0 region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Iusb2ss_16ffc_main_0_mstr0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iusb2ss_16ffc_main_0.mstr0 region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4800++0x03
line.long 0x00 "ISC_REGS_Iusb2ss_16ffc_main_1_mstr0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iusb2ss_16ffc_main_1.mstr0 region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4810++0x13
line.long 0x00 "ISC_REGS_Iusb2ss_16ffc_main_1_mstr0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb2ss_16ffc_main_1.mstr0 region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Iusb2ss_16ffc_main_1_mstr0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iusb2ss_16ffc_main_1.mstr0 region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Iusb2ss_16ffc_main_1_mstr0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb2ss_16ffc_main_1.mstr0 region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Iusb2ss_16ffc_main_1_mstr0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iusb2ss_16ffc_main_1.mstr0 region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Iusb2ss_16ffc_main_1_mstr0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iusb2ss_16ffc_main_1.mstr0 region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4C00++0x03
line.long 0x00 "ISC_REGS_Iusb2ss_16ffc_main_1_mstw0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iusb2ss_16ffc_main_1.mstw0 region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4C10++0x13
line.long 0x00 "ISC_REGS_Iusb2ss_16ffc_main_1_mstw0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iusb2ss_16ffc_main_1.mstw0 region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Iusb2ss_16ffc_main_1_mstw0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iusb2ss_16ffc_main_1.mstw0 region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Iusb2ss_16ffc_main_1_mstw0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iusb2ss_16ffc_main_1.mstw0 region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Iusb2ss_16ffc_main_1_mstw0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iusb2ss_16ffc_main_1.mstw0 region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Iusb2ss_16ffc_main_1_mstw0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iusb2ss_16ffc_main_1.mstw0 region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5000++0x03
line.long 0x00 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ik3_dss_ul_main_0.vbusm_dma region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5010++0x13
line.long 0x00 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ik3_dss_ul_main_0.vbusm_dma region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5030++0x13
line.long 0x00 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 1 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 1 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 1 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 1 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ik3_dss_ul_main_0.vbusm_dma region 2 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5050++0x13
line.long 0x00 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 2 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 2 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 2 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 2 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ik3_dss_ul_main_0.vbusm_dma region 3 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5070++0x13
line.long 0x00 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 3 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 3 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ik3_dss_ul_main_0.vbusm_dma region 3 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ik3_dss_ul_main_0.vbusm_dma region 3 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ik3_dss_ul_main_0_vbusm_dma_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ik3_dss_ul_main_0.vbusm_dma region 4 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5400++0x03
line.long 0x00 "ISC_REGS_Isa3ss_am62_main_0_ctxcach_ext_dma_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Isa3ss_am62_main_0.ctxcach_ext_dma region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5410++0x13
line.long 0x00 "ISC_REGS_Isa3ss_am62_main_0_ctxcach_ext_dma_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Isa3ss_am62_main_0.ctxcach_ext_dma region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Isa3ss_am62_main_0_ctxcach_ext_dma_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Isa3ss_am62_main_0.ctxcach_ext_dma region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Isa3ss_am62_main_0_ctxcach_ext_dma_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Isa3ss_am62_main_0.ctxcach_ext_dma region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Isa3ss_am62_main_0_ctxcach_ext_dma_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Isa3ss_am62_main_0.ctxcach_ext_dma region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Isa3ss_am62_main_0_ctxcach_ext_dma_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Isa3ss_am62_main_0.ctxcach_ext_dma region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
newline
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "CBASS0_QOS"
base ad:0x45D20000
group.long 0x500++0x03
line.long 0x00 "QOS_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_r_map0,The Map Register defines the fields for the master Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_r per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x900++0x03
line.long 0x00 "QOS_REGS_Isam62_a53_512kb_wrap_main_0_a53_quad_wrap_cba_axi_w_map0,The Map Register defines the fields for the master Isam62_a53_512kb_wrap_main_0.a53_quad_wrap_cba_axi_w per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0xD00)++0x03
line.long 0x00 "QOS_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_w_map$1,The Map Register defines the fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_w per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x1100)++0x03
line.long 0x00 "QOS_REGS_Ik3_gpu_axe116m_main_0_k3_gpu_m_vbusm_r_map$1,The Map Register defines the fields for the master Ik3_gpu_axe116m_main_0.k3_gpu_m_vbusm_r per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
repeat.end
group.long 0x1900++0x03
line.long 0x00 "QOS_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmw_map0,The Map Register defines the fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmw per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x1D00++0x03
line.long 0x00 "QOS_REGS_Idebugss_k3_wrap_cv0_main_0_vbusmr_map0,The Map Register defines the fields for the master Idebugss_k3_wrap_cv0_main_0.vbusmr per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x2100++0x03
line.long 0x00 "QOS_REGS_Igic500ss_1_4_main_0_mem_wr_vbusm_map0,The Map Register defines the fields for the master Igic500ss_1_4_main_0.mem_wr_vbusm per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x2500++0x03
line.long 0x00 "QOS_REGS_Igic500ss_1_4_main_0_mem_rd_vbusm_map0,The Map Register defines the fields for the master Igic500ss_1_4_main_0.mem_rd_vbusm per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x2900++0x03
line.long 0x00 "QOS_REGS_Iemmcsd8ss_main_0_emmcsdss_rd_map0,The Map Register defines the fields for the master Iemmcsd8ss_main_0.emmcsdss_rd per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x2D00++0x03
line.long 0x00 "QOS_REGS_Iemmcsd8ss_main_0_emmcsdss_wr_map0,The Map Register defines the fields for the master Iemmcsd8ss_main_0.emmcsdss_wr per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x3100++0x03
line.long 0x00 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_rd_map0,The Map Register defines the fields for the master Iemmcsd4ss_main_0.emmcsdss_rd per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x3500++0x03
line.long 0x00 "QOS_REGS_Iemmcsd4ss_main_0_emmcsdss_wr_map0,The Map Register defines the fields for the master Iemmcsd4ss_main_0.emmcsdss_wr per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x3900++0x03
line.long 0x00 "QOS_REGS_Iemmcsd4ss_main_1_emmcsdss_wr_map0,The Map Register defines the fields for the master Iemmcsd4ss_main_1.emmcsdss_wr per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x3D00++0x03
line.long 0x00 "QOS_REGS_Iemmcsd4ss_main_1_emmcsdss_rd_map0,The Map Register defines the fields for the master Iemmcsd4ss_main_1.emmcsdss_rd per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x4100++0x03
line.long 0x00 "QOS_REGS_Iusb2ss_16ffc_main_0_mstw0_map0,The Map Register defines the fields for the master Iusb2ss_16ffc_main_0.mstw0 per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x4500++0x03
line.long 0x00 "QOS_REGS_Iusb2ss_16ffc_main_0_mstr0_map0,The Map Register defines the fields for the master Iusb2ss_16ffc_main_0.mstr0 per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x4900++0x03
line.long 0x00 "QOS_REGS_Iusb2ss_16ffc_main_1_mstr0_map0,The Map Register defines the fields for the master Iusb2ss_16ffc_main_1.mstr0 per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x4D00++0x03
line.long 0x00 "QOS_REGS_Iusb2ss_16ffc_main_1_mstw0_map0,The Map Register defines the fields for the master Iusb2ss_16ffc_main_1.mstw0 per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x5100)++0x03
line.long 0x00 "QOS_REGS_Ik3_dss_ul_main_0_vbusm_dma_map$1,The Map Register defines the fields for the master Ik3_dss_ul_main_0.vbusm_dma per channel"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
repeat.end
group.long 0x5500++0x03
line.long 0x00 "QOS_REGS_Isa3ss_am62_main_0_ctxcach_ext_dma_map0,The Map Register defines the fields for the master Isa3ss_am62_main_0.ctxcach_ext_dma per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
tree.end
tree "CBASS_CENTRAL2_ERR"
base ad:0x3F012000
rgroup.long 0x00++0x07
line.long 0x00 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "CBASS_CENTRAL2_FW"
base ad:0x45010000
group.long 0x00++0x7F
line.long 0x00 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Ipsram16kx32e_main_0.ram_vb region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Ipsram16kx32e_main_0.ram_vb region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Ipsram16kx32e_main_0.ram_vb region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Ipsram16kx32e_main_0.ram_vb region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Ipsram16kx32e_main_0.ram_vb region 0 firewall"
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Ipsram16kx32e_main_0.ram_vb region 0 firewall"
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ipsram16kx32e_main_0.ram_vb region 0 firewall"
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Ipsram16kx32e_main_0.ram_vb region 0 firewall"
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Ipsram16kx32e_main_0.ram_vb region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Ipsram16kx32e_main_0.ram_vb region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Ipsram16kx32e_main_0.ram_vb region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Ipsram16kx32e_main_0.ram_vb region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Ipsram16kx32e_main_0.ram_vb region 1 firewall"
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Ipsram16kx32e_main_0.ram_vb region 1 firewall"
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ipsram16kx32e_main_0.ram_vb region 1 firewall"
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Ipsram16kx32e_main_0.ram_vb region 1 firewall"
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Ipsram16kx32e_main_0.ram_vb region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Ipsram16kx32e_main_0.ram_vb region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Ipsram16kx32e_main_0.ram_vb region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Ipsram16kx32e_main_0.ram_vb region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Ipsram16kx32e_main_0.ram_vb region 2 firewall"
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Ipsram16kx32e_main_0.ram_vb region 2 firewall"
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ipsram16kx32e_main_0.ram_vb region 2 firewall"
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Ipsram16kx32e_main_0.ram_vb region 2 firewall"
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Ipsram16kx32e_main_0.ram_vb region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Ipsram16kx32e_main_0.ram_vb region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Ipsram16kx32e_main_0.ram_vb region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Ipsram16kx32e_main_0.ram_vb region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Ipsram16kx32e_main_0.ram_vb region 3 firewall"
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Ipsram16kx32e_main_0.ram_vb region 3 firewall"
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ipsram16kx32e_main_0.ram_vb region 3 firewall"
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_Ipsram16kx32e_main_0_ram_vb_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Ipsram16kx32e_main_0.ram_vb region 3 firewall"
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
group.long 0x400++0xFF
line.long 0x00 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x80 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 4 firewall"
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region" "0,1"
bitfld.long 0x80 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 4 firewall"
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x88 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 4 firewall"
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x8C "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 4 firewall"
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x90 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x94 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x98 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x9C "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xA0 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 5 firewall"
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xA0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 5 firewall"
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xA8 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 5 firewall"
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xAC "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 5 firewall"
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xB0 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xB4 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xB8 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xBC "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xC0 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 6 firewall"
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xC0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 6 firewall"
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xC8 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 6 firewall"
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xCC "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 6 firewall"
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xD0 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xD4 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xD8 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xDC "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xE0 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 7 firewall"
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xE0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 7 firewall"
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xE8 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 7 firewall"
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xEC "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv region 7 firewall"
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xF0 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xF4 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0.slv.."
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xF8 "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xFC "FW_REGS_export_am62_main_central_cbass_to_am62_mcu_cbass_data_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
group.long 0x800++0x7F
line.long 0x00 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall"
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall"
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall"
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 0 firewall"
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall"
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall"
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall"
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 1 firewall"
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall"
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall"
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall"
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 2 firewall"
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall"
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall"
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall"
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRP_32b_dmsc_hsm_to_scrp_hsm_clk2_l0 region 3 firewall"
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
tree.end
tree "CBASS_CENTRAL2_GLB"
base ad:0x45B04000
rgroup.long 0x00++0x07
line.long 0x00 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "CBASS_CENTRAL2_ISC"
base ad:0x45804000
group.long 0x00++0x03
line.long 0x00 "ISC_REGS_Iicss_m_main_0_pr1_mst_vbusp0_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iicss_m_main_0.pr1_mst_vbusp0 region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
newline
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x13
line.long 0x00 "ISC_REGS_Iicss_m_main_0_pr1_mst_vbusp0_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_m_main_0.pr1_mst_vbusp0 region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Iicss_m_main_0_pr1_mst_vbusp0_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_m_main_0.pr1_mst_vbusp0 region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Iicss_m_main_0_pr1_mst_vbusp0_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_m_main_0.pr1_mst_vbusp0 region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Iicss_m_main_0_pr1_mst_vbusp0_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iicss_m_main_0.pr1_mst_vbusp0 region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Iicss_m_main_0_pr1_mst_vbusp0_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iicss_m_main_0.pr1_mst_vbusp0 region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
newline
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x400++0x03
line.long 0x00 "ISC_REGS_Iicss_m_main_0_pr1_mst_vbusp1_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iicss_m_main_0.pr1_mst_vbusp1 region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
newline
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x410++0x13
line.long 0x00 "ISC_REGS_Iicss_m_main_0_pr1_mst_vbusp1_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iicss_m_main_0.pr1_mst_vbusp1 region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Iicss_m_main_0_pr1_mst_vbusp1_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iicss_m_main_0.pr1_mst_vbusp1 region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Iicss_m_main_0_pr1_mst_vbusp1_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iicss_m_main_0.pr1_mst_vbusp1 region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Iicss_m_main_0_pr1_mst_vbusp1_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iicss_m_main_0.pr1_mst_vbusp1 region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Iicss_m_main_0_pr1_mst_vbusp1_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iicss_m_main_0.pr1_mst_vbusp1 region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
newline
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "CBASS_CENTRAL2_QOS"
base ad:0x45D04000
group.long 0x100++0x03
line.long 0x00 "QOS_REGS_Iicss_m_main_0_pr1_mst_vbusp0_map0,The Map Register defines the fields for the master Iicss_m_main_0.pr1_mst_vbusp0 per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x500++0x03
line.long 0x00 "QOS_REGS_Iicss_m_main_0_pr1_mst_vbusp1_map0,The Map Register defines the fields for the master Iicss_m_main_0.pr1_mst_vbusp1 per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
tree.end
tree "CBASS_DBG0_ERR"
base ad:0x200000
rgroup.long 0x00++0x07
line.long 0x00 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "CBASS_FW0_ERR"
base ad:0x220000
rgroup.long 0x00++0x07
line.long 0x00 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "CBASS_INFRA1_ERR"
base ad:0x210000
rgroup.long 0x00++0x07
line.long 0x00 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "CBASS_IPCSS0_ERR"
base ad:0x230000
rgroup.long 0x00++0x07
line.long 0x00 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "CBASS_IPCSS0_FW"
base ad:0x45028000
group.long 0x00++0xFF
line.long 0x00 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Idmss_am62_main_0.ipcss_vbm_dst region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 0 firewall"
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 0 firewall"
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 0 firewall"
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 0 firewall"
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Idmss_am62_main_0.ipcss_vbm_dst region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 1 firewall"
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 1 firewall"
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 1 firewall"
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 1 firewall"
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Idmss_am62_main_0.ipcss_vbm_dst region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 2 firewall"
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 2 firewall"
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 2 firewall"
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 2 firewall"
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Idmss_am62_main_0.ipcss_vbm_dst region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 3 firewall"
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 3 firewall"
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 3 firewall"
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 3 firewall"
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x80 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Idmss_am62_main_0.ipcss_vbm_dst region 4 firewall"
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x80 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x80 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 4 firewall"
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x88 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 4 firewall"
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x8C "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 4 firewall"
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x90 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 4 firewall"
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x94 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 4 firewall"
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x98 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 4 firewall"
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x9C "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 4 firewall"
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xA0 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Idmss_am62_main_0.ipcss_vbm_dst region 5 firewall"
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0xA0 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0xA0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 5 firewall"
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xA8 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 5 firewall"
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xAC "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 5 firewall"
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xB0 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 5 firewall"
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xB4 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 5 firewall"
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xB8 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 5 firewall"
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xBC "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 5 firewall"
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xC0 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Idmss_am62_main_0.ipcss_vbm_dst region 6 firewall"
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0xC0 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0xC0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 6 firewall"
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xC8 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 6 firewall"
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xCC "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 6 firewall"
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xD0 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 6 firewall"
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xD4 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 6 firewall"
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xD8 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 6 firewall"
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xDC "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 6 firewall"
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xE0 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Idmss_am62_main_0.ipcss_vbm_dst region 7 firewall"
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0xE0 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0xE0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 7 firewall"
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xE8 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 7 firewall"
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xEC "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Idmss_am62_main_0.ipcss_vbm_dst region 7 firewall"
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xF0 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 7 firewall"
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xF4 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Idmss_am62_main_0.ipcss_vbm_dst region 7 firewall"
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xF8 "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 7 firewall"
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xFC "FW_REGS_Idmss_am62_main_0_ipcss_vbm_dst_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Idmss_am62_main_0.ipcss_vbm_dst region 7 firewall"
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
group.long 0x400++0xFF
line.long 0x00 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 0 firewall"
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 0 firewall"
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 0 firewall"
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 0 firewall"
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 1 firewall"
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 1 firewall"
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 1 firewall"
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 1 firewall"
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 2 firewall"
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 2 firewall"
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 2 firewall"
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 2 firewall"
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 3 firewall"
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 3 firewall"
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 3 firewall"
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 3 firewall"
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x80 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 4 firewall"
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0x80 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x80 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 4 firewall"
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x88 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 4 firewall"
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x8C "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 4 firewall"
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x90 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 4 firewall"
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x94 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 4 firewall"
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x98 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 4 firewall"
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x9C "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 4 firewall"
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xA0 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 5 firewall"
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0xA0 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0xA0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 5 firewall"
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xA8 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 5 firewall"
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xAC "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 5 firewall"
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xB0 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 5 firewall"
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xB4 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 5 firewall"
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xB8 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 5 firewall"
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xBC "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 5 firewall"
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xC0 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 6 firewall"
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0xC0 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0xC0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 6 firewall"
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xC8 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 6 firewall"
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xCC "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 6 firewall"
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xD0 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 6 firewall"
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xD4 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 6 firewall"
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xD8 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 6 firewall"
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xDC "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 6 firewall"
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xE0 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 7 firewall"
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region" "0,1"
bitfld.long 0xE0 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0xE0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 7 firewall"
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xE8 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 7 firewall"
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xEC "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 7 firewall"
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
newline
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
newline
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
newline
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xF0 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 7 firewall"
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xF4 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 7 firewall"
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xF8 "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 7 firewall"
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xFC "FW_REGS_Isa3ss_am62_main_0_ipcss_vbm_dst_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave Isa3ss_am62_main_0.ipcss_vbm_dst region 7 firewall"
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
tree.end
tree "CBASS_IPCSS0_GLB"
base ad:0x45B01000
rgroup.long 0x00++0x07
line.long 0x00 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "CBASS_MCASP0_ERR"
base ad:0x240000
rgroup.long 0x00++0x07
line.long 0x00 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "CBASS_MISC_PERI0_ERR"
base ad:0x201F0000
rgroup.long 0x00++0x07
line.long 0x00 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "CMP_EVENT_INTROUTER0_INTR_ROUTER_CFG"
base ad:0xA30000
rgroup.long 0x00++0x07
line.long 0x00 "INTR_ROUTER_CFG_PID,Identification register"
bitfld.long 0x00 30.--31. "SCHEME,scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,function"
bitfld.long 0x00 11.--15. "RTLVER,rtl version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom id" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINREV,minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register"
bitfld.long 0x04 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1"
bitfld.long 0x04 0.--4. "MUX_CNTL,Mux control for interrupt N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "COMPUTE_CLUSTER0_PBIST_0_PBIST"
base ad:0x330000
group.long 0x00++0x7F
line.long 0x00 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF0L,"
line.long 0x04 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF1L,"
line.long 0x08 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF2L,"
line.long 0x0C "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF3L,"
line.long 0x10 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF4L,"
line.long 0x14 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF5L,"
line.long 0x18 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF6L,"
line.long 0x1C "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF7L,"
line.long 0x20 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF8L,"
line.long 0x24 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF9L,"
line.long 0x28 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF10L,"
line.long 0x2C "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF11L,"
line.long 0x30 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF12L,"
line.long 0x34 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF13L,"
line.long 0x38 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF14L,"
line.long 0x3C "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF15L,"
line.long 0x40 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF0U,"
line.long 0x44 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF1U,"
line.long 0x48 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF2U,"
line.long 0x4C "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF3U,"
line.long 0x50 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF4U,"
line.long 0x54 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF5U,"
line.long 0x58 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF6U,"
line.long 0x5C "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF7U,"
line.long 0x60 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF8U,"
line.long 0x64 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF9U,"
line.long 0x68 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF10U,"
line.long 0x6C "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF11U,"
line.long 0x70 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF12U,"
line.long 0x74 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF13U,"
line.long 0x78 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF14U,"
line.long 0x7C "K3_PBIST_4C28P_4BIT_WRAP_REGS_RF15U,"
group.long 0x100++0x27
line.long 0x00 "K3_PBIST_4C28P_4BIT_WRAP_REGS_A0,"
hexmask.long.word 0x00 0.--15. 1. "A0,Variable Address Register 0 (A0)"
line.long 0x04 "K3_PBIST_4C28P_4BIT_WRAP_REGS_A1,"
hexmask.long.word 0x04 0.--15. 1. "A1,Variable Address Register 1 (A1)"
line.long 0x08 "K3_PBIST_4C28P_4BIT_WRAP_REGS_A2,"
hexmask.long.word 0x08 0.--15. 1. "A2,Variable Address Register 2 (A2)"
line.long 0x0C "K3_PBIST_4C28P_4BIT_WRAP_REGS_A3,"
hexmask.long.word 0x0C 0.--15. 1. "A3,Variable Address Register 3 (A3)"
line.long 0x10 "K3_PBIST_4C28P_4BIT_WRAP_REGS_L0,"
hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)"
line.long 0x14 "K3_PBIST_4C28P_4BIT_WRAP_REGS_L1,"
hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)"
line.long 0x18 "K3_PBIST_4C28P_4BIT_WRAP_REGS_L2,"
hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)"
line.long 0x1C "K3_PBIST_4C28P_4BIT_WRAP_REGS_L3,"
hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)"
line.long 0x20 "K3_PBIST_4C28P_4BIT_WRAP_REGS_D,"
hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)"
hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)"
line.long 0x24 "K3_PBIST_4C28P_4BIT_WRAP_REGS_E,"
hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)"
hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)"
group.long 0x130++0x3F
line.long 0x00 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CA0,"
hexmask.long.word 0x00 0.--15. 1. "CA0,Constant Address Register 0 (CA0)"
line.long 0x04 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CA1,"
hexmask.long.word 0x04 0.--15. 1. "CA1,Constant Address Register 1 (CA1)"
line.long 0x08 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CA2,"
hexmask.long.word 0x08 0.--15. 1. "CA2,Constant Address Register 2 (CA2)"
line.long 0x0C "K3_PBIST_4C28P_4BIT_WRAP_REGS_CA3,"
hexmask.long.word 0x0C 0.--15. 1. "CA3,Constant Address Register 3 (CA3)"
line.long 0x10 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CL0,"
hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)"
line.long 0x14 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CL1,"
hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)"
line.long 0x18 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CL2,"
hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)"
line.long 0x1C "K3_PBIST_4C28P_4BIT_WRAP_REGS_CL3,"
hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)"
line.long 0x20 "K3_PBIST_4C28P_4BIT_WRAP_REGS_I0,"
hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)"
line.long 0x24 "K3_PBIST_4C28P_4BIT_WRAP_REGS_I1,"
hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)"
line.long 0x28 "K3_PBIST_4C28P_4BIT_WRAP_REGS_I2,"
hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)"
line.long 0x2C "K3_PBIST_4C28P_4BIT_WRAP_REGS_I3,"
hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)"
line.long 0x30 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RAMT,"
hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS"
hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS"
hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR"
bitfld.long 0x30 2.--5. "PLS,Pipeline Latency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3"
line.long 0x34 "K3_PBIST_4C28P_4BIT_WRAP_REGS_DLR,"
hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)"
bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1"
bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1"
bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1"
bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1"
newline
bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1"
bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1"
bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1"
bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1"
bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1"
newline
bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1"
bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1"
line.long 0x38 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CMS,"
bitfld.long 0x38 0.--3. "CMS,Clock Mux Select (CMS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "K3_PBIST_4C28P_4BIT_WRAP_REGS_STR,"
bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1"
bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1"
bitfld.long 0x3C 2. "STOP,Stop" "0,1"
bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1"
bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1"
group.quad 0x170++0x07
line.quad 0x00 "K3_PBIST_4C28P_4BIT_WRAP_REGS_SCR,"
hexmask.quad.byte 0x00 56.--63. 1. "SCR7,Address Scrambling Register 7"
hexmask.quad.byte 0x00 48.--55. 1. "SCR6,Address Scrambling Register 6"
hexmask.quad.byte 0x00 40.--47. 1. "SCR5,Address Scrambling Register 5"
hexmask.quad.byte 0x00 32.--39. 1. "SCR4,Address Scrambling Register 4"
hexmask.quad.byte 0x00 24.--31. 1. "SCR3,Address Scrambling Register 3"
newline
hexmask.quad.byte 0x00 16.--23. 1. "SCR2,Address Scrambling Register 2"
hexmask.quad.byte 0x00 8.--15. 1. "SCR1,Address Scrambling Register 1"
hexmask.quad.byte 0x00 0.--7. 1. "SCR0,Address Scrambling Register 0"
group.long 0x178++0x13
line.long 0x00 "K3_PBIST_4C28P_4BIT_WRAP_REGS_CSR,"
hexmask.long.byte 0x00 24.--31. 1. "CSR3,Chip Select 3 (CSR3)"
hexmask.long.byte 0x00 16.--23. 1. "CSR2,Chip Select 2 (CSR2)"
hexmask.long.byte 0x00 8.--15. 1. "CSR1,Chip Select 1(CSR1)"
hexmask.long.byte 0x00 0.--7. 1. "CSR0,Chip Select 0 (CSR0)"
line.long 0x04 "K3_PBIST_4C28P_4BIT_WRAP_REGS_FDLY,"
hexmask.long.byte 0x04 0.--7. 1. "FDLY,Fail Delay (FDLY)"
line.long 0x08 "K3_PBIST_4C28P_4BIT_WRAP_REGS_PACT,"
bitfld.long 0x08 0. "PACT,PBIST Activate (PACT)" "0,1"
line.long 0x0C "K3_PBIST_4C28P_4BIT_WRAP_REGS_PID,"
bitfld.long 0x0C 0.--4. "PID,PBIST ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "K3_PBIST_4C28P_4BIT_WRAP_REGS_OVER,"
bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1"
bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1"
bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1"
bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1"
rgroup.quad 0x190++0x17
line.quad 0x00 "K3_PBIST_4C28P_4BIT_WRAP_REGS_FSRF,"
bitfld.quad 0x00 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1"
bitfld.quad 0x00 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1"
line.quad 0x08 "K3_PBIST_4C28P_4BIT_WRAP_REGS_FSRC,"
bitfld.quad 0x08 32.--35. "FSRC1,Fail Status Count - Port 1 (FSRC1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 0.--3. "FSRC0,Fail Status Count - Port 0 (FSRC0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.quad 0x10 "K3_PBIST_4C28P_4BIT_WRAP_REGS_FSRA,"
hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)"
hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)"
rgroup.long 0x1A8++0x03
line.long 0x00 "K3_PBIST_4C28P_4BIT_WRAP_REGS_FSRDL0,"
rgroup.long 0x1B0++0x17
line.long 0x00 "K3_PBIST_4C28P_4BIT_WRAP_REGS_FSRDL1,"
line.long 0x04 "K3_PBIST_4C28P_4BIT_WRAP_REGS_MARGIN_MODE,"
bitfld.long 0x04 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3"
bitfld.long 0x04 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3"
line.long 0x08 "K3_PBIST_4C28P_4BIT_WRAP_REGS_WRENZ,"
bitfld.long 0x08 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3"
line.long 0x0C "K3_PBIST_4C28P_4BIT_WRAP_REGS_PAGE_PGS,"
bitfld.long 0x0C 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3"
line.long 0x10 "K3_PBIST_4C28P_4BIT_WRAP_REGS_ROM,"
bitfld.long 0x10 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3"
line.long 0x14 "K3_PBIST_4C28P_4BIT_WRAP_REGS_ALGO,"
hexmask.long.byte 0x14 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)"
hexmask.long.byte 0x14 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)"
hexmask.long.byte 0x14 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)"
hexmask.long.byte 0x14 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)"
group.quad 0x1C8++0x07
line.quad 0x00 "K3_PBIST_4C28P_4BIT_WRAP_REGS_RINFO,"
hexmask.quad.byte 0x00 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)"
hexmask.quad.byte 0x00 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)"
hexmask.quad.byte 0x00 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)"
hexmask.quad.byte 0x00 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)"
hexmask.quad.byte 0x00 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)"
newline
hexmask.quad.byte 0x00 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)"
hexmask.quad.byte 0x00 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)"
hexmask.quad.byte 0x00 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)"
tree.end
tree "CPSW0_ECC"
base ad:0x704000
rgroup.long 0x00++0x03
line.long 0x00 "CPSW_NUSS_VBUSP_ECC_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "CPSW_NUSS_VBUSP_ECC_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "CPSW_NUSS_VBUSP_ECC_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "CPSW_NUSS_VBUSP_ECC_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "CPSW_NUSS_VBUSP_ECC_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "CPSW_NUSS_VBUSP_ECC_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
bitfld.long 0x04 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
bitfld.long 0x04 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
bitfld.long 0x04 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
newline
bitfld.long 0x04 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
bitfld.long 0x04 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
bitfld.long 0x04 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
bitfld.long 0x04 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
newline
bitfld.long 0x04 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
bitfld.long 0x04 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
bitfld.long 0x04 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
bitfld.long 0x04 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
newline
bitfld.long 0x04 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
bitfld.long 0x04 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
bitfld.long 0x04 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
bitfld.long 0x04 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
newline
bitfld.long 0x04 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
bitfld.long 0x04 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
bitfld.long 0x04 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
bitfld.long 0x04 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "CPSW_NUSS_VBUSP_ECC_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
bitfld.long 0x00 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
newline
bitfld.long 0x00 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
bitfld.long 0x00 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
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bitfld.long 0x00 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
bitfld.long 0x00 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
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bitfld.long 0x00 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
bitfld.long 0x00 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
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bitfld.long 0x00 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "CPSW_NUSS_VBUSP_ECC_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
bitfld.long 0x00 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
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bitfld.long 0x00 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
bitfld.long 0x00 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
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bitfld.long 0x00 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
bitfld.long 0x00 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
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bitfld.long 0x00 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
bitfld.long 0x00 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
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bitfld.long 0x00 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "CPSW_NUSS_VBUSP_ECC_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "CPSW_NUSS_VBUSP_ECC_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
bitfld.long 0x04 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
bitfld.long 0x04 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
bitfld.long 0x04 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
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bitfld.long 0x04 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
bitfld.long 0x04 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
bitfld.long 0x04 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
bitfld.long 0x04 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
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bitfld.long 0x04 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
bitfld.long 0x04 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
bitfld.long 0x04 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
bitfld.long 0x04 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
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bitfld.long 0x04 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
bitfld.long 0x04 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
bitfld.long 0x04 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
bitfld.long 0x04 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
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bitfld.long 0x04 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
bitfld.long 0x04 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
bitfld.long 0x04 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
bitfld.long 0x04 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "CPSW_NUSS_VBUSP_ECC_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
bitfld.long 0x00 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
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bitfld.long 0x00 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
bitfld.long 0x00 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
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bitfld.long 0x00 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
bitfld.long 0x00 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
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bitfld.long 0x00 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
bitfld.long 0x00 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
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bitfld.long 0x00 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "CPSW_NUSS_VBUSP_ECC_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
bitfld.long 0x00 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
bitfld.long 0x00 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
bitfld.long 0x00 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
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bitfld.long 0x00 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
bitfld.long 0x00 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
bitfld.long 0x00 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
bitfld.long 0x00 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
newline
bitfld.long 0x00 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
bitfld.long 0x00 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
bitfld.long 0x00 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
bitfld.long 0x00 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x00 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
bitfld.long 0x00 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
bitfld.long 0x00 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
bitfld.long 0x00 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
newline
bitfld.long 0x00 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
bitfld.long 0x00 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
bitfld.long 0x00 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
bitfld.long 0x00 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "CPSW_NUSS_VBUSP_ECC_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "CPSW_NUSS_VBUSP_ECC_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "CPSW_NUSS_VBUSP_ECC_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "CPSW_NUSS_VBUSP_ECC_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "CPSW0_NUSS"
base ad:0x8000000
rgroup.long 0x00++0x17
line.long 0x00 "CPSW_NUSS_VBUSP_CPSW_NUSS_IDVER_REG,ID Version Register"
hexmask.long.word 0x00 16.--31. 1. "IDENT,Identification value"
newline
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
line.long 0x04 "CPSW_NUSS_VBUSP_SYNCE_COUNT_REG,SyncE Count Register"
line.long 0x08 "CPSW_NUSS_VBUSP_SYNCE_MUX_REG,SyncE Mux Register"
bitfld.long 0x08 0.--5. "SYNCE_SEL,Sync E Select Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "CPSW_NUSS_VBUSP_CONTROL_REG,Control Register"
bitfld.long 0x0C 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode" "The low power indicate state includes gating off..,The low power indicate state does not gate the.."
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bitfld.long 0x0C 0. "EEE_EN,Energy Efficient Ethernet Enable" "EEE is disabled,EEE is enabled"
line.long 0x10 "CPSW_NUSS_VBUSP_SGMII_NON_FIBER_MODE_REG,SGMII NON FIBER Mode Register"
bitfld.long 0x10 0.--1. "SGMII_NON_FIBER_MODE,This register bit goes to the CPSGMII mode input only" "0,1,2,3"
line.long 0x14 "CPSW_NUSS_VBUSP_SERDES_RESET_ISO_REG,SyncE Mux Register"
bitfld.long 0x14 0.--1. "SERDES_RESET_ISO,These bits control whether the SERDES ignores the hard reset for isolation or not" "0,1,2,3"
rgroup.long 0x1C++0x07
line.long 0x00 "CPSW_NUSS_VBUSP_SUBSSYSTEM_STATUS_REG,Subsystem Status Register"
bitfld.long 0x00 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW" "0,1"
line.long 0x04 "CPSW_NUSS_VBUSP_SUBSYSTEM_CONFIG_REG,Subsystem Configuration Register"
hexmask.long.byte 0x04 20.--27. 1. "XGMII,The Number of XGMII Ports included in the CPSW_NUSS"
newline
bitfld.long 0x04 19. "QSGMII,QSGMII is included in the CPSW_NUSS" "0,1"
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bitfld.long 0x04 18. "SGMII,SGMII is included in the CPSW_NUSS" "0,1"
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bitfld.long 0x04 17. "RGMII,RGMII is included in the CPSW_NUSS" "0,1"
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bitfld.long 0x04 16. "RMII,RMII is included in the CPSW_NUSS" "0,1"
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bitfld.long 0x04 8.--12. "NUM_GENF,The number of CPTS GENF outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x04 0.--7. 1. "NUM_PORTS,The total number of ports including the host port 0"
rgroup.long 0x30++0x07
line.long 0x00 "CPSW_NUSS_VBUSP_RGMII1_STATUS_REG,RGMII1 Status Register"
bitfld.long 0x00 3. "FULLDUPLEX,Rgmii1 full dulex" "Half-duplex,Full-duplex"
newline
bitfld.long 0x00 1.--2. "SPEED,Rgmii1 speed" "0,1,2,3"
newline
bitfld.long 0x00 0. "LINK,Rgmii1 link indicator" "Link is down,Link is up"
line.long 0x04 "CPSW_NUSS_VBUSP_RGMII2_STATUS_REG,RGMII2 Status Register"
bitfld.long 0x04 3. "FULLDUPLEX,Rgmii2 full dulex" "Half-duplex,Full-duplex"
newline
bitfld.long 0x04 1.--2. "SPEED,Rgmii2 speed" "0,1,2,3"
newline
bitfld.long 0x04 0. "LINK,Rgmii2 link indicator" "Link is down,Link is up"
rgroup.long 0x100++0x07
line.long 0x00 "CPSW_NUSS_VBUSP_SGMII_IDVER_REG,SGMII IDVER register"
hexmask.long.word 0x00 16.--31. 1. "TX_IDENT,MODULE value"
newline
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
line.long 0x04 "CPSW_NUSS_VBUSP_SOFT_RESET_REG,SGMII Soft Reset Register"
bitfld.long 0x04 1. "RT_SOFT_RESET,Transmit and receive software reset" "0,1"
newline
bitfld.long 0x04 0. "SOFT_RESET,Software reset" "0,1"
group.long 0x110++0x17
line.long 0x00 "CPSW_NUSS_VBUSP_CONTROL_REG,SGMII Control Register"
bitfld.long 0x00 6. "TEST_PATTERN_EN,Test pattern enable" "0,1"
newline
bitfld.long 0x00 5. "MASTER,Master mode" "0,1"
newline
bitfld.long 0x00 4. "LOOPBACK,Loopback mode" "0,1"
newline
bitfld.long 0x00 3. "MR_NP_LOADED,Next page loaded" "0,1"
newline
bitfld.long 0x00 2. "FAST_LINK_TIMER,Fast link timer" "0,1"
newline
bitfld.long 0x00 1. "MR_AN_RESTART,Auto-negotiation restart" "0,1"
newline
bitfld.long 0x00 0. "MR_AN_ENABLE,Auto-negotiation enable" "0,1"
line.long 0x04 "CPSW_NUSS_VBUSP_STATUS_REG,SGMII Status Register"
bitfld.long 0x04 5. "FIB_SIG_DETECT,Fiber signal detect" "0,1"
newline
bitfld.long 0x04 4. "LOCK,Lock" "0,1"
newline
bitfld.long 0x04 3. "MR_PAGE_RX,Next page received" "0,1"
newline
bitfld.long 0x04 2. "MR_AN_COMPLETE,Auto-negotiation complete" "0,1"
newline
bitfld.long 0x04 1. "AN_ERROR,Auto-negotiation error" "0,1"
newline
bitfld.long 0x04 0. "LINK,Link indicator" "0,1"
line.long 0x08 "CPSW_NUSS_VBUSP_MR_ADV_ABILITY_REG,SGMII MR Advertized Ability Register"
hexmask.long.word 0x08 0.--15. 1. "MR_ADV_ABILITY,Advertised ability"
line.long 0x0C "CPSW_NUSS_VBUSP_MR_NP_TX_REG,SGMII Next Pate Transmit Register"
hexmask.long.word 0x0C 0.--15. 1. "MR_NP_TX,Next page transmit"
line.long 0x10 "CPSW_NUSS_VBUSP_MR_LP_ADV_ABILITY_REG,SGMII Link Partner Advertized Ability Register"
hexmask.long.word 0x10 0.--15. 1. "MR_LP_ADV_ABILITY,Link partner advertised ability"
line.long 0x14 "CPSW_NUSS_VBUSP_MR_LP_NP_RX_REG,SGMII Link Partner Next Page Receive Register"
hexmask.long.word 0x14 0.--15. 1. "MR_LP_NP_RX,Link Partner Next Page Received"
group.long 0x140++0x0B
line.long 0x00 "CPSW_NUSS_VBUSP_DIAG_CLEAR_REG,SGMII Diagnostics Clear Register"
bitfld.long 0x00 0. "DIAG_CLEAR,Diagnostics clear" "0,1"
line.long 0x04 "CPSW_NUSS_VBUSP_DIAG_CONTROL_REG,SGMII Diagnostics Control Register"
bitfld.long 0x04 4.--6. "DIAG_SM_SEL,Diagnostic select" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0.--1. "DIAG_EDGE_SEL,Diagnostics hold signals edge select" "0,1,2,3"
line.long 0x08 "CPSW_NUSS_VBUSP_DIAG_STATUS_REG,SGMII Diagnostics Status Register"
hexmask.long.word 0x08 0.--15. 1. "DIAG_STATUS,Diagnostics status"
rgroup.long 0xF00++0x47
line.long 0x00 "CPSW_NUSS_VBUSP_MDIO_VERSION_REG,MDIO Version Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
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bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
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bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CPSW_NUSS_VBUSP_CONTROL_REG,MDIO Control Register"
rbitfld.long 0x04 31. "IDLE,MDIO state machine idle" "0,1"
newline
bitfld.long 0x04 30. "ENABLE,Enable control" "0,1"
newline
rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "0,1"
newline
bitfld.long 0x04 19. "FAULT,Fault indicator" "0,1"
newline
bitfld.long 0x04 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
newline
bitfld.long 0x04 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
newline
hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock divider"
line.long 0x08 "CPSW_NUSS_VBUSP_ALIVE_REG,MDIO Alive Register"
line.long 0x0C "CPSW_NUSS_VBUSP_LINK_REG,MDIO Link Register"
line.long 0x10 "CPSW_NUSS_VBUSP_LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register"
bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
line.long 0x14 "CPSW_NUSS_VBUSP_LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register"
bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
line.long 0x18 "CPSW_NUSS_VBUSP_LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register"
bitfld.long 0x18 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1"
line.long 0x1C "CPSW_NUSS_VBUSP_LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register"
bitfld.long 0x1C 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1"
line.long 0x20 "CPSW_NUSS_VBUSP_USER_INT_RAW_REG,MDIO User Interrupt Raw Register"
bitfld.long 0x20 0.--1. "USERINTRAW,User interrupt raw" "0,1,2,3"
line.long 0x24 "CPSW_NUSS_VBUSP_USER_INT_MASKED_REG,MDIO User Interrupt Masked Register"
bitfld.long 0x24 0.--1. "USERINTMASKED,User interrupt masked" "0,1,2,3"
line.long 0x28 "CPSW_NUSS_VBUSP_USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register"
bitfld.long 0x28 0.--1. "USERINTMASKSET,MDIO user interrupt mask set" "0,1,2,3"
line.long 0x2C "CPSW_NUSS_VBUSP_USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register"
bitfld.long 0x2C 0.--1. "USERINTMASKCLR,MDIO user interrupt mask clear" "0,1,2,3"
line.long 0x30 "CPSW_NUSS_VBUSP_MANUAL_IF_REG,MDIO Manual Interface Register"
bitfld.long 0x30 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1"
newline
bitfld.long 0x30 1. "MDIO_OE,MDIO Output Enable" "0,1"
newline
bitfld.long 0x30 0. "MDIO_PIN,MDIO Pin" "0,1"
line.long 0x34 "CPSW_NUSS_VBUSP_POLL_REG,MDIO Poll Register"
bitfld.long 0x34 31. "MANUALMODE,MDIO Manual Mode" "0,1"
newline
bitfld.long 0x34 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1"
newline
hexmask.long.byte 0x34 0.--7. 1. "IPG,MDIO IPG"
line.long 0x38 "CPSW_NUSS_VBUSP_POLL_EN_REG,MDIO Poll Enable Register"
line.long 0x3C "CPSW_NUSS_VBUSP_CLAUS45_REG,MDIO Clause45 Register"
line.long 0x40 "CPSW_NUSS_VBUSP_USER_ADDR0_REG,MDIO Address 0 Register"
hexmask.long.word 0x40 0.--15. 1. "USER_ADDR0,MDIO USER Address 0"
line.long 0x44 "CPSW_NUSS_VBUSP_USER_ADDR1_REG,MDIO Address 1 Register"
hexmask.long.word 0x44 0.--15. 1. "USER_ADDR1,MDIO USER Address 1"
rgroup.long 0x1000++0x03
line.long 0x00 "CPSW_NUSS_VBUSP_REVISION,Revision Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
newline
bitfld.long 0x00 11.--15. "RTLVER,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINREV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x1010++0x07
line.long 0x00 "CPSW_NUSS_VBUSP_eoi_reg,End of Interrupt Register"
hexmask.long.byte 0x00 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
line.long 0x04 "CPSW_NUSS_VBUSP_intr_vector_reg,Interrupt Vector Register"
group.long 0x1100++0x03
line.long 0x00 "CPSW_NUSS_VBUSP_enable_reg_out_pulse_0,Enable Register 0"
bitfld.long 0x00 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA,Enable Set for out_pulse_en_stat_penda" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA,Enable Set for out_pulse_en_mdio_penda" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA,Enable Set for out_pulse_en_evnt_penda" "0,1"
group.long 0x1300++0x03
line.long 0x00 "CPSW_NUSS_VBUSP_enable_clr_reg_out_pulse_0,Enable Clear Register 0"
bitfld.long 0x00 2. "ENABLE_OUT_PULSE_EN_STAT_PENDA_CLR,Enable Clear for out_pulse_en_stat_penda" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_OUT_PULSE_EN_MDIO_PENDA_CLR,Enable Clear for out_pulse_en_mdio_penda" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_OUT_PULSE_EN_EVNT_PENDA_CLR,Enable Clear for out_pulse_en_evnt_penda" "0,1"
rgroup.long 0x1500++0x03
line.long 0x00 "CPSW_NUSS_VBUSP_status_reg_out_pulse_0,Status Register 0"
bitfld.long 0x00 2. "STATUS_OUT_PULSE_STAT_PENDA,Status for out_pulse_en_stat_penda" "0,1"
newline
bitfld.long 0x00 1. "STATUS_OUT_PULSE_MDIO_PENDA,Status for out_pulse_en_mdio_penda" "0,1"
newline
bitfld.long 0x00 0. "STATUS_OUT_PULSE_EVNT_PENDA,Status for out_pulse_en_evnt_penda" "0,1"
rgroup.long 0x1A80++0x03
line.long 0x00 "CPSW_NUSS_VBUSP_intr_vector_reg_out_pulse,Interrupt Vector for out_pulse"
rgroup.long 0x20000++0x07
line.long 0x00 "CPSW_NUSS_VBUSP_CPSW_ID_VER_REG,CPSW ID Version"
hexmask.long.word 0x00 16.--31. 1. "IDENT,Identification Value"
newline
bitfld.long 0x00 11.--15. "RTL_VER,RTL Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor Version Value"
line.long 0x04 "CPSW_NUSS_VBUSP_CONTROL_REG,CPSW Switch Control"
bitfld.long 0x04 31. "ECC_CRC_MODE,ECC CRC Mode" "0,1"
newline
bitfld.long 0x04 19. "CUT_THRU_ENABLE,Cut-Thru enable" "0,1"
newline
bitfld.long 0x04 18. "EST_ENABLE,Intersperced Express Traffic enable" "0,1"
newline
bitfld.long 0x04 17. "IET_ENABLE,Intersperced Express Traffic enable" "0,1"
newline
bitfld.long 0x04 16. "EEE_ENABLE,Energy Efficient Ethernet enable" "0,1"
newline
bitfld.long 0x04 15. "P0_RX_PASS_CRC_ERR,Port 0 Pass Received CRC errors" "0,1"
newline
bitfld.long 0x04 14. "P0_RX_PAD,Port 0 Receive Short Packet Pad" "0,1"
newline
bitfld.long 0x04 13. "P0_TX_CRC_REMOVE,Port 0 Transmit CRC remove" "0,1"
newline
bitfld.long 0x04 12. "P0_TX_CRC_TYPE,Port 0 Transmit CRC Type" "0,1"
newline
bitfld.long 0x04 11. "P8_PASS_PRI_TAGGED,Port 8 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 10. "P7_PASS_PRI_TAGGED,Port 7 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 9. "P6_PASS_PRI_TAGGED,Port 6 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 8. "P5_PASS_PRI_TAGGED,Port 5 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 7. "P4_PASS_PRI_TAGGED,Port 4 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 6. "P3_PASS_PRI_TAGGED,Port 3 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 5. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 4. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 3. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 2. "P0_ENABLE,Port 0 Enable" "0,1"
newline
bitfld.long 0x04 1. "VLAN_AWARE,VLAN Aware Mode" "0,1"
newline
bitfld.long 0x04 0. "S_CN_SWITCH,VLAN Aware Mode" "0,1"
group.long 0x20010++0x17
line.long 0x00 "CPSW_NUSS_VBUSP_EM_CONTROL_REG,CPSW Emulation Control"
bitfld.long 0x00 1. "SOFT,Emulation Soft Bit" "0,1"
newline
bitfld.long 0x00 0. "FREE,Emulation Free Bit" "0,1"
line.long 0x04 "CPSW_NUSS_VBUSP_STAT_PORT_EN_REG,CPSW Statistics Port Enable"
bitfld.long 0x04 8. "P8_STAT_EN,Port 8 Statistics Enable" "0,1"
newline
bitfld.long 0x04 7. "P7_STAT_EN,Port 7 Statistics Enable" "0,1"
newline
bitfld.long 0x04 6. "P6_STAT_EN,Port 6 Statistics Enable" "0,1"
newline
bitfld.long 0x04 5. "P5_STAT_EN,Port 5 Statistics Enable" "0,1"
newline
bitfld.long 0x04 4. "P4_STAT_EN,Port 4 Statistics Enable" "0,1"
newline
bitfld.long 0x04 3. "P3_STAT_EN,Port 3 Statistics Enable" "0,1"
newline
bitfld.long 0x04 2. "P2_STAT_EN,Port 2 Statistics Enable" "0,1"
newline
bitfld.long 0x04 1. "P1_STAT_EN,Port 1 Statistics Enable" "0,1"
newline
bitfld.long 0x04 0. "P0_STAT_EN,Port 0 Statistics Enable" "0,1"
line.long 0x08 "CPSW_NUSS_VBUSP_PTYPE_REG,CPSW Transmit Priority Type"
bitfld.long 0x08 16. "P8_PTYPE_ESC,Port 8 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 15. "P7_PTYPE_ESC,Port 7 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 14. "P6_PTYPE_ESC,Port 6 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 13. "P5_PTYPE_ESC,Port 5 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 12. "P4_PTYPE_ESC,Port 4 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 11. "P3_PTYPE_ESC,Port 3 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 0.--4. "ESC_PRI_LD_VAL,Escalate Priority Load Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "CPSW_NUSS_VBUSP_SOFT_IDLE_REG,CPSW Software Idle"
bitfld.long 0x0C 0. "SOFT_IDLE,Software Idle" "0,1"
line.long 0x10 "CPSW_NUSS_VBUSP_THRU_RATE_REG,CPSW Thru Rate"
bitfld.long 0x10 12.--15. "SL_RX_THRU_RATE,Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 0.--3. "P0_RX_THRU_RATE,CPPI FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "CPSW_NUSS_VBUSP_GAP_THRESH_REG,CPSW Transmit FIFO Short Gap Threshold"
bitfld.long 0x14 0.--4. "GAP_THRESH,Short Gap Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2002C++0x1B
line.long 0x00 "CPSW_NUSS_VBUSP_EEE_PRESCALE_REG,CPSW Energy Efficient Ethernet Prescale Value"
hexmask.long.word 0x00 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value"
line.long 0x04 "CPSW_NUSS_VBUSP_TX_G_OFLOW_THRESH_SET_REG,CPSW PFC Tx Global Out Flow Threshold Set"
bitfld.long 0x04 28.--31. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 24.--27. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 20.--23. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 12.--15. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8.--11. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 4.--7. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--3. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CPSW_NUSS_VBUSP_TX_G_OFLOW_THRESH_CLR_REG,CPSW PFC Tx Global Out Flow Threshold Clear"
bitfld.long 0x08 28.--31. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 24.--27. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 20.--23. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 16.--19. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 12.--15. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 8.--11. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 4.--7. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0.--3. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_SET_L_REG,CPSW PFC Global Tx Buffer Threshold Set Low"
hexmask.long.byte 0x0C 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
newline
hexmask.long.byte 0x0C 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
newline
hexmask.long.byte 0x0C 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
newline
hexmask.long.byte 0x0C 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
line.long 0x10 "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_SET_H_REG,CPSW PFC Global Tx Buffer Threshold Set High"
hexmask.long.byte 0x10 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
newline
hexmask.long.byte 0x10 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
newline
hexmask.long.byte 0x10 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
newline
hexmask.long.byte 0x10 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
line.long 0x14 "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_CLR_L_REG,CPSW PFC Global Tx Buffer Threshold Clear Low"
hexmask.long.byte 0x14 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
newline
hexmask.long.byte 0x14 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
newline
hexmask.long.byte 0x14 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
newline
hexmask.long.byte 0x14 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
line.long 0x18 "CPSW_NUSS_VBUSP_TX_G_BUF_THRESH_CLR_H_REG,CPSW PFC Global Tx Buffer Threshold Clear High"
hexmask.long.byte 0x18 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
newline
hexmask.long.byte 0x18 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
newline
hexmask.long.byte 0x18 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
newline
hexmask.long.byte 0x18 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
group.long 0x20050++0x13
line.long 0x00 "CPSW_NUSS_VBUSP_VLAN_LTYPE_REG,VLAN Length/type"
hexmask.long.word 0x00 16.--31. 1. "VLAN_LTYPE_OUTER,Outer VLAN LType"
newline
hexmask.long.word 0x00 0.--15. 1. "VLAN_LTYPE_INNER,Inner VLAN LType"
line.long 0x04 "CPSW_NUSS_VBUSP_EST_TS_DOMAIN_REG,Enhanced Scheduled Traffic Host Event Domain"
hexmask.long.byte 0x04 0.--7. 1. "EST_TS_DOMAIN,Enhanced Scheduled Traffic Host Event Domain"
line.long 0x08 "CPSW_NUSS_VBUSP_CUT_THRESHOLD_REG,Cut-thru Threshold"
bitfld.long 0x08 0.--3. "CUT_THRESH,Cut-thru Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CPSW_NUSS_VBUSP_FREQUENCY_REG,CPSW CPPI_CLK Frequency in Mhz"
hexmask.long.word 0x0C 0.--9. 1. "CUT_THRESH,CPSW CPPI_CLK Frequency in Mhz"
line.long 0x10 "CPSW_NUSS_VBUSP_IET_HOLD_CNT_LD_VAL_REG,IET Hold Count Load Value for cut thru packets"
hexmask.long.byte 0x10 0.--7. 1. "IET_HOLD_CNT_LD_VAL,IET_HOLD_CNT_LD_VAL"
group.long 0x20100++0x1F
line.long 0x00 "CPSW_NUSS_VBUSP_TX_PRI0_MAXLEN_REG,Transmit Priority 0 Maximum Length"
hexmask.long.word 0x00 0.--13. 1. "TX_PRI0_MAXLEN,Transmit Priority 0 Maximum Length"
line.long 0x04 "CPSW_NUSS_VBUSP_TX_PRI1_MAXLEN_REG,Transmit Priority 1 Maximum Length"
hexmask.long.word 0x04 0.--13. 1. "TX_PRI1_MAXLEN,Transmit Priority 1 Maximum Length"
line.long 0x08 "CPSW_NUSS_VBUSP_TX_PRI2_MAXLEN_REG,Transmit Priority 2 Maximum Length"
hexmask.long.word 0x08 0.--13. 1. "TX_PRI2_MAXLEN,Transmit Priority 2 Maximum Length"
line.long 0x0C "CPSW_NUSS_VBUSP_TX_PRI3_MAXLEN_REG,Transmit Priority 3 Maximum Length"
hexmask.long.word 0x0C 0.--13. 1. "TX_PRI3_MAXLEN,Transmit Priority 3 Maximum Length"
line.long 0x10 "CPSW_NUSS_VBUSP_TX_PRI4_MAXLEN_REG,Transmit Priority 4 Maximum Length"
hexmask.long.word 0x10 0.--13. 1. "TX_PRI4_MAXLEN,Transmit Priority 4 Maximum Length"
line.long 0x14 "CPSW_NUSS_VBUSP_TX_PRI5_MAXLEN_REG,Transmit Priority 5 Maximum Length"
hexmask.long.word 0x14 0.--13. 1. "TX_PRI5_MAXLEN,Transmit Priority 5 Maximum Length"
line.long 0x18 "CPSW_NUSS_VBUSP_TX_PRI6_MAXLEN_REG,Transmit Priority 6 Maximum Length"
hexmask.long.word 0x18 0.--13. 1. "TX_PRI6_MAXLEN,Transmit Priority 6 Maximum Length"
line.long 0x1C "CPSW_NUSS_VBUSP_TX_PRI7_MAXLEN_REG,Transmit Priority 7 Maximum Length"
hexmask.long.word 0x1C 0.--13. 1. "TX_PRI7_MAXLEN,Transmit Priority 7 Maximum Length"
tree.end
tree "csi_rx_if0_CP_INTD_CFG_INTD_CFG"
base ad:0x30100000
rgroup.long 0x00++0x03
line.long 0x00 "CP_INTD__INTD_CFG__INTD_CFG_REVISION,Revision Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module ID"
bitfld.long 0x00 11.--15. "RTLVER,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJREV,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINREV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x07
line.long 0x00 "CP_INTD__INTD_CFG__INTD_CFG_eoi_reg,End of Interrupt Register"
hexmask.long.byte 0x00 0.--7. 1. "EOI_VECTOR,End of Interrupt Vector"
line.long 0x04 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg,Interrupt Vector Register"
group.long 0x100++0x07
line.long 0x00 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_level_0,Enable Register 0"
bitfld.long 0x00 4. "ENABLE_LEVEL_EN_INT_VP1_ERROVERFLOW,Enable Set for level_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x00 3. "ENABLE_LEVEL_EN_INT_VP1_ERRINLNFRM,Enable Set for level_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_LEVEL_EN_INT_VP0_ERROVERFLOW,Enable Set for level_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x00 1. "ENABLE_LEVEL_EN_INT_VP0_ERRINLNFRM,Enable Set for level_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_LEVEL_EN_FIFO_OVERFLOW,Enable Set for level_en_fifo_overflow" "0,1"
line.long 0x04 "CP_INTD__INTD_CFG__INTD_CFG_enable_reg_pulse_0,Enable Register 1"
bitfld.long 0x04 4. "ENABLE_PULSE_EN_INT_VP1_ERROVERFLOW,Enable Set for pulse_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x04 3. "ENABLE_PULSE_EN_INT_VP1_ERRINLNFRM,Enable Set for pulse_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_PULSE_EN_INT_VP0_ERROVERFLOW,Enable Set for pulse_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x04 1. "ENABLE_PULSE_EN_INT_VP0_ERRINLNFRM,Enable Set for pulse_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_PULSE_EN_FIFO_OVERFLOW,Enable Set for pulse_en_fifo_overflow" "0,1"
group.long 0x300++0x07
line.long 0x00 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_level_0,Enable Clear Register 0"
bitfld.long 0x00 4. "ENABLE_LEVEL_EN_INT_VP1_ERROVERFLOW_CLR,Enable Clear for level_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x00 3. "ENABLE_LEVEL_EN_INT_VP1_ERRINLNFRM_CLR,Enable Clear for level_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x00 2. "ENABLE_LEVEL_EN_INT_VP0_ERROVERFLOW_CLR,Enable Clear for level_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x00 1. "ENABLE_LEVEL_EN_INT_VP0_ERRINLNFRM_CLR,Enable Clear for level_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_LEVEL_EN_FIFO_OVERFLOW_CLR,Enable Clear for level_en_fifo_overflow" "0,1"
line.long 0x04 "CP_INTD__INTD_CFG__INTD_CFG_enable_clr_reg_pulse_0,Enable Clear Register 1"
bitfld.long 0x04 4. "ENABLE_PULSE_EN_INT_VP1_ERROVERFLOW_CLR,Enable Clear for pulse_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x04 3. "ENABLE_PULSE_EN_INT_VP1_ERRINLNFRM_CLR,Enable Clear for pulse_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x04 2. "ENABLE_PULSE_EN_INT_VP0_ERROVERFLOW_CLR,Enable Clear for pulse_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x04 1. "ENABLE_PULSE_EN_INT_VP0_ERRINLNFRM_CLR,Enable Clear for pulse_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x04 0. "ENABLE_PULSE_EN_FIFO_OVERFLOW_CLR,Enable Clear for pulse_en_fifo_overflow" "0,1"
group.long 0x500++0x07
line.long 0x00 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_level_0,Status Register 0"
bitfld.long 0x00 4. "STATUS_LEVEL_INT_VP1_ERROVERFLOW,Status write 1 to set for level_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x00 3. "STATUS_LEVEL_INT_VP1_ERRINLNFRM,Status write 1 to set for level_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x00 2. "STATUS_LEVEL_INT_VP0_ERROVERFLOW,Status write 1 to set for level_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x00 1. "STATUS_LEVEL_INT_VP0_ERRINLNFRM,Status write 1 to set for level_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x00 0. "STATUS_LEVEL_FIFO_OVERFLOW,Status write 1 to set for level_en_fifo_overflow" "0,1"
line.long 0x04 "CP_INTD__INTD_CFG__INTD_CFG_status_reg_pulse_0,Status Register 1"
bitfld.long 0x04 4. "STATUS_PULSE_INT_VP1_ERROVERFLOW,Status write 1 to set for pulse_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x04 3. "STATUS_PULSE_INT_VP1_ERRINLNFRM,Status write 1 to set for pulse_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x04 2. "STATUS_PULSE_INT_VP0_ERROVERFLOW,Status write 1 to set for pulse_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x04 1. "STATUS_PULSE_INT_VP0_ERRINLNFRM,Status write 1 to set for pulse_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x04 0. "STATUS_PULSE_FIFO_OVERFLOW,Status write 1 to set for pulse_en_fifo_overflow" "0,1"
group.long 0x700++0x07
line.long 0x00 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_level_0,Status Clear Register 0"
bitfld.long 0x00 4. "STATUS_LEVEL_INT_VP1_ERROVERFLOW_CLR,Status write 1 to clear for level_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x00 3. "STATUS_LEVEL_INT_VP1_ERRINLNFRM_CLR,Status write 1 to clear for level_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x00 2. "STATUS_LEVEL_INT_VP0_ERROVERFLOW_CLR,Status write 1 to clear for level_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x00 1. "STATUS_LEVEL_INT_VP0_ERRINLNFRM_CLR,Status write 1 to clear for level_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x00 0. "STATUS_LEVEL_FIFO_OVERFLOW_CLR,Status write 1 to clear for level_en_fifo_overflow" "0,1"
line.long 0x04 "CP_INTD__INTD_CFG__INTD_CFG_status_clr_reg_pulse_0,Status Clear Register 1"
bitfld.long 0x04 4. "STATUS_PULSE_INT_VP1_ERROVERFLOW_CLR,Status write 1 to clear for pulse_en_int_vp1_erroverflow" "0,1"
bitfld.long 0x04 3. "STATUS_PULSE_INT_VP1_ERRINLNFRM_CLR,Status write 1 to clear for pulse_en_int_vp1_errInLnFrm" "0,1"
newline
bitfld.long 0x04 2. "STATUS_PULSE_INT_VP0_ERROVERFLOW_CLR,Status write 1 to clear for pulse_en_int_vp0_erroverflow" "0,1"
bitfld.long 0x04 1. "STATUS_PULSE_INT_VP0_ERRINLNFRM_CLR,Status write 1 to clear for pulse_en_int_vp0_errInLnFrm" "0,1"
newline
bitfld.long 0x04 0. "STATUS_PULSE_FIFO_OVERFLOW_CLR,Status write 1 to clear for pulse_en_fifo_overflow" "0,1"
rgroup.long 0xA80++0x07
line.long 0x00 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_level,Interrupt Vector for level"
line.long 0x04 "CP_INTD__INTD_CFG__INTD_CFG_intr_vector_reg_pulse,Interrupt Vector for pulse"
tree.end
tree "csi_rx_if0_ECC_AGGR_CFG"
base ad:0x70E000
rgroup.long 0x00++0x03
line.long 0x00 "ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ECC_AGGR__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 7. "VP1_FIFO_RAMECC_PEND,Interrupt Pending Status for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 6. "VP0_FIFO_RAMECC_PEND,Interrupt Pending Status for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 5. "RAM_RAMECC3_PEND,Interrupt Pending Status for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x04 4. "RAM_RAMECC2_PEND,Interrupt Pending Status for ram_ramecc2_pend" "0,1"
bitfld.long 0x04 3. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1"
bitfld.long 0x04 2. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x04 1. "PSIL_FIFO_RAMECC_PEND,Interrupt Pending Status for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 7. "VP1_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 6. "VP0_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 5. "RAM_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x00 4. "RAM_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 3. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 1. "PSIL_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 7. "VP1_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 6. "VP0_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 5. "RAM_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x00 4. "RAM_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 3. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 1. "PSIL_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 7. "VP1_FIFO_RAMECC_PEND,Interrupt Pending Status for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 6. "VP0_FIFO_RAMECC_PEND,Interrupt Pending Status for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 5. "RAM_RAMECC3_PEND,Interrupt Pending Status for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x04 4. "RAM_RAMECC2_PEND,Interrupt Pending Status for ram_ramecc2_pend" "0,1"
bitfld.long 0x04 3. "RAM_RAMECC1_PEND,Interrupt Pending Status for ram_ramecc1_pend" "0,1"
bitfld.long 0x04 2. "RAM_RAMECC0_PEND,Interrupt Pending Status for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x04 1. "PSIL_FIFO_RAMECC_PEND,Interrupt Pending Status for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x04 0. "BUSECC_PEND,Interrupt Pending Status for busecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 7. "VP1_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 6. "VP0_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 5. "RAM_RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x00 4. "RAM_RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 3. "RAM_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc1_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 1. "PSIL_FIFO_RAMECC_ENABLE_SET,Interrupt Enable Set Register for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_SET,Interrupt Enable Set Register for busecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 7. "VP1_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp1_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 6. "VP0_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for vp0_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 5. "RAM_RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc3_pend" "0,1"
newline
bitfld.long 0x00 4. "RAM_RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc2_pend" "0,1"
bitfld.long 0x00 3. "RAM_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc1_pend" "0,1"
bitfld.long 0x00 2. "RAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ram_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 1. "PSIL_FIFO_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for psil_fifo_ramecc_pend" "0,1"
bitfld.long 0x00 0. "BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for busecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "csi_rx_if0_RX_SHIM_VBUSP_MMR_CSI2RXIF"
base ad:0x30102000
rgroup.long 0x00++0x03
line.long 0x00 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_csirx_id,nothing"
bitfld.long 0x00 30.--31. "SCHEME,scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,function"
bitfld.long 0x00 11.--15. "RTLVER,rtl version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,custom revision" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINREV,min revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_vp0,Video Port 0 configuration"
bitfld.long 0x00 31. "EN_CFG,Video Port enable" "0,1"
hexmask.long.word 0x00 16.--28. 1. "IH_CFG,(U13) input height in units of lines"
hexmask.long.word 0x00 0.--12. 1. "IW_CFG,(U13) input width in units of RAW data samples"
line.long 0x04 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_vp1,Video Port 1 configuration"
bitfld.long 0x04 31. "EN_CFG,Video Port enable" "0,1"
hexmask.long.word 0x04 16.--28. 1. "IH_CFG,(U13) input height in units of lines"
hexmask.long.word 0x04 0.--12. 1. "IW_CFG,(U13) input width in units of RAW data samples"
line.long 0x08 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_cntl,control register for csi rx wrapper"
rbitfld.long 0x08 11. "STREAM3_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
rbitfld.long 0x08 10. "STREAM2_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
rbitfld.long 0x08 9. "STREAM1_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
rbitfld.long 0x08 8. "STREAM0_IDLE,indicates if stream interface is idle(1) or not(0)" "0,1"
bitfld.long 0x08 0. "PIXEL_RESET,reset for the pixeal interface" "0,1"
group.long 0x20++0x0B
line.long 0x00 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_dmaCntx,DMA Channel Context"
bitfld.long 0x00 31. "EN_CFG,DMA context is enabled" "0,1"
bitfld.long 0x00 29. "RSV0,reserved" "0,1"
bitfld.long 0x00 26.--27. "YUV422_MODE_CFG,yuv422 mode" "UYVY,VYUY,YUYV,YVYU"
bitfld.long 0x00 24. "DUAL_PCK_CFG,dual packed format extraction for 8 bits or less" "0,1"
bitfld.long 0x00 20.--21. "SIZE_CFG,data size shift when unpacking " "0,1,2,3"
newline
bitfld.long 0x00 18. "PCK12_CFG,12-bit packing enable" "0,1"
bitfld.long 0x00 6.--9. "VIRTCH_CFG,CSI virtual channel index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "DATTYP_CFG,CSI data type index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_psi_cfg0,psi configuration register0"
hexmask.long.word 0x04 16.--31. 1. "DST_TAG,psi dst tag"
hexmask.long.word 0x04 0.--15. 1. "SRC_TAG,psi source tag"
line.long 0x08 "RX_SHIM__VBUSP_MMR__CSI2RXIF_REGS_psi_cfg1,psi configuration register1"
bitfld.long 0x08 8.--11. "PS_FLAGS,ps flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--4. "PKT_TYPE,psi packet type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "csi_rx_if0_VBUS2APB_WRAP_VBUSP_APB_CSI2RX"
base ad:0x30101000
rgroup.long 0x00++0x0B
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_device_config,This register provides information related to the current configuration. This should be read by FW to determine the number of streams available and other associated parameters that will influence how.."
bitfld.long 0x00 31. "STREAM3_MONITOR_PRESENT,Pixel stream 3 Monitor present" "0,1"
newline
bitfld.long 0x00 29.--30. "STREAM3_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle" "0,1,2,3"
newline
bitfld.long 0x00 27.--28. "STREAM3_FIFO_MODE,Stream 3 FIFO Mode" "0,1,2,3"
newline
bitfld.long 0x00 26. "STREAM2_MONITOR_PRESENT,Pixel stream 2 Monitor present" "0,1"
newline
bitfld.long 0x00 24.--25. "STREAM2_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle" "0,1,2,3"
newline
bitfld.long 0x00 22.--23. "STREAM2_FIFO_MODE,Stream 2 FIFO Mode" "0,1,2,3"
newline
bitfld.long 0x00 21. "STREAM1_MONITOR_PRESENT,Pixel stream 1 Monitor present" "0,1"
newline
bitfld.long 0x00 19.--20. "STREAM1_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle" "0,1,2,3"
newline
bitfld.long 0x00 17.--18. "STREAM1_FIFO_MODE,Stream 1 FIFO Mode" "0,1,2,3"
newline
bitfld.long 0x00 16. "STREAM0_MONITOR_PRESENT,Pixel stream 0 Monitor present" "0,1"
newline
bitfld.long 0x00 14.--15. "STREAM0_NUM_PIXELS,The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle" "0,1,2,3"
newline
bitfld.long 0x00 12.--13. "STREAM0_FIFO_MODE,Stream 0 FIFO Mode" "0,1,2,3"
newline
bitfld.long 0x00 10. "ASF_CONFIG,Additional Safety Features [ASF] Configuration" "None,Full ASF"
newline
bitfld.long 0x00 9. "VCX_CONFIG,Extended Virtual Channel [VCX] Configuration" "4 VCs,16 VCs"
newline
bitfld.long 0x00 7.--8. "DATAPATH_SIZE,Internal Datapath width" "0,1,2,3"
newline
bitfld.long 0x00 4.--6. "NUM_STREAMS,Number of Stream interfaces [1-4]" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "CDNS_PHY_PRESENT,Cadence DPDHY present" "0,1"
newline
bitfld.long 0x00 0.--2. "MAX_LANE_NB,Max Number of Lanes [1-4]" "0,1,2,3,4,5,6,7"
line.long 0x04 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_soft_reset,CSI2 Slave Controller Individual Soft Reset for Front and Protocol blocks. Writing to these registers will cause a single cycle pulse to be applied to the soft reset signals. Soft reset must only be.."
bitfld.long 0x04 1. "PROTOCOL,writing 1'b1 will apply a synchronous soft reset to the protocol module" "0,1"
newline
bitfld.long 0x04 0. "FRONT,writing 1'b1 will apply a synchronous soft reset to the Front module" "0,1"
line.long 0x08 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_static_cfg,Configuration register to set the physical/logical DPHY lane mapping. the number of lanes being used. external DPHY selection and ECC support for CSI2RX v2.0. This register should be set prior to enabling.."
bitfld.long 0x08 28.--30. "DL3_MAP,physical mapping of logical data lane 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 24.--26. "DL2_MAP,physical mapping of logical data lane 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 20.--22. "DL1_MAP,physical mapping of logical data lane 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 16.--18. "DL0_MAP,physical mapping of logical data lane 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 8.--10. "LANE_NB,The number of lanes" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 4. "V2P0_SUPPORT_ENABLE,Support extended VC up to 16 virtual channels [4-bits] and RAW16/20" "0,1"
newline
bitfld.long 0x08 0.--1. "SEL,selection of DPHY used as input of CSI2RX module" "0,1,2,3"
group.long 0x10++0x03
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_bypass_cfg,Error detection event flag configuration. This allows various error conditions to be masked that would normally prevent data being applied to the pixel interface. This applies to ALL streams that.."
bitfld.long 0x00 2. "DATA_ID,Enables Data ID error bypass for stream outputs" "0,1"
newline
bitfld.long 0x00 1. "ECC,Enables ECC error bypass for stream outputs" "0,1"
newline
bitfld.long 0x00 0. "CRC,Enables CRC error bypass for stream outputs" "0,1"
group.long 0x18++0x17
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_monitor_irqs,Information type Interrupt status (non-error conditions)"
bitfld.long 0x00 31. "STREAM3_LINE_CNT_ERROR_IRQ,Stream 3 Line count error interrupt" "0,1"
newline
bitfld.long 0x00 30. "STREAM3_FRAME_MISMATCH_IRQ,Stream 3 Frame mismatch error interrupt" "0,1"
newline
bitfld.long 0x00 29. "STREAM3_FRAME_CNT_ERROR_IRQ,Stream 3 Frame count error interrupt" "0,1"
newline
bitfld.long 0x00 28. "STREAM3_FCC_STOP_IRQ,Stream 3 FCC stop interrupt" "0,1"
newline
bitfld.long 0x00 27. "STREAM3_FCC_START_IRQ,Stream 3 FCC start interrupt" "0,1"
newline
bitfld.long 0x00 26. "STREAM3_FRAME_IRQ,Stream 3 Frame interrupt" "0,1"
newline
bitfld.long 0x00 25. "STREAM3_LB_IRQ,Stream 3 Line/byte interrupt" "0,1"
newline
bitfld.long 0x00 24. "STREAM3_TIMER_IRQ,Stream 3 Timer interrupt" "0,1"
newline
bitfld.long 0x00 23. "STREAM2_LINE_CNT_ERROR_IRQ,Stream 2 Line count error interrupt" "0,1"
newline
bitfld.long 0x00 22. "STREAM2_FRAME_MISMATCH_IRQ,Stream 2 Frame mismatch error interrupt" "0,1"
newline
bitfld.long 0x00 21. "STREAM2_FRAME_CNT_ERROR_IRQ,Stream 2 Frame count error interrupt" "0,1"
newline
bitfld.long 0x00 20. "STREAM2_FCC_STOP_IRQ,Stream 2 FCC stop interrupt" "0,1"
newline
bitfld.long 0x00 19. "STREAM2_FCC_START_IRQ,Stream 2 FCC start interrupt" "0,1"
newline
bitfld.long 0x00 18. "STREAM2_FRAME_IRQ,Stream 2 Frame interrupt" "0,1"
newline
bitfld.long 0x00 17. "STREAM2_LB_IRQ,Stream 2 Line/byte interrupt" "0,1"
newline
bitfld.long 0x00 16. "STREAM2_TIMER_IRQ,Stream 2 Timer interrupt" "0,1"
newline
bitfld.long 0x00 15. "STREAM1_LINE_CNT_ERROR_IRQ,Stream 1 Line count error interrupt" "0,1"
newline
bitfld.long 0x00 14. "STREAM1_FRAME_MISMATCH_IRQ,Stream 1 Frame mismatch error interrupt" "0,1"
newline
bitfld.long 0x00 13. "STREAM1_FRAME_CNT_ERROR_IRQ,Stream 1 Frame count error interrupt" "0,1"
newline
bitfld.long 0x00 12. "STREAM1_FCC_STOP_IRQ,Stream 1 FCC stop interrupt" "0,1"
newline
bitfld.long 0x00 11. "STREAM1_FCC_START_IRQ,Stream 1 FCC start interrupt" "0,1"
newline
bitfld.long 0x00 10. "STREAM1_FRAME_IRQ,Stream 1 Frame interrupt" "0,1"
newline
bitfld.long 0x00 9. "STREAM1_LB_IRQ,Stream 1 Line/byte interrupt" "0,1"
newline
bitfld.long 0x00 8. "STREAM1_TIMER_IRQ,Stream 1 Timer interrupt" "0,1"
newline
bitfld.long 0x00 7. "STREAM0_LINE_CNT_ERROR_IRQ,Stream 0 Line count error interrupt" "0,1"
newline
bitfld.long 0x00 6. "STREAM0_FRAME_MISMATCH_IRQ,Stream 0 Frame mismatch error interrupt" "0,1"
newline
bitfld.long 0x00 5. "STREAM0_FRAME_CNT_ERROR_IRQ,Stream 0 Frame count error interrupt" "0,1"
newline
bitfld.long 0x00 4. "STREAM0_FCC_STOP_IRQ,Stream 0 FCC stop interrupt" "0,1"
newline
bitfld.long 0x00 3. "STREAM0_FCC_START_IRQ,Stream 0 FCC start interrupt" "0,1"
newline
bitfld.long 0x00 2. "STREAM0_FRAME_IRQ,Stream 0 Frame interrupt" "0,1"
newline
bitfld.long 0x00 1. "STREAM0_LB_IRQ,Stream 0 Line/byte interrupt" "0,1"
newline
bitfld.long 0x00 0. "STREAM0_TIMER_IRQ,Stream 0 Timer interrupt" "0,1"
line.long 0x04 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_monitor_irqs_mask_cfg,Monitor interrupt mask"
bitfld.long 0x04 31. "STREAM3_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 3 Line count error" "0,1"
newline
bitfld.long 0x04 30. "STREAM3_FRAME_MISMATCH_IRQM,Interrupt mask for stream 3 Frame mismatch error" "0,1"
newline
bitfld.long 0x04 29. "STREAM3_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 3 Frame count error" "0,1"
newline
bitfld.long 0x04 28. "STREAM3_FCC_STOP_IRQM,Interrupt mask for stream 3 FCC stop" "0,1"
newline
bitfld.long 0x04 27. "STREAM3_FCC_START_IRQM,Interrupt mask for stream 3 FCC start" "0,1"
newline
bitfld.long 0x04 26. "STREAM3_FRAME_IRQM,Interrupt mask for stream 3 Frame" "0,1"
newline
bitfld.long 0x04 25. "STREAM3_LB_IRQM,Interrupt mask for stream 3 Line/byte" "0,1"
newline
bitfld.long 0x04 24. "STREAM3_TIMER_IRQM,Interrupt mask stream 3 Timer" "0,1"
newline
bitfld.long 0x04 23. "STREAM2_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 2 Line count error" "0,1"
newline
bitfld.long 0x04 22. "STREAM2_FRAME_MISMATCH_IRQM,Interrupt mask for stream 2 Frame mismatch error" "0,1"
newline
bitfld.long 0x04 21. "STREAM2_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 2 Frame count error" "0,1"
newline
bitfld.long 0x04 20. "STREAM2_FCC_STOP_IRQM,Interrupt mask for stream 2 FCC stop" "0,1"
newline
bitfld.long 0x04 19. "STREAM2_FCC_START_IRQM,Interrupt mask for stream 2 FCC start" "0,1"
newline
bitfld.long 0x04 18. "STREAM2_FRAME_IRQM,Interrupt mask for stream 2 Frame" "0,1"
newline
bitfld.long 0x04 17. "STREAM2_LB_IRQM,Interrupt mask for stream 2 Line/byte" "0,1"
newline
bitfld.long 0x04 16. "STREAM2_TIMER_IRQM,Interrupt mask stream 2 Timer" "0,1"
newline
bitfld.long 0x04 15. "STREAM1_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 1 Line count error" "0,1"
newline
bitfld.long 0x04 14. "STREAM1_FRAME_MISMATCH_IRQM,Interrupt mask for stream 1 Frame mismatch error" "0,1"
newline
bitfld.long 0x04 13. "STREAM1_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 1 Frame count error" "0,1"
newline
bitfld.long 0x04 12. "STREAM1_FCC_STOP_IRQM,Interrupt mask for stream 1 FCC stop" "0,1"
newline
bitfld.long 0x04 11. "STREAM1_FCC_START_IRQM,Interrupt mask for stream 1 FCC start" "0,1"
newline
bitfld.long 0x04 10. "STREAM1_FRAME_IRQM,Interrupt mask for stream 1 Frame" "0,1"
newline
bitfld.long 0x04 9. "STREAM1_LB_IRQM,Interrupt mask for stream 1 Line/byte" "0,1"
newline
bitfld.long 0x04 8. "STREAM1_TIMER_IRQM,Interrupt mask stream 1 Timer" "0,1"
newline
bitfld.long 0x04 7. "STREAM0_LINE_CNT_ERROR_IRQM,Interrupt mask for stream 0 Line count error" "0,1"
newline
bitfld.long 0x04 6. "STREAM0_FRAME_MISMATCH_IRQM,Interrupt mask for stream 0 Frame mismatch error" "0,1"
newline
bitfld.long 0x04 5. "STREAM0_FRAME_CNT_ERROR_IRQM,Interrupt mask for stream 0 Frame count error" "0,1"
newline
bitfld.long 0x04 4. "STREAM0_FCC_STOP_IRQM,Interrupt mask for stream 0 FCC stop" "0,1"
newline
bitfld.long 0x04 3. "STREAM0_FCC_START_IRQM,Interrupt mask for stream 0 FCC start" "0,1"
newline
bitfld.long 0x04 2. "STREAM0_FRAME_IRQM,Interrupt mask for stream 0 Frame" "0,1"
newline
bitfld.long 0x04 1. "STREAM0_LB_IRQM,Interrupt mask for stream 0 Line/byte" "0,1"
newline
bitfld.long 0x04 0. "STREAM0_TIMER_IRQM,Interrupt mask stream 0 Timer" "0,1"
line.long 0x08 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_info_irqs,Information type Interrupt status (non-error conditions)"
bitfld.long 0x08 14. "STREAM3_ABORT_IRQ,Stream 3 Abort process complete" "0,1"
newline
bitfld.long 0x08 13. "STREAM3_STOP_IRQ,Stream 3 Stop process complete" "0,1"
newline
bitfld.long 0x08 12. "STREAM2_ABORT_IRQ,Stream 2 Abort process complete" "0,1"
newline
bitfld.long 0x08 11. "STREAM2_STOP_IRQ,Stream 2 Stop process complete" "0,1"
newline
bitfld.long 0x08 10. "STREAM1_ABORT_IRQ,Stream 1 Abort process complete" "0,1"
newline
bitfld.long 0x08 9. "STREAM1_STOP_IRQ,Stream 1 Stop process complete" "0,1"
newline
bitfld.long 0x08 8. "STREAM0_ABORT_IRQ,Stream 0 Abort process complete" "0,1"
newline
bitfld.long 0x08 7. "STREAM0_STOP_IRQ,Stream 0 Stop process complete" "0,1"
newline
bitfld.long 0x08 6. "SP_GENERIC_RCVD_IRQ,A generic short packet has been received" "0,1"
newline
bitfld.long 0x08 5. "DESKEW_ENTRY_IRQ,Either clock or any datalane has entered deskew" "0,1"
newline
bitfld.long 0x08 4. "ECC_SPARES_NONZERO_IRQ,Bits 7:6 of the ECC byte are non-zero" "0,1"
newline
bitfld.long 0x08 3. "WAKEUP_IRQ,Wake-up interrupt" "0,1"
newline
bitfld.long 0x08 2. "SLEEP_IRQ,Sleep interrupt" "0,1"
newline
bitfld.long 0x08 1. "LP_RCVD_IRQ,Long Packet received by the protocol module" "0,1"
newline
bitfld.long 0x08 0. "SP_RCVD_IRQ,Short Packet received by the protocol module" "0,1"
line.long 0x0C "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_info_irqs_mask_cfg,Information interrupt mask"
bitfld.long 0x0C 14. "STREAM3_ABORT_IRQM,Interrupt mask for stream 3 Abort process" "0,1"
newline
bitfld.long 0x0C 13. "STREAM3_STOP_IRQM,Interrupt mask for Stream 3 Stop process complete" "0,1"
newline
bitfld.long 0x0C 12. "STREAM2_ABORT_IRQM,Interrupt mask for stream 2 Abort process" "0,1"
newline
bitfld.long 0x0C 11. "STREAM2_STOP_IRQM,Interrupt mask for Stream 2 Stop process complete" "0,1"
newline
bitfld.long 0x0C 10. "STREAM1_ABORT_IRQM,Interrupt mask for stream 1 Abort process" "0,1"
newline
bitfld.long 0x0C 9. "STREAM1_STOP_IRQM,Interrupt mask for Stream 1 Stop process complete" "0,1"
newline
bitfld.long 0x0C 8. "STREAM0_ABORT_IRQM,Interrupt mask for stream 0 Abort process" "0,1"
newline
bitfld.long 0x0C 7. "STREAM0_STOP_IRQM,Interrupt mask for Stream 0 Stop process complete" "0,1"
newline
bitfld.long 0x0C 6. "SP_GENERIC_RCVD_IRQM,Interrupt mask for Generic Short Packet received" "0,1"
newline
bitfld.long 0x0C 5. "DESKEW_ENTRY_IRQM,Interrupt mask for Deskew entry check" "0,1"
newline
bitfld.long 0x0C 4. "ECC_SPARES_NONZERO_IRQM,Interrupt mask for ECC spares check" "0,1"
newline
bitfld.long 0x0C 3. "WAKEUP_IRQM,Interrupt mask for Wake-up interrupt" "0,1"
newline
bitfld.long 0x0C 2. "SLEEP_IRQM,Interrupt mask for Sleep interrupt" "0,1"
newline
bitfld.long 0x0C 1. "LP_RCVD_IRQM,Interrupt mask for Long Packet received flag" "0,1"
newline
bitfld.long 0x0C 0. "SP_RCVD_IRQM,Interrupt mask for Short Packet received" "0,1"
line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_irqs,Datapath error interrupt status"
bitfld.long 0x10 19. "STREAM3_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[19] -> Stream 3 overflow" "0,1"
newline
bitfld.long 0x10 18. "STREAM2_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[18] -> Stream 2 overflow" "0,1"
newline
bitfld.long 0x10 17. "STREAM1_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[17] -> Stream 1 overflow" "0,1"
newline
bitfld.long 0x10 16. "STREAM0_FIFO_OVERFLOW_IRQ,Overflow of the Stream FIFO detected: stream_fifo_overflow[16] -> Stream 0 overflow" "0,1"
newline
bitfld.long 0x10 12. "FRONT_TRUNC_HDR_IRQ,A truncated header [short or Long] has been received" "0,1"
newline
bitfld.long 0x10 11. "PROT_TRUNCATED_PACKET_IRQ,A truncated Long packet has been received" "0,1"
newline
bitfld.long 0x10 10. "FRONT_LP_NO_PAYLOAD_IRQ,A truncated Long packet has been received" "0,1"
newline
bitfld.long 0x10 9. "SP_INVALID_RCVD_IRQ,A reserved or invalid short packet has been received" "0,1"
newline
bitfld.long 0x10 8. "INVALID_ACCESS_IRQ,Invalid access to the configuration register space" "0,1"
newline
bitfld.long 0x10 7. "DATA_ID_IRQ,Data ID error has been detected in the header packet" "0,1"
newline
bitfld.long 0x10 6. "HEADER_CORRECTED_ECC_IRQ,ECC error has been detected and corrected" "0,1"
newline
bitfld.long 0x10 5. "HEADER_ECC_IRQ,Unrecoverable ECC error has been detected" "0,1"
newline
bitfld.long 0x10 4. "PAYLOAD_CRC_IRQ,CRC error has been detected" "0,1"
newline
bitfld.long 0x10 0. "FRONT_FIFO_OVERFLOW_IRQ,Overflow detected in resynchronization FIFO between DPHY Lane Management and Protocol blocks" "0,1"
line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_irqs_mask_cfg,Datapath error interrupt enable Bits"
bitfld.long 0x14 19. "STREAM3_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[19] -> Stream 3 overflow" "0,1"
newline
bitfld.long 0x14 18. "STREAM2_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[18] -> Stream 2 overflow" "0,1"
newline
bitfld.long 0x14 17. "STREAM1_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[17] -> Stream 1 overflow" "0,1"
newline
bitfld.long 0x14 16. "STREAM0_FIFO_OVERFLOW_IRQM,Interrupt enable bit for: stream_fifo_overflow[16] -> Stream 0 overflow" "0,1"
newline
bitfld.long 0x14 12. "FRONT_TRUNC_HDR_IRQM,Interrupt enable bit for truncated hdr" "0,1"
newline
bitfld.long 0x14 11. "PROT_TRUNCATED_PACKET_IRQM,Interrupt enable bit for long packet payload with too many/few bytes" "0,1"
newline
bitfld.long 0x14 10. "FRONT_LP_NO_PAYLOAD_IRQM,Interrupt enable bit for long packet header received with no payload" "0,1"
newline
bitfld.long 0x14 9. "SP_INVALID_RCVD_IRQM,Interrupt enable bit for invalid short packet" "0,1"
newline
bitfld.long 0x14 8. "INVALID_ACCESS_IRQM,Interrupt enable bit for error_irqs_invalid_access" "0,1"
newline
bitfld.long 0x14 7. "DATA_ID_IRQM,Interrupt enable bit for error_irqs_data_id" "0,1"
newline
bitfld.long 0x14 6. "HEADER_CORRECTED_ECC_IRQM,Interrupt enable bit for error_irqs_header_corrected_ecc" "0,1"
newline
bitfld.long 0x14 5. "HEADER_ECC_IRQM,Interrupt enable bit for error_irqs_header_ecc" "0,1"
newline
bitfld.long 0x14 4. "PAYLOAD_CRC_IRQM,Interrupt enable bit for error_irqs_payload_crc" "0,1"
newline
bitfld.long 0x14 0. "FRONT_FIFO_OVERFLOW_IRQM,Interrupt enable bit for error_irqs_front_fifo_overflow" "0,1"
group.long 0x40++0x03
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_lane_control,DPHY lane control for data and clock lanes enables and resets"
bitfld.long 0x00 16. "CL_RESET,DPHY Clock lane Reset" "0,1"
newline
bitfld.long 0x00 15. "DL3_RESET,DPHY data lane 3 Reset" "0,1"
newline
bitfld.long 0x00 14. "DL2_RESET,DPHY data lane 2 Reset" "0,1"
newline
bitfld.long 0x00 13. "DL1_RESET,DPHY data lane 1 Reset" "0,1"
newline
bitfld.long 0x00 12. "DL0_RESET,DPHY data lane 0 Reset" "0,1"
newline
bitfld.long 0x00 4. "CL_ENABLE,DPHY Clock lane Enable" "0,1"
newline
bitfld.long 0x00 3. "DL3_ENABLE,DPHY data lane 3 Enable" "0,1"
newline
bitfld.long 0x00 2. "DL2_ENABLE,DPHY data lane 2 Enable" "0,1"
newline
bitfld.long 0x00 1. "DL1_ENABLE,DPHY data lane 1 Enable" "0,1"
newline
bitfld.long 0x00 0. "DL0_ENABLE,DPHY data lane 0 Enable" "0,1"
rgroup.long 0x48++0x0B
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_status,DPHY Clock and Data Lane mode status"
bitfld.long 0x00 22. "DL3_RXULPSESC,DPHY Data lane 3 ULPS Esc" "0,1"
newline
bitfld.long 0x00 21. "DL3_ULPSACTIVENOT,DPHY Data lane 3 ULPSActiveNot" "0,1"
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bitfld.long 0x00 20. "DL3_STOPSTATE,DPHY Data lane 3 Stop State" "0,1"
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bitfld.long 0x00 18. "DL2_RXULPSESC,DPHY Data lane 2 ULPS Esc" "0,1"
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bitfld.long 0x00 17. "DL2_ULPSACTIVENOT,DPHY Data lane 2 ULPSActiveNot" "0,1"
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bitfld.long 0x00 16. "DL2_STOPSTATE,DPHY Data lane 2 Stop State" "0,1"
newline
bitfld.long 0x00 14. "DL1_RXULPSESC,DPHY Data lane 1 ULPS Esc" "0,1"
newline
bitfld.long 0x00 13. "DL1_ULPSACTIVENOT,DPHY Data lane 1 ULPSActiveNot" "0,1"
newline
bitfld.long 0x00 12. "DL1_STOPSTATE,DPHY Data lane 1 Stop State" "0,1"
newline
bitfld.long 0x00 10. "DL0_RXULPSESC,DPHY Data lane 0 ULPS Esc" "0,1"
newline
bitfld.long 0x00 9. "DL0_ULPSACTIVENOT,DPHY Data lane 0 ULPSActiveNot" "0,1"
newline
bitfld.long 0x00 8. "DL0_STOPSTATE,DPHY Data lane 0 Stop State" "0,1"
newline
bitfld.long 0x00 2. "CL_RXULPSCLKNOT,DPHY Clock lane RxULPSClkNot" "0,1"
newline
bitfld.long 0x00 1. "CL_ULPSACTIVENOT,DPHY Clock lane ULPSActiveNot" "0,1"
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bitfld.long 0x00 0. "CL_STOPSTATE,DPHY Clock lane Stop State" "0,1"
line.long 0x04 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_err_status_irq,DPHY error interrupt status"
bitfld.long 0x04 20. "DL3_ERRSOTHS_IRQ,DPHY Data lane 3 ErrSotHS" "0,1"
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bitfld.long 0x04 16. "DL2_ERRSOTHS_IRQ,DPHY Data lane 2 ErrSotHS" "0,1"
newline
bitfld.long 0x04 12. "DL1_ERRSOTHS_IRQ,DPHY Data lane 1 ErrSotHS" "0,1"
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bitfld.long 0x04 8. "DL0_ERRSOTHS_IRQ,DPHY Data lane 0 ErrSotHS" "0,1"
line.long 0x08 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_dphy_err_irq_mask_cfg,DPHY error interrupt status"
bitfld.long 0x08 20. "DL3_ERRSOTHS_IRQM,DPHY Data lane 3 ErrSotHS mask" "0,1"
newline
bitfld.long 0x08 16. "DL2_ERRSOTHS_IRQM,DPHY Data lane 2 ErrSotHS mask" "0,1"
newline
bitfld.long 0x08 12. "DL1_ERRSOTHS_IRQM,DPHY Data lane 1 ErrSotHS mask" "0,1"
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bitfld.long 0x08 8. "DL0_ERRSOTHS_IRQM,DPHY Data lane 0 ErrSotHS mask" "0,1"
rgroup.long 0x60++0x03
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_integration_debug,Used to observe the current data field. extracted by the protocol block from the last short packet data field and FSM state"
bitfld.long 0x00 28.--31. "PROT_FSM_STATE,csi2rx_fsm_state" "?,WAIT_FOR_PACKET,PAYLOAD_DATA,?,PACKET_FOOTER_CHECK,?..."
newline
bitfld.long 0x00 22.--25. "PROT_VC,Protocol Virtual Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--21. "PROT_DT,Protocol Datatype" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x00 0.--15. 1. "PROT_WORD_COUNT,Protocol Word Count [Data Field]"
rgroup.long 0x74++0x03
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_error_debug,Error condition debug"
hexmask.long.word 0x00 16.--31. 1. "DATA_FIELD,Indicates the Data Field for an invalid CRC/ECC/Data ID"
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bitfld.long 0x00 6.--9. "VC,Indicates the Virtual Channel for a invalid CRC/ECC/Data ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--5. "DT,Indicates the Data Type for a invalid CRC/ECC/Data ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x80++0x03
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_test_generic,Generic test control and status register that controls and reads primary I/O"
hexmask.long.word 0x00 16.--31. 1. "STATUS,Test status - Directly reflects after resynchronisation into the pclk domain the state of 'test_generic_status' primary inputs"
newline
hexmask.long.word 0x00 0.--15. 1. "CTRL,Test control - Directly controls primary outputs 'test_generic_ctrl'"
group.long 0x100++0x2B
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_ctrl,CSI2RX Stream Data output datapath control. Start and Stop commands are independent for each output with the exception of pixel outputs that can never be enabled together"
bitfld.long 0x00 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1"
newline
bitfld.long 0x00 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately" "0,1"
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bitfld.long 0x00 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame" "0,1"
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bitfld.long 0x00 0. "START,Writing 1 in this register enables the corresponding datapath output" "0,1"
line.long 0x04 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_status,CSI2 Slave Controller Status"
bitfld.long 0x04 31. "RUNNING,The Stream is enabled" "0,1"
newline
bitfld.long 0x04 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1"
newline
bitfld.long 0x04 4.--7. "STREAM_FSM,Output to Stream FSM states" "STREAM_IDLE,STREAM_WAIT_CTRL_DATA // Expecting control data..,STREAM_CTRL // Check contents of Ctrl packet and..,STREAM_DATA // Pixel stream pixel data unpacking,STREAM_CONV_PIX_NB // 1st cycle delay for..,STREAM_CONV_PIX_NB_EXT // 2nd cycle delay for..,STREAM_DATA_START // Assert Hsync,STREAM_DATA_END // De-assert Hysnc,STREAM_FILL_WAIT // Elastic Buffer cfg - wait..,STREAM_STOP // Stop at the end of Frame - used..,STREAM_WAIT_CRC // Wait until CRC check has..,STREAM_WAIT_PKT_DONE // Wait for CRC to complete..,STREAM_PKT_DONE // Packet complete - no error..,STREAM_NULL // NULL pkt received,STREAM_FLUSH // Flush due to CRC error,?..."
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bitfld.long 0x04 0.--1. "PROTOCOL_FSM,Input to Stream FSM states" "PROT_IDLE,PROT_WAIT_CTRL,PROT_CTRL,PROT_DATA"
line.long 0x08 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration. This register is used to configure the data types and virtual channels are processed and output by this stream"
hexmask.long.word 0x08 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] -> Virtual Channel.."
newline
bitfld.long 0x08 15. "ENABLE_DT1,Enable processing of dt1" "0,1"
newline
bitfld.long 0x08 8.--13. "DATATYPE_SELECT1,Second data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x08 7. "ENABLE_DT0,Enable processing of dt0" "0,1"
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bitfld.long 0x08 0.--5. "DATATYPE_SELECT0,First data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration. This register is used to configure the output mode. It is also used to set up some Stream FIFO related settings"
hexmask.long.word 0x0C 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled"
newline
bitfld.long 0x0C 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type" "No bypass,unpack as RAW6,unpack as RAW7,unpack as RAW8,unpack as RAW10,unpack as RAW12,unpack as RAW14,unpack as RAW16"
newline
bitfld.long 0x0C 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates" "Full Line Buffer,Large Buffer [Fill Level Controlled],?..."
newline
bitfld.long 0x0C 4.--5. "NUM_PIXELS,Number of pixels to output from the stream" "0,1,2,3"
newline
bitfld.long 0x0C 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output" "0,1"
newline
bitfld.long 0x0C 0. "INTERFACE_MODE,Select the output configuration" "0,1"
line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_ctrl,Stream Monitor configuration"
hexmask.long.word 0x10 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames"
newline
bitfld.long 0x10 15. "FRAME_MON_EN,Enables monitor" "0,1"
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bitfld.long 0x10 11.--14. "FRAME_MON_VC,Indicates virtual channel for monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 10. "TIMER_EOF,Select the starting point of the timer" "Start of Frame event on selected virtual channel,End of Frame event on selected virtual channel"
newline
bitfld.long 0x10 9. "TIMER_EN,Enables timer based interrupt" "0,1"
newline
bitfld.long 0x10 5.--8. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 4. "LB_EN,Enables line/byte counter" "0,1"
newline
bitfld.long 0x10 0.--3. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_frame,Stream Monitor Frame. Used to observe the current frame number and packet size on monitored virtual channels"
hexmask.long.word 0x14 16.--31. 1. "PACKET_SIZE,Size of the current payload"
newline
hexmask.long.word 0x14 0.--15. 1. "NB,Number of the last frame processed"
line.long 0x18 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_monitor_lb,Stream Monitor Line. Used to specify the byte and line numbers that will generate an interrupt. This register must only be modified when the corresponding line/byte enable is disabled"
hexmask.long.word 0x18 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt"
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hexmask.long.word 0x18 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt"
line.long 0x1C "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_timer,Stream Timer. Used to specify the number of clock cycles until the interrupt is triggered after frame start or frame end"
hexmask.long 0x1C 0.--24. 1. "COUNT,Number of clock cycles"
line.long 0x20 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fcc_cfg,Stream Frame Capture Control configuration. Used to specify the frame count value when when the CSI2RX must generate interrupts FCC_START and FCC_STOP. This register must only be modified when the.."
hexmask.long.word 0x20 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface"
newline
hexmask.long.word 0x20 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface"
line.long 0x24 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fcc_ctrl,Stream Frame Capture Counter control. Used to enable / disable the FCC and specify which virtual channel it should operate on"
hexmask.long.word 0x24 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed"
newline
bitfld.long 0x24 1.--4. "FCC_VC,Indicates which VC should be used to generate FCC interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 0. "FCC_EN,Frame Capture Counter enable" "0,1"
line.long 0x28 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream0_fifo_fill_lvl,Stream FIFO fill level monitor"
bitfld.long 0x28 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0,1,2,3"
newline
hexmask.long.word 0x28 0.--9. 1. "COUNT,Peak fill level of FIFO"
group.long 0x200++0x2B
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_ctrl,CSI2RX Stream Data output datapath control. Start and Stop commands are independent for each output with the exception of pixel outputs that can never be enabled together"
bitfld.long 0x00 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1"
newline
bitfld.long 0x00 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately" "0,1"
newline
bitfld.long 0x00 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame" "0,1"
newline
bitfld.long 0x00 0. "START,Writing 1 in this register enables the corresponding datapath output" "0,1"
line.long 0x04 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_status,CSI2 Slave Controller Status"
bitfld.long 0x04 31. "RUNNING,The Stream is enabled" "0,1"
newline
bitfld.long 0x04 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1"
newline
bitfld.long 0x04 4.--7. "STREAM_FSM,Output to Stream FSM states" "STREAM_IDLE,STREAM_WAIT_CTRL_DATA // Expecting control data..,STREAM_CTRL // Check contents of Ctrl packet and..,STREAM_DATA // Pixel stream pixel data unpacking,STREAM_CONV_PIX_NB // 1st cycle delay for..,STREAM_CONV_PIX_NB_EXT // 2nd cycle delay for..,STREAM_DATA_START // Assert Hsync,STREAM_DATA_END // De-assert Hysnc,STREAM_FILL_WAIT // Elastic Buffer cfg - wait..,STREAM_STOP // Stop at the end of Frame - used..,STREAM_WAIT_CRC // Wait until CRC check has..,STREAM_WAIT_PKT_DONE // Wait for CRC to complete..,STREAM_PKT_DONE // Packet complete - no error..,STREAM_NULL // NULL pkt received,STREAM_FLUSH // Flush due to CRC error,?..."
newline
bitfld.long 0x04 0.--1. "PROTOCOL_FSM,Input to Stream FSM states" "PROT_IDLE,PROT_WAIT_CTRL,PROT_CTRL,PROT_DATA"
line.long 0x08 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration. This register is used to configure the data types and virtual channels are processed and output by this stream"
hexmask.long.word 0x08 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] -> Virtual Channel.."
newline
bitfld.long 0x08 15. "ENABLE_DT1,Enable processing of dt1" "0,1"
newline
bitfld.long 0x08 8.--13. "DATATYPE_SELECT1,Second data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x08 7. "ENABLE_DT0,Enable processing of dt0" "0,1"
newline
bitfld.long 0x08 0.--5. "DATATYPE_SELECT0,First data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration. This register is used to configure the output mode. It is also used to set up some Stream FIFO related settings"
hexmask.long.word 0x0C 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled"
newline
bitfld.long 0x0C 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type" "No bypass,unpack as RAW6,unpack as RAW7,unpack as RAW8,unpack as RAW10,unpack as RAW12,unpack as RAW14,unpack as RAW16"
newline
bitfld.long 0x0C 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates" "Full Line Buffer,Large Buffer [Fill Level Controlled],?..."
newline
bitfld.long 0x0C 4.--5. "NUM_PIXELS,Number of pixels to output from the stream" "0,1,2,3"
newline
bitfld.long 0x0C 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output" "0,1"
newline
bitfld.long 0x0C 0. "INTERFACE_MODE,Select the output configuration" "0,1"
line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_ctrl,Stream Monitor configuration"
hexmask.long.word 0x10 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames"
newline
bitfld.long 0x10 15. "FRAME_MON_EN,Enables monitor" "0,1"
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bitfld.long 0x10 11.--14. "FRAME_MON_VC,Indicates virtual channel for monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 10. "TIMER_EOF,Select the starting point of the timer" "Start of Frame event on selected virtual channel,End of Frame event on selected virtual channel"
newline
bitfld.long 0x10 9. "TIMER_EN,Enables timer based interrupt" "0,1"
newline
bitfld.long 0x10 5.--8. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 4. "LB_EN,Enables line/byte counter" "0,1"
newline
bitfld.long 0x10 0.--3. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_frame,Stream Monitor Frame. Used to observe the current frame number and packet size on monitored virtual channels"
hexmask.long.word 0x14 16.--31. 1. "PACKET_SIZE,Size of the current payload"
newline
hexmask.long.word 0x14 0.--15. 1. "NB,Number of the last frame processed"
line.long 0x18 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_monitor_lb,Stream Monitor Line. Used to specify the byte and line numbers that will generate an interrupt. This register must only be modified when the corresponding line/byte enable is disabled"
hexmask.long.word 0x18 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt"
newline
hexmask.long.word 0x18 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt"
line.long 0x1C "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_timer,Stream Timer. Used to specify the number of clock cycles until the interrupt is triggered after frame start or frame end"
hexmask.long 0x1C 0.--24. 1. "COUNT,Number of clock cycles"
line.long 0x20 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fcc_cfg,Stream Frame Capture Control configuration. Used to specify the frame count value when when the CSI2RX must generate interrupts FCC_START and FCC_STOP. This register must only be modified when the.."
hexmask.long.word 0x20 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface"
newline
hexmask.long.word 0x20 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface"
line.long 0x24 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fcc_ctrl,Stream Frame Capture Counter control. Used to enable / disable the FCC and specify which virtual channel it should operate on"
hexmask.long.word 0x24 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed"
newline
bitfld.long 0x24 1.--4. "FCC_VC,Indicates which VC should be used to generate FCC interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 0. "FCC_EN,Frame Capture Counter enable" "0,1"
line.long 0x28 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream1_fifo_fill_lvl,Stream FIFO fill level monitor"
bitfld.long 0x28 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0,1,2,3"
newline
hexmask.long.word 0x28 0.--9. 1. "COUNT,Peak fill level of FIFO"
group.long 0x300++0x2B
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_ctrl,CSI2RX Stream Data output datapath control. Start and Stop commands are independent for each output with the exception of pixel outputs that can never be enabled together"
bitfld.long 0x00 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1"
newline
bitfld.long 0x00 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately" "0,1"
newline
bitfld.long 0x00 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame" "0,1"
newline
bitfld.long 0x00 0. "START,Writing 1 in this register enables the corresponding datapath output" "0,1"
line.long 0x04 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_status,CSI2 Slave Controller Status"
bitfld.long 0x04 31. "RUNNING,The Stream is enabled" "0,1"
newline
bitfld.long 0x04 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1"
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bitfld.long 0x04 4.--7. "STREAM_FSM,Output to Stream FSM states" "STREAM_IDLE,STREAM_WAIT_CTRL_DATA // Expecting control data..,STREAM_CTRL // Check contents of Ctrl packet and..,STREAM_DATA // Pixel stream pixel data unpacking,STREAM_CONV_PIX_NB // 1st cycle delay for..,STREAM_CONV_PIX_NB_EXT // 2nd cycle delay for..,STREAM_DATA_START // Assert Hsync,STREAM_DATA_END // De-assert Hysnc,STREAM_FILL_WAIT // Elastic Buffer cfg - wait..,STREAM_STOP // Stop at the end of Frame - used..,STREAM_WAIT_CRC // Wait until CRC check has..,STREAM_WAIT_PKT_DONE // Wait for CRC to complete..,STREAM_PKT_DONE // Packet complete - no error..,STREAM_NULL // NULL pkt received,STREAM_FLUSH // Flush due to CRC error,?..."
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bitfld.long 0x04 0.--1. "PROTOCOL_FSM,Input to Stream FSM states" "PROT_IDLE,PROT_WAIT_CTRL,PROT_CTRL,PROT_DATA"
line.long 0x08 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration. This register is used to configure the data types and virtual channels are processed and output by this stream"
hexmask.long.word 0x08 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] -> Virtual Channel.."
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bitfld.long 0x08 15. "ENABLE_DT1,Enable processing of dt1" "0,1"
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bitfld.long 0x08 8.--13. "DATATYPE_SELECT1,Second data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 7. "ENABLE_DT0,Enable processing of dt0" "0,1"
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bitfld.long 0x08 0.--5. "DATATYPE_SELECT0,First data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration. This register is used to configure the output mode. It is also used to set up some Stream FIFO related settings"
hexmask.long.word 0x0C 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled"
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bitfld.long 0x0C 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type" "No bypass,unpack as RAW6,unpack as RAW7,unpack as RAW8,unpack as RAW10,unpack as RAW12,unpack as RAW14,unpack as RAW16"
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bitfld.long 0x0C 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates" "Full Line Buffer,Large Buffer [Fill Level Controlled],?..."
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bitfld.long 0x0C 4.--5. "NUM_PIXELS,Number of pixels to output from the stream" "0,1,2,3"
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bitfld.long 0x0C 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output" "0,1"
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bitfld.long 0x0C 0. "INTERFACE_MODE,Select the output configuration" "0,1"
line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_ctrl,Stream Monitor configuration"
hexmask.long.word 0x10 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames"
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bitfld.long 0x10 15. "FRAME_MON_EN,Enables monitor" "0,1"
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bitfld.long 0x10 11.--14. "FRAME_MON_VC,Indicates virtual channel for monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 10. "TIMER_EOF,Select the starting point of the timer" "Start of Frame event on selected virtual channel,End of Frame event on selected virtual channel"
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bitfld.long 0x10 9. "TIMER_EN,Enables timer based interrupt" "0,1"
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bitfld.long 0x10 5.--8. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 4. "LB_EN,Enables line/byte counter" "0,1"
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bitfld.long 0x10 0.--3. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_frame,Stream Monitor Frame. Used to observe the current frame number and packet size on monitored virtual channels"
hexmask.long.word 0x14 16.--31. 1. "PACKET_SIZE,Size of the current payload"
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hexmask.long.word 0x14 0.--15. 1. "NB,Number of the last frame processed"
line.long 0x18 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_monitor_lb,Stream Monitor Line. Used to specify the byte and line numbers that will generate an interrupt. This register must only be modified when the corresponding line/byte enable is disabled"
hexmask.long.word 0x18 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt"
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hexmask.long.word 0x18 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt"
line.long 0x1C "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_timer,Stream Timer. Used to specify the number of clock cycles until the interrupt is triggered after frame start or frame end"
hexmask.long 0x1C 0.--24. 1. "COUNT,Number of clock cycles"
line.long 0x20 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fcc_cfg,Stream Frame Capture Control configuration. Used to specify the frame count value when when the CSI2RX must generate interrupts FCC_START and FCC_STOP. This register must only be modified when the.."
hexmask.long.word 0x20 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface"
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hexmask.long.word 0x20 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface"
line.long 0x24 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fcc_ctrl,Stream Frame Capture Counter control. Used to enable / disable the FCC and specify which virtual channel it should operate on"
hexmask.long.word 0x24 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed"
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bitfld.long 0x24 1.--4. "FCC_VC,Indicates which VC should be used to generate FCC interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 0. "FCC_EN,Frame Capture Counter enable" "0,1"
line.long 0x28 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream2_fifo_fill_lvl,Stream FIFO fill level monitor"
bitfld.long 0x28 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0,1,2,3"
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hexmask.long.word 0x28 0.--9. 1. "COUNT,Peak fill level of FIFO"
group.long 0x400++0x2B
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_ctrl,CSI2RX Stream Data output datapath control. Start and Stop commands are independent for each output with the exception of pixel outputs that can never be enabled together"
bitfld.long 0x00 4. "SOFT_RST,Writing 1'b1 will apply a synchronous soft reset of this stream registers/FIFO" "0,1"
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bitfld.long 0x00 2. "ABORT,Writing 1 this register will cause the csi2rx to stop streaming on the corresponding output immediately" "0,1"
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bitfld.long 0x00 1. "STOP,Writing 1 in this register will cause csi2rx to stop streaming on the corresponding output at the end of the current frame" "0,1"
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bitfld.long 0x00 0. "START,Writing 1 in this register enables the corresponding datapath output" "0,1"
line.long 0x04 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_status,CSI2 Slave Controller Status"
bitfld.long 0x04 31. "RUNNING,The Stream is enabled" "0,1"
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bitfld.long 0x04 8. "READY_STATE,Indicates the state of the pushback signal pixel_ready_if for this stream" "0,1"
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bitfld.long 0x04 4.--7. "STREAM_FSM,Output to Stream FSM states" "STREAM_IDLE,STREAM_WAIT_CTRL_DATA // Expecting control data..,STREAM_CTRL // Check contents of Ctrl packet and..,STREAM_DATA // Pixel stream pixel data unpacking,STREAM_CONV_PIX_NB // 1st cycle delay for..,STREAM_CONV_PIX_NB_EXT // 2nd cycle delay for..,STREAM_DATA_START // Assert Hsync,STREAM_DATA_END // De-assert Hysnc,STREAM_FILL_WAIT // Elastic Buffer cfg - wait..,STREAM_STOP // Stop at the end of Frame - used..,STREAM_WAIT_CRC // Wait until CRC check has..,STREAM_WAIT_PKT_DONE // Wait for CRC to complete..,STREAM_PKT_DONE // Packet complete - no error..,STREAM_NULL // NULL pkt received,STREAM_FLUSH // Flush due to CRC error,?..."
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bitfld.long 0x04 0.--1. "PROTOCOL_FSM,Input to Stream FSM states" "PROT_IDLE,PROT_WAIT_CTRL,PROT_CTRL,PROT_DATA"
line.long 0x08 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_data_cfg,Secondary CSI2 Slave Controller Data outputs configuration. This register is used to configure the data types and virtual channels are processed and output by this stream"
hexmask.long.word 0x08 16.--31. 1. "VC_SELECT,Selection of Virtual Channels to be processed: Default '0' -> All Virtual Channels are processed vc_select0[16] -> Virtual Channel Select 0 is processed vc_select1[17] -> Virtual Channel Select 1 is processed vc_select2[18] -> Virtual Channel.."
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bitfld.long 0x08 15. "ENABLE_DT1,Enable processing of dt1" "0,1"
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bitfld.long 0x08 8.--13. "DATATYPE_SELECT1,Second data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 7. "ENABLE_DT0,Enable processing of dt0" "0,1"
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bitfld.long 0x08 0.--5. "DATATYPE_SELECT0,First data type format that this stream will process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_cfg,Primary CSI2 Slave Controller Data pixel outputs configuration. This register is used to configure the output mode. It is also used to set up some Stream FIFO related settings"
hexmask.long.word 0x0C 16.--31. 1. "FIFO_FILL,Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled"
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bitfld.long 0x0C 12.--14. "BPP_BYPASS,Force unpacking of any Data type as selected RAW type" "No bypass,unpack as RAW6,unpack as RAW7,unpack as RAW8,unpack as RAW10,unpack as RAW12,unpack as RAW14,unpack as RAW16"
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bitfld.long 0x0C 8.--9. "FIFO_MODE,Stream FIFO configuration which must be set in accordance to FIFO sizing flow control and the relationship between the link and pixel interface data rates" "Full Line Buffer,Large Buffer [Fill Level Controlled],?..."
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bitfld.long 0x0C 4.--5. "NUM_PIXELS,Number of pixels to output from the stream" "0,1,2,3"
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bitfld.long 0x0C 1. "LS_LE_MODE,Enable LS/LE control of HYSNC_VALID output" "0,1"
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bitfld.long 0x0C 0. "INTERFACE_MODE,Select the output configuration" "0,1"
line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_ctrl,Stream Monitor configuration"
hexmask.long.word 0x10 16.--31. 1. "FRAME_LENGTH,Indicates the frame length in lines to detect truncated frames"
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bitfld.long 0x10 15. "FRAME_MON_EN,Enables monitor" "0,1"
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bitfld.long 0x10 11.--14. "FRAME_MON_VC,Indicates virtual channel for monitor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 10. "TIMER_EOF,Select the starting point of the timer" "Start of Frame event on selected virtual channel,End of Frame event on selected virtual channel"
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bitfld.long 0x10 9. "TIMER_EN,Enables timer based interrupt" "0,1"
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bitfld.long 0x10 5.--8. "TIMER_VC,Indicates which VC should be used to generate timer based interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 4. "LB_EN,Enables line/byte counter" "0,1"
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bitfld.long 0x10 0.--3. "LB_VC,Indicates which VC should be used to generate line/byte counter interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_frame,Stream Monitor Frame. Used to observe the current frame number and packet size on monitored virtual channels"
hexmask.long.word 0x14 16.--31. 1. "PACKET_SIZE,Size of the current payload"
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hexmask.long.word 0x14 0.--15. 1. "NB,Number of the last frame processed"
line.long 0x18 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_monitor_lb,Stream Monitor Line. Used to specify the byte and line numbers that will generate an interrupt. This register must only be modified when the corresponding line/byte enable is disabled"
hexmask.long.word 0x18 16.--31. 1. "LINE_COUNT,Indicates the line number to generate an interrupt"
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hexmask.long.word 0x18 0.--15. 1. "BYTE_COUNT,Indicates the byte number of the line to generate an interrupt"
line.long 0x1C "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_timer,Stream Timer. Used to specify the number of clock cycles until the interrupt is triggered after frame start or frame end"
hexmask.long 0x1C 0.--24. 1. "COUNT,Number of clock cycles"
line.long 0x20 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fcc_cfg,Stream Frame Capture Control configuration. Used to specify the frame count value when when the CSI2RX must generate interrupts FCC_START and FCC_STOP. This register must only be modified when the.."
hexmask.long.word 0x20 16.--31. 1. "FRAME_COUNT_STOP,Indicates the frame number on which the interrupt should be generated and the stream will stop outputting data on the pixel interface"
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hexmask.long.word 0x20 0.--15. 1. "FRAME_COUNT_START,Indicates the frame number on which the interrupt should be generated and the stream will start outputting data on the pixel interface"
line.long 0x24 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fcc_ctrl,Stream Frame Capture Counter control. Used to enable / disable the FCC and specify which virtual channel it should operate on"
hexmask.long.word 0x24 16.--31. 1. "FRAME_COUNTER,Current Frame number being processed"
newline
bitfld.long 0x24 1.--4. "FCC_VC,Indicates which VC should be used to generate FCC interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 0. "FCC_EN,Frame Capture Counter enable" "0,1"
line.long 0x28 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_stream3_fifo_fill_lvl,Stream FIFO fill level monitor"
bitfld.long 0x28 12.--13. "MODE,00 -> Fill level detection disabled 01 -> Mode 1 10 -> Mode 2 11 -> Reserved" "0,1,2,3"
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hexmask.long.word 0x28 0.--9. 1. "COUNT,Peak fill level of FIFO"
group.long 0x900++0x13
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_status,ASF Interrupt Status Register"
hexmask.long 0x00 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write"
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bitfld.long 0x00 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
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bitfld.long 0x00 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
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bitfld.long 0x00 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
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bitfld.long 0x00 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1"
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bitfld.long 0x00 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1"
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bitfld.long 0x00 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
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bitfld.long 0x00 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x04 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_raw_status,ASF Interrupt Raw Status Register"
hexmask.long 0x04 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write"
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bitfld.long 0x04 6. "ASF_INTEGRITY_ERR,Integrity error interrupt" "0,1"
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bitfld.long 0x04 5. "ASF_PROTOCOL_ERR,Protocol error interrupt" "0,1"
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bitfld.long 0x04 4. "ASF_TRANS_TO_ERR,Transaction timeouts error interrupt" "0,1"
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bitfld.long 0x04 3. "ASF_CSR_ERR,Configuration and status registers error interrupt" "0,1"
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bitfld.long 0x04 2. "ASF_DAP_ERR,Data and address paths parity error interrupt" "0,1"
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bitfld.long 0x04 1. "ASF_SRAM_UNCORR_ERR,SRAM uncorrectable error interrupt" "0,1"
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bitfld.long 0x04 0. "ASF_SRAM_CORR_ERR,SRAM correctable error interrupt" "0,1"
line.long 0x08 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_mask,The ASF interrupt mask register indicating which interrupt bits in the ASF interrupt status register are masked"
hexmask.long 0x08 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write"
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bitfld.long 0x08 6. "ASF_INTEGRITY_ERR_MASK,Mask bit for integrity error interrupt" "0,1"
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bitfld.long 0x08 5. "ASF_PROTOCOL_ERR_MASK,Mask bit for protocol error interrupt" "0,1"
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bitfld.long 0x08 4. "ASF_TRANS_TO_ERR_MASK,Mask bit for transaction timeouts error interrupt" "0,1"
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bitfld.long 0x08 3. "ASF_CSR_ERR_MASK,Mask bit for configuration and status registers error interrupt" "0,1"
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bitfld.long 0x08 2. "ASF_DAP_ERR_MASK,Mask bit for data and address paths parity error interrupt" "0,1"
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bitfld.long 0x08 1. "ASF_SRAM_UNCORR_ERR_MASK,Mask bit for SRAM uncorrectable error interrupt" "0,1"
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bitfld.long 0x08 0. "ASF_SRAM_CORR_ERR_MASK,Mask bit for SRAM correctable error interrupt" "0,1"
line.long 0x0C "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_int_test,The ASF interrupt test register emulate hardware even"
hexmask.long 0x0C 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write"
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bitfld.long 0x0C 6. "ASF_INTEGRITY_ERR_TEST,Test bit for integrity error interrupt" "0,1"
newline
bitfld.long 0x0C 5. "ASF_PROTOCOL_ERR_TEST,Test bit for protocol error interrupt" "0,1"
newline
bitfld.long 0x0C 4. "ASF_TRANS_TO_ERR_TEST,Test bit for transaction timeouts error interrupt" "0,1"
newline
bitfld.long 0x0C 3. "ASF_CSR_ERR_TEST,Test bit for configuration and status registers error interrupt" "0,1"
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bitfld.long 0x0C 2. "ASF_DAP_ERR_TEST,Test bit for data and address paths parity error interrupt" "0,1"
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bitfld.long 0x0C 1. "ASF_SRAM_UNCORR_ERR_TEST,Test bit for SRAM uncorrectable error interrupt" "0,1"
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bitfld.long 0x0C 0. "ASF_SRAM_CORR_ERR_TEST,Test bit for SRAM correctable error interrupt" "0,1"
line.long 0x10 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_fatal_nonfatal_select,The fatal or non-fatal interrupt register selects whether a fatal (asf_int_fatal) or non-fatal (asf_int_nonfatal) interrupt is triggered"
hexmask.long 0x10 7.--31. 1. "RESERVED,Reserved read as 0 ignored on write"
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bitfld.long 0x10 6. "ASF_INTEGRITY_ERR,Enable integrity error interrupt as fatal" "0,1"
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bitfld.long 0x10 5. "ASF_PROTOCOL_ERR,Enable protocol error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 4. "ASF_TRANS_TO_ERR,Enable transaction timeouts error interrupt as fatal" "0,1"
newline
bitfld.long 0x10 3. "ASF_CSR_ERR,Enable configuration and status registers error interrupt as fatal" "0,1"
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bitfld.long 0x10 2. "ASF_DAP_ERR,Enable data and address paths parity error interrupt as fatal" "0,1"
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bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR,Enable SRAM uncorrectable error interrupt as fatal" "0,1"
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bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR,Enable SRAM correctable error interrupt as fatal" "0,1"
rgroup.long 0x920++0x0B
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_corr_fault_status,Status register for SRAM correctable fault"
hexmask.long.byte 0x00 24.--31. 1. "ASF_SRAM_CORR_FAULT_INST,Last SRAM instance that generated fault"
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hexmask.long.tbyte 0x00 0.--23. 1. "ASF_SRAM_CORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x04 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_uncorr_fault_status,Status register for SRAM uncorrectable fault"
hexmask.long.byte 0x04 24.--31. 1. "ASF_SRAM_UNCORR_FAULT_INST,Last SRAM instance that generated fault"
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hexmask.long.tbyte 0x04 0.--23. 1. "ASF_SRAM_UNCORR_FAULT_ADDR,Last SRAM address that generated fault"
line.long 0x08 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_sram_fault_stats,Statistics register for SRAM faults"
hexmask.long.word 0x08 16.--31. 1. "RESERVED,Reserved read as 0 ignored on write"
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hexmask.long.word 0x08 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS,Count of number of correctable errors if implemented"
group.long 0x930++0x0B
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_ctrl,Control register to configure the ASF transaction timeout monitors"
bitfld.long 0x00 31. "ASF_TRANS_TO_EN,Enable transaction timeout monitoring" "0,1"
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hexmask.long.word 0x00 0.--15. 1. "ASF_TRANS_TO_CTRL,Timer value to use for transaction timeout monitor"
line.long 0x04 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_fault_mask,Control register to mask out ASF transaction timeout faults from triggering interrupts"
bitfld.long 0x04 0. "ASF_TRANS_TO_FAULT_0_MASK,Mask register for each ASF transaction timeout fault source" "0,1"
line.long 0x08 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_trans_to_fault_status,Status register for transaction timeouts fault"
bitfld.long 0x08 0. "ASF_TRANS_TO_FAULT_0_STATUS,Status bits for transaction timeouts faults" "0,1"
group.long 0x940++0x07
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_protocol_fault_mask,Control register to mask out ASF Protocol faults from triggering interrupts"
bitfld.long 0x00 13. "ASF_PROTOCOL_FAULT_13_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 12. "ASF_PROTOCOL_FAULT_12_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 11. "ASF_PROTOCOL_FAULT_11_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 10. "ASF_PROTOCOL_FAULT_10_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 9. "ASF_PROTOCOL_FAULT_9_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 8. "ASF_PROTOCOL_FAULT_8_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 7. "ASF_PROTOCOL_FAULT_7_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 6. "ASF_PROTOCOL_FAULT_6_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 5. "ASF_PROTOCOL_FAULT_5_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 4. "ASF_PROTOCOL_FAULT_4_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 3. "ASF_PROTOCOL_FAULT_3_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 2. "ASF_PROTOCOL_FAULT_2_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 1. "ASF_PROTOCOL_FAULT_1_MASK,Mask register for each ASF protocol fault source" "0,1"
newline
bitfld.long 0x00 0. "ASF_PROTOCOL_FAULT_0_MASK,Mask register for each ASF protocol fault source" "0,1"
line.long 0x04 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_asf_protocol_fault_status,Status register for protocol faults"
bitfld.long 0x04 13. "ASF_PROTOCOL_FAULT_13_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 12. "ASF_PROTOCOL_FAULT_12_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 11. "ASF_PROTOCOL_FAULT_11_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 10. "ASF_PROTOCOL_FAULT_10_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 9. "ASF_PROTOCOL_FAULT_9_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 8. "ASF_PROTOCOL_FAULT_8_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 7. "ASF_PROTOCOL_FAULT_7_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 6. "ASF_PROTOCOL_FAULT_6_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 5. "ASF_PROTOCOL_FAULT_5_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 4. "ASF_PROTOCOL_FAULT_4_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 3. "ASF_PROTOCOL_FAULT_3_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 2. "ASF_PROTOCOL_FAULT_2_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 1. "ASF_PROTOCOL_FAULT_1_STATUS,Status bits for protocol faults" "0,1"
newline
bitfld.long 0x04 0. "ASF_PROTOCOL_FAULT_0_STATUS,Status bits for protocol faults" "0,1"
rgroup.long 0xFFC++0x03
line.long 0x00 "VBUS2APB_WRAP__VBUSP_APB__CSI2RX_REGS_id_prod_ver,This register is hard-coded in order to allow software to identify the product and its release version"
hexmask.long.word 0x00 16.--31. 1. "PRODUCT_ID,Product Identification Number [IP5022/IP5022A]"
newline
hexmask.long.word 0x00 0.--15. 1. "VERSION_ID,Product Version Number [R200]"
tree.end
tree "CTRL_MMR0_CFG0"
base ad:0x100000
rgroup.long 0x00++0x03
line.long 0x00 "CFG0_PID,"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16,"
newline
bitfld.long 0x00 11.--15. "PID_MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "PID_CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x08++0x03
line.long 0x00 "CFG0_MMR_CFG1,"
bitfld.long 0x00 31. "MMR_CFG1_PROXY_EN,Proxy addressing activated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions"
group.long 0x1008++0x2B
line.long 0x00 "CFG0_LOCK0_KICK0,"
line.long 0x04 "CFG0_LOCK0_KICK1,"
line.long 0x08 "CFG0_intr_raw_status,"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "CFG0_intr_enabled_status_clear,"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "CFG0_intr_enable,"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "CFG0_intr_enable_clear,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "CFG0_eoi,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value"
line.long 0x1C "CFG0_fault_address,"
line.long 0x20 "CFG0_fault_type_status,"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "CFG0_fault_attr_status,"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "CFG0_fault_clear,"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
rgroup.long 0x1100++0x1B
line.long 0x00 "CFG0_CLAIMREG_P0_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P0_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P0_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P0_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P0_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P0_R5_READONLY,"
line.long 0x18 "CFG0_CLAIMREG_P0_R6_READONLY,"
rgroup.long 0x2000++0x03
line.long 0x00 "CFG0_PID_PROXY,"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16_PROXY,"
newline
bitfld.long 0x00 11.--15. "PID_MISC_PROXY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR_PROXY," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "PID_CUSTOM_PROXY," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR_PROXY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x2008++0x03
line.long 0x00 "CFG0_MMR_CFG1_PROXY,"
bitfld.long 0x00 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing activated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions"
group.long 0x3008++0x2B
line.long 0x00 "CFG0_LOCK0_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK0_KICK1_PROXY,"
line.long 0x08 "CFG0_intr_raw_status_PROXY,"
bitfld.long 0x08 3. "PROXY_ERR_PROXY,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR_PROXY,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR_PROXY,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR_PROXY,Protection violation error" "0,1"
line.long 0x0C "CFG0_intr_enabled_status_clear_PROXY,"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR_PROXY,Protection violation error" "0,1"
line.long 0x10 "CFG0_intr_enable_PROXY,"
bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable" "0,1"
line.long 0x14 "CFG0_intr_enable_clear_PROXY,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear" "0,1"
line.long 0x18 "CFG0_eoi_PROXY,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value"
line.long 0x1C "CFG0_fault_address_PROXY,"
line.long 0x20 "CFG0_fault_type_status_PROXY,"
bitfld.long 0x20 6. "FAULT_NS_PROXY,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE_PROXY,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "CFG0_fault_attr_status_PROXY,"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID_PROXY,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID"
line.long 0x28 "CFG0_fault_clear_PROXY,"
bitfld.long 0x28 0. "FAULT_CLR_PROXY,Fault clear" "0,1"
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x3100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P0_R$1,"
repeat.end
group.long 0x4044++0x07
line.long 0x00 "CFG0_ENET1_CTRL,"
bitfld.long 0x00 4. "ENET1_CTRL_RGMII_ID_MODE,Port1 RGMII internal transmit delay selection" "Internal transmit delay,No intenal transmit delay"
newline
bitfld.long 0x00 0.--2. "ENET1_CTRL_PORT_MODE_SEL,Selects Ethernet switch Port1 interface Field values (others are reserved)" "GMII/MII (not supported),RMII,RGMII,SGMII (not supported),QSGMII (not supported),XFI (not supported),QSGMII_SUB (not supported),Reserved"
line.long 0x04 "CFG0_ENET2_CTRL,"
bitfld.long 0x04 4. "ENET2_CTRL_RGMII_ID_MODE,Port2 RGMII internal transmit delay selection" "Internal transmit delay,No intenal transmit delay"
newline
bitfld.long 0x04 0.--2. "ENET2_CTRL_PORT_MODE_SEL,Selects Ethernet switch Port2 interface Field values (others are reserved)" "GMII/MII (not supported),RMII,RGMII,SGMII (not supported),QSGMII (not supported),XFI (not supported),QSGMII_SUB (not supported),Reserved"
group.long 0x4100++0x03
line.long 0x00 "CFG0_ICSSM0_CTRL0,"
abitfld.long 0x00 0.--19. "ICSSM0_CTRL0_GPM_BIDI,Controls operation of the ICSSM0 PRU0_GPO pins" "0x00000=In GPO mode pin n functions as GPM..,0x00001=In GPO mode pin n functions as GPM.."
group.long 0x4130++0x03
line.long 0x00 "CFG0_EPWM_TB_CLKEN,"
bitfld.long 0x00 2. "EPWM_TB_CLKEN_EPWM2_TB_CLKEN,Activates Timebase Clock of EPWM2 When Set" "0,1"
newline
bitfld.long 0x00 1. "EPWM_TB_CLKEN_EPWM1_TB_CLKEN,Activates Timebase Clock of EPWM1 When Set" "0,1"
newline
bitfld.long 0x00 0. "EPWM_TB_CLKEN_EPWM0_TB_CLKEN,Activates Timebase Clock of EPWM0 When Set" "0,1"
group.long 0x4140++0x0B
line.long 0x00 "CFG0_EPWM0_CTRL,"
bitfld.long 0x00 8.--10. "EPWM0_CTRL_SYNCIN_SEL,Selects the source of the EPWM0 synchronization input Field values (others are reserved)" "EPWM0_SYNCIN Pin,None,Time Sync Router 19,Compare Event Router 32,ICSSM Host Interrupt 6,None,None,None"
newline
bitfld.long 0x00 4. "EPWM0_CTRL_EALLOW,Activate write access to EPWM tripzone registers" "Deactivated,Activated"
line.long 0x04 "CFG0_EPWM1_CTRL,"
bitfld.long 0x04 4. "EPWM1_CTRL_EALLOW,Activate write access to EPWM tripzone registers" "Deactivated,Activated"
line.long 0x08 "CFG0_EPWM2_CTRL,"
bitfld.long 0x08 4. "EPWM2_CTRL_EALLOW,Activate write access to EPWM tripzone registers" "Deactivated,Activated"
group.long 0x4170++0x07
line.long 0x00 "CFG0_SOCA_SEL,"
bitfld.long 0x00 0.--1. "SOCA_SEL_SOCA_SEL,Selects the SOC A output source Field values (others are reserved)" "OR of all EPWM SOCA outputs,ICSSM Host Interrupt 1,None,None"
line.long 0x04 "CFG0_SOCB_SEL,"
bitfld.long 0x04 0.--1. "SOCB_SEL_SOCB_SEL,Selects the SOC B output source Field values (others are reserved)" "OR of all EPWM SOCB ouputs,ICSSM Host Interrupt 1,None,None"
group.long 0x4180++0x0B
line.long 0x00 "CFG0_EQEP0_CTRL,"
bitfld.long 0x00 0.--4. "EQEP0_CTRL_SOCA_SEL,Selects the source of SOCA input for EQEP0 Field values (others are reserved): undefined - undefined undefined - undefined" "?,?,EPWM SOCA_OUT,EPWM SOCB_OUT,MCU_TIMER0 PWM,MCU_TIMER1 PWM,MCU_TIMER2 PWM,MCU_TIMER3 PWM,TIMER0 PWM,TIMER1 PWM,TIMER2 PWM,TIMER3 PWM,TIMER4 PWM,TIMER5 PWM,TIMER6 PWM,TIMER7 PWM,WKUP TIMER0 PWM,WKUP TIMER1 PWM,?,?,ICSSM PR1 IEP0,?,?,?,ICSSM PR1 HOST INTR PEND4,ICSSM PR1 HOST INTR PEND5,?..."
line.long 0x04 "CFG0_EQEP1_CTRL,"
bitfld.long 0x04 0.--4. "EQEP1_CTRL_SOCA_SEL,Selects the source of SOCA input for EQEP1 Field values (others are reserved): undefined - undefined undefined - undefined" "?,?,EPWM SOCA_OUT,EPWM SOCB_OUT,MCU_TIMER0 PWM,MCU_TIMER1 PWM,MCU_TIMER2 PWM,MCU_TIMER3 PWM,TIMER0 PWM,TIMER1 PWM,TIMER2 PWM,TIMER3 PWM,TIMER4 PWM,TIMER5 PWM,TIMER6 PWM,TIMER7 PWM,WKUP TIMER0 PWM,WKUP TIMER1 PWM,?,?,ICSSM PR1 IEP0,?,?,?,ICSSM PR1 HOST INTR PEND4,ICSSM PR1 HOST INTR PEND5,?..."
line.long 0x08 "CFG0_EQEP2_CTRL,"
bitfld.long 0x08 0.--4. "EQEP2_CTRL_SOCA_SEL,Selects the source of SOCA input for EQEP2 Field values (others are reserved): undefined - undefined undefined - undefined" "?,?,EPWM SOCA_OUT,EPWM SOCB_OUT,MCU_TIMER0 PWM,MCU_TIMER1 PWM,MCU_TIMER2 PWM,MCU_TIMER3 PWM,TIMER0 PWM,TIMER1 PWM,TIMER2 PWM,TIMER3 PWM,TIMER4 PWM,TIMER5 PWM,TIMER6 PWM,TIMER7 PWM,WKUP TIMER0 PWM,WKUP TIMER1 PWM,?,?,ICSSM PR1 IEP0,?,?,?,ICSSM PR1 HOST INTR PEND4,ICSSM PR1 HOST INTR PEND5,?..."
rgroup.long 0x41A0++0x03
line.long 0x00 "CFG0_EQEP_STAT,"
bitfld.long 0x00 2. "EQEP_STAT_PHASE_ERR2,EQEP2 Phase error status" "No error,Phase error occurred"
newline
bitfld.long 0x00 1. "EQEP_STAT_PHASE_ERR1,EQEP1 Phase error status" "No error,Phase error occurred"
newline
bitfld.long 0x00 0. "EQEP_STAT_PHASE_ERR0,EQEP0 Phase error status" "No error,Phase error occurred"
group.long 0x4204++0x03
line.long 0x00 "CFG0_TIMER1_CTRL,"
bitfld.long 0x00 8. "TIMER1_CTRL_CASCADE_EN,Activates cascading of TIMER1 to TIMER0" "0,1"
group.long 0x420C++0x03
line.long 0x00 "CFG0_TIMER3_CTRL,"
bitfld.long 0x00 8. "TIMER3_CTRL_CASCADE_EN,Activates cascading of TIMER3 to TIMER2" "0,1"
group.long 0x4214++0x03
line.long 0x00 "CFG0_TIMER5_CTRL,"
bitfld.long 0x00 8. "TIMER5_CTRL_CASCADE_EN,Activates cascading of TIMER5 to TIMER4" "0,1"
group.long 0x421C++0x03
line.long 0x00 "CFG0_TIMER7_CTRL,"
bitfld.long 0x00 8. "TIMER7_CTRL_CASCADE_EN,Activates cascading of TIMER7 to TIMER6" "0,1"
rgroup.long 0x44C0++0x0B
line.long 0x00 "CFG0_EMMC0_STAT,"
bitfld.long 0x00 0. "EMMC0_STAT_SIG1P8_EN,Status of 1.8V Signal Activate from EMMC0 Module" "0,1"
line.long 0x04 "CFG0_EMMC1_STAT,"
bitfld.long 0x04 0. "EMMC1_STAT_SIG1P8_EN,Status of 1.8V Signal Activate from EMMC1 Module" "0,1"
line.long 0x08 "CFG0_EMMC2_STAT,"
bitfld.long 0x08 0. "EMMC2_STAT_SIG1P8_EN,Status of 1.8V Signal Activate from EMMC2 Module" "0,1"
group.long 0x4700++0x03
line.long 0x00 "CFG0_FSS_CTRL,"
bitfld.long 0x00 8. "FSS_CTRL_S0_BOOT_SIZE,Selects the size of the boot block to be used for the S0 (OSPI0) flash interface" "S0 boot size is 64 MB,S0 boot size is 128 MB"
newline
bitfld.long 0x00 0.--5. "FSS_CTRL_S0_BOOT_SEG,Selects the boot block to be used for the S0 (OSPI0) flash interface" "Use block 0,Use block,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Use block 63"
rgroup.long 0x4750++0x03
line.long 0x00 "CFG0_DCC_STAT,"
bitfld.long 0x00 16. "DCC_STAT_MCU_DCC0_INTR_DONE,MCU_DCC0 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 6. "DCC_STAT_DCC6_INTR_DONE,DCC6 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 5. "DCC_STAT_DCC5_INTR_DONE,DCC5 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 4. "DCC_STAT_DCC4_INTR_DONE,DCC4 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 3. "DCC_STAT_DCC3_INTR_DONE,DCC3 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 2. "DCC_STAT_DCC2_INTR_DONE,DCC2 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 1. "DCC_STAT_DCC1_INTR_DONE,DCC1 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 0. "DCC_STAT_DCC0_INTR_DONE,DCC0 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
group.long 0x5008++0x07
line.long 0x00 "CFG0_LOCK1_KICK0,"
line.long 0x04 "CFG0_LOCK1_KICK1,"
rgroup.long 0x5100++0x3B
line.long 0x00 "CFG0_CLAIMREG_P1_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P1_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P1_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P1_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P1_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P1_R5_READONLY,"
line.long 0x18 "CFG0_CLAIMREG_P1_R6_READONLY,"
line.long 0x1C "CFG0_CLAIMREG_P1_R7_READONLY,"
line.long 0x20 "CFG0_CLAIMREG_P1_R8_READONLY,"
line.long 0x24 "CFG0_CLAIMREG_P1_R9_READONLY,"
line.long 0x28 "CFG0_CLAIMREG_P1_R10_READONLY,"
line.long 0x2C "CFG0_CLAIMREG_P1_R11_READONLY,"
line.long 0x30 "CFG0_CLAIMREG_P1_R12_READONLY,"
line.long 0x34 "CFG0_CLAIMREG_P1_R13_READONLY,"
line.long 0x38 "CFG0_CLAIMREG_P1_R14_READONLY,"
group.long 0x6044++0x07
line.long 0x00 "CFG0_ENET1_CTRL_PROXY,"
bitfld.long 0x00 4. "ENET1_CTRL_RGMII_ID_MODE_PROXY,Port1 RGMII internal transmit delay selection" "Internal transmit delay,No intenal transmit delay"
newline
bitfld.long 0x00 0.--2. "ENET1_CTRL_PORT_MODE_SEL_PROXY,Selects Ethernet switch Port1 interface Field values (others are reserved)" "GMII/MII (not supported),RMII,RGMII,SGMII (not supported),QSGMII (not supported),XFI (not supported),QSGMII_SUB (not supported),Reserved"
line.long 0x04 "CFG0_ENET2_CTRL_PROXY,"
bitfld.long 0x04 4. "ENET2_CTRL_RGMII_ID_MODE_PROXY,Port2 RGMII internal transmit delay selection" "Internal transmit delay,No intenal transmit delay"
newline
bitfld.long 0x04 0.--2. "ENET2_CTRL_PORT_MODE_SEL_PROXY,Selects Ethernet switch Port2 interface Field values (others are reserved)" "GMII/MII (not supported),RMII,RGMII,SGMII (not supported),QSGMII (not supported),XFI (not supported),QSGMII_SUB (not supported),Reserved"
group.long 0x6100++0x03
line.long 0x00 "CFG0_ICSSM0_CTRL0_PROXY,"
abitfld.long 0x00 0.--19. "ICSSM0_CTRL0_GPM_BIDI_PROXY,Controls operation of the ICSSM0 PRU0_GPO pins" "0x00000=In GPO mode pin n functions as GPM..,0x00001=In GPO mode pin n functions as GPM.."
group.long 0x6130++0x03
line.long 0x00 "CFG0_EPWM_TB_CLKEN_PROXY,"
bitfld.long 0x00 2. "EPWM_TB_CLKEN_EPWM2_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM2 When Set" "0,1"
newline
bitfld.long 0x00 1. "EPWM_TB_CLKEN_EPWM1_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM1 When Set" "0,1"
newline
bitfld.long 0x00 0. "EPWM_TB_CLKEN_EPWM0_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM0 When Set" "0,1"
group.long 0x6140++0x0B
line.long 0x00 "CFG0_EPWM0_CTRL_PROXY,"
bitfld.long 0x00 8.--10. "EPWM0_CTRL_SYNCIN_SEL_PROXY,Selects the source of the EPWM0 synchronization input Field values (others are reserved)" "EPWM0_SYNCIN Pin,None,Time Sync Router 19,Compare Event Router 32,ICSSM Host Interrupt 6,None,None,None"
newline
bitfld.long 0x00 4. "EPWM0_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers" "Deactivated,Activated"
line.long 0x04 "CFG0_EPWM1_CTRL_PROXY,"
bitfld.long 0x04 4. "EPWM1_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers" "Deactivated,Activated"
line.long 0x08 "CFG0_EPWM2_CTRL_PROXY,"
bitfld.long 0x08 4. "EPWM2_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers" "Deactivated,Activated"
group.long 0x6170++0x07
line.long 0x00 "CFG0_SOCA_SEL_PROXY,"
bitfld.long 0x00 0.--1. "SOCA_SEL_SOCA_SEL_PROXY,Selects the SOC A output source Field values (others are reserved)" "OR of all EPWM SOCA outputs,ICSSM Host Interrupt 1,None,None"
line.long 0x04 "CFG0_SOCB_SEL_PROXY,"
bitfld.long 0x04 0.--1. "SOCB_SEL_SOCB_SEL_PROXY,Selects the SOC B output source Field values (others are reserved)" "OR of all EPWM SOCB ouputs,ICSSM Host Interrupt 1,None,None"
group.long 0x6180++0x0B
line.long 0x00 "CFG0_EQEP0_CTRL_PROXY,"
bitfld.long 0x00 0.--4. "EQEP0_CTRL_SOCA_SEL_PROXY,Selects the source of SOCA input for EQEP0 Field values (others are reserved): undefined - undefined undefined - undefined" "?,?,EPWM SOCA_OUT,EPWM SOCB_OUT,MCU_TIMER0 PWM,MCU_TIMER1 PWM,MCU_TIMER2 PWM,MCU_TIMER3 PWM,TIMER0 PWM,TIMER1 PWM,TIMER2 PWM,TIMER3 PWM,TIMER4 PWM,TIMER5 PWM,TIMER6 PWM,TIMER7 PWM,WKUP TIMER0 PWM,WKUP TIMER1 PWM,?,?,ICSSM PR1 IEP0,?,?,?,ICSSM PR1 HOST INTR PEND4,ICSSM PR1 HOST INTR PEND5,?..."
line.long 0x04 "CFG0_EQEP1_CTRL_PROXY,"
bitfld.long 0x04 0.--4. "EQEP1_CTRL_SOCA_SEL_PROXY,Selects the source of SOCA input for EQEP1 Field values (others are reserved): undefined - undefined undefined - undefined" "?,?,EPWM SOCA_OUT,EPWM SOCB_OUT,MCU_TIMER0 PWM,MCU_TIMER1 PWM,MCU_TIMER2 PWM,MCU_TIMER3 PWM,TIMER0 PWM,TIMER1 PWM,TIMER2 PWM,TIMER3 PWM,TIMER4 PWM,TIMER5 PWM,TIMER6 PWM,TIMER7 PWM,WKUP TIMER0 PWM,WKUP TIMER1 PWM,?,?,ICSSM PR1 IEP0,?,?,?,ICSSM PR1 HOST INTR PEND4,ICSSM PR1 HOST INTR PEND5,?..."
line.long 0x08 "CFG0_EQEP2_CTRL_PROXY,"
bitfld.long 0x08 0.--4. "EQEP2_CTRL_SOCA_SEL_PROXY,Selects the source of SOCA input for EQEP2 Field values (others are reserved): undefined - undefined undefined - undefined" "?,?,EPWM SOCA_OUT,EPWM SOCB_OUT,MCU_TIMER0 PWM,MCU_TIMER1 PWM,MCU_TIMER2 PWM,MCU_TIMER3 PWM,TIMER0 PWM,TIMER1 PWM,TIMER2 PWM,TIMER3 PWM,TIMER4 PWM,TIMER5 PWM,TIMER6 PWM,TIMER7 PWM,WKUP TIMER0 PWM,WKUP TIMER1 PWM,?,?,ICSSM PR1 IEP0,?,?,?,ICSSM PR1 HOST INTR PEND4,ICSSM PR1 HOST INTR PEND5,?..."
rgroup.long 0x61A0++0x03
line.long 0x00 "CFG0_EQEP_STAT_PROXY,"
bitfld.long 0x00 2. "EQEP_STAT_PHASE_ERR2_PROXY,EQEP2 Phase error status" "No error,Phase error occurred"
newline
bitfld.long 0x00 1. "EQEP_STAT_PHASE_ERR1_PROXY,EQEP1 Phase error status" "No error,Phase error occurred"
newline
bitfld.long 0x00 0. "EQEP_STAT_PHASE_ERR0_PROXY,EQEP0 Phase error status" "No error,Phase error occurred"
group.long 0x6204++0x03
line.long 0x00 "CFG0_TIMER1_CTRL_PROXY,"
bitfld.long 0x00 8. "TIMER1_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER1 to TIMER0" "0,1"
group.long 0x620C++0x03
line.long 0x00 "CFG0_TIMER3_CTRL_PROXY,"
bitfld.long 0x00 8. "TIMER3_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER3 to TIMER2" "0,1"
group.long 0x6214++0x03
line.long 0x00 "CFG0_TIMER5_CTRL_PROXY,"
bitfld.long 0x00 8. "TIMER5_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER5 to TIMER4" "0,1"
group.long 0x621C++0x03
line.long 0x00 "CFG0_TIMER7_CTRL_PROXY,"
bitfld.long 0x00 8. "TIMER7_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER7 to TIMER6" "0,1"
rgroup.long 0x64C0++0x0B
line.long 0x00 "CFG0_EMMC0_STAT_PROXY,"
bitfld.long 0x00 0. "EMMC0_STAT_SIG1P8_EN_PROXY,Status of 1.8V Signal Activate from EMMC0 Module" "0,1"
line.long 0x04 "CFG0_EMMC1_STAT_PROXY,"
bitfld.long 0x04 0. "EMMC1_STAT_SIG1P8_EN_PROXY,Status of 1.8V Signal Activate from EMMC1 Module" "0,1"
line.long 0x08 "CFG0_EMMC2_STAT_PROXY,"
bitfld.long 0x08 0. "EMMC2_STAT_SIG1P8_EN_PROXY,Status of 1.8V Signal Activate from EMMC2 Module" "0,1"
group.long 0x6700++0x03
line.long 0x00 "CFG0_FSS_CTRL_PROXY,"
bitfld.long 0x00 8. "FSS_CTRL_S0_BOOT_SIZE_PROXY,Selects the size of the boot block to be used for the S0 (OSPI0) flash interface" "S0 boot size is 64 MB,S0 boot size is 128 MB"
newline
bitfld.long 0x00 0.--5. "FSS_CTRL_S0_BOOT_SEG_PROXY,Selects the boot block to be used for the S0 (OSPI0) flash interface" "Use block 0,Use block,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Use block 63"
rgroup.long 0x6750++0x03
line.long 0x00 "CFG0_DCC_STAT_PROXY,"
bitfld.long 0x00 16. "DCC_STAT_MCU_DCC0_INTR_DONE_PROXY,MCU_DCC0 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 6. "DCC_STAT_DCC6_INTR_DONE_PROXY,DCC6 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 5. "DCC_STAT_DCC5_INTR_DONE_PROXY,DCC5 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 4. "DCC_STAT_DCC4_INTR_DONE_PROXY,DCC4 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 3. "DCC_STAT_DCC3_INTR_DONE_PROXY,DCC3 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 2. "DCC_STAT_DCC2_INTR_DONE_PROXY,DCC2 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 1. "DCC_STAT_DCC1_INTR_DONE_PROXY,DCC1 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 0. "DCC_STAT_DCC0_INTR_DONE_PROXY,DCC0 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
group.long 0x7008++0x07
line.long 0x00 "CFG0_LOCK1_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK1_KICK1_PROXY,"
repeat 15. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
group.long ($2+0x7100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P1_R$1,"
repeat.end
group.long 0x8000++0x03
line.long 0x00 "CFG0_OBSCLK0_CTRL,"
bitfld.long 0x00 16. "OBSCLK0_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the OBSCLK0 divider value" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "OBSCLK0_CTRL_CLK_DIV,OBSCLK0 output divider Divides the selected clock by clkdiv+1 for output to the OBSCLK0 pins"
newline
bitfld.long 0x00 0.--4. "OBSCLK0_CTRL_CLK_SEL,OBSCLK0 clock source selection" "MAIN_PLL0_HSDIV0_CLKOUT,MAIN_PLL1_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV0_CLKOUT,MAIN_PLL8_HSDIV0_CLKOUT,MAIN_PLL12_HSDIV0_CLKOUT,CLK_12M_RC,HFOSC0_CLKOUT_32K,PLLCTRL_OBSCLK,HFOSC0_CLKOUT,CLK_32K,cpsw2g_cpts_genf0,cpsw2g_cpts_genf1,MCU_PLL0_HSDIV0_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,MAIN_PLL16_HSDIV0_CLKOUT,MAIN_PLL17_HSDIV0_CLKOUT,MAIN_SYSCLK0,DEVICE_CLKOUT_32K,?..."
group.long 0x8010++0x03
line.long 0x00 "CFG0_CLKOUT_CTRL,"
bitfld.long 0x00 0. "CLKOUT_CTRL_CLK_SEL,Selects CLKOUT clock source Field values (others are reserved)" "MAIN_PLL2_HSDIV1_CLKOUT / 5,MAIN_PLL2_HSDIV1_CLKOUT / 10"
group.long 0x8040++0x03
line.long 0x00 "CFG0_ICSSM0_CLKSEL,"
bitfld.long 0x00 16.--18. "ICSSM0_CLKSEL_IEP_CLKSEL,Selects the ICSSM0 IEP clock source Field values (others are reserved)" "MAIN_PLL2_HSDIV5_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,CPGEMAC_CPTS_RFT_CLK,reserved,MCU_EXT_REFCLK0,EXT_REFCLK1,MCU_SYSCLK0,MAIN_SYSCLK0"
newline
bitfld.long 0x00 0. "ICSSM0_CLKSEL_CORE_CLKSEL,Selects the ICSSM0 functional clock source Field values (others are reserved)" "MAIN_PLL2_HSDIV0_CLKOUT,MAIN_PLL0_HSDIV9_CLKOUT"
group.long 0x8060++0x0B
line.long 0x00 "CFG0_MAIN_PLL0_CLKSEL,"
bitfld.long 0x00 31. "MAIN_PLL0_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL0" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL0_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset" "Exit bypass mode (based on MAIN..,Maintain bypass mode"
line.long 0x04 "CFG0_MAIN_PLL1_CLKSEL,"
bitfld.long 0x04 31. "MAIN_PLL1_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL1 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x04 23. "MAIN_PLL1_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
line.long 0x08 "CFG0_MAIN_PLL2_CLKSEL,"
bitfld.long 0x08 31. "MAIN_PLL2_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL2 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x08 23. "MAIN_PLL2_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
group.long 0x8080++0x03
line.long 0x00 "CFG0_MAIN_PLL8_CLKSEL,"
bitfld.long 0x00 31. "MAIN_PLL8_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL8" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL8_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset" "Exit bypass mode (based on MAIN..,Maintain bypass mode"
group.long 0x8090++0x03
line.long 0x00 "CFG0_MAIN_PLL12_CLKSEL,"
bitfld.long 0x00 31. "MAIN_PLL12_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL12" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL12_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset" "Exit bypass mode (based on MAIN..,Maintain bypass mode"
group.long 0x80A0++0x07
line.long 0x00 "CFG0_MAIN_PLL16_CLKSEL,"
bitfld.long 0x00 31. "MAIN_PLL16_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL16 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL16_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
line.long 0x04 "CFG0_MAIN_PLL17_CLKSEL,"
bitfld.long 0x04 31. "MAIN_PLL17_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL17 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x04 23. "MAIN_PLL17_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
group.long 0x8140++0x03
line.long 0x00 "CFG0_CPSW_CLKSEL,"
bitfld.long 0x00 0.--2. "CPSW_CLKSEL_CPTS_CLKSEL,Selects the clock source for the CPSW Ethernet switch Common Platform Time Stamp module Field values (others are reserved)" "MAIN_PLL2_HSDIV5_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,CP_GEMAC_CPTS0_RFT_CLK (Pin),Reserved,MCU_EXT_REFCLK0 (Pin),EXT_REFCLK1 (Pin),MCU_SYSCLK0,MAIN_SYSCLK0"
group.long 0x8160++0x03
line.long 0x00 "CFG0_EMMC0_CLKSEL,"
bitfld.long 0x00 16. "EMMC0_CLKSEL_EMMCSD_IO_CLKLB_SEL,Selects IO Pad Loopback for the MMC Module Field values (others are reserved)" "Loopback from Unbonded Pad MMCSD0_CLKLB,Loopback from IO Pin MMCSD0_CLK"
newline
bitfld.long 0x00 0. "EMMC0_CLKSEL_EMMCSD_REFCLK_SEL,Selects the functional clock for the MMC Module Field values (others are reserved)" "MAIN_PLL0_HSDIV5_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT"
group.long 0x8168++0x07
line.long 0x00 "CFG0_EMMC1_CLKSEL,"
bitfld.long 0x00 16. "EMMC1_CLKSEL_EMMCSD_IO_CLKLB_SEL,Selects IO Pad Loopback for the MMC Module Field values (others are reserved)" "Loopback from Unbonded Pad MMCSD1_CLKLB,Loopback from IO Pin MMCSD1_CLK"
newline
bitfld.long 0x00 0. "EMMC1_CLKSEL_EMMCSD_REFCLK_SEL,Selects the functional clock for the MMC Module Field values (others are reserved)" "MAIN_PLL0_HSDIV5_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT"
line.long 0x04 "CFG0_EMMC2_CLKSEL,"
bitfld.long 0x04 16. "EMMC2_CLKSEL_EMMCSD_IO_CLKLB_SEL,Selects IO Pad Loopback for the MMC Module Field values (others are reserved)" "Loopback from Unbonded Pad MMCSD2_CLKLB,Loopback from IO Pin MMCSD2_CLK"
newline
bitfld.long 0x04 0. "EMMC2_CLKSEL_EMMCSD_REFCLK_SEL,Selects the functional clock for the MMC Module Field values (others are reserved)" "MAIN_PLL0_HSDIV5_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT"
group.long 0x8180++0x03
line.long 0x00 "CFG0_GPMC_CLKSEL,"
bitfld.long 0x00 0. "GPMC_CLKSEL_CLK_SEL,Selects the GPMC clock source: Field values (others are reserved)" "MAIN_PLL0_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV7_CLKOUT"
group.long 0x81B0++0x1F
line.long 0x00 "CFG0_TIMER0_CLKSEL,"
bitfld.long 0x00 0.--3. "TIMER0_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x04 "CFG0_TIMER1_CLKSEL,"
bitfld.long 0x04 0.--3. "TIMER1_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x08 "CFG0_TIMER2_CLKSEL,"
bitfld.long 0x08 0.--3. "TIMER2_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x0C "CFG0_TIMER3_CLKSEL,"
bitfld.long 0x0C 0.--3. "TIMER3_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x10 "CFG0_TIMER4_CLKSEL,"
bitfld.long 0x10 0.--3. "TIMER4_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x14 "CFG0_TIMER5_CLKSEL,"
bitfld.long 0x14 0.--3. "TIMER5_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x18 "CFG0_TIMER6_CLKSEL,"
bitfld.long 0x18 0.--3. "TIMER6_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x1C "CFG0_TIMER7_CLKSEL,"
bitfld.long 0x1C 0.--3. "TIMER7_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
group.long 0x8200++0x0B
line.long 0x00 "CFG0_SPI0_CLKSEL,"
bitfld.long 0x00 16. "SPI0_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
line.long 0x04 "CFG0_SPI1_CLKSEL,"
bitfld.long 0x04 16. "SPI1_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
line.long 0x08 "CFG0_SPI2_CLKSEL,"
bitfld.long 0x08 16. "SPI2_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
group.long 0x8240++0x1B
line.long 0x00 "CFG0_USART0_CLK_CTRL,"
bitfld.long 0x00 16. "USART0_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART0 clock programmable divider value" "0,1"
newline
bitfld.long 0x00 0.--1. "USART0_CLK_CTRL_CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x04 "CFG0_USART1_CLK_CTRL,"
bitfld.long 0x04 16. "USART1_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART1 clock programmable divider value" "0,1"
newline
bitfld.long 0x04 0.--1. "USART1_CLK_CTRL_CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x08 "CFG0_USART2_CLK_CTRL,"
bitfld.long 0x08 16. "USART2_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART2 clock programmable divider value" "0,1"
newline
bitfld.long 0x08 0.--1. "USART2_CLK_CTRL_CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x0C "CFG0_USART3_CLK_CTRL,"
bitfld.long 0x0C 16. "USART3_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART3 clock programmable divider value" "0,1"
newline
bitfld.long 0x0C 0.--1. "USART3_CLK_CTRL_CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x10 "CFG0_USART4_CLK_CTRL,"
bitfld.long 0x10 16. "USART4_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART4 clock programmable divider value" "0,1"
newline
bitfld.long 0x10 0.--1. "USART4_CLK_CTRL_CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x14 "CFG0_USART5_CLK_CTRL,"
bitfld.long 0x14 16. "USART5_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART5 clock programmable divider value" "0,1"
newline
bitfld.long 0x14 0.--1. "USART5_CLK_CTRL_CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x18 "CFG0_USART6_CLK_CTRL,"
bitfld.long 0x18 16. "USART6_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART6 clock programmable divider value" "0,1"
newline
bitfld.long 0x18 0.--1. "USART6_CLK_CTRL_CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
group.long 0x8280++0x1B
line.long 0x00 "CFG0_USART0_CLKSEL,"
bitfld.long 0x00 0. "USART0_CLKSEL_CLK_SEL,Selects the clock source for UART0: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x04 "CFG0_USART1_CLKSEL,"
bitfld.long 0x04 0. "USART1_CLKSEL_CLK_SEL,Selects the clock source for UART1: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x08 "CFG0_USART2_CLKSEL,"
bitfld.long 0x08 0. "USART2_CLKSEL_CLK_SEL,Selects the clock source for UART2: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x0C "CFG0_USART3_CLKSEL,"
bitfld.long 0x0C 0. "USART3_CLKSEL_CLK_SEL,Selects the clock source for UART3: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x10 "CFG0_USART4_CLKSEL,"
bitfld.long 0x10 0. "USART4_CLKSEL_CLK_SEL,Selects the clock source for UART4: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x14 "CFG0_USART5_CLKSEL,"
bitfld.long 0x14 0. "USART5_CLKSEL_CLK_SEL,Selects the clock source for UART5: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x18 "CFG0_USART6_CLKSEL,"
bitfld.long 0x18 0. "USART6_CLKSEL_CLK_SEL,Selects the clock source for UART6: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
group.long 0x82E0++0x07
line.long 0x00 "CFG0_AUDIO_REFCLK0_CTRL,"
bitfld.long 0x00 15. "AUDIO_REFCLK0_CTRL_CLKOUT_EN,AUDIO_REFCLK 0 output activate This bit is inverted to drive the active low output buffer activate" "AUDIO_EXT_REFCLK0 pin is configured as an input,AUDIO_EXT_REFCLK0 pin is configured as an output"
newline
bitfld.long 0x00 0.--2. "AUDIO_REFCLK0_CTRL_CLK_SEL,Selects the source of AUDIO_REFCLK0 Field values (others are reserved)" "MCASP0_AHCLKR,MCASP1_AHCLKR,MCASP2_AHCLKR,MCASP0_AHCLKX,MCASP1_AHCLKX,MCASP2_AHCLKX,MAIN_PLL1_HSDIV6_CLKOUT,MAIN_PLL1_HSDIV8_CLKOUT"
line.long 0x04 "CFG0_AUDIO_REFCLK1_CTRL,"
bitfld.long 0x04 15. "AUDIO_REFCLK1_CTRL_CLKOUT_EN,AUDIO_REFCLK 1 output activate This bit is inverted to drive the active low output buffer activate" "AUDIO_EXT_REFCLK1 pin is configured as an input,AUDIO_EXT_REFCLK1 pin is configured as an output"
newline
bitfld.long 0x04 0.--2. "AUDIO_REFCLK1_CTRL_CLK_SEL,Selects the source of AUDIO_REFCLK1 Field values (others are reserved)" "MCASP0_AHCLKR,MCASP1_AHCLKR,MCASP2_AHCLKR,MCASP0_AHCLKX,MCASP1_AHCLKX,MCASP2_AHCLKX,MAIN_PLL1_HSDIV6_CLKOUT,MAIN_PLL1_HSDIV8_CLKOUT"
group.long 0x8300++0x03
line.long 0x00 "CFG0_DPI0_CLK_CTRL,"
bitfld.long 0x00 9. "DPI0_CLK_CTRL_SYNC_CLK_INVDIS,Clock edge select for DPI0 sync outputs" "HSYNC and VSYNC are driven on the falling edge..,HSYNC and VSYNC are driven on the rising edge of.."
newline
bitfld.long 0x00 8. "DPI0_CLK_CTRL_DATA_CLK_INVDIS,Clock edge select for DPI0 data outputs" "DATA and DE are driven on the falling edge of clk,DATA and DE are driven on the rising edge of clk.."
group.long 0x8320++0x03
line.long 0x00 "CFG0_DSS_DISPC0_CLKSEL1,"
bitfld.long 0x00 0. "DSS_DISPC0_CLKSEL1_DPI1_PCLK,DPI Lane 1 pixel Clock Source Field values (others are reserved)" "MAIN_PLL17_HSDIV0_CLKOUT,VOUT0_EXTPCLKIN"
group.long 0x8330++0x0B
line.long 0x00 "CFG0_MCASP0_CLKSEL,"
bitfld.long 0x00 0. "MCASP0_CLKSEL_AUXCLK_SEL,Selects the AUXCLK input source for McASP0 Field values (others are reserved)" "MAIN_PLL2_HSDIV8_CLKOUT,MAIN_PLL1_HSDIV6_CLKOUT"
line.long 0x04 "CFG0_MCASP1_CLKSEL,"
bitfld.long 0x04 0. "MCASP1_CLKSEL_AUXCLK_SEL,Selects the AUXCLK input source for McASP0 Field values (others are reserved)" "MAIN_PLL2_HSDIV8_CLKOUT,MAIN_PLL1_HSDIV6_CLKOUT"
line.long 0x08 "CFG0_MCASP2_CLKSEL,"
bitfld.long 0x08 0. "MCASP2_CLKSEL_AUXCLK_SEL,Selects the AUXCLK input source for McASP0 Field values (others are reserved)" "MAIN_PLL2_HSDIV8_CLKOUT,MAIN_PLL1_HSDIV6_CLKOUT"
group.long 0x8350++0x0B
line.long 0x00 "CFG0_MCASP0_AHCLKSEL,"
bitfld.long 0x00 8.--9. "MCASP0_AHCLKSEL_AHCLKX_SEL,Selects the AHCLKX input source for McASP0 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
newline
bitfld.long 0x00 0.--1. "MCASP0_AHCLKSEL_AHCLKR_SEL,Selects the AHCLKR input source for McASP0 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
line.long 0x04 "CFG0_MCASP1_AHCLKSEL,"
bitfld.long 0x04 8.--9. "MCASP1_AHCLKSEL_AHCLKX_SEL,Selects the AHCLKX input source for McASP1 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
newline
bitfld.long 0x04 0.--1. "MCASP1_AHCLKSEL_AHCLKR_SEL,Selects the AHCLKR input source for McASP1 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
line.long 0x08 "CFG0_MCASP2_AHCLKSEL,"
bitfld.long 0x08 8.--9. "MCASP2_AHCLKSEL_AHCLKX_SEL,Selects the AHCLKX input source for McASP2 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
newline
bitfld.long 0x08 0.--1. "MCASP2_AHCLKSEL_AHCLKR_SEL,Selects the AHCLKR input source for McASP2 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
group.long 0x8380++0x0F
line.long 0x00 "CFG0_WWD0_CLKSEL,"
bitfld.long 0x00 31. "WWD0_CLKSEL_WRTLOCK,When set locks WWD0_CLKSEL from further writes until the next module reset" "0,1"
newline
bitfld.long 0x00 0.--1. "WWD0_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
line.long 0x04 "CFG0_WWD1_CLKSEL,"
bitfld.long 0x04 31. "WWD1_CLKSEL_WRTLOCK,When set locks WWD1_CLKSEL from further writes until the next module reset" "0,1"
newline
bitfld.long 0x04 0.--1. "WWD1_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
line.long 0x08 "CFG0_WWD2_CLKSEL,"
bitfld.long 0x08 31. "WWD2_CLKSEL_WRTLOCK,When set locks WWD2_CLKSEL from further writes until the next module reset" "0,1"
newline
bitfld.long 0x08 0.--1. "WWD2_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
line.long 0x0C "CFG0_WWD3_CLKSEL,"
bitfld.long 0x0C 31. "WWD3_CLKSEL_WRTLOCK,When set locks WWD3_CLKSEL from further writes until the next module reset" "0,1"
newline
bitfld.long 0x0C 0.--1. "WWD3_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
group.long 0x83BC++0x03
line.long 0x00 "CFG0_WWD15_CLKSEL,"
bitfld.long 0x00 31. "WWD15_CLKSEL_WRTLOCK,When set locks WWD15_CLKSEL from further writes until the next module reset" "0,1"
newline
bitfld.long 0x00 0.--1. "WWD15_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
group.long 0x8480++0x03
line.long 0x00 "CFG0_MCAN0_CLKSEL,"
bitfld.long 0x00 0.--1. "MCAN0_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection" "MAIN_PLL0_HSDIV4_CLKOUT,MCU_EXT_REFCLK0,EXT_REFCLK1 (pin),HFOSC0_CLKOUT"
group.long 0x8500++0x03
line.long 0x00 "CFG0_OSPI0_CLKSEL,"
bitfld.long 0x00 4. "OSPI0_CLKSEL_LOOPCLK_SEL,OBSPI0 Loopback clock source Field values (others are reserved)" "Board Level Loopback,Internal Loopback"
newline
bitfld.long 0x00 0. "OSPI0_CLKSEL_CLK_SEL,OSPI0 reference clock selection Field values (others are reserved)" "MAIN_PLL0_HSDIV1_CLKOUT,MAIN_PLL1_HSDIV5_CLKOUT"
group.long 0x8600++0x13
line.long 0x00 "CFG0_OLDI0_DAT0_IO_CTRL,"
bitfld.long 0x00 31. "OLDI0_DAT0_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x00 30. "OLDI0_DAT0_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x00 24.--25. "OLDI0_DAT0_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x00 16.--19. "OLDI0_DAT0_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13. "OLDI0_DAT0_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x00 12. "OLDI0_DAT0_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 11. "OLDI0_DAT0_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 10. "OLDI0_DAT0_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x00 9. "OLDI0_DAT0_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x00 8. "OLDI0_DAT0_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 1.--3. "OLDI0_DAT0_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "OLDI0_DAT0_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x04 "CFG0_OLDI0_DAT1_IO_CTRL,"
bitfld.long 0x04 31. "OLDI0_DAT1_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x04 30. "OLDI0_DAT1_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x04 24.--25. "OLDI0_DAT1_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x04 16.--19. "OLDI0_DAT1_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 13. "OLDI0_DAT1_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x04 12. "OLDI0_DAT1_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 11. "OLDI0_DAT1_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 10. "OLDI0_DAT1_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x04 9. "OLDI0_DAT1_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x04 8. "OLDI0_DAT1_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 1.--3. "OLDI0_DAT1_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "OLDI0_DAT1_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x08 "CFG0_OLDI0_DAT2_IO_CTRL,"
bitfld.long 0x08 31. "OLDI0_DAT2_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x08 30. "OLDI0_DAT2_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x08 24.--25. "OLDI0_DAT2_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x08 16.--19. "OLDI0_DAT2_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 13. "OLDI0_DAT2_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x08 12. "OLDI0_DAT2_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 11. "OLDI0_DAT2_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 10. "OLDI0_DAT2_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x08 9. "OLDI0_DAT2_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x08 8. "OLDI0_DAT2_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 1.--3. "OLDI0_DAT2_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0. "OLDI0_DAT2_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x0C "CFG0_OLDI0_DAT3_IO_CTRL,"
bitfld.long 0x0C 31. "OLDI0_DAT3_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x0C 30. "OLDI0_DAT3_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x0C 24.--25. "OLDI0_DAT3_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x0C 16.--19. "OLDI0_DAT3_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 13. "OLDI0_DAT3_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x0C 12. "OLDI0_DAT3_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 11. "OLDI0_DAT3_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 10. "OLDI0_DAT3_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x0C 9. "OLDI0_DAT3_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x0C 8. "OLDI0_DAT3_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 1.--3. "OLDI0_DAT3_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "OLDI0_DAT3_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x10 "CFG0_OLDI0_CLK_IO_CTRL,"
bitfld.long 0x10 31. "OLDI0_CLK_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x10 30. "OLDI0_CLK_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x10 24.--25. "OLDI0_CLK_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x10 16.--19. "OLDI0_CLK_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 13. "OLDI0_CLK_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x10 12. "OLDI0_CLK_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 11. "OLDI0_CLK_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 10. "OLDI0_CLK_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x10 9. "OLDI0_CLK_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x10 8. "OLDI0_CLK_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 1.--3. "OLDI0_CLK_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0. "OLDI0_CLK_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
group.long 0x8620++0x13
line.long 0x00 "CFG0_OLDI1_DAT0_IO_CTRL,"
bitfld.long 0x00 31. "OLDI1_DAT0_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x00 30. "OLDI1_DAT0_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x00 24.--25. "OLDI1_DAT0_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x00 16.--19. "OLDI1_DAT0_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13. "OLDI1_DAT0_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x00 12. "OLDI1_DAT0_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 11. "OLDI1_DAT0_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 10. "OLDI1_DAT0_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x00 9. "OLDI1_DAT0_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x00 8. "OLDI1_DAT0_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 1.--3. "OLDI1_DAT0_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "OLDI1_DAT0_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x04 "CFG0_OLDI1_DAT1_IO_CTRL,"
bitfld.long 0x04 31. "OLDI1_DAT1_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x04 30. "OLDI1_DAT1_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x04 24.--25. "OLDI1_DAT1_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x04 16.--19. "OLDI1_DAT1_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 13. "OLDI1_DAT1_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x04 12. "OLDI1_DAT1_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 11. "OLDI1_DAT1_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 10. "OLDI1_DAT1_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x04 9. "OLDI1_DAT1_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x04 8. "OLDI1_DAT1_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 1.--3. "OLDI1_DAT1_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "OLDI1_DAT1_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x08 "CFG0_OLDI1_DAT2_IO_CTRL,"
bitfld.long 0x08 31. "OLDI1_DAT2_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x08 30. "OLDI1_DAT2_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x08 24.--25. "OLDI1_DAT2_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x08 16.--19. "OLDI1_DAT2_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 13. "OLDI1_DAT2_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x08 12. "OLDI1_DAT2_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 11. "OLDI1_DAT2_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 10. "OLDI1_DAT2_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x08 9. "OLDI1_DAT2_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x08 8. "OLDI1_DAT2_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 1.--3. "OLDI1_DAT2_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0. "OLDI1_DAT2_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x0C "CFG0_OLDI1_DAT3_IO_CTRL,"
bitfld.long 0x0C 31. "OLDI1_DAT3_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x0C 30. "OLDI1_DAT3_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x0C 24.--25. "OLDI1_DAT3_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x0C 16.--19. "OLDI1_DAT3_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 13. "OLDI1_DAT3_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x0C 12. "OLDI1_DAT3_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 11. "OLDI1_DAT3_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 10. "OLDI1_DAT3_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x0C 9. "OLDI1_DAT3_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x0C 8. "OLDI1_DAT3_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 1.--3. "OLDI1_DAT3_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "OLDI1_DAT3_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x10 "CFG0_OLDI1_CLK_IO_CTRL,"
bitfld.long 0x10 31. "OLDI1_CLK_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x10 30. "OLDI1_CLK_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x10 24.--25. "OLDI1_CLK_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x10 16.--19. "OLDI1_CLK_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 13. "OLDI1_CLK_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x10 12. "OLDI1_CLK_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 11. "OLDI1_CLK_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 10. "OLDI1_CLK_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x10 9. "OLDI1_CLK_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x10 8. "OLDI1_CLK_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 1.--3. "OLDI1_CLK_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0. "OLDI1_CLK_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
group.long 0x8700++0x07
line.long 0x00 "CFG0_OLDI_PD_CTRL,"
rbitfld.long 0x00 31. "OLDI_PD_CTRL_BGOK,Status of the Bandgap" "0,1"
newline
bitfld.long 0x00 8. "OLDI_PD_CTRL_PD_BG,When Set forces the LVDS Bandgap into Power Down" "0,1"
newline
bitfld.long 0x00 1. "OLDI_PD_CTRL_PD_OLDI1,When Set overrides the biase_en of all OLDI1 LVDS IO to force power down" "0,1"
newline
bitfld.long 0x00 0. "OLDI_PD_CTRL_PD_OLDI0,When Set overrides the biase_en of all OLDI0 LVDS IO to force power down" "0,1"
line.long 0x04 "CFG0_OLDI_LB_CTRL,"
bitfld.long 0x04 0. "OLDI_LB_CTRL_OLDI_SEL,When" "OLDI0 loopback data is routed to DSS,OLDI1 loopback data is routed to DSS"
group.long 0x9008++0x07
line.long 0x00 "CFG0_LOCK2_KICK0,"
line.long 0x04 "CFG0_LOCK2_KICK1,"
rgroup.long 0x9100++0x3B
line.long 0x00 "CFG0_CLAIMREG_P2_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P2_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P2_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P2_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P2_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P2_R5_READONLY,"
line.long 0x18 "CFG0_CLAIMREG_P2_R6_READONLY,"
line.long 0x1C "CFG0_CLAIMREG_P2_R7_READONLY,"
line.long 0x20 "CFG0_CLAIMREG_P2_R8_READONLY,"
line.long 0x24 "CFG0_CLAIMREG_P2_R9_READONLY,"
line.long 0x28 "CFG0_CLAIMREG_P2_R10_READONLY,"
line.long 0x2C "CFG0_CLAIMREG_P2_R11_READONLY,"
line.long 0x30 "CFG0_CLAIMREG_P2_R12_READONLY,"
line.long 0x34 "CFG0_CLAIMREG_P2_R13_READONLY,"
line.long 0x38 "CFG0_CLAIMREG_P2_R14_READONLY,"
group.long 0xA000++0x03
line.long 0x00 "CFG0_OBSCLK0_CTRL_PROXY,"
bitfld.long 0x00 16. "OBSCLK0_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the OBSCLK0 divider value" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "OBSCLK0_CTRL_CLK_DIV_PROXY,OBSCLK0 output divider Divides the selected clock by clkdiv+1 for output to the OBSCLK0 pins"
newline
bitfld.long 0x00 0.--4. "OBSCLK0_CTRL_CLK_SEL_PROXY,OBSCLK0 clock source selection" "MAIN_PLL0_HSDIV0_CLKOUT,MAIN_PLL1_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV0_CLKOUT,MAIN_PLL8_HSDIV0_CLKOUT,MAIN_PLL12_HSDIV0_CLKOUT,CLK_12M_RC,HFOSC0_CLKOUT_32K,PLLCTRL_OBSCLK,HFOSC0_CLKOUT,CLK_32K,cpsw2g_cpts_genf0,cpsw2g_cpts_genf1,MCU_PLL0_HSDIV0_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,MAIN_PLL16_HSDIV0_CLKOUT,MAIN_PLL17_HSDIV0_CLKOUT,MAIN_SYSCLK0,DEVICE_CLKOUT_32K,?..."
group.long 0xA010++0x03
line.long 0x00 "CFG0_CLKOUT_CTRL_PROXY,"
bitfld.long 0x00 0. "CLKOUT_CTRL_CLK_SEL_PROXY,Selects CLKOUT clock source Field values (others are reserved)" "MAIN_PLL2_HSDIV1_CLKOUT / 5,MAIN_PLL2_HSDIV1_CLKOUT / 10"
group.long 0xA040++0x03
line.long 0x00 "CFG0_ICSSM0_CLKSEL_PROXY,"
bitfld.long 0x00 16.--18. "ICSSM0_CLKSEL_IEP_CLKSEL_PROXY,Selects the ICSSM0 IEP clock source Field values (others are reserved)" "MAIN_PLL2_HSDIV5_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,CPGEMAC_CPTS_RFT_CLK,reserved,MCU_EXT_REFCLK0,EXT_REFCLK1,MCU_SYSCLK0,MAIN_SYSCLK0"
newline
bitfld.long 0x00 0. "ICSSM0_CLKSEL_CORE_CLKSEL_PROXY,Selects the ICSSM0 functional clock source Field values (others are reserved)" "MAIN_PLL2_HSDIV0_CLKOUT,MAIN_PLL0_HSDIV9_CLKOUT"
group.long 0xA060++0x0B
line.long 0x00 "CFG0_MAIN_PLL0_CLKSEL_PROXY,"
bitfld.long 0x00 31. "MAIN_PLL0_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL0" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL0_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset" "Exit bypass mode (based on MAIN..,Maintain bypass mode"
line.long 0x04 "CFG0_MAIN_PLL1_CLKSEL_PROXY,"
bitfld.long 0x04 31. "MAIN_PLL1_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL1 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x04 23. "MAIN_PLL1_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset" "0,1"
line.long 0x08 "CFG0_MAIN_PLL2_CLKSEL_PROXY,"
bitfld.long 0x08 31. "MAIN_PLL2_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL2 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x08 23. "MAIN_PLL2_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset" "0,1"
group.long 0xA080++0x03
line.long 0x00 "CFG0_MAIN_PLL8_CLKSEL_PROXY,"
bitfld.long 0x00 31. "MAIN_PLL8_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL8" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL8_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset" "Exit bypass mode (based on MAIN..,Maintain bypass mode"
group.long 0xA090++0x03
line.long 0x00 "CFG0_MAIN_PLL12_CLKSEL_PROXY,"
bitfld.long 0x00 31. "MAIN_PLL12_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL12" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL12_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset" "Exit bypass mode (based on MAIN..,Maintain bypass mode"
group.long 0xA0A0++0x07
line.long 0x00 "CFG0_MAIN_PLL16_CLKSEL_PROXY,"
bitfld.long 0x00 31. "MAIN_PLL16_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL16 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL16_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset" "0,1"
line.long 0x04 "CFG0_MAIN_PLL17_CLKSEL_PROXY,"
bitfld.long 0x04 31. "MAIN_PLL17_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL17 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x04 23. "MAIN_PLL17_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset" "0,1"
group.long 0xA140++0x03
line.long 0x00 "CFG0_CPSW_CLKSEL_PROXY,"
bitfld.long 0x00 0.--2. "CPSW_CLKSEL_CPTS_CLKSEL_PROXY,Selects the clock source for the CPSW Ethernet switch Common Platform Time Stamp module Field values (others are reserved)" "MAIN_PLL2_HSDIV5_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,CP_GEMAC_CPTS0_RFT_CLK (Pin),Reserved,MCU_EXT_REFCLK0 (Pin),EXT_REFCLK1 (Pin),MCU_SYSCLK0,MAIN_SYSCLK0"
group.long 0xA160++0x03
line.long 0x00 "CFG0_EMMC0_CLKSEL_PROXY,"
bitfld.long 0x00 16. "EMMC0_CLKSEL_EMMCSD_IO_CLKLB_SEL_PROXY,Selects IO Pad Loopback for the MMC Module Field values (others are reserved)" "Loopback from Unbonded Pad MMCSD0_CLKLB,Loopback from IO Pin MMCSD0_CLK"
newline
bitfld.long 0x00 0. "EMMC0_CLKSEL_EMMCSD_REFCLK_SEL_PROXY,Selects the functional clock for the MMC Module Field values (others are reserved)" "MAIN_PLL0_HSDIV5_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT"
group.long 0xA168++0x07
line.long 0x00 "CFG0_EMMC1_CLKSEL_PROXY,"
bitfld.long 0x00 16. "EMMC1_CLKSEL_EMMCSD_IO_CLKLB_SEL_PROXY,Selects IO Pad Loopback for the MMC Module Field values (others are reserved)" "Loopback from Unbonded Pad MMCSD1_CLKLB,Loopback from IO Pin MMCSD1_CLK"
newline
bitfld.long 0x00 0. "EMMC1_CLKSEL_EMMCSD_REFCLK_SEL_PROXY,Selects the functional clock for the MMC Module Field values (others are reserved)" "MAIN_PLL0_HSDIV5_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT"
line.long 0x04 "CFG0_EMMC2_CLKSEL_PROXY,"
bitfld.long 0x04 16. "EMMC2_CLKSEL_EMMCSD_IO_CLKLB_SEL_PROXY,Selects IO Pad Loopback for the MMC Module Field values (others are reserved)" "Loopback from Unbonded Pad MMCSD2_CLKLB,Loopback from IO Pin MMCSD2_CLK"
newline
bitfld.long 0x04 0. "EMMC2_CLKSEL_EMMCSD_REFCLK_SEL_PROXY,Selects the functional clock for the MMC Module Field values (others are reserved)" "MAIN_PLL0_HSDIV5_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT"
group.long 0xA180++0x03
line.long 0x00 "CFG0_GPMC_CLKSEL_PROXY,"
bitfld.long 0x00 0. "GPMC_CLKSEL_CLK_SEL_PROXY,Selects the GPMC clock source: Field values (others are reserved)" "MAIN_PLL0_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV7_CLKOUT"
group.long 0xA1B0++0x1F
line.long 0x00 "CFG0_TIMER0_CLKSEL_PROXY,"
bitfld.long 0x00 0.--3. "TIMER0_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x04 "CFG0_TIMER1_CLKSEL_PROXY,"
bitfld.long 0x04 0.--3. "TIMER1_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x08 "CFG0_TIMER2_CLKSEL_PROXY,"
bitfld.long 0x08 0.--3. "TIMER2_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x0C "CFG0_TIMER3_CLKSEL_PROXY,"
bitfld.long 0x0C 0.--3. "TIMER3_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x10 "CFG0_TIMER4_CLKSEL_PROXY,"
bitfld.long 0x10 0.--3. "TIMER4_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x14 "CFG0_TIMER5_CLKSEL_PROXY,"
bitfld.long 0x14 0.--3. "TIMER5_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x18 "CFG0_TIMER6_CLKSEL_PROXY,"
bitfld.long 0x18 0.--3. "TIMER6_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x1C "CFG0_TIMER7_CLKSEL_PROXY,"
bitfld.long 0x1C 0.--3. "TIMER7_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
group.long 0xA200++0x0B
line.long 0x00 "CFG0_SPI0_CLKSEL_PROXY,"
bitfld.long 0x00 16. "SPI0_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
line.long 0x04 "CFG0_SPI1_CLKSEL_PROXY,"
bitfld.long 0x04 16. "SPI1_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
line.long 0x08 "CFG0_SPI2_CLKSEL_PROXY,"
bitfld.long 0x08 16. "SPI2_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
group.long 0xA240++0x1B
line.long 0x00 "CFG0_USART0_CLK_CTRL_PROXY,"
bitfld.long 0x00 16. "USART0_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART0 clock programmable divider value" "0,1"
newline
bitfld.long 0x00 0.--1. "USART0_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x04 "CFG0_USART1_CLK_CTRL_PROXY,"
bitfld.long 0x04 16. "USART1_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART1 clock programmable divider value" "0,1"
newline
bitfld.long 0x04 0.--1. "USART1_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x08 "CFG0_USART2_CLK_CTRL_PROXY,"
bitfld.long 0x08 16. "USART2_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART2 clock programmable divider value" "0,1"
newline
bitfld.long 0x08 0.--1. "USART2_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x0C "CFG0_USART3_CLK_CTRL_PROXY,"
bitfld.long 0x0C 16. "USART3_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART3 clock programmable divider value" "0,1"
newline
bitfld.long 0x0C 0.--1. "USART3_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x10 "CFG0_USART4_CLK_CTRL_PROXY,"
bitfld.long 0x10 16. "USART4_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART4 clock programmable divider value" "0,1"
newline
bitfld.long 0x10 0.--1. "USART4_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x14 "CFG0_USART5_CLK_CTRL_PROXY,"
bitfld.long 0x14 16. "USART5_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART5 clock programmable divider value" "0,1"
newline
bitfld.long 0x14 0.--1. "USART5_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x18 "CFG0_USART6_CLK_CTRL_PROXY,"
bitfld.long 0x18 16. "USART6_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART6 clock programmable divider value" "0,1"
newline
bitfld.long 0x18 0.--1. "USART6_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
group.long 0xA280++0x1B
line.long 0x00 "CFG0_USART0_CLKSEL_PROXY,"
bitfld.long 0x00 0. "USART0_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART0: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x04 "CFG0_USART1_CLKSEL_PROXY,"
bitfld.long 0x04 0. "USART1_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART1: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x08 "CFG0_USART2_CLKSEL_PROXY,"
bitfld.long 0x08 0. "USART2_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART2: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x0C "CFG0_USART3_CLKSEL_PROXY,"
bitfld.long 0x0C 0. "USART3_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART3: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x10 "CFG0_USART4_CLKSEL_PROXY,"
bitfld.long 0x10 0. "USART4_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART4: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x14 "CFG0_USART5_CLKSEL_PROXY,"
bitfld.long 0x14 0. "USART5_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART5: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x18 "CFG0_USART6_CLKSEL_PROXY,"
bitfld.long 0x18 0. "USART6_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART6: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
group.long 0xA2E0++0x07
line.long 0x00 "CFG0_AUDIO_REFCLK0_CTRL_PROXY,"
bitfld.long 0x00 15. "AUDIO_REFCLK0_CTRL_CLKOUT_EN_PROXY,AUDIO_REFCLK 0 output activate This bit is inverted to drive the active low output buffer activate" "AUDIO_EXT_REFCLK0 pin is configured as an input,AUDIO_EXT_REFCLK0 pin is configured as an output"
newline
bitfld.long 0x00 0.--2. "AUDIO_REFCLK0_CTRL_CLK_SEL_PROXY,Selects the source of AUDIO_REFCLK0 Field values (others are reserved)" "MCASP0_AHCLKR,MCASP1_AHCLKR,MCASP2_AHCLKR,MCASP0_AHCLKX,MCASP1_AHCLKX,MCASP2_AHCLKX,MAIN_PLL1_HSDIV6_CLKOUT,MAIN_PLL1_HSDIV8_CLKOUT"
line.long 0x04 "CFG0_AUDIO_REFCLK1_CTRL_PROXY,"
bitfld.long 0x04 15. "AUDIO_REFCLK1_CTRL_CLKOUT_EN_PROXY,AUDIO_REFCLK 1 output activate This bit is inverted to drive the active low output buffer activate" "AUDIO_EXT_REFCLK1 pin is configured as an input,AUDIO_EXT_REFCLK1 pin is configured as an output"
newline
bitfld.long 0x04 0.--2. "AUDIO_REFCLK1_CTRL_CLK_SEL_PROXY,Selects the source of AUDIO_REFCLK1 Field values (others are reserved)" "MCASP0_AHCLKR,MCASP1_AHCLKR,MCASP2_AHCLKR,MCASP0_AHCLKX,MCASP1_AHCLKX,MCASP2_AHCLKX,MAIN_PLL1_HSDIV6_CLKOUT,MAIN_PLL1_HSDIV8_CLKOUT"
group.long 0xA300++0x03
line.long 0x00 "CFG0_DPI0_CLK_CTRL_PROXY,"
bitfld.long 0x00 9. "DPI0_CLK_CTRL_SYNC_CLK_INVDIS_PROXY,Clock edge select for DPI0 sync outputs" "HSYNC and VSYNC are driven on the falling edge..,HSYNC and VSYNC are driven on the rising edge of.."
newline
bitfld.long 0x00 8. "DPI0_CLK_CTRL_DATA_CLK_INVDIS_PROXY,Clock edge select for DPI0 data outputs" "DATA and DE are driven on the falling edge of clk,DATA and DE are driven on the rising edge of clk.."
group.long 0xA320++0x03
line.long 0x00 "CFG0_DSS_DISPC0_CLKSEL1_PROXY,"
bitfld.long 0x00 0. "DSS_DISPC0_CLKSEL1_DPI1_PCLK_PROXY,DPI Lane 1 pixel Clock Source Field values (others are reserved)" "MAIN_PLL17_HSDIV0_CLKOUT,VOUT0_EXTPCLKIN"
group.long 0xA330++0x0B
line.long 0x00 "CFG0_MCASP0_CLKSEL_PROXY,"
bitfld.long 0x00 0. "MCASP0_CLKSEL_AUXCLK_SEL_PROXY,Selects the AUXCLK input source for McASP0 Field values (others are reserved)" "MAIN_PLL2_HSDIV8_CLKOUT,MAIN_PLL1_HSDIV6_CLKOUT"
line.long 0x04 "CFG0_MCASP1_CLKSEL_PROXY,"
bitfld.long 0x04 0. "MCASP1_CLKSEL_AUXCLK_SEL_PROXY,Selects the AUXCLK input source for McASP0 Field values (others are reserved)" "MAIN_PLL2_HSDIV8_CLKOUT,MAIN_PLL1_HSDIV6_CLKOUT"
line.long 0x08 "CFG0_MCASP2_CLKSEL_PROXY,"
bitfld.long 0x08 0. "MCASP2_CLKSEL_AUXCLK_SEL_PROXY,Selects the AUXCLK input source for McASP0 Field values (others are reserved)" "MAIN_PLL2_HSDIV8_CLKOUT,MAIN_PLL1_HSDIV6_CLKOUT"
group.long 0xA350++0x0B
line.long 0x00 "CFG0_MCASP0_AHCLKSEL_PROXY,"
bitfld.long 0x00 8.--9. "MCASP0_AHCLKSEL_AHCLKX_SEL_PROXY,Selects the AHCLKX input source for McASP0 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
newline
bitfld.long 0x00 0.--1. "MCASP0_AHCLKSEL_AHCLKR_SEL_PROXY,Selects the AHCLKR input source for McASP0 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
line.long 0x04 "CFG0_MCASP1_AHCLKSEL_PROXY,"
bitfld.long 0x04 8.--9. "MCASP1_AHCLKSEL_AHCLKX_SEL_PROXY,Selects the AHCLKX input source for McASP1 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
newline
bitfld.long 0x04 0.--1. "MCASP1_AHCLKSEL_AHCLKR_SEL_PROXY,Selects the AHCLKR input source for McASP1 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
line.long 0x08 "CFG0_MCASP2_AHCLKSEL_PROXY,"
bitfld.long 0x08 8.--9. "MCASP2_AHCLKSEL_AHCLKX_SEL_PROXY,Selects the AHCLKX input source for McASP2 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
newline
bitfld.long 0x08 0.--1. "MCASP2_AHCLKSEL_AHCLKR_SEL_PROXY,Selects the AHCLKR input source for McASP2 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
group.long 0xA380++0x0F
line.long 0x00 "CFG0_WWD0_CLKSEL_PROXY,"
bitfld.long 0x00 31. "WWD0_CLKSEL_WRTLOCK_PROXY,When set locks WWD0_CLKSEL from further writes until the next module reset" "0,1"
newline
bitfld.long 0x00 0.--1. "WWD0_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
line.long 0x04 "CFG0_WWD1_CLKSEL_PROXY,"
bitfld.long 0x04 31. "WWD1_CLKSEL_WRTLOCK_PROXY,When set locks WWD1_CLKSEL from further writes until the next module reset" "0,1"
newline
bitfld.long 0x04 0.--1. "WWD1_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
line.long 0x08 "CFG0_WWD2_CLKSEL_PROXY,"
bitfld.long 0x08 31. "WWD2_CLKSEL_WRTLOCK_PROXY,When set locks WWD2_CLKSEL from further writes until the next module reset" "0,1"
newline
bitfld.long 0x08 0.--1. "WWD2_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
line.long 0x0C "CFG0_WWD3_CLKSEL_PROXY,"
bitfld.long 0x0C 31. "WWD3_CLKSEL_WRTLOCK_PROXY,When set locks WWD3_CLKSEL from further writes until the next module reset" "0,1"
newline
bitfld.long 0x0C 0.--1. "WWD3_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
group.long 0xA3BC++0x03
line.long 0x00 "CFG0_WWD15_CLKSEL_PROXY,"
bitfld.long 0x00 31. "WWD15_CLKSEL_WRTLOCK_PROXY,When set locks WWD15_CLKSEL from further writes until the next module reset" "0,1"
newline
bitfld.long 0x00 0.--1. "WWD15_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
group.long 0xA480++0x03
line.long 0x00 "CFG0_MCAN0_CLKSEL_PROXY,"
bitfld.long 0x00 0.--1. "MCAN0_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection" "MAIN_PLL0_HSDIV4_CLKOUT,MCU_EXT_REFCLK0,EXT_REFCLK1 (pin),HFOSC0_CLKOUT"
group.long 0xA500++0x03
line.long 0x00 "CFG0_OSPI0_CLKSEL_PROXY,"
bitfld.long 0x00 4. "OSPI0_CLKSEL_LOOPCLK_SEL_PROXY,OBSPI0 Loopback clock source Field values (others are reserved)" "Board Level Loopback,Internal Loopback"
newline
bitfld.long 0x00 0. "OSPI0_CLKSEL_CLK_SEL_PROXY,OSPI0 reference clock selection Field values (others are reserved)" "MAIN_PLL0_HSDIV1_CLKOUT,MAIN_PLL1_HSDIV5_CLKOUT"
group.long 0xA600++0x13
line.long 0x00 "CFG0_OLDI0_DAT0_IO_CTRL_PROXY,"
bitfld.long 0x00 31. "OLDI0_DAT0_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
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bitfld.long 0x00 30. "OLDI0_DAT0_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
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bitfld.long 0x00 24.--25. "OLDI0_DAT0_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x00 16.--19. "OLDI0_DAT0_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13. "OLDI0_DAT0_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x00 12. "OLDI0_DAT0_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 11. "OLDI0_DAT0_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 10. "OLDI0_DAT0_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
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bitfld.long 0x00 9. "OLDI0_DAT0_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x00 8. "OLDI0_DAT0_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
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bitfld.long 0x00 1.--3. "OLDI0_DAT0_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "OLDI0_DAT0_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x04 "CFG0_OLDI0_DAT1_IO_CTRL_PROXY,"
bitfld.long 0x04 31. "OLDI0_DAT1_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x04 30. "OLDI0_DAT1_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x04 24.--25. "OLDI0_DAT1_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x04 16.--19. "OLDI0_DAT1_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 13. "OLDI0_DAT1_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x04 12. "OLDI0_DAT1_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 11. "OLDI0_DAT1_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 10. "OLDI0_DAT1_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x04 9. "OLDI0_DAT1_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x04 8. "OLDI0_DAT1_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 1.--3. "OLDI0_DAT1_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "OLDI0_DAT1_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x08 "CFG0_OLDI0_DAT2_IO_CTRL_PROXY,"
bitfld.long 0x08 31. "OLDI0_DAT2_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x08 30. "OLDI0_DAT2_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x08 24.--25. "OLDI0_DAT2_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x08 16.--19. "OLDI0_DAT2_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 13. "OLDI0_DAT2_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x08 12. "OLDI0_DAT2_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 11. "OLDI0_DAT2_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 10. "OLDI0_DAT2_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x08 9. "OLDI0_DAT2_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x08 8. "OLDI0_DAT2_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 1.--3. "OLDI0_DAT2_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0. "OLDI0_DAT2_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x0C "CFG0_OLDI0_DAT3_IO_CTRL_PROXY,"
bitfld.long 0x0C 31. "OLDI0_DAT3_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x0C 30. "OLDI0_DAT3_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x0C 24.--25. "OLDI0_DAT3_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x0C 16.--19. "OLDI0_DAT3_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 13. "OLDI0_DAT3_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x0C 12. "OLDI0_DAT3_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 11. "OLDI0_DAT3_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 10. "OLDI0_DAT3_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x0C 9. "OLDI0_DAT3_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x0C 8. "OLDI0_DAT3_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 1.--3. "OLDI0_DAT3_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "OLDI0_DAT3_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x10 "CFG0_OLDI0_CLK_IO_CTRL_PROXY,"
bitfld.long 0x10 31. "OLDI0_CLK_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x10 30. "OLDI0_CLK_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x10 24.--25. "OLDI0_CLK_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x10 16.--19. "OLDI0_CLK_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 13. "OLDI0_CLK_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x10 12. "OLDI0_CLK_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 11. "OLDI0_CLK_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 10. "OLDI0_CLK_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x10 9. "OLDI0_CLK_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x10 8. "OLDI0_CLK_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 1.--3. "OLDI0_CLK_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0. "OLDI0_CLK_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
group.long 0xA620++0x13
line.long 0x00 "CFG0_OLDI1_DAT0_IO_CTRL_PROXY,"
bitfld.long 0x00 31. "OLDI1_DAT0_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x00 30. "OLDI1_DAT0_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x00 24.--25. "OLDI1_DAT0_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x00 16.--19. "OLDI1_DAT0_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13. "OLDI1_DAT0_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x00 12. "OLDI1_DAT0_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 11. "OLDI1_DAT0_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 10. "OLDI1_DAT0_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x00 9. "OLDI1_DAT0_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x00 8. "OLDI1_DAT0_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 1.--3. "OLDI1_DAT0_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "OLDI1_DAT0_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x04 "CFG0_OLDI1_DAT1_IO_CTRL_PROXY,"
bitfld.long 0x04 31. "OLDI1_DAT1_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x04 30. "OLDI1_DAT1_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x04 24.--25. "OLDI1_DAT1_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x04 16.--19. "OLDI1_DAT1_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 13. "OLDI1_DAT1_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x04 12. "OLDI1_DAT1_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 11. "OLDI1_DAT1_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 10. "OLDI1_DAT1_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x04 9. "OLDI1_DAT1_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x04 8. "OLDI1_DAT1_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 1.--3. "OLDI1_DAT1_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "OLDI1_DAT1_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x08 "CFG0_OLDI1_DAT2_IO_CTRL_PROXY,"
bitfld.long 0x08 31. "OLDI1_DAT2_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x08 30. "OLDI1_DAT2_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x08 24.--25. "OLDI1_DAT2_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x08 16.--19. "OLDI1_DAT2_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 13. "OLDI1_DAT2_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x08 12. "OLDI1_DAT2_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 11. "OLDI1_DAT2_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 10. "OLDI1_DAT2_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x08 9. "OLDI1_DAT2_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x08 8. "OLDI1_DAT2_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 1.--3. "OLDI1_DAT2_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0. "OLDI1_DAT2_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x0C "CFG0_OLDI1_DAT3_IO_CTRL_PROXY,"
bitfld.long 0x0C 31. "OLDI1_DAT3_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x0C 30. "OLDI1_DAT3_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x0C 24.--25. "OLDI1_DAT3_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x0C 16.--19. "OLDI1_DAT3_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 13. "OLDI1_DAT3_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x0C 12. "OLDI1_DAT3_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 11. "OLDI1_DAT3_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 10. "OLDI1_DAT3_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x0C 9. "OLDI1_DAT3_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x0C 8. "OLDI1_DAT3_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 1.--3. "OLDI1_DAT3_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "OLDI1_DAT3_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x10 "CFG0_OLDI1_CLK_IO_CTRL_PROXY,"
bitfld.long 0x10 31. "OLDI1_CLK_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x10 30. "OLDI1_CLK_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x10 24.--25. "OLDI1_CLK_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x10 16.--19. "OLDI1_CLK_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 13. "OLDI1_CLK_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x10 12. "OLDI1_CLK_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 11. "OLDI1_CLK_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 10. "OLDI1_CLK_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x10 9. "OLDI1_CLK_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x10 8. "OLDI1_CLK_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 1.--3. "OLDI1_CLK_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0. "OLDI1_CLK_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
group.long 0xA700++0x07
line.long 0x00 "CFG0_OLDI_PD_CTRL_PROXY,"
rbitfld.long 0x00 31. "OLDI_PD_CTRL_BGOK_PROXY,Status of the Bandgap" "0,1"
newline
bitfld.long 0x00 8. "OLDI_PD_CTRL_PD_BG_PROXY,When Set forces the LVDS Bandgap into Power Down" "0,1"
newline
bitfld.long 0x00 1. "OLDI_PD_CTRL_PD_OLDI1_PROXY,When Set overrides the biase_en of all OLDI1 LVDS IO to force power down" "0,1"
newline
bitfld.long 0x00 0. "OLDI_PD_CTRL_PD_OLDI0_PROXY,When Set overrides the biase_en of all OLDI0 LVDS IO to force power down" "0,1"
line.long 0x04 "CFG0_OLDI_LB_CTRL_PROXY,"
bitfld.long 0x04 0. "OLDI_LB_CTRL_OLDI_SEL_PROXY,When" "OLDI0 loopback data is routed to DSS,OLDI1 loopback data is routed to DSS"
group.long 0xB008++0x07
line.long 0x00 "CFG0_LOCK2_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK2_KICK1_PROXY,"
repeat 15. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
group.long ($2+0xB100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P2_R$1,"
repeat.end
group.long 0x10500++0x03
line.long 0x00 "CFG0_MAIN_PLL_TEST_CLKSEL,"
bitfld.long 0x00 17. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL17,Selects the alternate clock source for MAIN PLL17 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 16. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL16,Selects the alternate clock source for MAIN PLL16 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 12. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL12,Selects the alternate clock source for MAIN PLL12 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 8. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL8,Selects the alternate clock source for MAIN PLL8 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 2. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL2,Selects the alternate clock source for MAIN PLL2 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 1. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL1,Selects the alternate clock source for MAIN PLL1 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 0. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL0,Selects the alternate clock source for MAIN PLL0 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
group.long 0x11008++0x07
line.long 0x00 "CFG0_LOCK4_KICK0,"
line.long 0x04 "CFG0_LOCK4_KICK1,"
rgroup.long 0x11100++0x2B
line.long 0x00 "CFG0_CLAIMREG_P4_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P4_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P4_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P4_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P4_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P4_R5_READONLY,"
line.long 0x18 "CFG0_CLAIMREG_P4_R6_READONLY,"
line.long 0x1C "CFG0_CLAIMREG_P4_R7_READONLY,"
line.long 0x20 "CFG0_CLAIMREG_P4_R8_READONLY,"
line.long 0x24 "CFG0_CLAIMREG_P4_R9_READONLY,"
line.long 0x28 "CFG0_CLAIMREG_P4_R10_READONLY,"
group.long 0x12500++0x03
line.long 0x00 "CFG0_MAIN_PLL_TEST_CLKSEL_PROXY,"
bitfld.long 0x00 17. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL17_PROXY,Selects the alternate clock source for MAIN PLL17 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 16. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL16_PROXY,Selects the alternate clock source for MAIN PLL16 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 12. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL12_PROXY,Selects the alternate clock source for MAIN PLL12 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 8. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL8_PROXY,Selects the alternate clock source for MAIN PLL8 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 2. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL2_PROXY,Selects the alternate clock source for MAIN PLL2 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 1. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL1_PROXY,Selects the alternate clock source for MAIN PLL1 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 0. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL0_PROXY,Selects the alternate clock source for MAIN PLL0 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
group.long 0x13008++0x07
line.long 0x00 "CFG0_LOCK4_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK4_KICK1_PROXY,"
repeat 11. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 )
group.long ($2+0x13100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P4_R$1,"
repeat.end
group.long 0x19008++0x07
line.long 0x00 "CFG0_LOCK6_KICK0,"
line.long 0x04 "CFG0_LOCK6_KICK1,"
rgroup.long 0x19100++0x23
line.long 0x00 "CFG0_CLAIMREG_P6_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P6_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P6_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P6_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P6_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P6_R5_READONLY,"
line.long 0x18 "CFG0_CLAIMREG_P6_R6_READONLY,"
line.long 0x1C "CFG0_CLAIMREG_P6_R7_READONLY,"
line.long 0x20 "CFG0_CLAIMREG_P6_R8_READONLY,"
group.long 0x1B008++0x07
line.long 0x00 "CFG0_LOCK6_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK6_KICK1_PROXY,"
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
group.long ($2+0x1B100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P6_R$1,"
repeat.end
tree.end
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list ad:0x800000 ad:0x804000 ad:0x808000 ad:0x80C000 ad:0x810000 ad:0x814000 ad:0x818000)
tree "DCC$1"
base $2
group.long 0x00++0x37
line.long 0x00 "CFG_DCCGCTRL,Starts / stops the counters"
bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..."
newline
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CFG_DCCREV,Specifies the module version"
bitfld.long 0x04 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01" "0,1,2,3"
hexmask.long.word 0x04 16.--27. 1. "FUNC,Reflects software-compatability"
newline
bitfld.long 0x04 11.--15. "RTL,Incremented for releases due to spec changes or post-release design changes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 6.--7. "CUSTOM,Indicates a special version of the module" "0,1,2,3"
bitfld.long 0x04 0.--5. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)"
line.long 0x0C "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)"
line.long 0x14 "CFG_DCCSTAT,Specifies the status of the DCC Module"
bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag"
bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occured" "no effect,clear the error flag"
line.long 0x18 "CFG_DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "CFG_DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "CFG_DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "CFG_DCCCLKSRC1,Selects the clock source for counter 1"
bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection for counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 0.--4. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x28 "CFG_DCCCLKSRC0,Selects the clock source for counter 0"
bitfld.long 0x28 12.--15. "KEY,This field enables or disables clock source selection for counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC"
bitfld.long 0x2C 8.--11. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 4.--7. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 0.--3. "CONT_ON_ERR,Continues to next window of comparison despite the error condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs"
bitfld.long 0x30 5. "COUNT1_FIFO_FULL,Count1 FIFO Full" "Count1 FIFO is not full,Count1 FIFO is full"
bitfld.long 0x30 4. "VALID0_FIFO_FULL,Valid0 FIFO Full" "Valid0 FIFO is not full,Valid0 FIFO is full"
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bitfld.long 0x30 3. "COUNT0_FIFO_FULL,Count0 FIFO Full" "Count0 FIFO is not full,Count0 FIFO is full"
bitfld.long 0x30 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty" "Count1 FIFO is not empty,Count1 FIFO is empty"
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bitfld.long 0x30 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty" "Valid0 FIFO is not empty,Valid0 FIFO is empty"
bitfld.long 0x30 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty" "Count0 FIFO is not empty,Count0 FIFO is empty"
line.long 0x34 "CFG_DCCERRCNT,Counts number of errors since last clear"
hexmask.long.word 0x34 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset"
tree.end
repeat.end
tree "DDR16SS0_REGS_SS_CFG_SSCFG"
base ad:0xF300000
rgroup.long 0x00++0x07
line.long 0x00 "REGS__SS_CFG__SSCFG_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem"
hexmask.long.word 0x00 16.--31. 1. "MOD_ID,Module ID"
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bitfld.long 0x00 11.--15. "RTL_VER,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJ_REV,Major revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MIN_REV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "REGS__SS_CFG__SSCFG_SS_CTL_REG,The Subsystem Control Register contains fields for control functions required for submodules in the subsystem"
bitfld.long 0x04 0. "PHY_PLL_BYPASS,Cadence PHY De-Skew PLL bypass" "0,1"
group.long 0x20++0x1F
line.long 0x00 "REGS__SS_CFG__SSCFG_V2A_CTL_REG,The VBUSM2AXI Control register contains control functions required for the VBUSM2AXI submodule"
bitfld.long 0x00 10. "SDRAM_3QT,Setting this field to a 1 will modify SDRAM Index to be 3/4 its programmed value to support 3 6 12 and 24 GB sizes" "0,1"
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bitfld.long 0x00 5.--9. "SDRAM_IDX,SDRAM Index = log2(connected SDRAM size) - 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "REGION_IDX,Region Index = log2(CBA region size) - 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "REGS__SS_CFG__SSCFG_V2A_R1_MAT_REG,The Range 1 Match Register allows a single master to a range of masters to change their priority mapping"
bitfld.long 0x04 31. "RANGE1_RANGEEN_A,The range1_rangeen_a enables the RouteID AND'd with range1_mask_a to match the range1_routeid_a" "0,1"
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bitfld.long 0x04 28.--30. "RANGE1_MASK_A,The range1_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x04 16.--27. 1. "RANGE1_ROUTEID_A,The range1_routeid_a is the value that is compared to the RouteID arriving on the command interface"
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bitfld.long 0x04 15. "RANGE1_RANGEEN_B,The range1_rangeen_b enables the RouteID AND'd with range1_mask_b to match the range1_routeid_b" "0,1"
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bitfld.long 0x04 12.--14. "RANGE1_MASK_B,The range1_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x04 0.--11. 1. "RANGE1_ROUTEID_B,The range1_routeid_b is the value that is compared to the RouteID arriving on the command interface"
line.long 0x08 "REGS__SS_CFG__SSCFG_V2A_R2_MAT_REG,The Range 2 Match Register allows a single master to a range of masters to change their priority mapping"
bitfld.long 0x08 31. "RANGE2_RANGEEN_A,The range2_rangeen_a enables the RouteID AND'd with range2_mask_a to match the range2_routeid_a" "0,1"
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bitfld.long 0x08 28.--30. "RANGE2_MASK_A,The range2_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x08 16.--27. 1. "RANGE2_ROUTEID_A,The range2_routeid_a is the value that is compared to the RouteID arriving on the command interface"
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bitfld.long 0x08 15. "RANGE2_RANGEEN_B,The range2_rangeen_b enables the RouteID AND'd with range2_mask_b to match the range2_routeid_b" "0,1"
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bitfld.long 0x08 12.--14. "RANGE2_MASK_B,The range2_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x08 0.--11. 1. "RANGE2_ROUTEID_B,The range2_routeid_b is the value that is compared to the RouteID arriving on the command interface"
line.long 0x0C "REGS__SS_CFG__SSCFG_V2A_R3_MAT_REG,The Range 3 Match Register allows a single master to a range of masters to change their priority mapping"
bitfld.long 0x0C 31. "RANGE3_RANGEEN_A,The range3_rangeen_a enables the RouteID AND'd with range3_mask_a to match the range3_routeid_a" "0,1"
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bitfld.long 0x0C 28.--30. "RANGE3_MASK_A,The range3_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0C 16.--27. 1. "RANGE3_ROUTEID_A,The range3_routeid_a is the value that is compared to the RouteID arriving on the command interface"
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bitfld.long 0x0C 15. "RANGE3_RANGEEN_B,The range3_rangeen_b enables the RouteID AND'd with range3_mask_b to match the range3_routeid_b" "0,1"
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bitfld.long 0x0C 12.--14. "RANGE3_MASK_B,The range3_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0C 0.--11. 1. "RANGE3_ROUTEID_B,The range3_routeid_b is the value that is compared to the RouteID arriving on the command interface"
line.long 0x10 "REGS__SS_CFG__SSCFG_V2A_DEF_PRI_MAP_REG,The Default Priority Mapping Register is the default map for the inbound VBUSM.C priority to AXI priority"
bitfld.long 0x10 28.--30. "PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x10 24.--26. "PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x10 20.--22. "PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x10 16.--18. "PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x10 12.--14. "PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x10 8.--10. "PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x10 4.--6. "PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x10 0.--2. "PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7" "highest priority,?,?,?,?,?,?,lowest priority"
line.long 0x14 "REGS__SS_CFG__SSCFG_V2A_R1_PRI_MAP_REG,The Range 1 Priority Mapping Register is used to map the inbound VBUSM.C priority to AXI priority when a RouteID match 1 occurs"
bitfld.long 0x14 28.--30. "RANGE1_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 1" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x14 24.--26. "RANGE1_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 1" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x14 20.--22. "RANGE1_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 1" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x14 16.--18. "RANGE1_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 1" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x14 12.--14. "RANGE1_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 1" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x14 8.--10. "RANGE1_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 1" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x14 4.--6. "RANGE1_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 1" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x14 0.--2. "RANGE1_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 1" "highest priority,?,?,?,?,?,?,lowest priority"
line.long 0x18 "REGS__SS_CFG__SSCFG_V2A_R2_PRI_MAP_REG,The Range 2 Priority Mapping Register is used to map the inbound VBUSM.C priority to AXI priority when a RouteID match 2 occurs"
bitfld.long 0x18 28.--30. "RANGE2_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 2" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x18 24.--26. "RANGE2_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 2" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x18 20.--22. "RANGE2_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 2" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x18 16.--18. "RANGE2_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 2" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x18 12.--14. "RANGE2_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 2" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x18 8.--10. "RANGE2_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 2" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x18 4.--6. "RANGE2_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 2" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x18 0.--2. "RANGE2_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 2" "highest priority,?,?,?,?,?,?,lowest priority"
line.long 0x1C "REGS__SS_CFG__SSCFG_V2A_R3_PRI_MAP_REG,The Range 3 Priority Mapping Register is used to map the inbound VBUSM.C priority to AXI priority when a RouteID match 3 occurs"
bitfld.long 0x1C 28.--30. "RANGE3_PRIMAP0,The field contains AXI priority value for VBUSM.C priority 0 for range match 3" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x1C 24.--26. "RANGE3_PRIMAP1,The field contains AXI priority value for VBUSM.C priority 1 for range match 3" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x1C 20.--22. "RANGE3_PRIMAP2,The field contains AXI priority value for VBUSM.C priority 2 for range match 3" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x1C 16.--18. "RANGE3_PRIMAP3,The field contains AXI priority value for VBUSM.C priority 3 for range match 3" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x1C 12.--14. "RANGE3_PRIMAP4,The field contains AXI priority value for VBUSM.C priority 4 for range match 3" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x1C 8.--10. "RANGE3_PRIMAP5,The field contains AXI priority value for VBUSM.C priority 5 for range match 3" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x1C 4.--6. "RANGE3_PRIMAP6,The field contains AXI priority value for VBUSM.C priority 6 for range match 3" "highest priority,?,?,?,?,?,?,lowest priority"
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bitfld.long 0x1C 0.--2. "RANGE3_PRIMAP7,The field contains AXI priority value for VBUSM.C priority 7 for range match 3" "highest priority,?,?,?,?,?,?,lowest priority"
group.long 0x70++0x07
line.long 0x00 "REGS__SS_CFG__SSCFG_V2A_AERR_LOG1_REG,The Address Error Log 1 register displays the RouteID and lsb of the address for the first VBUSM.C command that was outside the programmed addressing range"
hexmask.long.word 0x00 16.--31. 1. "AERR_ADDR_LSB,Address[15:0] of the VBUSM.C command"
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hexmask.long.word 0x00 0.--11. 1. "AERR_ROUTE_ID,RouteID of the VBUSM.C write command"
line.long 0x04 "REGS__SS_CFG__SSCFG_V2A_AERR_LOG2_REG,The Address Error Log 2 registers displays the msb of the address for the first VBUSM.C command that was outside the programmed addressing range"
group.long 0x9C++0x17
line.long 0x00 "REGS__SS_CFG__SSCFG_V2A_BUS_TO,"
hexmask.long.tbyte 0x00 0.--23. 1. "BUS_TIMER,AXI bus timeout value"
line.long 0x04 "REGS__SS_CFG__SSCFG_V2A_INT_RAW_REG,"
bitfld.long 0x04 5. "ECCM1BERR,Raw status of SDRAM ECC multi 1-bit errors in same SDRAM burst" "0,1"
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bitfld.long 0x04 4. "ECC2BERR,Raw status of SDRAM ECC 2-bit error" "0,1"
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bitfld.long 0x04 3. "ECC1BERR,Raw status of SDRAM ECC 1-bit error" "0,1"
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bitfld.long 0x04 2. "TOERR,Raw status of VBUSM2AXI interrupt for controller AXI interface timeout" "0,1"
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bitfld.long 0x04 1. "AERR,Raw status of VBUSM2AXI interrupt for VBUSM.C address outside the programmed range" "0,1"
line.long 0x08 "REGS__SS_CFG__SSCFG_V2A_INT_STAT_REG,"
bitfld.long 0x08 5. "ECCM1BERR,Enabled status of SDRAM ECC multi 1-bit errors in same SDRAM burst" "0,1"
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bitfld.long 0x08 4. "ECC2BERR,Enabled status of SDRAM ECC 2-bit error" "0,1"
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bitfld.long 0x08 3. "ECC1BERR,Enabled status of SDRAM ECC 1-bit error" "0,1"
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bitfld.long 0x08 2. "TOERR,Enabled status of VBUSM2AXI interrupt for controller AXI interface timeout" "0,1"
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bitfld.long 0x08 1. "AERR,Enabled status of VBUSM2AXI interrupt for VBUSM.C address outside the programmed range" "0,1"
line.long 0x0C "REGS__SS_CFG__SSCFG_V2A_INT_SET_REG,"
bitfld.long 0x0C 5. "ECCM1BERR_EN,Enable set for SDRAM ECC multi 1-bit errors in same SDRAM burst" "0,1"
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bitfld.long 0x0C 4. "ECC2BERR_EN,Enable set for SDRAM ECC 2-bit error" "0,1"
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bitfld.long 0x0C 3. "ECC1BERR_EN,Enable set for SDRAM ECC 1-bit error" "0,1"
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bitfld.long 0x0C 2. "TOERR_EN,Enable set for VBUSM2AXI interrupt for controller AXI interface timeout" "0,1"
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bitfld.long 0x0C 1. "AERR_EN,Enable set for VBUSM2AXI interrupt for VBUSM.C address outside the programmed range" "0,1"
line.long 0x10 "REGS__SS_CFG__SSCFG_V2A_INT_CLR_REG,"
bitfld.long 0x10 5. "ECCM1BERR_EN,Enable clear for SDRAM ECC multi 1-bit errors in same SDRAM burst" "0,1"
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bitfld.long 0x10 4. "ECC2BERR_EN,Enable clear for SDRAM ECC 2-bit error" "0,1"
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bitfld.long 0x10 3. "ECC1BERR_EN,Enable clear for SDRAM ECC 1-bit error" "0,1"
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bitfld.long 0x10 2. "TOERR_EN,Enable clear for VBUSM2AXI interrupt for controller AXI interface timeout" "0,1"
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bitfld.long 0x10 1. "AERR_EN,Enable clear for VBUSM2AXI interrupt for VBUSM.C address outside the programmed range" "0,1"
line.long 0x14 "REGS__SS_CFG__SSCFG_V2A_EOI_REG,"
bitfld.long 0x14 0.--1. "EOI,Software End Of Interrupt (EOI) control" "0,1,2,3"
group.long 0x100++0x13
line.long 0x00 "REGS__SS_CFG__SSCFG_PERF_CNT_SEL_REG,The Performance Counter Select register is used to select the statistic type to be counted in the corresponding Performance Counter register"
bitfld.long 0x00 24.--29. "CNT4_SEL,Statistic select for Performance Counter 4 register" "Counts every Write command,Counts every Read command,Counts every read as a result of a RMW command,Counts every Activate command,Counts every Precharge command,Counts every Precharge All command,Counts every Mode Register Read command,Counts every Mode Register Write command,Counts every Per Bank Refresh command,Counts every Auto Refresh command,Counts every ZQ Calib Long command,Counts every ZQ Calib Short command,Counts every Write-to-Read and Read-to-Write..,Counts every Write-to-Write address collision,Counts every Write-to-Read address collision,Counts every Read-to-Write address collision,Counts every Read-to-Read address collision,Counts every exit from Power-Down Self-Refresh..,Counts every entry into Power-Down Self-Refresh..,Counts every cycle for which the DDR Controller..,Counts every exit from Power-Down mode,Counts every entry into Power-Down mode,Counts every cycle for which the DDR Controller..,Counts every exit from Self-Refresh mode,Counts every entry into Self-Refresh mode,Counts every cycle for which the DDR Controller..,Reserved,Reserved,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,?..."
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bitfld.long 0x00 16.--21. "CNT3_SEL,Statistic select for Performance Counter 3 register" "Counts every Write command,Counts every Read command,Counts every read as a result of a RMW command,Counts every Activate command,Counts every Precharge command,Counts every Precharge All command,Counts every Mode Register Read command,Counts every Mode Register Write command,Counts every Per Bank Refresh command,Counts every Auto Refresh command,Counts every ZQ Calib Long command,Counts every ZQ Calib Short command,Counts every Write-to-Read and Read-to-Write..,Counts every Write-to-Write address collision,Counts every Write-to-Read address collision,Counts every Read-to-Write address collision,Counts every Read-to-Read address collision,Counts every exit from Power-Down Self-Refresh..,Counts every entry into Power-Down Self-Refresh..,Counts every cycle for which the DDR Controller..,Counts every exit from Power-Down mode,Counts every entry into Power-Down mode,Counts every cycle for which the DDR Controller..,Counts every exit from Self-Refresh mode,Counts every entry into Self-Refresh mode,Counts every cycle for which the DDR Controller..,Reserved,Reserved,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,?..."
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bitfld.long 0x00 8.--13. "CNT2_SEL,Statistic select for Performance Counter 2 register" "Counts every Write command,Counts every Read command,Counts every read as a result of a RMW command,Counts every Activate command,Counts every Precharge command,Counts every Precharge All command,Counts every Mode Register Read command,Counts every Mode Register Write command,Counts every Per Bank Refresh command,Counts every Auto Refresh command,Counts every ZQ Calib Long command,Counts every ZQ Calib Short command,Counts every Write-to-Read and Read-to-Write..,Counts every Write-to-Write address collision,Counts every Write-to-Read address collision,Counts every Read-to-Write address collision,Counts every Read-to-Read address collision,Counts every exit from Power-Down Self-Refresh..,Counts every entry into Power-Down Self-Refresh..,Counts every cycle for which the DDR Controller..,Counts every exit from Power-Down mode,Counts every entry into Power-Down mode,Counts every cycle for which the DDR Controller..,Counts every exit from Self-Refresh mode,Counts every entry into Self-Refresh mode,Counts every cycle for which the DDR Controller..,Reserved,Reserved,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,?..."
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bitfld.long 0x00 0.--5. "CNT1_SEL,Statistic select for Performance Counter 1 register" "Counts every Write command,Counts every Read command,Counts every read as a result of a RMW command,Counts every Activate command,Counts every Precharge command,Counts every Precharge All command,Counts every Mode Register Read command,Counts every Mode Register Write command,Counts every Per Bank Refresh command,Counts every Auto Refresh command,Counts every ZQ Calib Long command,Counts every ZQ Calib Short command,Counts every Write-to-Read and Read-to-Write..,Counts every Write-to-Write address collision,Counts every Write-to-Read address collision,Counts every Read-to-Write address collision,Counts every Read-to-Read address collision,Counts every exit from Power-Down Self-Refresh..,Counts every entry into Power-Down Self-Refresh..,Counts every cycle for which the DDR Controller..,Counts every exit from Power-Down mode,Counts every entry into Power-Down mode,Counts every cycle for which the DDR Controller..,Counts every exit from Self-Refresh mode,Counts every entry into Self-Refresh mode,Counts every cycle for which the DDR Controller..,Reserved,Reserved,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,Counts every cycle for which the DDR Controller..,?..."
line.long 0x04 "REGS__SS_CFG__SSCFG_PERF_CNT1_REG,"
line.long 0x08 "REGS__SS_CFG__SSCFG_PERF_CNT2_REG,"
line.long 0x0C "REGS__SS_CFG__SSCFG_PERF_CNT3_REG,"
line.long 0x10 "REGS__SS_CFG__SSCFG_PERF_CNT4_REG,"
group.long 0x120++0x0B
line.long 0x00 "REGS__SS_CFG__SSCFG_ECC_CTRL_REG,"
bitfld.long 0x00 8.--10. "COR_ECC_THRESH,Threshold for 1-bit ECC errors in multiple data words in an SDRAM burst that create an uncorrected error fault indication" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "WR_ALLOC,When set to 1 an unassigned ECC cache-line will be allocated for a write with routeID that do not match any of the mapped routeID's" "0,1"
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bitfld.long 0x00 2. "ECC_CK,Set 1 to enable ECC verification for read accesses when ecc_en=1" "0,1"
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bitfld.long 0x00 1. "RMW_EN,Read modify write enable" "0,1"
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bitfld.long 0x00 0. "ECC_EN,DRAM ECC enable" "0,1"
line.long 0x04 "REGS__SS_CFG__SSCFG_ECC_RID_INDX_REG,"
bitfld.long 0x04 0.--5. "ECCRID_ADR,This index specifies the ECC cache entry number that the eccrid_val is mapped to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "REGS__SS_CFG__SSCFG_ECC_RID_VAL_REG,"
bitfld.long 0x08 15. "ECCRID_VAL_VLD,A 1 in this field indicates that value in eccrid_val is valid" "0,1"
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hexmask.long.word 0x08 0.--11. 1. "ECCRID_VAL,RouteID value written or read"
group.long 0x130++0x17
line.long 0x00 "REGS__SS_CFG__SSCFG_ECC_R0_STR_ADDR_REG,"
hexmask.long.tbyte 0x00 0.--16. 1. "ECC_STR_ADR_0,Start caddress[31:16] for ECC range 0"
line.long 0x04 "REGS__SS_CFG__SSCFG_ECC_R0_END_ADDR_REG,"
hexmask.long.tbyte 0x04 0.--16. 1. "ECC_END_ADR_0,End caddress[31:16] for ECC range 0"
line.long 0x08 "REGS__SS_CFG__SSCFG_ECC_R1_STR_ADDR_REG,"
hexmask.long.tbyte 0x08 0.--16. 1. "ECC_STR_ADR_1,Start caddress[31:16] for ECC range 1"
line.long 0x0C "REGS__SS_CFG__SSCFG_ECC_R1_END_ADDR_REG,"
hexmask.long.tbyte 0x0C 0.--16. 1. "ECC_END_ADR_1,End caddress[31:16] for ECC range 1"
line.long 0x10 "REGS__SS_CFG__SSCFG_ECC_R2_STR_ADDR_REG,"
hexmask.long.tbyte 0x10 0.--16. 1. "ECC_STR_ADR_2,Start caddress[31:16] for ECC range 2"
line.long 0x14 "REGS__SS_CFG__SSCFG_ECC_R2_END_ADDR_REG,"
hexmask.long.tbyte 0x14 0.--16. 1. "ECC_END_ADR_2,End caddress[31:16] for ECC range 2"
group.long 0x150++0x17
line.long 0x00 "REGS__SS_CFG__SSCFG_ECC_1B_ERR_CNT_REG,"
hexmask.long.word 0x00 0.--15. 1. "ECC_1B_ERR_CNT,16-bit counter that displays number of 1-bit ECC errors on SDRAM data"
line.long 0x04 "REGS__SS_CFG__SSCFG_ECC_1B_ERR_THRSH_REG,"
hexmask.long.word 0x04 0.--15. 1. "ECC_1B_ERR_THRSH,ECC 1-bit error threshold"
line.long 0x08 "REGS__SS_CFG__SSCFG_ECC_1B_ERR_ADR_LOG_REG,"
hexmask.long 0x08 0.--28. 1. "ECC_1B_ERR_ADR,ECC 1-bit error address"
line.long 0x0C "REGS__SS_CFG__SSCFG_ECC_1B_ERR_MSK_LOG_REG,"
bitfld.long 0x0C 0.--3. "ECC_1B_ERR_MSK,ECC 1-bit error mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "REGS__SS_CFG__SSCFG_ECC_2B_ERR_ADR_LOG_REG,"
hexmask.long 0x10 0.--28. 1. "ECC_2B_ERR_ADR,ECC 2-bit error address"
line.long 0x14 "REGS__SS_CFG__SSCFG_ECC_2B_ERR_MSK_LOG_REG,"
bitfld.long 0x14 0.--3. "ECC_2B_ERR_MSK,ECC 2-bit error mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x184++0x27
line.long 0x00 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL1_REG,"
hexmask.long.byte 0x00 24.--31. 1. "JTAG_DATAOUT_TSEL_RD_SEL,Controls jtag_dataout_tsel_rd_sel port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1"
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hexmask.long.byte 0x00 16.--23. 1. "JTAG_DATAOUT_TSEL_WR_SEL,Controls jtag_dataout_tsel_wr_sel port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1"
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hexmask.long.byte 0x00 8.--15. 1. "JTAG_DATAOUT_TSEL_ADDR_SEL,Controls jtag_dataout_tsel_addr_sel port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1"
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bitfld.long 0x00 7. "JTAG_DATAOUT_TSEL_ADDR_EN,Controls jtag_dataout_tsel_addr_en port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x00 6. "JTAG_DATAOUT_TSEL_EN,Controls jtag_dataout_tsel_en port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x00 5. "JTAG_ENABLE_TERM,Controls jtag_enable_term port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x00 4. "JTAG_ENABLE_OE,Controls jtag_enable_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x00 3. "JTAG_ENABLE_IE,Controls jtag_enable_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x00 2. "JTAG_ENABLE_DRIVE,Controls jtag_enable_drive port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x00 1. "JTAG_ENABLE,Controls jtag_enable port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x00 0. "HVM_TEST_EN," "0,1"
line.long 0x04 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL2_REG,"
bitfld.long 0x04 31. "JTAG_DATAOUT_PAD_ADR_IO_CFG0,Controls jtag_dataout_pad_adr_io_cfg[0] port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x04 30. "JTAG_DATAOUT_PAD_ACS_IO_CFG0,Controls jtag_dataout_pad_acs_io_cfg[0] port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x04 29. "JTAG_DATAOUT_PAD_DSLICE_IO_CFG2,Controls jtag_dataout_pad_dslice_io_cfg[2] port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x04 28. "JTAG_DATAOUT_PAD_DSLICE_IO_CFG0,Controls jtag_dataout_pad_dslice_io_cfg[0] port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x04 27. "JTAG_DATAOUT_ATB_EN,Controls jtag_dataout_atb_en port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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hexmask.long.word 0x04 15.--26. 1. "JTAG_DATAOUT_VREF_CTRL_DQ,Controls jtag_dataout_vref_ctrl_dq port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1"
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hexmask.long.word 0x04 6.--14. 1. "JTAG_DATAOUT_PHY_RX_CAL_CODE,Controls jtag_dataout_phy_rx_cal_code port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1"
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bitfld.long 0x04 0.--5. "JTAG_DATAOUT_PHY_DSLICE_PAD_RX_CTLE_SETTING,Controls jtag_dataout_phy_dslice_pad_rx_ctle_setting port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL3_REG,"
hexmask.long.word 0x08 16.--31. 1. "JTAG_DATAOUT_ATB_CTRL,Controls jtag_dataout_atb_ctrl port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1"
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hexmask.long.word 0x08 0.--15. 1. "JTAG_DATAOUT_PAD_ATB_CTRL,Controls jtag_dataout_pad_atb_ctrl port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1"
line.long 0x0C "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL4_REG,"
bitfld.long 0x0C 31. "JTAG_DATAOUT_ERROR_N_OE,Controls jtag_dataout_error_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x0C 30. "JTAG_DATAOUT_PARITY_IN_OE,Controls jtag_dataout_parity_in_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x0C 28.--29. "JTAG_DATAOUT_ODT_OE,Controls jtag_dataout_odt_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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hexmask.long.word 0x0C 14.--27. 1. "JTAG_DATAOUT_ADDRESS_OE,Controls jtag_dataout_address_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1"
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bitfld.long 0x0C 12.--13. "JTAG_DATAOUT_BANK_OE,Controls jtag_dataout_bank_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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bitfld.long 0x0C 10.--11. "JTAG_DATAOUT_BG_OE,Controls jtag_dataout_bg_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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bitfld.long 0x0C 9. "JTAG_DATAOUT_WE_N_OE,Controls jtag_dataout_we_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x0C 8. "JTAG_DATAOUT_CAS_N_OE,Controls jtag_dataout_cas_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x0C 7. "JTAG_DATAOUT_RAS_N_OE,Controls jtag_dataout_ras_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x0C 6. "JTAG_DATAOUT_ACT_N_OE,Controls jtag_dataout_act_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x0C 4.--5. "JTAG_DATAOUT_CS_N_OE,Controls jtag_dataout_cs_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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bitfld.long 0x0C 3. "JTAG_DATAOUT_MEM_CLK_0_OE,Controls jtag_dataout_mem_clk_0_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x0C 1.--2. "JTAG_DATAOUT_CKE_OE,Controls jtag_dataout_cke_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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bitfld.long 0x0C 0. "JTAG_DATAOUT_RESET_N_OE,Controls jtag_dataout_reset_n_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
line.long 0x10 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL5_REG,"
bitfld.long 0x10 20.--21. "JTAG_DATAOUT_DQS_OE,Controls jtag_dataout_dqs_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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bitfld.long 0x10 16.--17. "JTAG_DATAOUT_DM_OE,Controls jtag_dataout_dm_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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hexmask.long.word 0x10 0.--15. 1. "JTAG_DATAOUT_DATA_OE,Controls jtag_dataout_data_oe port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1"
line.long 0x14 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL6_REG,"
bitfld.long 0x14 31. "JTAG_DATAOUT_ERROR_N,Controls jtag_dataout_error_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x14 30. "JTAG_DATAOUT_PARITY_IN,Controls jtag_dataout_parity_in port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x14 28.--29. "JTAG_DATAOUT_ODT,Controls jtag_dataout_odt port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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hexmask.long.word 0x14 14.--27. 1. "JTAG_DATAOUT_ADDRESS,Controls jtag_dataout_address port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1"
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bitfld.long 0x14 12.--13. "JTAG_DATAOUT_BANK,Controls jtag_dataout_bank port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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bitfld.long 0x14 10.--11. "JTAG_DATAOUT_BG,Controls jtag_dataout_bg port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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bitfld.long 0x14 9. "JTAG_DATAOUT_WE_N,Controls jtag_dataout_we_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x14 8. "JTAG_DATAOUT_CAS_N,Controls jtag_dataout_cas_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x14 7. "JTAG_DATAOUT_RAS_N,Controls jtag_dataout_ras_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x14 6. "JTAG_DATAOUT_ACT_N,Controls jtag_dataout_act_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x14 4.--5. "JTAG_DATAOUT_CS_N,Controls jtag_dataout_cs_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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bitfld.long 0x14 3. "JTAG_DATAOUT_MEM_CLK_0,Controls jtag_dataout_mem_clk_0 port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x14 1.--2. "JTAG_DATAOUT_CKE,Controls jtag_dataout_cke port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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bitfld.long 0x14 0. "JTAG_DATAOUT_RESET_N,Controls jtag_dataout_reset_n port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
line.long 0x18 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL7_REG,"
bitfld.long 0x18 20.--21. "JTAG_DATAOUT_DQS,Controls jtag_dataout_dqs port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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bitfld.long 0x18 16.--17. "JTAG_DATAOUT_DM,Controls jtag_dataout_dm port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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hexmask.long.word 0x18 0.--15. 1. "JTAG_DATAOUT_DATA,Controls jtag_dataout_data port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1"
line.long 0x1C "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL8_REG,"
bitfld.long 0x1C 31. "JTAG_DATAOUT_ERROR_N_IE,Controls jtag_dataout_error_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x1C 30. "JTAG_DATAOUT_PARITY_IN_IE,Controls jtag_dataout_parity_in_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x1C 28.--29. "JTAG_DATAOUT_ODT_IE,Controls jtag_dataout_odt_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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hexmask.long.word 0x1C 14.--27. 1. "JTAG_DATAOUT_ADDRESS_IE,Controls jtag_dataout_address_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1"
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bitfld.long 0x1C 12.--13. "JTAG_DATAOUT_BANK_IE,Controls jtag_dataout_bank_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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bitfld.long 0x1C 10.--11. "JTAG_DATAOUT_BG_IE,Controls jtag_dataout_bg_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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bitfld.long 0x1C 9. "JTAG_DATAOUT_WE_N_IE,Controls jtag_dataout_we_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x1C 8. "JTAG_DATAOUT_CAS_N_IE,Controls jtag_dataout_cas_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x1C 7. "JTAG_DATAOUT_RAS_N_IE,Controls jtag_dataout_ras_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x1C 6. "JTAG_DATAOUT_ACT_N_IE,Controls jtag_dataout_act_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x1C 4.--5. "JTAG_DATAOUT_CS_N_IE,Controls jtag_dataout_cs_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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bitfld.long 0x1C 3. "JTAG_DATAOUT_MEM_CLK_0_IE,Controls jtag_dataout_mem_clk_0_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
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bitfld.long 0x1C 1.--2. "JTAG_DATAOUT_CKE_IE,Controls jtag_dataout_cke_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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bitfld.long 0x1C 0. "JTAG_DATAOUT_RESET_N_IE,Controls jtag_dataout_reset_n_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1"
line.long 0x20 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL9_REG,"
bitfld.long 0x20 20.--21. "JTAG_DATAOUT_DQS_IE,Controls jtag_dataout_dqs_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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bitfld.long 0x20 16.--17. "JTAG_DATAOUT_DM_IE,Controls jtag_dataout_dm_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1" "0,1,2,3"
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hexmask.long.word 0x20 0.--15. 1. "JTAG_DATAOUT_DATA_IE,Controls jtag_dataout_data_ie port on the PHY when ddrss_bs_mode=0 and hvm_test_en=1"
line.long 0x24 "REGS__SS_CFG__SSCFG_PHY_TEST_CTRL10_REG,"
abitfld.long 0x24 0.--7. "HVM_CLK_DIV,Divfactor to divide ddrss_ddr_pll_clk to generate PCLK for HVM tests when ddrss_bs_mode=0 and hvm_test_en=1" "0x00=div by 1,0x01=div by 2 and so on"
rgroup.long 0x1C0++0x07
line.long 0x00 "REGS__SS_CFG__SSCFG_PHY_TEST_STAT1_REG,"
bitfld.long 0x00 31. "JTAG_DATAIN_ERROR_N,Displays value of jtag_datain_error_n port on the PHY" "0,1"
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bitfld.long 0x00 30. "JTAG_DATAIN_PARITY_IN,Displays value of jtag_datain_parity_in port on the PHY" "0,1"
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bitfld.long 0x00 28.--29. "JTAG_DATAIN_ODT,Displays value of jtag_datain_odt port on the PHY" "0,1,2,3"
newline
hexmask.long.word 0x00 14.--27. 1. "JTAG_DATAIN_ADDRESS,Displays value of jtag_datain_address port on the PHY"
newline
bitfld.long 0x00 12.--13. "JTAG_DATAIN_BANK,Displays value of jtag_datain_bank port on the PHY" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "JTAG_DATAIN_BG,Displays value of jtag_datain_bg port on the PHY" "0,1,2,3"
newline
bitfld.long 0x00 9. "JTAG_DATAIN_WE_N,Displays value of jtag_datain_we_n port on the PHY" "0,1"
newline
bitfld.long 0x00 8. "JTAG_DATAIN_CAS_N,Displays value of jtag_datain_cas_n port on the PHY" "0,1"
newline
bitfld.long 0x00 7. "JTAG_DATAIN_RAS_N,Displays value of jtag_datain_ras_n port on the PHY" "0,1"
newline
bitfld.long 0x00 6. "JTAG_DATAIN_ACT_N,Displays value of jtag_datain_act_n port on the PHY" "0,1"
newline
bitfld.long 0x00 4.--5. "JTAG_DATAIN_CS_N,Displays value of jtag_datain_cs_n port on the PHY" "0,1,2,3"
newline
bitfld.long 0x00 3. "JTAG_DATAIN_MEM_CLK_0,Displays value of jtag_datain_mem_clk_0 port on the PHY" "0,1"
newline
bitfld.long 0x00 1.--2. "JTAG_DATAIN_CKE,Displays value of jtag_datain_cke port on the PHY" "0,1,2,3"
newline
bitfld.long 0x00 0. "JTAG_DATAIN_RESET_N,Displays value of jtag_datain_reset_n port on the PHY" "0,1"
line.long 0x04 "REGS__SS_CFG__SSCFG_PHY_TEST_STAT2_REG,"
bitfld.long 0x04 20.--21. "JTAG_DATAIN_DQS,Displays value of jtag_datain_dqs port on the PHY" "0,1,2,3"
newline
bitfld.long 0x04 16.--17. "JTAG_DATAIN_DM,Displays value of jtag_datain_dm port on the PHY" "0,1,2,3"
newline
hexmask.long.word 0x04 0.--15. 1. "JTAG_DATAIN_DATA,Displays value of jtag_datain_data port on the PHY"
tree.end
tree "DFTSS0"
base ad:0x500000
group.long 0x1E0++0x13
line.long 0x00 "MEM_PACT,This register is equivalent to pbist active in the PBIST controller"
bitfld.long 0x00 0. "PACK,Enable to start the fail-processing state machine" "0,1"
line.long 0x04 "MEM_FAIL_DELAY,This register is equivalent to FDLY in the PBIST controller"
hexmask.long.byte 0x04 0.--7. 1. "FDLY,This register makes sure that there is delay between processing fails from different controllers"
line.long 0x08 "MEM_PBIST_ID,This register is equivalent to PBIST_ID in the PBIST controller"
bitfld.long 0x08 0.--3. "PBISTID,The combiner is treated as a pbist controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "MEM_STATUS,This register shows fail status at any time during testing"
line.long 0x10 "MEM_MASK0,This register is used to determine which controllers are enabled for datalogging"
group.long 0x1F0++0x03
line.long 0x00 "MEM_MASK1,This register enables PBIST controllers for ROM testing"
group.long 0x1F0++0x03
line.long 0x00 "MEM_MASK2,This register enables pbist controllers for VLCT reads"
tree.end
tree "DMASS0_BCDMA_0_BCDMA_BCHAN"
base ad:0x48420000
group.long 0x00++0x03
line.long 0x00 "BCDMA_BCHAN_CFG,The Channel Configuration Register is used to initialize static mode settings for the Block Copy DMA channel"
bitfld.long 0x00 31. "PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer" "Channel will drop current work and move on,Channel will pause and wait for SW to.."
bitfld.long 0x00 16.--19. "CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10.--11. "BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel" "32 Bytes,64 Bytes All other..,?..."
group.long 0x64++0x03
line.long 0x00 "BCDMA_BCHAN_PRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface"
bitfld.long 0x00 28.--30. "PRIORITY,Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "ORDERID,Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80++0x03
line.long 0x00 "BCDMA_BCHAN_ST_SCHED,The Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)"
bitfld.long 0x00 0.--1. "PRIORITY,Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx/Rx DMA units" "High priority,Medium - high priority,Medium - low priority,Low priority Arbitration between bins is.."
tree.end
tree "DMASS0_BCDMA_0_BCDMA_BCHANRT"
base ad:0x4C000000
group.long 0x00++0x03
line.long 0x00 "BCDMA_BCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel"
bitfld.long 0x00 31. "TX_ENABLE,This field enables or disables the channel" "channel is disabled,channel is enabled This field will be cleared by.."
bitfld.long 0x00 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down" "0,1"
bitfld.long 0x00 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately" "0,1"
bitfld.long 0x00 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events" "0,1"
newline
rbitfld.long 0x00 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel" "0,1"
group.long 0x08++0x03
line.long 0x00 "BCDMA_BCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way"
bitfld.long 0x00 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
rgroup.long 0x40++0x0F
line.long 0x00 "BCDMA_BCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits"
bitfld.long 0x00 31. "TRING_PEND,The channel ring has a descriptor" "0,1"
bitfld.long 0x00 30. "TXQ_PEND,The channel fifo is available" "0,1"
bitfld.long 0x00 29. "PKTID_AVAIL,The channel has an available packet id" "0,1"
bitfld.long 0x00 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1"
newline
bitfld.long 0x00 25. "BUSY,The channel is busy" "0,1"
bitfld.long 0x00 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1"
bitfld.long 0x00 23. "IN_PACKET,The channel is currently in a packet" "0,1"
bitfld.long 0x00 22. "OK,The channel is ready to be scheduled" "0,1"
newline
bitfld.long 0x00 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1"
bitfld.long 0x00 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1"
bitfld.long 0x00 17. "TX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x00 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1"
line.long 0x04 "BCDMA_BCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits"
bitfld.long 0x04 31. "TX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x04 24. "WAVAIL,The fifo has space for a burst size" "0,1"
bitfld.long 0x04 8. "TDNULL,Channel is trying to teardown and has met conditions" "0,1"
bitfld.long 0x04 7. "CHANNEL_OK,Channel is trying to schedule a transaction" "0,1"
newline
bitfld.long 0x04 6. "CHANNEL_BUSY,The channel is active" "0,1"
bitfld.long 0x04 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1"
line.long 0x08 "BCDMA_BCHANRT_TRT_STATUS2,The Status Register provides a read only view of channel status bits"
bitfld.long 0x08 31. "RRING_PEND,The channel ring has a descriptor" "0,1"
bitfld.long 0x08 30. "RXQ_PEND,The channel fifo is available" "0,1"
bitfld.long 0x08 29. "PKTID_AVAIL,The channel has an available packet id" "0,1"
bitfld.long 0x08 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1"
newline
bitfld.long 0x08 25. "BUSY,The channel is busy" "0,1"
bitfld.long 0x08 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1"
bitfld.long 0x08 23. "IN_PACKET,The channel is currently in a packet" "0,1"
bitfld.long 0x08 22. "OK,The channel is ready to be scheduled" "0,1"
newline
bitfld.long 0x08 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1"
bitfld.long 0x08 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1"
bitfld.long 0x08 17. "RX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x08 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1"
line.long 0x0C "BCDMA_BCHANRT_TRT_STATUS3,The Status Register provides a read only view of channel status bits"
bitfld.long 0x0C 31. "RX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x0C 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1"
bitfld.long 0x0C 24. "FIFO_BUSY,The fifo has data" "0,1"
group.long 0x80++0x03
line.long 0x00 "BCDMA_BCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel"
group.long 0x100++0x03
line.long 0x00 "BCDMA_BCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel"
group.long 0x400++0x03
line.long 0x00 "BCDMA_BCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x408++0x03
line.long 0x00 "BCDMA_BCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x410++0x03
line.long 0x00 "BCDMA_BCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
tree.end
tree "DMASS0_BCDMA_0_BCDMA_CRED"
base ad:0x45812000
group.long 0x00++0x03
line.long 0x00 "BCDMA_CRED_CRED_CRED,The Credentials Register provides credentials to be used when performing memory accesses using this flow"
bitfld.long 0x00 26. "SECURE,Secure attribute" "0,1"
bitfld.long 0x00 24.--25. "PRIV,Privelege attribute" "0,1,2,3"
hexmask.long.byte 0x00 16.--23. 1. "PRIVID,Privelege ID attribute"
tree.end
tree "DMASS0_BCDMA_0_BCDMA_GCFG"
base ad:0x485C0100
rgroup.long 0x00++0x0B
line.long 0x00 "BCDMA_GCFG_REVISION,The Revision Register contains the major and minor revisions for the module"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "BCDMA_GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the BCDMA in the system"
hexmask.long.word 0x04 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported"
line.long 0x08 "BCDMA_GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted"
bitfld.long 0x08 1. "SOFT,Soft" "0,1"
bitfld.long 0x08 0. "FREE,Free" "0,1"
group.long 0x10++0x03
line.long 0x00 "BCDMA_GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy"
bitfld.long 0x00 31. "TOUT,Timeout occurred" "0,1"
hexmask.long.word 0x00 0.--15. 1. "TOUT_CNT,Timeout period"
rgroup.long 0x20++0x13
line.long 0x00 "BCDMA_GCFG_CAP0,The Capabilities Register 0 specifies which standard features this BCDMA instance supports"
bitfld.long 0x00 19. "GLOBAL_TRIG,Global triggers 0 and 1 are supported" "0,1"
bitfld.long 0x00 18. "LOCAL_TRIG,Dedicated local trigger is supported" "0,1"
bitfld.long 0x00 17. "EOL,EOL field is supported" "0,1"
bitfld.long 0x00 16. "STATIC,STATIC field is supported" "0,1"
bitfld.long 0x00 15. "TYPE15,Type 15 TR is supported" "0,1"
bitfld.long 0x00 14. "TYPE14,Type 14 TR is supported" "0,1"
newline
bitfld.long 0x00 13. "TYPE13,Type 13 TR is supported" "0,1"
bitfld.long 0x00 12. "TYPE12,Type 12 TR is supported" "0,1"
bitfld.long 0x00 11. "TYPE11,Type 11 TR is supported" "0,1"
bitfld.long 0x00 10. "TYPE10,Type 10 TR is supported" "0,1"
bitfld.long 0x00 9. "TYPE9,Type 9 TR is supported" "0,1"
bitfld.long 0x00 8. "TYPE8,Type 8 TR is supported" "0,1"
newline
bitfld.long 0x00 7. "TYPE7,Type 7 TR is supported" "0,1"
bitfld.long 0x00 6. "TYPE6,Type 6 TR is supported" "0,1"
bitfld.long 0x00 5. "TYPE5,Type 5 TR is supported" "0,1"
bitfld.long 0x00 4. "TYPE4,Type 4 TR is supported" "0,1"
bitfld.long 0x00 3. "TYPE3,Type 3 TR is supported" "0,1"
bitfld.long 0x00 2. "TYPE2,Type 2 TR is supported" "0,1"
newline
bitfld.long 0x00 1. "TYPE1,Type 1 TR is supported" "0,1"
bitfld.long 0x00 0. "TYPE0,Type 0 TR is supported" "0,1"
line.long 0x04 "BCDMA_GCFG_CAP1,The Capabilities Register 1 specifies which standard features this BCDMA instance supports"
bitfld.long 0x04 3. "SECTR,Maximum second TR function that is supported" "0,1"
bitfld.long 0x04 2. "DFMT,Maximum data reformatting function that is supported" "0,1"
bitfld.long 0x04 1. "ELTYPE,Maximum element type value that is supported" "0,1"
bitfld.long 0x04 0. "AMODE,The maximum AMODE that is supported" "0,1"
line.long 0x08 "BCDMA_GCFG_CAP2,The Capabilities Register 2 specifies how many resources this BCDMA instance supports"
hexmask.long.word 0x08 18.--26. 1. "RCHAN_CNT,Rx split channel count"
hexmask.long.word 0x08 9.--17. 1. "TCHAN_CNT,Tx split channel count"
hexmask.long.word 0x08 0.--8. 1. "CHAN_CNT,BC channel count"
line.long 0x0C "BCDMA_GCFG_CAP3,The Capabilities Register 3 specifies how many resources this BCDMA instance supports"
hexmask.long.word 0x0C 23.--31. 1. "UCHAN_CNT,BC ultra high capacity internal channel count"
hexmask.long.word 0x0C 14.--22. 1. "HCHAN_CNT,BC high capacity internal channel count"
line.long 0x10 "BCDMA_GCFG_CAP4,The Capabilities Register 4 specifies how many resources this BCDMA instance supports"
hexmask.long.byte 0x10 24.--31. 1. "TUCHAN_CNT,TX ultra high capacity internal channel count"
hexmask.long.byte 0x10 16.--23. 1. "THCHAN_CNT,TX high capacity internal channel count"
hexmask.long.byte 0x10 8.--15. 1. "RUCHAN_CNT,RX ultra high capacity internal channel count"
hexmask.long.byte 0x10 0.--7. 1. "RHCHAN_CNT,RX high capacity internal channel count"
group.long 0x60++0x07
line.long 0x00 "BCDMA_GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks"
hexmask.long.tbyte 0x00 15.--31. 1. "NOGATE_RSVD4,Reserved PM signals"
bitfld.long 0x00 14. "NOGATE_RDEC2,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x00 12.--13. "NOGATE_RSVD3,Reserved PM signals" "0,1,2,3"
bitfld.long 0x00 11. "NOGATE_SDEC3,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x00 8.--10. "NOGATE_RSVD2,Reserved PM signals" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7. "NOGATE_WARB3,When set inhibits automatic gating of clock" "0,1"
newline
bitfld.long 0x00 4.--6. "NOGATE_RSVD1,Reserved PM signals" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "NOGATE_CARB3,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x00 2. "NOGATE_CARB2,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x00 0.--1. "NOGATE_RSVD0,Reserved PM signals" "0,1,2,3"
line.long 0x04 "BCDMA_GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks"
bitfld.long 0x04 31. "NOGATE_EDC,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 30. "NOGATE_STATS,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 29. "NOGATE_PROXY,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 28. "NOGATE_PSILIF,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 27. "NOGATE_P2P,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 26. "NOGATE_RSVD8,Reserved PM signals" "0,1"
newline
bitfld.long 0x04 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 23. "NOGATE_RPCF,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 22. "NOGATE_TPCF,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 21. "NOGATE_PCF,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 19.--20. "NOGATE_RSVD7,Reserved PM signals" "0,1,2,3"
newline
bitfld.long 0x04 18. "NOGATE_CFG,When set inhibits automatic gating of clock" "0,1"
hexmask.long.byte 0x04 11.--17. 1. "NOGATE_RSVD6,Reserved PM signals"
bitfld.long 0x04 10. "NOGATE_TRCU,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 9. "NOGATE_RSVD5,Reserved PM signals" "0,1"
bitfld.long 0x04 8. "NOGATE_EVTCU,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 7. "NOGATE_RWU3,When set inhibits automatic gating of clock" "0,1"
newline
bitfld.long 0x04 6. "NOGATE_RWU2,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 5. "NOGATE_RWU1,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 4. "NOGATE_RWU0,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 3. "NOGATE_TRU3,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 2. "NOGATE_TRU2,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 1. "NOGATE_TRU1,When set inhibits automatic gating of clock" "0,1"
newline
bitfld.long 0x04 0. "NOGATE_TRU0,When set inhibits automatic gating of clock" "0,1"
group.long 0x78++0x07
line.long 0x00 "BCDMA_GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register"
bitfld.long 0x00 31. "DBG_EN,Debug enable" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from"
hexmask.long.byte 0x00 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers"
line.long 0x04 "BCDMA_GCFG_DBGD,This register provides read only debug data"
tree.end
tree "DMASS0_BCDMA_0_BCDMA_RCHAN"
base ad:0x484C2000
group.long 0x00++0x03
line.long 0x00 "BCDMA_RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel"
bitfld.long 0x00 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer" "Channel will drop current work and move on,Channel will pause and wait for SW to.."
bitfld.long 0x00 16.--19. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14. "RX_IGNORE_LONG,This field controls whether or not long packets will be treated as exceptions or ignored for the channel" "Long packets are treated as exceptions and..,Long packets are ignored and the next TR will be.."
bitfld.long 0x00 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel" "32 Bytes,64 Bytes All other..,?..."
group.long 0x64++0x07
line.long 0x00 "BCDMA_RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface"
bitfld.long 0x00 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "BCDMA_RCHAN_RTHRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread"
hexmask.long.word 0x04 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel"
group.long 0x80++0x03
line.long 0x00 "BCDMA_RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)"
bitfld.long 0x00 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units" "High priority,Medium - high priority,Medium - low priority,Low priority Arbitration between bins is.."
tree.end
tree "DMASS0_BCDMA_0_BCDMA_RCHANRT"
base ad:0x4A820000
group.long 0x00++0x03
line.long 0x00 "BCDMA_RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel"
bitfld.long 0x00 31. "RX_ENABLE,This field enables or disables the channel" "channel is disabled,channel is enabled This field will be cleared by.."
bitfld.long 0x00 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete" "0,1"
bitfld.long 0x00 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately" "0,1"
bitfld.long 0x00 28. "RX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events" "0,1"
newline
rbitfld.long 0x00 1. "RX_STARVATION,Rx starvation" "0,1"
rbitfld.long 0x00 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel" "0,1"
group.long 0x08++0x03
line.long 0x00 "BCDMA_RCHANRT_RRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way"
bitfld.long 0x00 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
rgroup.long 0x40++0x07
line.long 0x00 "BCDMA_RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits"
bitfld.long 0x00 31. "RRING_PEND,The channel ring has a descriptor" "0,1"
bitfld.long 0x00 30. "RXQ_PEND,The channel fifo is available" "0,1"
bitfld.long 0x00 29. "PKTID_AVAIL,The channel has an available packet id" "0,1"
bitfld.long 0x00 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1"
newline
bitfld.long 0x00 25. "BUSY,The channel is busy" "0,1"
bitfld.long 0x00 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1"
bitfld.long 0x00 23. "IN_PACKET,The channel is currently in a packet" "0,1"
bitfld.long 0x00 22. "OK,The channel is ready to be scheduled" "0,1"
newline
bitfld.long 0x00 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1"
bitfld.long 0x00 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1"
bitfld.long 0x00 17. "RX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x00 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1"
line.long 0x04 "BCDMA_RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits"
bitfld.long 0x04 31. "RX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x04 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1"
bitfld.long 0x04 24. "FIFO_BUSY,The fifo has data" "0,1"
bitfld.long 0x04 7. "CHANNEL_OK,Channel is trying to send data" "0,1"
newline
bitfld.long 0x04 6. "CHANNEL_BUSY,Channel has active transactions" "0,1"
bitfld.long 0x04 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1"
group.long 0x80++0x03
line.long 0x00 "BCDMA_RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel"
repeat 10. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 )
group.long ($2+0x200)++0x03
line.long 0x00 "BCDMA_RCHANRT_RRT_PEER$1,This register provides access to the remote peer's realtime register at 0x400"
repeat.end
group.long 0x228++0x17
line.long 0x00 "BCDMA_RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A"
line.long 0x04 "BCDMA_RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B"
line.long 0x08 "BCDMA_RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C"
line.long 0x0C "BCDMA_RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D"
line.long 0x10 "BCDMA_RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E"
line.long 0x14 "BCDMA_RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F"
group.long 0x400++0x03
line.long 0x00 "BCDMA_RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x408++0x03
line.long 0x00 "BCDMA_RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x410++0x03
line.long 0x00 "BCDMA_RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
tree.end
tree "DMASS0_BCDMA_0_BCDMA_RING"
base ad:0x48600000
group.long 0x40++0x0B
line.long 0x00 "BCDMA_RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host"
line.long 0x04 "BCDMA_RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host"
bitfld.long 0x04 16.--19. "ASEL,Ring base address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "ADDR_HI,Ring base address (MSBs)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "BCDMA_RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host"
bitfld.long 0x08 29.--31. "QMODE,Defines the mode for this ring or queue" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x08 0.--15. 1. "SIZE,Tx Ring element count"
tree.end
tree "DMASS0_BCDMA_0_BCDMA_RINGRT"
base ad:0x4BC00000
group.long 0x10++0x03
line.long 0x00 "BCDMA_RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring"
hexmask.long.byte 0x00 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy"
group.long 0x18++0x03
line.long 0x00 "BCDMA_RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring"
hexmask.long.tbyte 0x00 0.--16. 1. "OCC,Total number of valid entries on the ring"
group.long 0x1010++0x03
line.long 0x00 "BCDMA_RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring"
bitfld.long 0x00 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy"
group.long 0x1018++0x03
line.long 0x00 "BCDMA_RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring"
bitfld.long 0x00 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel" "0,1"
hexmask.long.tbyte 0x00 0.--16. 1. "OCC,Total number of valid entries on the ring"
tree.end
tree "DMASS0_BCDMA_0_BCDMA_TCHAN"
base ad:0x484A4000
group.long 0x00++0x03
line.long 0x00 "BCDMA_TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel"
bitfld.long 0x00 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer" "Channel will drop current work and move on,Channel will pause and wait for SW to.."
bitfld.long 0x00 16.--19. "TX_CHAN_TYPE,Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel" "32 Bytes,64 Bytes All other..,?..."
bitfld.long 0x00 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral" "return immediately once all traffic is complete..,wait until remote peer sends back a completion.."
newline
bitfld.long 0x00 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete" "TD packet is sent,Suppress sending TD packet"
group.long 0x64++0x07
line.long 0x00 "BCDMA_TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface"
bitfld.long 0x00 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "BCDMA_TCHAN_TTHRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread"
hexmask.long.word 0x04 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel"
group.long 0x70++0x03
line.long 0x00 "BCDMA_TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel"
hexmask.long.byte 0x00 0.--7. 1. "FDEPTH,FIFO"
group.long 0x80++0x03
line.long 0x00 "BCDMA_TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)"
bitfld.long 0x00 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units" "High priority,Medium - high priority,Medium - low priority,Low priority Arbitration between bins is.."
tree.end
tree "DMASS0_BCDMA_0_BCDMA_TCHANRT"
base ad:0x4AA40000
group.long 0x00++0x03
line.long 0x00 "BCDMA_TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel"
bitfld.long 0x00 31. "TX_ENABLE,This field enables or disables the channel" "channel is disabled,channel is enabled This field will be cleared by.."
bitfld.long 0x00 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down" "0,1"
bitfld.long 0x00 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately" "0,1"
bitfld.long 0x00 28. "TX_FORCED_TEARDOWN,Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events" "0,1"
newline
rbitfld.long 0x00 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel" "0,1"
group.long 0x08++0x03
line.long 0x00 "BCDMA_TCHANRT_TRT_SWTRIG,The Software Trigger Register provides a mechanism by which software can directly trigger the channel in a secure way"
bitfld.long 0x00 0. "TRIGGER,Trigger: writing this bit with a value of 1 will cause the trigger event to be sent to this channel" "0,1"
rgroup.long 0x40++0x07
line.long 0x00 "BCDMA_TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits"
bitfld.long 0x00 31. "TRING_PEND,The channel ring has a descriptor" "0,1"
bitfld.long 0x00 30. "TXQ_PEND,The channel fifo is available" "0,1"
bitfld.long 0x00 29. "PKTID_AVAIL,The channel has an available packet id" "0,1"
bitfld.long 0x00 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1"
newline
bitfld.long 0x00 25. "BUSY,The channel is busy" "0,1"
bitfld.long 0x00 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1"
bitfld.long 0x00 23. "IN_PACKET,The channel is currently in a packet" "0,1"
bitfld.long 0x00 22. "OK,The channel is ready to be scheduled" "0,1"
newline
bitfld.long 0x00 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1"
bitfld.long 0x00 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1"
bitfld.long 0x00 17. "TX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x00 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1"
line.long 0x04 "BCDMA_TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits"
bitfld.long 0x04 31. "TX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x04 24. "WAVAIL,The fifo has space for a burst size" "0,1"
bitfld.long 0x04 8. "TDNULL,The channel has met the conditions to do teardown" "0,1"
bitfld.long 0x04 7. "CHANNEL_OK,Channel is trying to schedule work" "0,1"
newline
bitfld.long 0x04 6. "CHANNEL_BUSY,Channel has outstanding work to do" "0,1"
bitfld.long 0x04 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1"
group.long 0x80++0x03
line.long 0x00 "BCDMA_TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel"
repeat 10. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 )
group.long ($2+0x200)++0x03
line.long 0x00 "BCDMA_TCHANRT_TRT_PEER$1,This register provides access to the remote peer's realtime register at 0x400"
repeat.end
group.long 0x228++0x17
line.long 0x00 "BCDMA_TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A"
line.long 0x04 "BCDMA_TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B"
line.long 0x08 "BCDMA_TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C"
line.long 0x0C "BCDMA_TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D"
line.long 0x10 "BCDMA_TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E"
line.long 0x14 "BCDMA_TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F"
group.long 0x400++0x03
line.long 0x00 "BCDMA_TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x408++0x03
line.long 0x00 "BCDMA_TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x410++0x03
line.long 0x00 "BCDMA_TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
tree.end
tree "DMASS0_ECC_AGGR_0_ECCAGGR"
base ad:0x3F005000
rgroup.long 0x00++0x03
line.long 0x00 "ECCAGGR_REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "ECCAGGR_REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ECCAGGR_REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ECCAGGR_REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "ECCAGGR_REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECCAGGR_REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 27. "MSRAM_RAMECC0_PEND,Interrupt Pending Status for msram_ramecc0_pend" "0,1"
bitfld.long 0x04 26. "SEC_PROXY_BUFRAM_RAMECC_PEND,Interrupt Pending Status for sec_proxy_bufram_ramecc_pend" "0,1"
bitfld.long 0x04 25. "SEC_PROXY_STRAM_RAMECC_PEND,Interrupt Pending Status for sec_proxy_stram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 24. "RINGACC_STRAM_RAMECC_PEND,Interrupt Pending Status for ringacc_stram_ramecc_pend" "0,1"
bitfld.long 0x04 23. "MAP_RAMECC_PEND,Interrupt Pending Status for map_ramecc_pend" "0,1"
bitfld.long 0x04 22. "SR_RAMECC_PEND,Interrupt Pending Status for sr_ramecc_pend" "0,1"
newline
bitfld.long 0x04 21. "BCDMA_RNGOCC_RAMECC_PEND,Interrupt Pending Status for bcdma_rngocc_ramecc_pend" "0,1"
bitfld.long 0x04 20. "BCDMA_STS_RAMECC1_PEND,Interrupt Pending Status for bcdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x04 19. "BCDMA_STS_RAMECC0_PEND,Interrupt Pending Status for bcdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x04 18. "BCDMA_RPCF2_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x04 17. "BCDMA_RPCF1_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 16. "BCDMA_RPCF0_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf0_ramecc_pend" "0,1"
newline
bitfld.long 0x04 15. "BCDMA_TPCF1_RAMECC_PEND,Interrupt Pending Status for bcdma_tpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 14. "BCDMA_TPCF0_RAMECC_PEND,Interrupt Pending Status for bcdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x04 13. "PCFD1_RAMECC_PEND,Interrupt Pending Status for pcfd1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 12. "PCFD0_RAMECC_PEND,Interrupt Pending Status for pcfd0_ramecc_pend" "0,1"
bitfld.long 0x04 11. "BCDMA_STATE_RAMECC_PEND,Interrupt Pending Status for bcdma_state_ramecc_pend" "0,1"
bitfld.long 0x04 10. "BCDMA_CFG_RAMECC_PEND,Interrupt Pending Status for bcdma_cfg_ramecc_pend" "0,1"
newline
bitfld.long 0x04 9. "PKTDMA_RNGOCC_RAMECC_PEND,Interrupt Pending Status for pktdma_rngocc_ramecc_pend" "0,1"
bitfld.long 0x04 8. "PKTDMA_STS_RAMECC1_PEND,Interrupt Pending Status for pktdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x04 7. "PKTDMA_STS_RAMECC0_PEND,Interrupt Pending Status for pktdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x04 6. "PKTDMA_RPCF2_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x04 5. "PKTDMA_RPCF1_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 4. "PKTDMA_RPCF0_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf0_ramecc_pend" "0,1"
newline
bitfld.long 0x04 3. "PKTDMA_TPCF1_RAMECC_PEND,Interrupt Pending Status for pktdma_tpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 2. "PKTDMA_TPCF0_RAMECC_PEND,Interrupt Pending Status for pktdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x04 1. "PKTDMA_STATE_RAMECC_PEND,Interrupt Pending Status for pktdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x04 0. "PKTDMA_CFG_RAMECC_PEND,Interrupt Pending Status for pktdma_cfg_ramecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ECCAGGR_REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 27. "MSRAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for msram_ramecc0_pend" "0,1"
bitfld.long 0x00 26. "SEC_PROXY_BUFRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sec_proxy_bufram_ramecc_pend" "0,1"
bitfld.long 0x00 25. "SEC_PROXY_STRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sec_proxy_stram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 24. "RINGACC_STRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for ringacc_stram_ramecc_pend" "0,1"
bitfld.long 0x00 23. "MAP_RAMECC_ENABLE_SET,Interrupt Enable Set Register for map_ramecc_pend" "0,1"
bitfld.long 0x00 22. "SR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sr_ramecc_pend" "0,1"
newline
bitfld.long 0x00 21. "BCDMA_RNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rngocc_ramecc_pend" "0,1"
bitfld.long 0x00 20. "BCDMA_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for bcdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x00 19. "BCDMA_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for bcdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 18. "BCDMA_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x00 17. "BCDMA_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 16. "BCDMA_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 15. "BCDMA_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 14. "BCDMA_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 13. "PCFD1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pcfd1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 12. "PCFD0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pcfd0_ramecc_pend" "0,1"
bitfld.long 0x00 11. "BCDMA_STATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_state_ramecc_pend" "0,1"
bitfld.long 0x00 10. "BCDMA_CFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_cfg_ramecc_pend" "0,1"
newline
bitfld.long 0x00 9. "PKTDMA_RNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rngocc_ramecc_pend" "0,1"
bitfld.long 0x00 8. "PKTDMA_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for pktdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x00 7. "PKTDMA_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for pktdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 6. "PKTDMA_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x00 5. "PKTDMA_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 4. "PKTDMA_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "PKTDMA_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "PKTDMA_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "PKTDMA_STATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PKTDMA_CFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_cfg_ramecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ECCAGGR_REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 27. "MSRAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for msram_ramecc0_pend" "0,1"
bitfld.long 0x00 26. "SEC_PROXY_BUFRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sec_proxy_bufram_ramecc_pend" "0,1"
bitfld.long 0x00 25. "SEC_PROXY_STRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sec_proxy_stram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 24. "RINGACC_STRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ringacc_stram_ramecc_pend" "0,1"
bitfld.long 0x00 23. "MAP_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for map_ramecc_pend" "0,1"
bitfld.long 0x00 22. "SR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sr_ramecc_pend" "0,1"
newline
bitfld.long 0x00 21. "BCDMA_RNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rngocc_ramecc_pend" "0,1"
bitfld.long 0x00 20. "BCDMA_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x00 19. "BCDMA_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 18. "BCDMA_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x00 17. "BCDMA_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 16. "BCDMA_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 15. "BCDMA_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 14. "BCDMA_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 13. "PCFD1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pcfd1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 12. "PCFD0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pcfd0_ramecc_pend" "0,1"
bitfld.long 0x00 11. "BCDMA_STATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_state_ramecc_pend" "0,1"
bitfld.long 0x00 10. "BCDMA_CFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_cfg_ramecc_pend" "0,1"
newline
bitfld.long 0x00 9. "PKTDMA_RNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rngocc_ramecc_pend" "0,1"
bitfld.long 0x00 8. "PKTDMA_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x00 7. "PKTDMA_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 6. "PKTDMA_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x00 5. "PKTDMA_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 4. "PKTDMA_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "PKTDMA_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "PKTDMA_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "PKTDMA_STATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PKTDMA_CFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_cfg_ramecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ECCAGGR_REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECCAGGR_REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 27. "MSRAM_RAMECC0_PEND,Interrupt Pending Status for msram_ramecc0_pend" "0,1"
bitfld.long 0x04 26. "SEC_PROXY_BUFRAM_RAMECC_PEND,Interrupt Pending Status for sec_proxy_bufram_ramecc_pend" "0,1"
bitfld.long 0x04 25. "SEC_PROXY_STRAM_RAMECC_PEND,Interrupt Pending Status for sec_proxy_stram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 24. "RINGACC_STRAM_RAMECC_PEND,Interrupt Pending Status for ringacc_stram_ramecc_pend" "0,1"
bitfld.long 0x04 23. "MAP_RAMECC_PEND,Interrupt Pending Status for map_ramecc_pend" "0,1"
bitfld.long 0x04 22. "SR_RAMECC_PEND,Interrupt Pending Status for sr_ramecc_pend" "0,1"
newline
bitfld.long 0x04 21. "BCDMA_RNGOCC_RAMECC_PEND,Interrupt Pending Status for bcdma_rngocc_ramecc_pend" "0,1"
bitfld.long 0x04 20. "BCDMA_STS_RAMECC1_PEND,Interrupt Pending Status for bcdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x04 19. "BCDMA_STS_RAMECC0_PEND,Interrupt Pending Status for bcdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x04 18. "BCDMA_RPCF2_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x04 17. "BCDMA_RPCF1_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 16. "BCDMA_RPCF0_RAMECC_PEND,Interrupt Pending Status for bcdma_rpcf0_ramecc_pend" "0,1"
newline
bitfld.long 0x04 15. "BCDMA_TPCF1_RAMECC_PEND,Interrupt Pending Status for bcdma_tpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 14. "BCDMA_TPCF0_RAMECC_PEND,Interrupt Pending Status for bcdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x04 13. "PCFD1_RAMECC_PEND,Interrupt Pending Status for pcfd1_ramecc_pend" "0,1"
newline
bitfld.long 0x04 12. "PCFD0_RAMECC_PEND,Interrupt Pending Status for pcfd0_ramecc_pend" "0,1"
bitfld.long 0x04 11. "BCDMA_STATE_RAMECC_PEND,Interrupt Pending Status for bcdma_state_ramecc_pend" "0,1"
bitfld.long 0x04 10. "BCDMA_CFG_RAMECC_PEND,Interrupt Pending Status for bcdma_cfg_ramecc_pend" "0,1"
newline
bitfld.long 0x04 9. "PKTDMA_RNGOCC_RAMECC_PEND,Interrupt Pending Status for pktdma_rngocc_ramecc_pend" "0,1"
bitfld.long 0x04 8. "PKTDMA_STS_RAMECC1_PEND,Interrupt Pending Status for pktdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x04 7. "PKTDMA_STS_RAMECC0_PEND,Interrupt Pending Status for pktdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x04 6. "PKTDMA_RPCF2_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x04 5. "PKTDMA_RPCF1_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 4. "PKTDMA_RPCF0_RAMECC_PEND,Interrupt Pending Status for pktdma_rpcf0_ramecc_pend" "0,1"
newline
bitfld.long 0x04 3. "PKTDMA_TPCF1_RAMECC_PEND,Interrupt Pending Status for pktdma_tpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 2. "PKTDMA_TPCF0_RAMECC_PEND,Interrupt Pending Status for pktdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x04 1. "PKTDMA_STATE_RAMECC_PEND,Interrupt Pending Status for pktdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x04 0. "PKTDMA_CFG_RAMECC_PEND,Interrupt Pending Status for pktdma_cfg_ramecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ECCAGGR_REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 27. "MSRAM_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for msram_ramecc0_pend" "0,1"
bitfld.long 0x00 26. "SEC_PROXY_BUFRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sec_proxy_bufram_ramecc_pend" "0,1"
bitfld.long 0x00 25. "SEC_PROXY_STRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sec_proxy_stram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 24. "RINGACC_STRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for ringacc_stram_ramecc_pend" "0,1"
bitfld.long 0x00 23. "MAP_RAMECC_ENABLE_SET,Interrupt Enable Set Register for map_ramecc_pend" "0,1"
bitfld.long 0x00 22. "SR_RAMECC_ENABLE_SET,Interrupt Enable Set Register for sr_ramecc_pend" "0,1"
newline
bitfld.long 0x00 21. "BCDMA_RNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rngocc_ramecc_pend" "0,1"
bitfld.long 0x00 20. "BCDMA_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for bcdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x00 19. "BCDMA_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for bcdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 18. "BCDMA_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x00 17. "BCDMA_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 16. "BCDMA_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_rpcf0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 15. "BCDMA_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 14. "BCDMA_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 13. "PCFD1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pcfd1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 12. "PCFD0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pcfd0_ramecc_pend" "0,1"
bitfld.long 0x00 11. "BCDMA_STATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_state_ramecc_pend" "0,1"
bitfld.long 0x00 10. "BCDMA_CFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for bcdma_cfg_ramecc_pend" "0,1"
newline
bitfld.long 0x00 9. "PKTDMA_RNGOCC_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rngocc_ramecc_pend" "0,1"
bitfld.long 0x00 8. "PKTDMA_STS_RAMECC1_ENABLE_SET,Interrupt Enable Set Register for pktdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x00 7. "PKTDMA_STS_RAMECC0_ENABLE_SET,Interrupt Enable Set Register for pktdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 6. "PKTDMA_RPCF2_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x00 5. "PKTDMA_RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 4. "PKTDMA_RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_rpcf0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "PKTDMA_TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "PKTDMA_TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "PKTDMA_STATE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PKTDMA_CFG_RAMECC_ENABLE_SET,Interrupt Enable Set Register for pktdma_cfg_ramecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ECCAGGR_REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 27. "MSRAM_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for msram_ramecc0_pend" "0,1"
bitfld.long 0x00 26. "SEC_PROXY_BUFRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sec_proxy_bufram_ramecc_pend" "0,1"
bitfld.long 0x00 25. "SEC_PROXY_STRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sec_proxy_stram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 24. "RINGACC_STRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ringacc_stram_ramecc_pend" "0,1"
bitfld.long 0x00 23. "MAP_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for map_ramecc_pend" "0,1"
bitfld.long 0x00 22. "SR_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for sr_ramecc_pend" "0,1"
newline
bitfld.long 0x00 21. "BCDMA_RNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rngocc_ramecc_pend" "0,1"
bitfld.long 0x00 20. "BCDMA_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x00 19. "BCDMA_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 18. "BCDMA_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x00 17. "BCDMA_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 16. "BCDMA_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_rpcf0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 15. "BCDMA_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 14. "BCDMA_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 13. "PCFD1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pcfd1_ramecc_pend" "0,1"
newline
bitfld.long 0x00 12. "PCFD0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pcfd0_ramecc_pend" "0,1"
bitfld.long 0x00 11. "BCDMA_STATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_state_ramecc_pend" "0,1"
bitfld.long 0x00 10. "BCDMA_CFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for bcdma_cfg_ramecc_pend" "0,1"
newline
bitfld.long 0x00 9. "PKTDMA_RNGOCC_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rngocc_ramecc_pend" "0,1"
bitfld.long 0x00 8. "PKTDMA_STS_RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_sts_ramecc1_pend" "0,1"
bitfld.long 0x00 7. "PKTDMA_STS_RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_sts_ramecc0_pend" "0,1"
newline
bitfld.long 0x00 6. "PKTDMA_RPCF2_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf2_ramecc_pend" "0,1"
bitfld.long 0x00 5. "PKTDMA_RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 4. "PKTDMA_RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_rpcf0_ramecc_pend" "0,1"
newline
bitfld.long 0x00 3. "PKTDMA_TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "PKTDMA_TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_tpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "PKTDMA_STATE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_state_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "PKTDMA_CFG_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for pktdma_cfg_ramecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ECCAGGR_REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ECCAGGR_REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ECCAGGR_REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ECCAGGR_REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "DMASS0_INTAGGR_0_INTAGGR_CFG"
base ad:0x48110000
rgroup.quad 0x00++0x17
line.quad 0x00 "INTAGGR_CFG_REVISION,The Revision Register contains the major and minor revisions for the module"
hexmask.quad.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.quad 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.quad 0x00 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.quad 0x08 "INTAGGR_CFG_INTCAP,The IntCap Register contains information on virtual interrupts"
hexmask.quad.word 0x08 16.--31. 1. "VINTR_CNT,Virtual interrupt register/pin count"
hexmask.quad.word 0x08 0.--15. 1. "SEVT_CNT,Number of 'event to virt int' mapping registers"
line.quad 0x10 "INTAGGR_CFG_AUXCAP,The AuxCap Register contains information on additional capabilities"
hexmask.quad.word 0x10 48.--63. 1. "UNMAP_CNT,Number of multicast event registers"
hexmask.quad.word 0x10 32.--47. 1. "MEVI_CNT,Number of multicast event registers"
hexmask.quad.word 0x10 16.--31. 1. "LEVI_CNT,Local input events for local to global translation"
hexmask.quad.word 0x10 0.--15. 1. "GEVI_CNT,Number of event counting registers"
tree.end
tree "DMASS0_INTAGGR_0_INTAGGR_GCNTCFG"
base ad:0x48220000
group.quad 0x00++0x07
line.quad 0x00 "INTAGGR_GCNTCFG_map,The Global Event Mapping register controls the egress global event index for this event count"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "GEVIDX,Global event index"
tree.end
tree "DMASS0_INTAGGR_0_INTAGGR_GCNTRTI"
base ad:0x4A000000
group.quad 0x00++0x07
line.quad 0x00 "INTAGGR_GCNTRTI_count,The ETL Count register is read by software to determine how many times the event message has been received"
hexmask.quad 0x00 0.--31. 1. "CCNT,Current count"
tree.end
tree "DMASS0_INTAGGR_0_INTAGGR_IMAP"
base ad:0x48100000
group.quad 0x00++0x07
line.quad 0x00 "INTAGGR_IMAP_INTMAP,The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto"
hexmask.quad.word 0x00 8.--16. 1. "REGNUM,Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in"
bitfld.quad 0x00 0.--5. "BITNUM,Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "DMASS0_INTAGGR_0_INTAGGR_INTR"
base ad:0x48000000
group.quad 0x00++0x27
line.quad 0x00 "INTAGGR_INTR_ENABLE_SET,The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt output"
line.quad 0x08 "INTAGGR_INTR_ENABLE_CLR,The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual interrupt output"
line.quad 0x10 "INTAGGR_INTR_STATUS_SET,The Interrupt Status register is read by software to determine the cause of an interrupt"
line.quad 0x18 "INTAGGR_INTR_STATUS,The Interrupt Status register is read by software to determine the cause of an interrupt"
line.quad 0x20 "INTAGGR_INTR_STATUS_MSKD,The Interrupt Masked Status register can be read by software to determine the cause of an interrupt"
tree.end
tree "DMASS0_INTAGGR_0_INTAGGR_L2G"
base ad:0x48120000
group.quad 0x00++0x07
line.quad 0x00 "INTAGGR_L2G_map,This register determines how the ordinal local event is translated to a global event on the outgoing event transport lane"
bitfld.quad 0x00 31. "MODE,Local event detection mode" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "GEVIDX,Global event index"
tree.end
tree "DMASS0_INTAGGR_0_INTAGGR_MCAST"
base ad:0x48210000
group.quad 0x00++0x07
line.quad 0x00 "INTAGGR_MCAST_mcmap,This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces"
bitfld.quad 0x00 63. "IRQMODE1,IRQ Mode Flag 1" "0,1"
hexmask.quad.word 0x00 32.--47. 1. "GEVIDX1,Global event index 1"
bitfld.quad 0x00 31. "IRQMODE0,IRQ Mode Flag 0" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "GEVIDX0,Global event index 0"
tree.end
tree "DMASS0_INTAGGR_0_INTAGGR_UNMAP"
base ad:0x48180000
group.quad 0x8000++0x07
line.quad 0x00 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "UMAPIDX,Global event index"
group.quad 0x9000++0x07
line.quad 0x00 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "UMAPIDX,Global event index"
group.quad 0xA000++0x07
line.quad 0x00 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "UMAPIDX,Global event index"
group.quad 0xB000++0x07
line.quad 0x00 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "UMAPIDX,Global event index"
group.quad 0xC000++0x07
line.quad 0x00 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "UMAPIDX,Global event index"
group.quad 0xD000++0x07
line.quad 0x00 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "UMAPIDX,Global event index"
group.quad 0x10000++0x07
line.quad 0x00 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "UMAPIDX,Global event index"
group.quad 0x11000++0x07
line.quad 0x00 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "UMAPIDX,Global event index"
group.quad 0x12000++0x07
line.quad 0x00 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "UMAPIDX,Global event index"
group.quad 0x13000++0x07
line.quad 0x00 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "UMAPIDX,Global event index"
group.quad 0x14000++0x07
line.quad 0x00 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "UMAPIDX,Global event index"
group.quad 0x15000++0x07
line.quad 0x00 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "UMAPIDX,Global event index"
group.quad 0x16000++0x07
line.quad 0x00 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "UMAPIDX,Global event index"
group.quad 0x17000++0x07
line.quad 0x00 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "UMAPIDX,Global event index"
group.quad 0x18000++0x07
line.quad 0x00 "INTAGGR_UNMAP_map,The Global Event Mapping register controls the egress global event index for this unmapped event"
bitfld.quad 0x00 31. "IRQMODE,IRQ Mode Flag" "0,1"
hexmask.quad.word 0x00 0.--15. 1. "UMAPIDX,Global event index"
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_CRED"
base ad:0x45810000
group.long 0x00++0x03
line.long 0x00 "PKTDMA_CRED_CRED_CRED,The Credentials Register provides credentials to be used when performing memory accesses using this flow"
bitfld.long 0x00 31. "CHK_SECURE,Check secure control bit" "0,1"
bitfld.long 0x00 26. "SECURE,Secure attribute" "0,1"
bitfld.long 0x00 24.--25. "PRIV,Privelege attribute" "0,1,2,3"
hexmask.long.byte 0x00 16.--23. 1. "PRIVID,Privelege ID attribute"
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_GCFG"
base ad:0x485C0000
rgroup.long 0x00++0x0B
line.long 0x00 "PKTDMA_GCFG_REVISION,The Revision Register contains the major and minor revisions for the module"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PKTDMA_GCFG_PERF_CTRL,The performance control register contains fields which can be used to adjust the performance of the PKTDMA in the system"
hexmask.long.word 0x04 0.--15. 1. "TIMEOUT_CNT,This feature is not currently supported"
line.long 0x08 "PKTDMA_GCFG_EMU_CTRL,The emulation control register is used to control the behavior of the DMA when the emususp input is asserted"
bitfld.long 0x08 1. "SOFT,Soft" "0,1"
bitfld.long 0x08 0. "FREE,Free" "0,1"
group.long 0x10++0x03
line.long 0x00 "PKTDMA_GCFG_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy"
bitfld.long 0x00 31. "TOUT,Timeout occurred" "0,1"
hexmask.long.word 0x00 0.--15. 1. "TOUT_CNT,Timeout period"
hgroup.long 0x20++0x07
hide.long 0x00 "PKTDMA_GCFG_CAP0,The Capabilities Register 0 specifies which standard features this PKTDMA instance supports"
hide.long 0x04 "PKTDMA_GCFG_CAP1,The Capabilities Register 1 specifies which standard features this PKTDMA instance supports"
rgroup.long 0x28++0x0B
line.long 0x00 "PKTDMA_GCFG_CAP2,The Capabilities Register 2 specifies how many resources this PKTDMA instance supports"
hexmask.long.word 0x00 18.--26. 1. "RCHAN_CNT,Rx internal channel count"
hexmask.long.word 0x00 0.--8. 1. "TCHAN_CNT,Tx internal channel count"
line.long 0x04 "PKTDMA_GCFG_CAP3,The Capabilities Register 3 specifies how many resources this PKTDMA instance supports"
hexmask.long.word 0x04 23.--31. 1. "UCHAN_CNT,Tx ultra high capacity internal channel count"
hexmask.long.word 0x04 14.--22. 1. "HCHAN_CNT,Tx high capacity internal channel count"
hexmask.long.word 0x04 0.--13. 1. "RFLOW_CNT,Rx flow table entry count"
line.long 0x08 "PKTDMA_GCFG_CAP4,The Capabilities Register 4 specifies how many resources this PKTDMA instance supports"
hexmask.long.word 0x08 0.--13. 1. "TFLOW_CNT,Tx flow table entry count"
group.long 0x60++0x07
line.long 0x00 "PKTDMA_GCFG_PM0,This register enables or inhibits automatic clock gating to individual sub-blocks"
bitfld.long 0x00 31. "NOGATE_RDU3,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x00 30. "NOGATE_RDU2,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x00 29. "NOGATE_RDU1,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x00 28. "NOGATE_RDU0,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x00 27. "NOGATE_TDU3,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x00 26. "NOGATE_TDU2,When set inhibits automatic gating of clock" "0,1"
newline
bitfld.long 0x00 25. "NOGATE_TDU1,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x00 24. "NOGATE_TDU0,When set inhibits automatic gating of clock" "0,1"
hexmask.long.word 0x00 13.--23. 1. "NOGATE_RSVD4,Reserved PM signals"
bitfld.long 0x00 12. "NOGATE_RDEC,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x00 9.--11. "NOGATE_RSVD3,Reserved PM signals" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "NOGATE_SDEC,When set inhibits automatic gating of clock" "0,1"
newline
bitfld.long 0x00 5.--7. "NOGATE_RSVD2,Reserved PM signals" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "NOGATE_WARB,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x00 1.--3. "NOGATE_RSVD1,Reserved PM signals" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "NOGATE_CARB,When set inhibits automatic gating of clock" "0,1"
line.long 0x04 "PKTDMA_GCFG_PM1,This register enables or inhibits automatic clock gating to individual sub-blocks"
bitfld.long 0x04 31. "NOGATE_RSVD12,Reserved PM signals" "0,1"
bitfld.long 0x04 30. "NOGATE_STATS,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 29. "NOGATE_PROXY,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 28. "NOGATE_RSVD11,Reserved PM signals" "0,1"
bitfld.long 0x04 27. "NOGATE_P2P,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 26. "NOGATE_RSVD10,Reserved PM signals" "0,1"
newline
bitfld.long 0x04 25. "NOGATE_EHANDLER,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 24. "NOGATE_RINGOCC,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 23. "NOGATE_RSVD9,Reserved PM signals" "0,1"
bitfld.long 0x04 22. "NOGATE_TPCF,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 19.--21. "NOGATE_RSVD8,Reserved PM signals" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 18. "NOGATE_CFG,When set inhibits automatic gating of clock" "0,1"
newline
bitfld.long 0x04 16.--17. "NOGATE_RSVD7,Reserved PM signals" "0,1,2,3"
bitfld.long 0x04 15. "NOGATE_RFLOWFW,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 14. "NOGATE_RSVD6,Reserved PM signals" "0,1"
bitfld.long 0x04 13. "NOGATE_RCU,When set inhibits automatic gating of clock" "0,1"
bitfld.long 0x04 12. "NOGATE_TCU,When set inhibits automatic gating of clock" "0,1"
hexmask.long.word 0x04 0.--11. 1. "NOGATE_RSVD5,Reserved PM signals"
group.long 0x78++0x07
line.long 0x00 "PKTDMA_GCFG_DBGA,This register provides a writable address which allows debug information to be read from the Debug Data Register"
bitfld.long 0x00 31. "DBG_EN,Debug enable" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "DBG_UNIT,Selects which unit to read debug information from"
hexmask.long.byte 0x00 0.--7. 1. "DBG_ADDR,Selects offset within unit to access seperate debug registers"
line.long 0x04 "PKTDMA_GCFG_DBGD,This register provides read only debug data"
group.long 0x88++0x03
line.long 0x00 "PKTDMA_GCFG_RFLOWFWSTAT,The Rx Flow FW Status Register 0 captures information about the thread/channel and received flow ID which failed a range check"
bitfld.long 0x00 31. "PEND,This bit is set whenever the Flow ID firewall detects a Flow ID is out of range for an incoming packet" "0,1"
hexmask.long.word 0x00 16.--29. 1. "FLOWID,This is the flow ID that was received on the trapped packet"
hexmask.long.word 0x00 0.--8. 1. "CHANNEL,This is the channel number on which the trapped packet was received"
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_RCHAN"
base ad:0x484C0000
group.long 0x00++0x03
line.long 0x00 "PKTDMA_RCHAN_RCFG,The Rx Channel Configuration Register is used to initialize static mode settings for the Rx DMA channel"
bitfld.long 0x00 31. "RX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer" "Channel will drop current work and move on,Channel will pause and wait for SW to.."
bitfld.long 0x00 16.--19. "RX_CHAN_TYPE,Rx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host" "?,?,Channel performs packet oriented data transfers..,Channel performs packet oriented data transfers..,?..."
newline
bitfld.long 0x00 10.--11. "RX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel" "0,1,2,3"
group.long 0x64++0x07
line.long 0x00 "PKTDMA_RCHAN_RPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface"
bitfld.long 0x00 28.--30. "PRIORITY,Rx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem*_cepriority outputs during all transactions for this channel" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "ORDERID,Rx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PKTDMA_RCHAN_THRD_ID,The thread ID mapping register is used to pair the Rx DMA channel to a specific destination thread"
hexmask.long.word 0x04 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel"
group.long 0x80++0x03
line.long 0x00 "PKTDMA_RCHAN_RST_SCHED,The Rx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)"
bitfld.long 0x00 0.--1. "PRIORITY,Rx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Rx DMA units" "High priority,Medium - high priority,Medium - low priority,Low priority Arbitration between bins is.."
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_RCHANRT"
base ad:0x4A800000
group.long 0x00++0x03
line.long 0x00 "PKTDMA_RCHANRT_RRT_CTL,The Rx Channel Realtime Control Register contains real-time control and status information for the Rx DMA channel"
bitfld.long 0x00 31. "RX_ENABLE,This field enables or disables the channel" "channel is disabled,channel is enabled This field will be cleared by.."
bitfld.long 0x00 30. "RX_TEARDOWN,This field indicates whether or not an Rx teardown operation is complete" "0,1"
bitfld.long 0x00 29. "RX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately" "0,1"
bitfld.long 0x00 0. "RX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel" "0,1"
rgroup.long 0x40++0x07
line.long 0x00 "PKTDMA_RCHANRT_RRT_STATUS0,The Status Register provides a read only view of channel status bits"
bitfld.long 0x00 31. "RRING_PEND,The channel ring has a descriptor" "0,1"
bitfld.long 0x00 30. "RXQ_PEND,The channel fifo is available" "0,1"
bitfld.long 0x00 29. "PKTID_AVAIL,The channel has an available packet id" "0,1"
bitfld.long 0x00 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1"
newline
bitfld.long 0x00 25. "BUSY,The channel is busy" "0,1"
bitfld.long 0x00 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1"
bitfld.long 0x00 23. "IN_PACKET,The channel is currently in a packet" "0,1"
bitfld.long 0x00 22. "OK,The channel is ready to be scheduled" "0,1"
newline
bitfld.long 0x00 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1"
bitfld.long 0x00 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1"
bitfld.long 0x00 17. "RX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x00 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1"
line.long 0x04 "PKTDMA_RCHANRT_RRT_STATUS1,The Status Register provides a read only view of channel status bits"
bitfld.long 0x04 31. "RX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x04 25. "FIFO_PEND,The FIFO has enough data for a burst" "0,1"
bitfld.long 0x04 24. "FIFO_BUSY,The fifo has data" "0,1"
bitfld.long 0x04 7. "CHANNEL_OK,The channel is trying to schedule work" "0,1"
newline
bitfld.long 0x04 6. "CHANNEL_BUSY,The channel has active work" "0,1"
bitfld.long 0x04 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1"
group.long 0x80++0x03
line.long 0x00 "PKTDMA_RCHANRT_RRT_STDATA,The State Data Registers contain the current working state of the Rx DMA channel"
repeat 10. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 )
group.long ($2+0x200)++0x03
line.long 0x00 "PKTDMA_RCHANRT_RRT_PEER$1,This register provides access to the remote peer's realtime register at 0x400"
repeat.end
group.long 0x228++0x17
line.long 0x00 "PKTDMA_RCHANRT_RRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A"
line.long 0x04 "PKTDMA_RCHANRT_RRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B"
line.long 0x08 "PKTDMA_RCHANRT_RRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C"
line.long 0x0C "PKTDMA_RCHANRT_RRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D"
line.long 0x10 "PKTDMA_RCHANRT_RRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E"
line.long 0x14 "PKTDMA_RCHANRT_RRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F"
group.long 0x400++0x0B
line.long 0x00 "PKTDMA_RCHANRT_RRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
line.long 0x04 "PKTDMA_RCHANRT_RRT_DCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
line.long 0x08 "PKTDMA_RCHANRT_RRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x410++0x03
line.long 0x00 "PKTDMA_RCHANRT_RRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_RFLOW"
base ad:0x48430000
group.long 0x00++0x03
line.long 0x00 "PKTDMA_RFLOW_RFA,The Rx Flow N Configuration Register A contains static configuration information for the Rx DMA flow"
bitfld.long 0x00 30. "RX_EINFO_PRESENT,Rx Extended Packet Info Block Present: This bit controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor" "0,1"
bitfld.long 0x00 29. "RX_PSINFO_PRESENT,Rx PS Words Present: This bit controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor" "0,1"
bitfld.long 0x00 28. "RX_ERROR_HANDLING,Rx Error Handling Mode: This bit controls the error handling mode for the flow and is only used when channel errors (i.e. descriptor starvation) occurs" "Starvation errors result in dropping packet and..,Starvation errors result in the channel waiting.."
hexmask.long.word 0x00 16.--24. 1. "RX_SOP_OFFSET,Rx Start of Packet Offset: This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer)"
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_RING"
base ad:0x485E0000
group.long 0x40++0x0B
line.long 0x00 "PKTDMA_RING_BA_LO,The Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host"
line.long 0x04 "PKTDMA_RING_BA_HI,The Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host"
bitfld.long 0x04 16.--19. "ASEL,Ring base address select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "ADDR_HI,Ring base address (MSBs)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "PKTDMA_RING_SIZE,The Ring Size Register contains the element count for the ring which is used to hand off pending work for the channel from the Host"
bitfld.long 0x08 29.--31. "QMODE,Defines the mode for this ring or queue" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 24.--26. "RING_ELSIZE," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x08 0.--15. 1. "SIZE,Tx Ring element count"
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_RINGRT"
base ad:0x4B800000
group.long 0x10++0x03
line.long 0x00 "PKTDMA_RINGRT_RT_FDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring"
hexmask.long.byte 0x00 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy"
group.long 0x18++0x03
line.long 0x00 "PKTDMA_RINGRT_RT_FOCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring"
hexmask.long.tbyte 0x00 0.--16. 1. "OCC,Total number of valid entries on the ring"
group.long 0x1010++0x03
line.long 0x00 "PKTDMA_RINGRT_RT_RDB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring"
bitfld.long 0x00 31. "TDOWN_ACK,This bit is set to 1 to ackowledge (and clear) the tdown_complete bit in the corresponding Ring N Occupancy Register" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy"
group.long 0x1018++0x03
line.long 0x00 "PKTDMA_RINGRT_RT_ROCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring"
bitfld.long 0x00 31. "TDOWN_COMPLETE,This bit when set indicates that a teardown is complete on the channel" "0,1"
hexmask.long.tbyte 0x00 0.--16. 1. "OCC,Total number of valid entries on the ring"
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_TCHAN"
base ad:0x484A0000
group.long 0x00++0x03
line.long 0x00 "PKTDMA_TCHAN_TCFG,The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel"
bitfld.long 0x00 31. "TX_PAUSE_ON_ERR,Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer" "Channel will drop current work and move on,Channel will pause and wait for SW to.."
newline
bitfld.long 0x00 30. "TX_FILT_EINFO,This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application" "DMA controller will pass extended packet info..,DMA controller will filter extended packet info.."
newline
bitfld.long 0x00 29. "TX_FILT_PSWORDS,This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application" "DMA controller will pass PS words if present in..,DMA controller will filter PS words"
newline
rbitfld.long 0x00 16.--19. "TX_CHAN_TYPE,Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--11. "TX_BURST_SIZE,Specifies the nominal burst size and alignment for data transfers on this channel" "0,1,2,3"
newline
bitfld.long 0x00 9. "TX_TDTYPE,Specifies whether or not the channel should immediately return a teardown completion response to the default completion queue or wait until a status message is returned from the remote PSI-L paired peripheral" "return immediately once all traffic is complete..,wait until remote peer sends back a completion.."
newline
bitfld.long 0x00 8. "TX_NOTDPKT,Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete" "TD packet is sent,Suppress sending TD packet"
group.long 0x64++0x07
line.long 0x00 "PKTDMA_TCHAN_TPRI_CTRL,The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface"
bitfld.long 0x00 28.--30. "PRIORITY,Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--3. "ORDERID,Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PKTDMA_TCHAN_THRD_ID,The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread"
hexmask.long.word 0x04 0.--15. 1. "THREAD_ID,Thread ID: This field contains the (up-to) 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel"
group.long 0x70++0x03
line.long 0x00 "PKTDMA_TCHAN_TFIFO_DEPTH,The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel"
hexmask.long.byte 0x00 0.--7. 1. "FDEPTH,FIFO"
group.long 0x80++0x03
line.long 0x00 "PKTDMA_TCHAN_TST_SCHED,The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s)"
bitfld.long 0x00 0.--1. "PRIORITY,Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units" "High priority,Medium - high priority,Medium - low priority,Low priority Arbitration between bins is.."
tree.end
tree "DMASS0_PKTDMA_0_PKTDMA_TCHANRT"
base ad:0x4AA00000
group.long 0x00++0x03
line.long 0x00 "PKTDMA_TCHANRT_TRT_CTL,The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel"
bitfld.long 0x00 31. "TX_ENABLE,This field enables or disables the channel" "channel is disabled,channel is enabled This field will be cleared by.."
bitfld.long 0x00 30. "TX_TEARDOWN,Channel teardown: Setting this bit will request the channel to be torn down" "0,1"
bitfld.long 0x00 29. "TX_PAUSE,Channel pause: Setting this bit will cause the channel to pause processing immediately" "0,1"
bitfld.long 0x00 0. "TX_ERROR,Channel error: This bit will be set anytime an error has occurred on the channel" "0,1"
rgroup.long 0x40++0x07
line.long 0x00 "PKTDMA_TCHANRT_TRT_STATUS0,The Status Register provides a read only view of channel status bits"
bitfld.long 0x00 31. "TRING_PEND,The channel ring has a descriptor" "0,1"
bitfld.long 0x00 30. "TXQ_PEND,The channel fifo is available" "0,1"
bitfld.long 0x00 29. "PKTID_AVAIL,The channel has an available packet id" "0,1"
bitfld.long 0x00 28. "PKTID_BUSY,There is an outstanding pktid for the channel" "0,1"
newline
bitfld.long 0x00 25. "BUSY,The channel is busy" "0,1"
bitfld.long 0x00 24. "TRANSBUSY,The channel has an outstanding transaction" "0,1"
bitfld.long 0x00 23. "IN_PACKET,The channel is currently in a packet" "0,1"
bitfld.long 0x00 22. "OK,The channel is ready to be scheduled" "0,1"
newline
bitfld.long 0x00 21. "WAVAIL,The fifo for the channel has space to place a burst size entry" "0,1"
bitfld.long 0x00 18. "TDOWN_MSG_PEND,A teardown message is pending" "0,1"
bitfld.long 0x00 17. "TX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x00 16. "ERR_EVENT_REQS,The channel is trying to schedule an error event" "0,1"
line.long 0x04 "PKTDMA_TCHANRT_TRT_STATUS1,The Status Register provides a read only view of channel status bits"
bitfld.long 0x04 31. "TX_REQS,The channel is sending a schedule request" "0,1"
bitfld.long 0x04 26. "SOP_WAVAIL,The FIFO has space for the start of a packet" "0,1"
bitfld.long 0x04 25. "MOP_WAVAIL,The FIFO has space for the middle of a packet" "0,1"
bitfld.long 0x04 24. "WAVAIL,The fifo has space for a burst size" "0,1"
newline
bitfld.long 0x04 8. "TDNULL,The channel has met the conditions to attempt to teardown" "0,1"
bitfld.long 0x04 7. "CHANNEL_OK,The channel is trying to schedule work" "0,1"
bitfld.long 0x04 6. "CHANNEL_BUSY,The channel has active work" "0,1"
bitfld.long 0x04 3. "IN_PACKET_ARRAY,The channel is in a packet" "0,1"
group.long 0x80++0x03
line.long 0x00 "PKTDMA_TCHANRT_TRT_STDATA,The State Data Registers contain the current working state of the Tx DMA channel"
repeat 10. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 )
group.long ($2+0x200)++0x03
line.long 0x00 "PKTDMA_TCHANRT_TRT_PEER$1,This register provides access to the remote peer's realtime register at 0x400"
repeat.end
group.long 0x228++0x17
line.long 0x00 "PKTDMA_TCHANRT_TRT_PEER10,This register provides access to the remote peer's realtime register at 0x40A"
line.long 0x04 "PKTDMA_TCHANRT_TRT_PEER11,This register provides access to the remote peer's realtime register at 0x40B"
line.long 0x08 "PKTDMA_TCHANRT_TRT_PEER12,This register provides access to the remote peer's realtime register at 0x40C"
line.long 0x0C "PKTDMA_TCHANRT_TRT_PEER13,This register provides access to the remote peer's realtime register at 0x40D"
line.long 0x10 "PKTDMA_TCHANRT_TRT_PEER14,This register provides access to the remote peer's realtime register at 0x40E"
line.long 0x14 "PKTDMA_TCHANRT_TRT_PEER15,This register provides access to the remote peer's realtime register at 0x40F"
group.long 0x400++0x03
line.long 0x00 "PKTDMA_TCHANRT_TRT_PCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x408++0x03
line.long 0x00 "PKTDMA_TCHANRT_TRT_BCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
group.long 0x410++0x03
line.long 0x00 "PKTDMA_TCHANRT_TRT_SBCNT,The statistics registers are supplied to give software applications operational progress status for the channel"
tree.end
tree "DMASS0_PSILCFG_0_PSILCFG_PROXY"
base ad:0x48130000
rgroup.long 0x00++0x03
line.long 0x00 "PSILCFG_PROXY_REVISION,The Revision Register contains the major and minor revisions for the module"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "PSILCFG_PROXY_PSIL_TO,The PSI-L proxy timeout register controls the timeout watchdog and reports timeout occurrances on PSI-L configuration transactions issued by the built in PSI-L proxy"
bitfld.long 0x00 31. "TOUT,Timeout occurred" "0,1"
hexmask.long.word 0x00 0.--15. 1. "TOUT_CNT,Timeout period"
group.long 0x100++0x0B
line.long 0x00 "PSILCFG_PROXY_PSIL_CMDA,The Command Register A contains the busy indicator. direction. and thread number for the configuration transaction"
bitfld.long 0x00 31. "PROXY_BUSY,Indication that a configuration read or write is in progress" "0,1"
bitfld.long 0x00 30. "PROXY_DIR,Direction of configuration transaction" "0,1"
bitfld.long 0x00 29. "PROXY_TOUT,Indication that a timeout occurred" "0,1"
hexmask.long.word 0x00 0.--15. 1. "PROXY_THREAD_ID,Thread ID to which configuration read or write is being sent"
line.long 0x04 "PSILCFG_PROXY_PSIL_CMDB,The Command Register B contains the byte enables and word address for the configuration transaction"
bitfld.long 0x04 28.--31. "PROXY_BYTEN,Byte enables to use for configuration read or write" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 0.--15. 1. "PROXY_ADDRESS,Word (32-bit) address within thread configuration space for transaction"
line.long 0x08 "PSILCFG_PROXY_PSIL_WDATA,The Write Data Register contains the data which is to be written during the configuration transaction"
group.long 0x140++0x03
line.long 0x00 "PSILCFG_PROXY_PSIL_RDATA,The Read Data Register contains the data which which was read back during the configuration transaction"
tree.end
tree "DMASS0_PSILSS_0_ETLSW_MMRS"
base ad:0x48230000
rgroup.long 0x00++0x07
line.long 0x00 "ETLSW_MMRS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ETLSW_MMRS_config,The Config Register shows configured params"
hexmask.long.word 0x04 0.--15. 1. "ENDPOINTS,Number of endpoints supported"
group.long 0x10++0x03
line.long 0x00 "ETLSW_MMRS_event,The Event Register defines the event to produce for a link down event"
hexmask.long.word 0x00 0.--15. 1. "EVT,The event to produce"
rgroup.long 0x20++0x03
line.long 0x00 "ETLSW_MMRS_link,The Link Register shows the current status of the endpoint links"
group.long 0x40++0x03
line.long 0x00 "ETLSW_MMRS_down,The Link Down Register shows which links are down for the endpoints"
tree.end
tree "DMASS0_PSILSS_0_PSILSS_MMRS"
base ad:0x48140000
rgroup.long 0x00++0x07
line.long 0x00 "PSILSS_MMRS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PSILSS_MMRS_config,The Config Register shows configured params"
hexmask.long.word 0x04 0.--15. 1. "ENDPOINTS,Number of endpoints supported"
group.long 0x10++0x03
line.long 0x00 "PSILSS_MMRS_event,The Event Register defines the event to produce for a link down event"
hexmask.long.word 0x00 0.--15. 1. "EVT,The event to produce"
rgroup.long 0x20++0x03
line.long 0x00 "PSILSS_MMRS_link,The Link Register shows the current status of the endpoint links"
group.long 0x40++0x03
line.long 0x00 "PSILSS_MMRS_down,The Link Down Register shows which links are down for the endpoints"
tree.end
tree "DMASS0_RINGACC_0_RINGACC_CFG"
base ad:0x49800000
group.long 0x40++0x13
line.long 0x00 "RINGACC_CFG_BA_LO,The Tx Ring Base Address Lo Register contains the 32 LSBs of the base address for the ring which is used to hand off pending work for the channel from the Host"
line.long 0x04 "RINGACC_CFG_BA_HI,The Tx Ring Base Address Hi Register contains the 16 MSBs of the base address for the ring which is used to hand off pending work for the channel from the Host"
hexmask.long.word 0x04 0.--15. 1. "ADDR_HI,Tx Ring base address (MSBs)"
line.long 0x08 "RINGACC_CFG_SIZE,The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host"
bitfld.long 0x08 30.--31. "QMODE,Defines the mode for this ring or queue" "0,1,2,3"
bitfld.long 0x08 24.--26. "ELSIZE,Ring element size" "4 bytes,8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,RESERVED"
hexmask.long.tbyte 0x08 0.--19. 1. "SIZE,Tx Ring element count"
line.long 0x0C "RINGACC_CFG_EVT,The Ring Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote the occurrence of an up event [empty to not-empty] or a down event [non-empty to empty] for this ring"
hexmask.long.word 0x0C 0.--15. 1. "EVT,Defines the event for this ring or queue"
line.long 0x10 "RINGACC_CFG_ORDERID,The Ring OrderID Register contains the bus orderid value for the ring memory access"
bitfld.long 0x10 4. "REPLACE,Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field" "bypass and use the orderid from the source..,use the orderid MMR field value for the.."
bitfld.long 0x10 0.--3. "ORDERID,Defines the bus orderid value for this ring or queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "DMASS0_RINGACC_0_RINGACC_GCFG"
base ad:0x48240000
rgroup.long 0x00++0x03
line.long 0x00 "RINGACC_GCFG_revision,The Revision Register contains the major and minor revisions for the module"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "RINGACC_GCFG_trace_ctl,Trace Control Register"
bitfld.long 0x00 31. "EN,Trace enable" "disable,enable"
bitfld.long 0x00 30. "ALL_QUEUES,Trace everything" "only the selected queue,every queue"
bitfld.long 0x00 29. "MSG,Trace message data" "include only the operation,include message data"
hexmask.long.word 0x00 0.--15. 1. "QUEUE,Queue number when tracing a single queue"
group.long 0x20++0x03
line.long 0x00 "RINGACC_GCFG_overflow,Overflow Queue Register"
hexmask.long.word 0x00 0.--15. 1. "QUEUE,Queue to send overflow messages"
group.long 0x40++0x07
line.long 0x00 "RINGACC_GCFG_error_evt,The Error Event Register is an Output Event Steering 'OES' register that specifies the event number used to denote detection of a ring memory transaction bus error"
hexmask.long.word 0x00 0.--15. 1. "EVT,Event to send when detecting a bus error"
line.long 0x04 "RINGACC_GCFG_error_log,Error Log Register"
bitfld.long 0x04 31. "PUSH,Bus error was caused by a push" "pop,push"
hexmask.long.word 0x04 0.--15. 1. "QUEUE,Queue that received the bus error"
tree.end
tree "DMASS0_RINGACC_0_RINGACC_RT"
base ad:0x49000000
group.long 0x10++0x03
line.long 0x00 "RINGACC_RT_RT_DB,The Ring N Doorbell Register is written by software to increment or decrement the number of entries on a Ring"
hexmask.long.byte 0x00 0.--7. 1. "ENTRY_CNT,Signed number of entries by which to increment the ring occupancy"
group.long 0x18++0x0F
line.long 0x00 "RINGACC_RT_RT_OCC,The Ring N Occupancy Register can be read by software to determine the total number of valid entries on a ring"
hexmask.long.tbyte 0x00 0.--20. 1. "OCC,Total number of valid entries on the ring"
line.long 0x04 "RINGACC_RT_RT_INDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current SW read index for the Ring for the channel"
hexmask.long.tbyte 0x04 0.--19. 1. "INDX,Current SW owned read index for the ring"
line.long 0x08 "RINGACC_RT_RT_HWOCC,The Ring N Hardware Occupancy Register contains the early increment/decrement version of the the total number of valid entries on a ring"
hexmask.long.tbyte 0x08 0.--20. 1. "OCC,Total number of valid entries on the ring"
line.long 0x0C "RINGACC_RT_RT_HWINDX,The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel"
hexmask.long.tbyte 0x0C 0.--19. 1. "INDX,Current HW owned read index for the ring"
tree.end
tree "DPHY_RX0_MMR_SLV_K3_DPHY_WRAP"
base ad:0x30111000
group.long 0x00++0x03
line.long 0x00 "MMR__SLV__K3_DPHY_WRAP_REGS_lane,lane control and status"
bitfld.long 0x00 31. "RXCLKACTIVEHSCLK,Receiver high speed clock active: Driven active when the receiver high speed clock is active" "Receiver high speed clock not active,Receiver high speed clock active"
newline
bitfld.long 0x00 30. "CMN_READY,Common ready indication: Indicates the completion of the startup process of the common module" "Indicates that the startup process for the..,Indicates that the startup process for the.."
newline
bitfld.long 0x00 26. "PSO_DISABLE,Disable power shut off: Disables the ability to switch off the analog switched power islands in the lane when in the ultra low power state" "Power islands are switched off and on under the..,Power island shutoff functions disabled and.."
newline
bitfld.long 0x00 24. "PSO_CMN,Disable power shut off: Power Shutoff signal for CMN" "CMN is power ON,CMN is power OFF"
newline
bitfld.long 0x00 23. "LANE_RSTB_CMN,SW reset for CMN" "asserted,released"
newline
abitfld.long 0x00 16.--22. "PSM_CLOCK_FREQ,PMA state machine clock frequency divider control: This signal specifies a divider value used to create an internal divided clock that is a function of the psm_clock clock" "0x00=Reserved #,0x01=Div 1 #,0x02=Div 2 #,0x03=Div 3 #,0x04=Div 4"
newline
bitfld.long 0x00 9.--11. "IPCONFIG_CMN,This signal decides which clock lane acts as master clock lane to all data lanes" "Left RX clk lane provides clock to all left and..,Left RX clk lane provides clock to all right..,Right RX clk lane provides clock to all right..,Right RX clk lane provides clock to all left and..,?..."
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bitfld.long 0x00 8. "CLK_SWAPDPDN_DL_L_3,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "Not swapped,Swapped"
newline
bitfld.long 0x00 7. "CLK_SWAPDPDN_DL_L_2,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "Not swapped,Swapped"
newline
bitfld.long 0x00 6. "DATA_SWAPDPDN_DL_L_3,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "Not swapped,Swapped"
newline
bitfld.long 0x00 5. "DATA_SWAPDPDN_DL_L_2,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "Not swapped,Swapped"
newline
bitfld.long 0x00 4. "CLK_SWAPDPDN_DL_L_1,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "Not swapped,Swapped"
newline
bitfld.long 0x00 3. "CLK_SWAPDPDN_DL_L_0,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "Not swapped,Swapped"
newline
bitfld.long 0x00 2. "DATA_SWAPDPDN_DL_L_1,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "Not swapped,Swapped"
newline
bitfld.long 0x00 1. "DATA_SWAPDPDN_DL_L_0,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "Not swapped,Swapped"
newline
bitfld.long 0x00 0. "CLK_SWAPDPDN_CL_L,Swap DP and DN: When enabled the rx_p and rx_m differential pins will be swapped" "Not swapped,Swapped"
tree.end
tree "DPHY_RX0_VBUS2APB_WRAP_VBUSP_K3_DPHY_RX"
base ad:0x30110000
group.long 0x20++0x03
line.long 0x00 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT2,CMN_DIG_TBIT2"
bitfld.long 0x00 10. "O_CMN_RX_MODE_EN,Enable CMN RX related StateMachines" "0,1"
bitfld.long 0x00 9. "O_CMN_TX_MODE_EN,Enable CMN TX related StateMachines" "0,1"
newline
hexmask.long.byte 0x00 1.--8. 1. "O_SSM_WAIT_BGCAL_EN,Wait time for Calibrations enable after bandgap is enabled [in us]"
bitfld.long 0x00 0. "O_CMN_SSM_EN,Enable CMN startup state machine" "0,1"
group.long 0x40++0x03
line.long 0x00 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT10,CMN_DIG_TBIT10"
hexmask.long.byte 0x00 20.--27. 1. "O_ANA_PLL_BYTECLK_DIV,Byteclk divider value"
hexmask.long.word 0x00 10.--19. 1. "O_ANA_PLL_GM_PWM_DIV_LOW,Low division value setting for the gm PWM control divider"
newline
hexmask.long.word 0x00 0.--9. 1. "O_ANA_PLL_GM_PWM_DIV_HIGH,High division value setting for the gm PWM control divider"
group.long 0x4C++0x07
line.long 0x00 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT13,CMN_DIG_TBIT13"
hexmask.long.word 0x00 22.--31. 1. "O_ANA_PLL_FB_DIV_LOW_TM,forced value for pll_fb_div_clk_low"
bitfld.long 0x00 21. "O_ANA_PLL_FB_DIV_LOW_TM_SEL,pll_fb_div_clk_low forced from test registers" "0,1"
newline
hexmask.long.word 0x00 11.--20. 1. "O_ANA_PLL_FB_DIV_HIGH_TM,forced value for pll_fb_div_clk_high"
bitfld.long 0x00 10. "O_ANA_PLL_FB_DIV_HIGH_TM_SEL,pll_fb_div_clk_high forced from test registers" "0,1"
line.long 0x04 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_CMN0_CMN_DIG_TBIT14,CMN_DIG_TBIT14"
bitfld.long 0x04 7.--12. "O_ANA_PLL_OP_DIV_TM,forced value for op_div" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 6. "O_ANA_PLL_OP_DIV_TM_SEL,op_div forced from test registers" "0,1"
newline
bitfld.long 0x04 1.--5. "O_ANA_PLL_IP_DIV_TM,forced value for ip_div" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0. "O_ANA_PLL_IP_DIV_TM_SEL,ip_div forced from test registers" "0,1"
group.long 0xB00++0x0F
line.long 0x00 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT0,PHY_BAND_CONTROL"
bitfld.long 0x00 5.--9. "BAND_CTL_REG_R,Data Rate [80_100] MHz" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "BAND_CTL_REG_L,Data Rate [80_100] MHz" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT1,PHY_PSM_CONFIG"
hexmask.long.byte 0x04 1.--8. 1. "PSM_CLOCK_FREQ,psm_clock freq value"
bitfld.long 0x04 0. "PSM_CLOCK_FREQ_EN,take psm_clock_freq from tbit" "0,1"
line.long 0x08 "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT2,PHY_PI_PH2_DL_CONFIG"
bitfld.long 0x08 28.--31. "POWER_SW_2_TIME_DL_R_3,power_sw_2_time_dl_r_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 24.--27. "POWER_SW_2_TIME_DL_R_2,power_sw_2_time_dl_r_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 20.--23. "POWER_SW_2_TIME_DL_R_1,power_sw_2_time_dl_r_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 16.--19. "POWER_SW_2_TIME_DL_R_0,power_sw_2_time_dl_r_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 12.--15. "POWER_SW_2_TIME_DL_L_3,power_sw_2_time_dl_l_3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 8.--11. "POWER_SW_2_TIME_DL_L_2,power_sw_2_time_dl_l_2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 4.--7. "POWER_SW_2_TIME_DL_L_1,power_sw_2_time_dl_l_1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--3. "POWER_SW_2_TIME_DL_L_0,power_sw_2_time_dl_l_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "VBUS2APB_WRAP__VBUSP__K3_DPHY_RX_REGS_PCS_TX_DIG_TBIT3,PHY_PI_PH2_CL_CMN_CONFIG"
bitfld.long 0x0C 8.--11. "POWER_SW_2_TIME_CMN,power_sw_2_time_cmn" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 4.--7. "POWER_SW_2_TIME_CL_R,power_sw_2_time_cl_r" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0.--3. "POWER_SW_2_TIME_CL_L,power_sw_2_time_cl_l" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "DSS0_COMMON"
base ad:0x30200000
rgroup.long 0x04++0x07
line.long 0x00 "COMMON_DSS_REVISION,This register contains the K3_DSS revision number"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID Field"
bitfld.long 0x00 11.--15. "REVRTL,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "COMMON_DSS_SYSCONFIG,This register controls various parameters related to software reset and IP idle"
hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED4,Write 0's for future compatibility"
rbitfld.long 0x04 8.--13. "RESERVED3,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x04 6.--7. "RESERVED2,Write 0's for future compatibility" "0,1,2,3"
newline
bitfld.long 0x04 5. "WARMRESET,Warm reset" "0,1"
bitfld.long 0x04 3.--4. "IDLEMODE,Deprecated" "0,1,2,3"
rbitfld.long 0x04 2. "RESERVED1,Write 0's for future compatibility" "0,1"
newline
bitfld.long 0x04 1. "SOFTRESET,Software reset" "0,1"
bitfld.long 0x04 0. "AUTOCLKGATING,Internal clock gating strategy" "0,1"
rgroup.long 0x20++0x13
line.long 0x00 "COMMON_DSS_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information"
bitfld.long 0x00 9. "DISPC_IDLE_STATUS,Idle status of DISPC" "0,1"
bitfld.long 0x00 5. "OLDI_RESETDONE,Reset status of OLDI" "0,1"
bitfld.long 0x00 1.--2. "DISPC_VP_RESETDONE,Reset status of VP pixel clock domain" "0,1,2,3"
newline
bitfld.long 0x00 0. "DISPC_FUNC_RESETDONE,Reset status of DISPC Functional clock domain" "0,1"
line.long 0x04 "COMMON_DISPC_IRQ_EOI,End-Of-Interrupt register. to be used if pulse interrupts are used"
bitfld.long 0x04 0. "EOI,Write 1 to acknowledge a pulse IRQ" "0,1"
line.long 0x08 "COMMON_DISPC_IRQSTATUS_RAW,RAW Interrupt status"
bitfld.long 0x08 4.--5. "VID_IRQ,VID IRQ STATUS" "0,1,2,3"
bitfld.long 0x08 0.--1. "VP_IRQ,VP IRQ STATUS" "0,1,2,3"
line.long 0x0C "COMMON_DISPC_IRQSTATUS,Interrupt status"
bitfld.long 0x0C 4.--5. "VID_IRQ,VID IRQ STATUS" "0,1,2,3"
bitfld.long 0x0C 0.--1. "VP_IRQ,VP IRQ STATUS" "0,1,2,3"
line.long 0x10 "COMMON_DISPC_IRQENABLE_SET,SET Interrupt enable"
bitfld.long 0x10 4.--5. "SET_VID_IRQ,VID IRQ" "0,1,2,3"
bitfld.long 0x10 0.--1. "SET_VP_IRQ,VP IRQ" "0,1,2,3"
group.long 0x40++0x0B
line.long 0x00 "COMMON_DISPC_IRQENABLE_CLR,CLR Interrupt enable"
bitfld.long 0x00 4.--5. "CLR_VID_IRQ,VID IRQ" "0,1,2,3"
bitfld.long 0x00 0.--1. "CLR_VP_IRQ,VP IRQ" "0,1,2,3"
line.long 0x04 "COMMON_VID_IRQENABLE_0,This register allows to mask/unmask the VID_0 internal sources of interrupt. on an event-by-event basis"
bitfld.long 0x04 2. "SAFETYREGION_EN,Safety Feature IRQ" "0,1"
bitfld.long 0x04 1. "VIDENDWINDOW_EN,Video End Window" "0,1"
bitfld.long 0x04 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow" "0,1"
line.long 0x08 "COMMON_VID_IRQENABLE_1,This register allows to mask/unmask the VIDL_0 internal sources of interrupt. on an event-by-event basis"
bitfld.long 0x08 2. "SAFETYREGION_EN,Safety Feature IRQ" "0,1"
bitfld.long 0x08 1. "VIDENDWINDOW_EN,Video End Window" "0,1"
bitfld.long 0x08 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow" "0,1"
group.long 0x58++0x07
line.long 0x00 "COMMON_VID_IRQSTATUS_0,This register groups all the status of the VID_0 internal events that generate an interrupt"
bitfld.long 0x00 2. "SAFETYREGION_IRQ,Safety Feature IRQ" "0,1"
bitfld.long 0x00 1. "VIDENDWINDOW_IRQ,Video End Window" "0,1"
bitfld.long 0x00 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow" "0,1"
line.long 0x04 "COMMON_VID_IRQSTATUS_1,This register groups all the status of the VIDL_0 internal events that generate an interrupt"
bitfld.long 0x04 2. "SAFETYREGION_IRQ,Safety Feature IRQ" "0,1"
bitfld.long 0x04 1. "VIDENDWINDOW_IRQ,Video End Window" "0,1"
bitfld.long 0x04 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow" "0,1"
group.long 0x70++0x07
line.long 0x00 "COMMON_VP_IRQENABLE_0,This register allows to mask/unmask the VP_0 internal sources of interrupt. on an event-by-event basis"
bitfld.long 0x00 12. "DUMMY_EN,Dummy IRQ for future use" "0,1"
bitfld.long 0x00 11. "VPSYNC_EN,Go bit clear event" "0,1"
bitfld.long 0x00 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP" "0,1"
newline
bitfld.long 0x00 6.--9. "SAFETYREGION_EN,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1"
bitfld.long 0x00 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1"
newline
bitfld.long 0x00 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number" "0,1"
bitfld.long 0x00 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1"
bitfld.long 0x00 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1"
newline
bitfld.long 0x00 0. "VPFRAMEDONE_EN,Frame Done for Video Port" "0,1"
line.long 0x04 "COMMON_VP_IRQENABLE_1,This register allows to mask/unmask the VP_1 internal sources of interrupt. on an event-by-event basis"
bitfld.long 0x04 12. "DUMMY_EN,Dummy IRQ for future use" "0,1"
bitfld.long 0x04 11. "VPSYNC_EN,Go bit clear event" "0,1"
bitfld.long 0x04 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP" "0,1"
newline
bitfld.long 0x04 6.--9. "SAFETYREGION_EN,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1"
bitfld.long 0x04 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1"
newline
bitfld.long 0x04 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number" "0,1"
bitfld.long 0x04 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1"
bitfld.long 0x04 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1"
newline
bitfld.long 0x04 0. "VPFRAMEDONE_EN,Frame Done for Video Port" "0,1"
group.long 0x7C++0x07
line.long 0x00 "COMMON_VP_IRQSTATUS_0,This register groups all the status of the VP_0 internal events that generate an interrupt"
bitfld.long 0x00 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1"
bitfld.long 0x00 11. "VPSYNC_IRQ,Go bit clear event" "0,1"
bitfld.long 0x00 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ" "0,1"
newline
bitfld.long 0x00 6.--9. "SAFETYREGION_IRQ,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1"
bitfld.long 0x00 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output" "0,1"
newline
bitfld.long 0x00 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number" "0,1"
bitfld.long 0x00 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field" "0,1"
bitfld.long 0x00 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output" "0,1"
newline
bitfld.long 0x00 0. "VPFRAMEDONE_IRQ,Frame Done for VP" "0,1"
line.long 0x04 "COMMON_VP_IRQSTATUS_1,This register groups all the status of the VP_1 internal events that generate an interrupt"
bitfld.long 0x04 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1"
bitfld.long 0x04 11. "VPSYNC_IRQ,Go bit clear event" "0,1"
bitfld.long 0x04 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ" "0,1"
newline
bitfld.long 0x04 6.--9. "SAFETYREGION_IRQ,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1"
bitfld.long 0x04 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output" "0,1"
newline
bitfld.long 0x04 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number" "0,1"
bitfld.long 0x04 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field" "0,1"
bitfld.long 0x04 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output" "0,1"
newline
bitfld.long 0x04 0. "VPFRAMEDONE_IRQ,Frame Done for VP" "0,1"
group.long 0x90++0x1F
line.long 0x00 "COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE,MFLAG control register"
bitfld.long 0x00 6. "MFLAG_START,MFLAG_START for DMA master port" "0,1"
bitfld.long 0x00 0.--1. "MFLAG_CTRL,MFLAG_CTRL for DMA master port" "0,1,2,3"
line.long 0x04 "COMMON_DISPC_GLOBAL_OUTPUT_ENABLE,DISPC global output enable register"
bitfld.long 0x04 16.--18. "VP_GO,Global GO Command for the VP[2:0] output" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0.--2. "VP_ENABLE,Global VP[2:0] Enable" "0,1,2,3,4,5,6,7"
line.long 0x08 "COMMON_DISPC_GLOBAL_BUFFER,The register configures the DMA buffers allocations to the pipelines for DMA"
bitfld.long 0x08 31. "BUFFERFILLING,Controls if the DMA buffers are re-filled only when the LOW threshold is reached or if all DMA buffers are re-filled when at least one of them reaches the LOW threshold" "0,1"
bitfld.long 0x08 3.--5. "VIDL1_BUFFER,VIDL1 DMA buffer allocation to one of the pipelines" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 0.--2. "VID_BUFFER,VID DMA buffer allocation to one of the pipelines" "0,1,2,3,4,5,6,7"
line.long 0x0C "COMMON_DSS_CBA_CFG,This register contains CBA specific config bits in DSS"
bitfld.long 0x0C 6.--8. "RESERVED1,Reserved : TI internal" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 3.--5. "PRI_HI,The value sent out on the PRI_HI bus from DSS to CBA Indicates the priority level for high-priority [MFLAG] transactions" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0.--2. "PRI_LO,The value sent out on the PRI_LO bus from DSS to CBA Indicates the priority level for normal [non-MFLAG] transactions" "0,1,2,3,4,5,6,7"
line.long 0x10 "COMMON_DISPC_DBG_CONTROL,DISPC debug status control register"
hexmask.long.byte 0x10 1.--8. 1. "DBGMUXSEL,Mux select for the debug status"
bitfld.long 0x10 0. "DBGEN,Enable debug ports" "0,1"
line.long 0x14 "COMMON_DISPC_DBG_STATUS,DISPC debug status register"
line.long 0x18 "COMMON_DISPC_CLKGATING_DISABLE,Register to control clock gating at DISPC sub-module level"
bitfld.long 0x18 18.--19. "VP,Clock gating control for VP[2:0]" "0,1,2,3"
bitfld.long 0x18 14.--15. "OVR,Clock gating control for OVR[2:0]" "0,1,2,3"
bitfld.long 0x18 3.--4. "VID,Clock gating control for VID" "0,1,2,3"
newline
bitfld.long 0x18 0. "DMA,Clock gating control for DMA" "0,1"
line.long 0x1C "COMMON_DISPC_SECURE_DISABLE,Disable security settings throughout DSS IP"
bitfld.long 0x1C 0. "SECURE_DISABLE,Secure disable bit" "0,1"
tree.end
tree "DSS0_COMMON1"
base ad:0x30201000
group.long 0x24++0x0F
line.long 0x00 "COMMON1_DISPC_IRQ_EOI,End Of Interrupt number"
hexmask.long 0x00 1.--31. 1. "RESERVED,"
bitfld.long 0x00 0. "EOI,Software End Of Interrupt [EOI] control if pulse interrupts are used" "0,1"
line.long 0x04 "COMMON1_DISPC_IRQSTATUS_RAW,RAW Interrupt status"
bitfld.long 0x04 4.--5. "VID_IRQ,VID IRQ STATUS" "0,1,2,3"
bitfld.long 0x04 0.--1. "VP_IRQ,VP IRQ STATUS" "0,1,2,3"
line.long 0x08 "COMMON1_DISPC_IRQSTATUS,Interrupt status"
bitfld.long 0x08 4.--5. "VID_IRQ,VID IRQ STATUS" "0,1,2,3"
bitfld.long 0x08 0.--1. "VP_IRQ,VP IRQ STATUS" "0,1,2,3"
line.long 0x0C "COMMON1_DISPC_IRQENABLE_SET,SET Interrupt enable"
bitfld.long 0x0C 4.--5. "SET_VID_IRQ,VID IRQ" "0,1,2,3"
bitfld.long 0x0C 0.--1. "SET_VP_IRQ,VP IRQ" "0,1,2,3"
group.long 0x40++0x0B
line.long 0x00 "COMMON1_DISPC_IRQENABLE_CLR,CLR Interrupt enable"
bitfld.long 0x00 4.--5. "CLR_VID_IRQ,VID IRQ" "0,1,2,3"
bitfld.long 0x00 0.--1. "CLR_VP_IRQ,VP IRQ" "0,1,2,3"
line.long 0x04 "COMMON1_VID_IRQENABLE_0,This register allows to mask/unmask the VID_0 internal sources of interrupt. on an event-by-event basis"
bitfld.long 0x04 2. "SAFETYREGION_EN,Safety Feature IRQ" "0,1"
bitfld.long 0x04 1. "VIDENDWINDOW_EN,Video End Window" "0,1"
bitfld.long 0x04 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow" "0,1"
line.long 0x08 "COMMON1_VID_IRQENABLE_1,This register allows to mask/unmask the VIDL_0 internal sources of interrupt. on an event-by-event basis"
bitfld.long 0x08 2. "SAFETYREGION_EN,Safety Feature IRQ" "0,1"
bitfld.long 0x08 1. "VIDENDWINDOW_EN,Video End Window" "0,1"
bitfld.long 0x08 0. "VIDBUFFERUNDERFLOW_EN,Video DMA Buffer Underflow" "0,1"
group.long 0x54++0x03
line.long 0x00 "COMMON1_DISPC_SECURE,Security bit settings for different DISPC sub-modules"
bitfld.long 0x00 15.--16. "OVR_SECURE,Secure bit for OVR" "0,1,2,3"
bitfld.long 0x00 4.--5. "VID_SECURE,Secure bit for VID" "0,1,2,3"
bitfld.long 0x00 0.--1. "VP_SECURE,Secure bit for VP [Unused in K3_DSS]" "0,1,2,3"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x58)++0x03
line.long 0x00 "COMMON1_VID_IRQSTATUS_$1,This register groups all the status of the VID_0 internal events that generate an interrupt"
bitfld.long 0x00 2. "SAFETYREGION_IRQ,Safety Feature IRQ" "0,1"
bitfld.long 0x00 1. "VIDENDWINDOW_IRQ,Video End Window" "0,1"
bitfld.long 0x00 0. "VIDBUFFERUNDERFLOW_IRQ,Video DMA Buffer Underflow" "0,1"
repeat.end
group.long 0x70++0x07
line.long 0x00 "COMMON1_VP_IRQENABLE_0,This register allows to mask/unmask the VP_0 internal sources of interrupt. on an event-by-event basis"
bitfld.long 0x00 12. "DUMMY_EN,Dummy IRQ for future use" "0,1"
bitfld.long 0x00 11. "VPSYNC_EN,Go bit clear event" "0,1"
bitfld.long 0x00 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP" "0,1"
bitfld.long 0x00 6.--9. "SAFETYREGION_EN,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1"
bitfld.long 0x00 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1"
bitfld.long 0x00 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number" "0,1"
bitfld.long 0x00 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1"
newline
bitfld.long 0x00 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1"
bitfld.long 0x00 0. "VPFRAMEDONE_EN,Frame Done for Video Port" "0,1"
line.long 0x04 "COMMON1_VP_IRQENABLE_1,This register allows to mask/unmask the VP_1 internal sources of interrupt. on an event-by-event basis"
bitfld.long 0x04 12. "DUMMY_EN,Dummy IRQ for future use" "0,1"
bitfld.long 0x04 11. "VPSYNC_EN,Go bit clear event" "0,1"
bitfld.long 0x04 10. "SECURITYVIOLATION_EN,Security Violation interrupt for OVR/VP" "0,1"
bitfld.long 0x04 6.--9. "SAFETYREGION_EN,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 5. "ACBIASCOUNTSTATUS_EN,AC BIAS transition counter has decremented to zero" "0,1"
bitfld.long 0x04 4. "VPSYNCLOST_EN,Synchronization Lost for Video Port" "0,1"
bitfld.long 0x04 3. "VPPROGRAMMEDLINENUMBER_EN,Programmed Line Number" "0,1"
bitfld.long 0x04 2. "VPVSYNC_ODD_EN,VSYNC for odd field from interlace mode only" "0,1"
newline
bitfld.long 0x04 1. "VPVSYNC_EN,Vertical Synchronization for VP" "0,1"
bitfld.long 0x04 0. "VPFRAMEDONE_EN,Frame Done for Video Port" "0,1"
group.long 0x7C++0x07
line.long 0x00 "COMMON1_VP_IRQSTATUS_0,This register groups all the status of the VP_0 internal events that generate an interrupt"
bitfld.long 0x00 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1"
bitfld.long 0x00 11. "VPSYNC_IRQ,Go bit clear event" "0,1"
bitfld.long 0x00 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ" "0,1"
bitfld.long 0x00 6.--9. "SAFETYREGION_IRQ,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1"
bitfld.long 0x00 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output" "0,1"
bitfld.long 0x00 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number" "0,1"
bitfld.long 0x00 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field" "0,1"
newline
bitfld.long 0x00 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output" "0,1"
bitfld.long 0x00 0. "VPFRAMEDONE_IRQ,Frame Done for VP" "0,1"
line.long 0x04 "COMMON1_VP_IRQSTATUS_1,This register groups all the status of the VP_1 internal events that generate an interrupt"
bitfld.long 0x04 12. "DUMMY_IRQ,Dummy IRQ for future use" "0,1"
bitfld.long 0x04 11. "VPSYNC_IRQ,Go bit clear event" "0,1"
bitfld.long 0x04 10. "SECURITYVIOLATION_IRQ,Security Violation IRQ" "0,1"
bitfld.long 0x04 6.--9. "SAFETYREGION_IRQ,Safety Feature IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 5. "ACBIASCOUNTSTATUS_IRQ,AC BIAS transition counter has decremented to zero" "0,1"
bitfld.long 0x04 4. "VPSYNCLOST_IRQ,Synchronization Lost on VP output" "0,1"
bitfld.long 0x04 3. "VPPROGRAMMEDLINENUMBER_IRQ,Programmed Line Number" "0,1"
bitfld.long 0x04 2. "VPVSYNC_ODD_IRQ,VSYNC for odd field" "0,1"
newline
bitfld.long 0x04 1. "VPVSYNC_IRQ,Vertical Synchronization for VP output" "0,1"
bitfld.long 0x04 0. "VPFRAMEDONE_IRQ,Frame Done for VP" "0,1"
tree.end
tree "DSS0_OVR1"
base ad:0x30207000
group.long 0x00++0x03
line.long 0x00 "OVR1_CONFIG,The control register configures the Display Controller module for the VP output"
hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED1,"
rbitfld.long 0x00 13. "RESERVED3," "0,1"
rbitfld.long 0x00 12. "RESERVED2," "0,1"
bitfld.long 0x00 11. "TCKLCDSELECTION,Transparency Color Key Selection" "0,1"
bitfld.long 0x00 10. "TCKLCDENABLE,Transparency Color Key Enable" "0,1"
hexmask.long.byte 0x00 2.--9. 1. "RESERVED,"
newline
bitfld.long 0x00 1. "COLORBAREN,Enable the Color-Bar" "0,1"
rbitfld.long 0x00 0. "RESERVED6," "0,1"
group.long 0x08++0x27
line.long 0x00 "OVR1_DEFAULT_COLOR,The control register configures the default solid background color LSB[31:0]"
line.long 0x04 "OVR1_DEFAULT_COLOR2,The control register configures the default solid background color MSB[47:32]"
hexmask.long.word 0x04 16.--31. 1. "RESERVED,"
hexmask.long.word 0x04 0.--15. 1. "DEFAULTCOLOR,16-bit MSB of ARGB background color"
line.long 0x08 "OVR1_TRANS_COLOR_MAX,The register sets the max transparency color value for the overlays"
line.long 0x0C "OVR1_TRANS_COLOR_MAX2,The register sets the max transparency color value for the overlays"
hexmask.long 0x0C 4.--31. 1. "RESERVED,"
bitfld.long 0x0C 0.--3. "TRANSCOLORKEY,MSB[35:32]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "OVR1_TRANS_COLOR_MIN,The register sets the min transparency color value for the overlays"
line.long 0x14 "OVR1_TRANS_COLOR_MIN2,The register sets the min transparency color value for the overlays"
hexmask.long 0x14 4.--31. 1. "RESERVED,"
bitfld.long 0x14 0.--3. "TRANSCOLORKEY,MSB[35:32]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "OVR1_ATTRIBUTES_0,The register configures the attributes of layer-0. ZORDER= 0. of the Overlay manager"
rbitfld.long 0x18 31. "RESERVED1," "0,1"
hexmask.long.word 0x18 19.--30. 1. "POSY,Y position of the layer"
rbitfld.long 0x18 18. "RESERVED," "0,1"
hexmask.long.word 0x18 6.--17. 1. "POSX,X position of the layer"
rbitfld.long 0x18 5. "RESERVED2," "0,1"
bitfld.long 0x18 1.--4. "CHANNELIN,Input channel connected to Layer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 0. "ENABLE,Layer Enable" "0,1"
line.long 0x1C "OVR1_ATTRIBUTES_1,The register configures the attributes of layer-1. ZORDER= 1. of the Overlay manager"
rbitfld.long 0x1C 31. "RESERVED1," "0,1"
hexmask.long.word 0x1C 19.--30. 1. "POSY,Y position of the layer"
rbitfld.long 0x1C 18. "RESERVED," "0,1"
hexmask.long.word 0x1C 6.--17. 1. "POSX,X position of the layer"
rbitfld.long 0x1C 5. "RESERVED2," "0,1"
bitfld.long 0x1C 1.--4. "CHANNELIN,Input channel connected to Layer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 0. "ENABLE,Layer Enable" "0,1"
line.long 0x20 "OVR1_ATTRIBUTES_2,The register configures the attributes of layer-2. ZORDER= 2. of the Overlay manager"
rbitfld.long 0x20 31. "RESERVED1," "0,1"
hexmask.long.word 0x20 19.--30. 1. "POSY,Y position of the layer"
rbitfld.long 0x20 18. "RESERVED," "0,1"
hexmask.long.word 0x20 6.--17. 1. "POSX,X position of the layer"
rbitfld.long 0x20 5. "RESERVED2," "0,1"
bitfld.long 0x20 1.--4. "CHANNELIN,Input channel connected to Layer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 0. "ENABLE,Layer Enable" "0,1"
line.long 0x24 "OVR1_ATTRIBUTES_3,The register configures the attributes of layer-3. ZORDER= 3. of the Overlay manager"
rbitfld.long 0x24 31. "RESERVED1," "0,1"
hexmask.long.word 0x24 19.--30. 1. "POSY,Y position of the layer"
rbitfld.long 0x24 18. "RESERVED," "0,1"
hexmask.long.word 0x24 6.--17. 1. "POSX,X position of the layer"
rbitfld.long 0x24 5. "RESERVED2," "0,1"
bitfld.long 0x24 1.--4. "CHANNELIN,Input channel connected to Layer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 0. "ENABLE,Layer Enable" "0,1"
tree.end
tree "DSS0_OVR2"
base ad:0x30208000
group.long 0x00++0x03
line.long 0x00 "OVR2_CONFIG,The control register configures the Display Controller module for the VP output"
hexmask.long.tbyte 0x00 14.--31. 1. "RESERVED1,"
rbitfld.long 0x00 13. "RESERVED3," "0,1"
rbitfld.long 0x00 12. "RESERVED2," "0,1"
bitfld.long 0x00 11. "TCKLCDSELECTION,Transparency Color Key Selection" "0,1"
bitfld.long 0x00 10. "TCKLCDENABLE,Transparency Color Key Enable" "0,1"
hexmask.long.byte 0x00 2.--9. 1. "RESERVED,"
newline
bitfld.long 0x00 1. "COLORBAREN,Enable the Color-Bar" "0,1"
rbitfld.long 0x00 0. "RESERVED6," "0,1"
group.long 0x08++0x27
line.long 0x00 "OVR2_DEFAULT_COLOR,The control register configures the default solid background color LSB[31:0]"
line.long 0x04 "OVR2_DEFAULT_COLOR2,The control register configures the default solid background color MSB[47:32]"
hexmask.long.word 0x04 16.--31. 1. "RESERVED,"
hexmask.long.word 0x04 0.--15. 1. "DEFAULTCOLOR,16-bit MSB of ARGB background color"
line.long 0x08 "OVR2_TRANS_COLOR_MAX,The register sets the max transparency color value for the overlays"
line.long 0x0C "OVR2_TRANS_COLOR_MAX2,The register sets the max transparency color value for the overlays"
hexmask.long 0x0C 4.--31. 1. "RESERVED,"
bitfld.long 0x0C 0.--3. "TRANSCOLORKEY,MSB[35:32]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "OVR2_TRANS_COLOR_MIN,The register sets the min transparency color value for the overlays"
line.long 0x14 "OVR2_TRANS_COLOR_MIN2,The register sets the min transparency color value for the overlays"
hexmask.long 0x14 4.--31. 1. "RESERVED,"
bitfld.long 0x14 0.--3. "TRANSCOLORKEY,MSB[35:32]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "OVR2_ATTRIBUTES_0,The register configures the attributes of layer-0. ZORDER= 0. of the Overlay manager"
rbitfld.long 0x18 31. "RESERVED1," "0,1"
hexmask.long.word 0x18 19.--30. 1. "POSY,Y position of the layer"
rbitfld.long 0x18 18. "RESERVED," "0,1"
hexmask.long.word 0x18 6.--17. 1. "POSX,X position of the layer"
rbitfld.long 0x18 5. "RESERVED2," "0,1"
bitfld.long 0x18 1.--4. "CHANNELIN,Input channel connected to Layer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 0. "ENABLE,Layer Enable" "0,1"
line.long 0x1C "OVR2_ATTRIBUTES_1,The register configures the attributes of layer-1. ZORDER= 1. of the Overlay manager"
rbitfld.long 0x1C 31. "RESERVED1," "0,1"
hexmask.long.word 0x1C 19.--30. 1. "POSY,Y position of the layer"
rbitfld.long 0x1C 18. "RESERVED," "0,1"
hexmask.long.word 0x1C 6.--17. 1. "POSX,X position of the layer"
rbitfld.long 0x1C 5. "RESERVED2," "0,1"
bitfld.long 0x1C 1.--4. "CHANNELIN,Input channel connected to Layer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 0. "ENABLE,Layer Enable" "0,1"
line.long 0x20 "OVR2_ATTRIBUTES_2,The register configures the attributes of layer-2. ZORDER= 2. of the Overlay manager"
rbitfld.long 0x20 31. "RESERVED1," "0,1"
hexmask.long.word 0x20 19.--30. 1. "POSY,Y position of the layer"
rbitfld.long 0x20 18. "RESERVED," "0,1"
hexmask.long.word 0x20 6.--17. 1. "POSX,X position of the layer"
rbitfld.long 0x20 5. "RESERVED2," "0,1"
bitfld.long 0x20 1.--4. "CHANNELIN,Input channel connected to Layer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 0. "ENABLE,Layer Enable" "0,1"
line.long 0x24 "OVR2_ATTRIBUTES_3,The register configures the attributes of layer-3. ZORDER= 3. of the Overlay manager"
rbitfld.long 0x24 31. "RESERVED1," "0,1"
hexmask.long.word 0x24 19.--30. 1. "POSY,Y position of the layer"
rbitfld.long 0x24 18. "RESERVED," "0,1"
hexmask.long.word 0x24 6.--17. 1. "POSX,X position of the layer"
rbitfld.long 0x24 5. "RESERVED2," "0,1"
bitfld.long 0x24 1.--4. "CHANNELIN,Input channel connected to Layer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 0. "ENABLE,Layer Enable" "0,1"
tree.end
tree "DSS0_VID"
base ad:0x30206000
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x00)++0x03
line.long 0x00 "VID_ACCUH_$1,The register configures the resize accumulator init values for horizontal up/down-sampling of the video window"
hexmask.long.tbyte 0x00 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x08)++0x03
line.long 0x00 "VID_ACCUH2_$1,The register configures the resize accumulator init value for horizontal up/down-sampling of the video window"
hexmask.long.tbyte 0x00 0.--23. 1. "HORIZONTALACCU,Horizontal initialization accu signed value"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x10)++0x03
line.long 0x00 "VID_ACCUV_$1,The register configures the resize accumulator init values for horizontal and vertical up/down-sampling of the video window"
hexmask.long.tbyte 0x00 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x18)++0x03
line.long 0x00 "VID_ACCUV2_$1,The register configures the resize accumulator init value for vertical up/down-sampling of the video window"
hexmask.long.tbyte 0x00 0.--23. 1. "VERTICALACCU,Vertical initialization accu signed value"
repeat.end
group.long 0x20++0x07
line.long 0x00 "VID_ATTRIBUTES,The register configures the attributes of the video window"
bitfld.long 0x00 31. "LUMAKEYENABLE,Enable Luma Key transparency matching" "0,1"
bitfld.long 0x00 30. "GAMMAINVERSION,Inverse Gamma support [using the CLUT table]" "0,1"
bitfld.long 0x00 28. "PREMULTIPLYALPHA,The field configures the DISPC VID to process incoming data as premultiplied alpha data or non premultiplied alpha data" "0,1"
newline
bitfld.long 0x00 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "0,1"
bitfld.long 0x00 23. "ARBITRATION,Determines the priority of the video pipeline" "0,1"
bitfld.long 0x00 21. "VERTICALTAPS,Video Vertical Resize Tap Number" "0,1"
newline
bitfld.long 0x00 19. "BUFPRELOAD,Video Preload Value" "0,1"
rbitfld.long 0x00 18. "RESERVED7,Write 0's for future compatibility" "0,1"
bitfld.long 0x00 17. "SELFREFRESHAUTO,Automatic self refresh mode" "0,1"
newline
bitfld.long 0x00 12. "FLIP,Describes the frame buffer flip operation" "0,1"
bitfld.long 0x00 11. "FULLRANGE,Color Space Conversion full range setting" "0,1"
bitfld.long 0x00 10. "NIBBLEMODE,Video Nibble mode [only for 1- 2- and 4-bpp]" "0,1"
newline
bitfld.long 0x00 9. "COLORCONVENABLE,Enable the color space conversion" "0,1"
bitfld.long 0x00 7.--8. "RESIZEENABLE,Video Resize Enable" "0,1,2,3"
bitfld.long 0x00 1.--6. "FORMAT,Video Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "ENABLE,Video pipeline Enable" "0,1"
line.long 0x04 "VID_ATTRIBUTES2,The register configures the attributes of the video window"
bitfld.long 0x04 26.--30. "TAGS,Number of OCP TAGS to be used for the pipeline [from 0x0 to 0xF]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 10. "YUV_ALIGN,Alignment [MSB or LSB align] for unpacked 10b/12b YUV data" "0,1"
bitfld.long 0x04 9. "YUV_MODE,Mode of packing for YUV data [only for 10b/12b formats]" "0,1"
newline
bitfld.long 0x04 7.--8. "YUV_SIZE,Size of YUV data 8b/10b/12b" "0,1,2,3"
bitfld.long 0x04 4.--6. "VC1_RANGE_CBCR,Defines the VC1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 1.--3. "VC1_RANGE_Y,Defines the VC1 range value for the Y component from 0 to 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "VC1ENABLE,Enable/disable the VC1 range mapping processing" "0,1"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x28)++0x03
line.long 0x00 "VID_BA_$1,The register configures the base address of the single video buffer"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x30)++0x03
line.long 0x00 "VID_BA_UV_$1,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window"
repeat.end
rgroup.long 0x38++0x33
line.long 0x00 "VID_BUF_SIZE_STATUS,The register returns the Video buffer size for the video pipeline"
hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0"
hexmask.long.word 0x00 0.--15. 1. "BUFSIZE,Video DMA buffer Size in number of 128-bits"
line.long 0x04 "VID_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline"
hexmask.long.word 0x04 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold"
hexmask.long.word 0x04 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer Low Threshold"
line.long 0x08 "VID_CSC_COEF0,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x08 27.--31. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x08 16.--26. 1. "C01,C01 Coefficient"
rbitfld.long 0x08 11.--15. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x08 0.--10. 1. "C00,C00 Coefficient"
line.long 0x0C "VID_CSC_COEF1,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x0C 27.--31. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x0C 16.--26. 1. "C10,C10 Coefficient"
rbitfld.long 0x0C 11.--15. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x0C 0.--10. 1. "C02,C02 Coefficient"
line.long 0x10 "VID_CSC_COEF2,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x10 27.--31. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x10 16.--26. 1. "C12,C12 Coefficient"
rbitfld.long 0x10 11.--15. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x10 0.--10. 1. "C11,C11 Coefficient"
line.long 0x14 "VID_CSC_COEF3,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x14 27.--31. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x14 16.--26. 1. "C21,C21 coefficient"
rbitfld.long 0x14 11.--15. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x14 0.--10. 1. "C20,C20 coefficient"
line.long 0x18 "VID_CSC_COEF4,The register configures the color space conversion matrix coefficients"
hexmask.long.tbyte 0x18 11.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0"
hexmask.long.word 0x18 0.--10. 1. "C22,C22 Coefficient"
line.long 0x1C "VID_CSC_COEF5,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x1C 19.--31. 1. "PREOFFSET2,Row-2 pre-offset"
hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET1,Row1 pre-offset"
line.long 0x20 "VID_CSC_COEF6,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x20 19.--31. 1. "POSTOFFSET1,Row-1 post-offset"
hexmask.long.word 0x20 3.--15. 1. "PREOFFSET3,Row-3 pre-offset"
line.long 0x24 "VID_FIRH,The register configures the resize factor for horizontal up/down-sampling of the video window"
hexmask.long.tbyte 0x24 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter"
line.long 0x28 "VID_FIRH2,The register configures the resize factor for horizontal up/down-sampling of the video window"
hexmask.long.tbyte 0x28 0.--23. 1. "FIRHINC,Horizontal increment of the up/down-sampling filter for Cb and Cr"
line.long 0x2C "VID_FIRV,The register configures the resize factor for vertical up/down-sampling of the video window"
hexmask.long.tbyte 0x2C 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter"
line.long 0x30 "VID_FIRV2,The register configures the resize factor for vertical up/down-sampling of the video window"
hexmask.long.tbyte 0x30 0.--23. 1. "FIRVINC,Vertical increment of the up/down-sampling filter for Cb and Cr"
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
group.long ($2+0x6C)++0x03
line.long 0x00 "VID_FIR_COEF_H0_$1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases"
hexmask.long.word 0x00 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 0"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
group.long ($2+0x90)++0x03
line.long 0x00 "VID_FIR_COEF_H0_C_$1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15"
hexmask.long.word 0x00 0.--9. 1. "FIRHC0,Unsigned coefficient C0 for the horizontal up/down-scaling with the phase 0"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xB4)++0x03
line.long 0x00 "VID_FIR_COEF_H12_$1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the 16 phases"
hexmask.long.word 0x00 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 0"
hexmask.long.word 0x00 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 0"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xF4)++0x03
line.long 0x00 "VID_FIR_COEF_H12_C_$1,The bank of registers configures the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window for the phases from 0 to 15"
hexmask.long.word 0x00 20.--29. 1. "FIRHC2,Signed coefficient C2 for the horizontal up/down-scaling with the phase 0"
hexmask.long.word 0x00 10.--19. 1. "FIRHC1,Signed coefficient C1 for the horizontal up/down-scaling with the phase 0"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
group.long ($2+0x134)++0x03
line.long 0x00 "VID_FIR_COEF_V0_$1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases"
hexmask.long.word 0x00 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 0"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
group.long ($2+0x158)++0x03
line.long 0x00 "VID_FIR_COEF_V0_C_$1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15"
hexmask.long.word 0x00 0.--9. 1. "FIRVC0,Unsigned coefficient C0 for the vertical up/down-scaling with the phase 0"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x17C)++0x03
line.long 0x00 "VID_FIR_COEF_V12_$1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the 16 phases"
hexmask.long.word 0x00 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 0"
hexmask.long.word 0x00 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 0"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x1BC)++0x03
line.long 0x00 "VID_FIR_COEF_V12_C_$1,The bank of registers configures the up/down-scaling coefficients for the vertical resize of the video picture associated with the video window for the phases from 0 to 15"
hexmask.long.word 0x00 20.--29. 1. "FIRVC2,Signed coefficient C2 for the vertical up/down-scaling with the phase 0"
hexmask.long.word 0x00 10.--19. 1. "FIRVC1,Signed coefficient C1 for the vertical up/down-scaling with the phase 0"
repeat.end
group.long 0x1FC++0x03
line.long 0x00 "VID_GLOBAL_ALPHA,The register defines the global alpha value for the video pipeline"
hexmask.long.byte 0x00 0.--7. 1. "GLOBALALPHA,Global alpha value from 0 to 255"
group.long 0x208++0x0B
line.long 0x00 "VID_MFLAG_THRESHOLD,MFLAG_THRESHOLD Register"
hexmask.long.word 0x00 16.--31. 1. "HT_MFLAG,MFlag High Threshold"
hexmask.long.word 0x00 0.--15. 1. "LT_MFLAG,MFlag Low Threshold"
line.long 0x04 "VID_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer before up/down-scaling"
hexmask.long.word 0x04 16.--27. 1. "MEMSIZEY,Number of lines of the video picture Encoded value [from 1 to 4096] to specify the number of lines of the video picture in memory [program to value minus one] When predecimation is set the value represents the size of the image after.."
hexmask.long.word 0x04 0.--11. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value [from 1 to 4096] to specify the number of pixels of the video picture in memory [program to value minus one]"
line.long 0x08 "VID_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0"
hexmask.long.byte 0x08 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels Encoded unsigned value [from 1 to 255] to specify the number of bytes between two pixels in the video buffer"
group.long 0x218++0x0B
line.long 0x00 "VID_PRELOAD,The register configures the DMA buffer of the video pipeline"
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0"
hexmask.long.word 0x00 0.--11. 1. "PRELOAD,DMA buffer preload value Number of 128-bit words defining the preload value"
line.long 0x04 "VID_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window"
line.long 0x08 "VID_SIZE,The register configures the size of the video window"
hexmask.long.word 0x08 16.--27. 1. "SIZEY,Number of lines of the video window Encoded value [from 1 to 4096] to specify the number of lines of the video window [program size -1]"
hexmask.long.word 0x08 0.--11. 1. "SIZEX,Number of pixels of the video window Encoded value [from 1 to 4096] to specify the number of pixels of the video window [program size -1]"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x22C)++0x03
line.long 0x00 "VID_BA_EXT_$1,The register configures the 16-bit base address extension"
hexmask.long.word 0x00 0.--15. 1. "BA_EXT,Video base address extension [16 bits]"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x234)++0x03
line.long 0x00 "VID_BA_UV_EXT_$1,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8"
hexmask.long.word 0x00 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]"
repeat.end
group.long 0x23C++0x03
line.long 0x00 "VID_CSC_COEF7,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x00 19.--31. 1. "POSTOFFSET3,Row-3 post-offset"
hexmask.long.word 0x00 3.--15. 1. "POSTOFFSET2,Row-2 post-offset"
group.long 0x248++0x03
line.long 0x00 "VID_ROW_INC_UV,The register configures the number of bytes to increment at the end of the row for the UV buffer associated with the video window for YUV420 formats"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x260)++0x03
line.long 0x00 "VID_CLUT_$1,The register configures the Color Look Up Table CLUT for VID pipeline"
hexmask.long.byte 0x00 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX"
hexmask.long.byte 0x00 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX"
newline
hexmask.long.byte 0x00 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX"
repeat.end
group.long 0x2A0++0x1B
line.long 0x00 "VID_SAFETY_ATTRIBUTES,The register configures the safety sub-region"
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,"
bitfld.long 0x00 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]" "No frames are skipped,Even Frames are skipped starting from second..,Odd Frames are skipped starting from first frame..,Reserved"
hexmask.long.byte 0x00 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature"
newline
bitfld.long 0x00 2. "SEEDSELECT,Initial seed selection control" "0,1"
bitfld.long 0x00 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1"
bitfld.long 0x00 0. "ENABLE,Safety check Enable for the region" "0,1"
line.long 0x04 "VID_SAFETY_CAPT_SIGNATURE,The register captures the signature from the MISR of the safety sub-region"
line.long 0x08 "VID_SAFETY_POSITION,The register configures the position of the safety sub-region"
hexmask.long.word 0x08 16.--27. 1. "POSY,Y position of the safety sub-region"
hexmask.long.word 0x08 0.--11. 1. "POSX,X position of the safety sub-region"
line.long 0x0C "VID_SAFETY_REF_SIGNATURE,The register configures the reference signature of the safety sub-region"
line.long 0x10 "VID_SAFETY_SIZE,The register configures the size of the safety sub-region"
hexmask.long.word 0x10 16.--27. 1. "SIZEY,Height of the safety sub-region"
hexmask.long.word 0x10 0.--11. 1. "SIZEX,Width of the safety sub-region"
line.long 0x14 "VID_SAFETY_LFSR_SEED,The register configures the seed [initial value] of the MISR"
line.long 0x18 "VID_LUMAKEY,The register configures the LUMA KEY transparency min and max values"
rbitfld.long 0x18 28.--31. "RESERVED1,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 16.--27. 1. "LUMAKEYMAX,12b luma_key_max value"
rbitfld.long 0x18 12.--15. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x18 0.--11. 1. "LUMAKEYMIN,12b luma_key_min value"
tree.end
tree "DSS0_VIDL1"
base ad:0x30202000
group.long 0x20++0x07
line.long 0x00 "VIDL1_ATTRIBUTES,The register configures the attributes of the video window"
bitfld.long 0x00 31. "LUMAKEYENABLE,Enable Luma Key transparency matching" "0,1"
bitfld.long 0x00 30. "GAMMAINVERSION,Inverse Gamma support [using the CLUT table]" "0,1"
bitfld.long 0x00 28. "PREMULTIPLYALPHA,The field configures the DISPC VID to process incoming data as premultiplied alpha data or non premultiplied alpha data" "0,1"
newline
bitfld.long 0x00 24. "SELFREFRESH,Enables the self refresh of the video window from its own DMA buffer only" "0,1"
bitfld.long 0x00 23. "ARBITRATION,Determines the priority of the video pipeline" "0,1"
rbitfld.long 0x00 21. "RESERVED3,Write 0's for future compatibility" "0,1"
newline
bitfld.long 0x00 19. "BUFPRELOAD,Video Preload Value" "0,1"
rbitfld.long 0x00 18. "RESERVED7,Write 0's for future compatibility" "0,1"
bitfld.long 0x00 17. "SELFREFRESHAUTO,Automatic self refresh mode" "0,1"
newline
bitfld.long 0x00 12. "FLIP,Describes the frame buffer flip operation" "0,1"
bitfld.long 0x00 11. "FULLRANGE,Color Space Conversion full range setting" "0,1"
bitfld.long 0x00 10. "NIBBLEMODE,Video Nibble mode [only for 1- 2- and 4-bpp]" "0,1"
newline
bitfld.long 0x00 9. "COLORCONVENABLE,Enable the color space conversion" "0,1"
rbitfld.long 0x00 7.--8. "RESERVED8,Write 0's for future compatibility" "0,1,2,3"
bitfld.long 0x00 1.--6. "FORMAT,Video Format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0. "ENABLE,Video pipeline Enable" "0,1"
line.long 0x04 "VIDL1_ATTRIBUTES2,The register configures the attributes of the video window"
bitfld.long 0x04 26.--30. "TAGS,Number of OCP TAGS to be used for the pipeline [from 0x0 to 0xF]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 10. "YUV_ALIGN,Alignment [MSB or LSB align] for unpacked 10b/12b YUV data" "0,1"
bitfld.long 0x04 9. "YUV_MODE,Mode of packing for YUV data [only for 10b/12b formats]" "0,1"
newline
bitfld.long 0x04 7.--8. "YUV_SIZE,Size of YUV data 8b/10b/12b" "0,1,2,3"
bitfld.long 0x04 4.--6. "VC1_RANGE_CBCR,Defines the VC1 range value for the CbCr component from 0 to 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 1.--3. "VC1_RANGE_Y,Defines the VC1 range value for the Y component from 0 to 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "VC1ENABLE,Enable/disable the VC1 range mapping processing" "0,1"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x28)++0x03
line.long 0x00 "VIDL1_BA_$1,The register configures the base address of the single video buffer"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x30)++0x03
line.long 0x00 "VIDL1_BA_UV_$1,The register configures the base address of the UV buffer for two plane YUV or RGB buffer for two plane RGB565-A8. for the video window"
repeat.end
rgroup.long 0x38++0x23
line.long 0x00 "VIDL1_BUF_SIZE_STATUS,The register returns the Video buffer size for the video pipeline"
hexmask.long.word 0x00 16.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0"
hexmask.long.word 0x00 0.--15. 1. "BUFSIZE,Video DMA buffer Size in number of 128-bits"
line.long 0x04 "VIDL1_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline"
hexmask.long.word 0x04 16.--31. 1. "BUFHIGHTHRESHOLD,DMA buffer High Threshold"
hexmask.long.word 0x04 0.--15. 1. "BUFLOWTHRESHOLD,DMA buffer Low Threshold"
line.long 0x08 "VIDL1_CSC_COEF0,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x08 27.--31. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x08 16.--26. 1. "C01,C01 Coefficient"
rbitfld.long 0x08 11.--15. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x08 0.--10. 1. "C00,C00 Coefficient"
line.long 0x0C "VIDL1_CSC_COEF1,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x0C 27.--31. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x0C 16.--26. 1. "C10,C10 Coefficient"
rbitfld.long 0x0C 11.--15. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x0C 0.--10. 1. "C02,C02 Coefficient"
line.long 0x10 "VIDL1_CSC_COEF2,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x10 27.--31. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x10 16.--26. 1. "C12,C12 Coefficient"
rbitfld.long 0x10 11.--15. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x10 0.--10. 1. "C11,C11 Coefficient"
line.long 0x14 "VIDL1_CSC_COEF3,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x14 27.--31. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x14 16.--26. 1. "C21,C21 coefficient"
rbitfld.long 0x14 11.--15. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x14 0.--10. 1. "C20,C20 coefficient"
line.long 0x18 "VIDL1_CSC_COEF4,The register configures the color space conversion matrix coefficients"
hexmask.long.tbyte 0x18 11.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0"
hexmask.long.word 0x18 0.--10. 1. "C22,C22 Coefficient"
line.long 0x1C "VIDL1_CSC_COEF5,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x1C 19.--31. 1. "PREOFFSET2,Row-2 pre-offset"
hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET1,Row1 pre-offset"
line.long 0x20 "VIDL1_CSC_COEF6,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x20 19.--31. 1. "POSTOFFSET1,Row-1 post-offset"
hexmask.long.word 0x20 3.--15. 1. "PREOFFSET3,Row-3 pre-offset"
group.long 0x1FC++0x03
line.long 0x00 "VIDL1_GLOBAL_ALPHA,The register defines the global alpha value for the video pipeline"
hexmask.long.byte 0x00 0.--7. 1. "GLOBALALPHA,Global alpha value from 0 to 255"
group.long 0x208++0x0B
line.long 0x00 "VIDL1_MFLAG_THRESHOLD,MFLAG_THRESHOLD Register"
hexmask.long.word 0x00 16.--31. 1. "HT_MFLAG,MFLAG High Threshold"
hexmask.long.word 0x00 0.--15. 1. "LT_MFLAG,MFLAG Low Threshold"
line.long 0x04 "VIDL1_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer before up/down-scaling"
hexmask.long.word 0x04 16.--27. 1. "MEMSIZEY,Number of lines of the video picture Encoded value [from 1 to 4096] to specify the number of lines of the video picture in memory [program to value minus one]"
hexmask.long.word 0x04 0.--11. 1. "MEMSIZEX,Number of pixels of the video picture Encoded value [from 1 to 4096] to specify the number of pixels of the video picture in memory [program to value minus one]"
line.long 0x08 "VIDL1_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0"
hexmask.long.byte 0x08 0.--7. 1. "PIXELINC,Number of bytes to increment between two pixels Encoded unsigned value [from 1 to 255] to specify the number of bytes between two pixels in the video buffer"
group.long 0x218++0x07
line.long 0x00 "VIDL1_PRELOAD,The register configures the DMA buffer of the video pipeline"
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0"
hexmask.long.word 0x00 0.--11. 1. "PRELOAD,DMA buffer preload value"
line.long 0x04 "VIDL1_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x22C)++0x03
line.long 0x00 "VIDL1_BA_EXT_$1,The register configures the 16-bit base address extension"
hexmask.long.word 0x00 0.--15. 1. "BA_EXT,Video base address extension [16 bits]"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x234)++0x03
line.long 0x00 "VIDL1_BA_UV_EXT_$1,The register configures the 16-bit base address extension of the UV buffer for two plane YUV or the RGB buffer for two plane RGB565-A8"
hexmask.long.word 0x00 0.--15. 1. "BA_UV_EXT,Video base address extension [16 bits]"
repeat.end
group.long 0x23C++0x03
line.long 0x00 "VIDL1_CSC_COEF7,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x00 19.--31. 1. "POSTOFFSET3,Row-3 post-offset"
hexmask.long.word 0x00 3.--15. 1. "POSTOFFSET2,Row-2 post-offset"
group.long 0x248++0x03
line.long 0x00 "VIDL1_ROW_INC_UV,The register configures the number of bytes to increment at the end of the row for the UV buffer associated with the video window for YUV420 formats"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x260)++0x03
line.long 0x00 "VIDL1_CLUT_$1,The register configures the Color Look Up Table CLUT for VID pipeline"
hexmask.long.byte 0x00 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "VALUE_R,8-bit R-value to store at the location in the table defined by the bit-field INDEX"
hexmask.long.byte 0x00 8.--15. 1. "VALUE_G,8-bit G-value to store at the location in the table defined by the bit-field INDEX"
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hexmask.long.byte 0x00 0.--7. 1. "VALUE_B,8-bit B-value to store at the location in the table defined by the bit-field INDEX"
repeat.end
group.long 0x2A0++0x1B
line.long 0x00 "VIDL1_SAFETY_ATTRIBUTES,The register configures the safety sub-region"
bitfld.long 0x00 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]" "No frames are skipped,Even Frames are skipped starting from second..,Odd Frames are skipped starting from first frame..,Reserved"
hexmask.long.byte 0x00 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature"
bitfld.long 0x00 2. "SEEDSELECT,Initial seed selection control" "0,1"
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bitfld.long 0x00 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1"
bitfld.long 0x00 0. "ENABLE,Safety check Enable for the region" "0,1"
line.long 0x04 "VIDL1_SAFETY_CAPT_SIGNATURE,The register captures the signature from the MISR of the safety sub-region"
line.long 0x08 "VIDL1_SAFETY_POSITION,The register configures the position of the safety sub-region"
hexmask.long.word 0x08 16.--27. 1. "POSY,Y position of the safety sub-region"
hexmask.long.word 0x08 0.--11. 1. "POSX,X position of the safety sub-region"
line.long 0x0C "VIDL1_SAFETY_REF_SIGNATURE,The register configures the reference signature of the safety sub-region"
line.long 0x10 "VIDL1_SAFETY_SIZE,The register configures the size of the safety sub-region"
hexmask.long.word 0x10 16.--27. 1. "SIZEY,Height of the safety sub-region"
hexmask.long.word 0x10 0.--11. 1. "SIZEX,Width of the safety sub-region"
line.long 0x14 "VIDL1_SAFETY_LFSR_SEED,The register configures the seed [initial value] of the MISR"
line.long 0x18 "VIDL1_LUMAKEY,The register configures the LUMA KEY transparency min and max values"
rbitfld.long 0x18 28.--31. "RESERVED1,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x18 16.--27. 1. "LUMAKEYMAX,12b luma_key_max value"
rbitfld.long 0x18 12.--15. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x18 0.--11. 1. "LUMAKEYMIN,12b luma_key_min value"
tree.end
tree "DSS0_VP1"
base ad:0x3020A000
group.long 0x00++0x13
line.long 0x00 "VP1_CONFIG,The control register configures the Display Controller module for the VP output"
rbitfld.long 0x00 27.--31. "RESERVED3," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "COLORCONVPOS,Determines the position of the COLORCONV module" "0,1"
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bitfld.long 0x00 25. "FULLRANGE,Color Space Conversion full range setting" "0,1"
bitfld.long 0x00 24. "COLORCONVENABLE,Enable the color space conversion" "0,1"
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bitfld.long 0x00 23. "FIDFIRST,Selects the first field to output in case of interlace mode" "0,1"
bitfld.long 0x00 22. "OUTPUTMODEENABLE,Selects between progressive and interlace mode for the VP output" "0,1"
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bitfld.long 0x00 21. "BT1120ENABLE,Selects BT-1120 format on the VP output" "0,1"
bitfld.long 0x00 20. "BT656ENABLE,Selects BT-656 format on the VP output" "0,1"
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rbitfld.long 0x00 17.--19. "RESERVED2,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "BUFFERHANDSHAKE,Deprecated" "0,1"
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bitfld.long 0x00 15. "CPR,Deprecated" "0,1"
rbitfld.long 0x00 9.--14. "RESERVED1,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8. "EXTERNALSYNCEN,Deprecated" "0,1"
bitfld.long 0x00 7. "VSYNCGATED,VSYNC Gated Enabled [VP output]" "0,1"
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bitfld.long 0x00 6. "HSYNCGATED,HSYNC Gated Enabled [VP output]" "0,1"
bitfld.long 0x00 5. "PIXELCLOCKGATED,Pixel Clock Gated Enabled [VP output]" "0,1"
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bitfld.long 0x00 4. "PIXELDATAGATED,Pixel Data Gated Enabled [VP output]" "0,1"
bitfld.long 0x00 3. "HDMIMODE,Deprecated" "0,1"
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bitfld.long 0x00 2. "GAMMAENABLE,Enable the gamma Shadow bit-field" "0,1"
bitfld.long 0x00 1. "DATAENABLEGATED,DE Gated Enable Shadow bit-field" "0,1"
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bitfld.long 0x00 0. "PIXELGATED,Pixel Gated Enable" "0,1"
line.long 0x04 "VP1_CONTROL,The control register configures the Display Controller module for the VP output"
bitfld.long 0x04 30.--31. "SPATIALTEMPORALDITHERINGFRAMES,Spatial/Temporal dithering number of frames for the VP output Shadow bit-field" "0,1,2,3"
rbitfld.long 0x04 27.--29. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 25.--26. "TDMUNUSEDBITS,State of unused bits [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3"
bitfld.long 0x04 23.--24. "TDMCYCLEFORMAT,Cycle format [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3"
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bitfld.long 0x04 21.--22. "TDMPARALLELMODE,Output Interface width [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3"
bitfld.long 0x04 20. "TDMENABLE,Enable the multiple cycle format for the VP output Shadow bit-field" "0,1"
newline
rbitfld.long 0x04 17.--19. "RESERVED1," "0,1,2,3,4,5,6,7"
bitfld.long 0x04 14.--16. "HT,Hold Time for output" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 13. "RESERVED3," "0,1"
rbitfld.long 0x04 12. "RESERVED6," "0,1"
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bitfld.long 0x04 11. "STALLMODE,Deprecated" "0,1"
bitfld.long 0x04 8.--10. "DATALINES,Width of the data bus on VP output Shadow bit-field" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 7. "STDITHERENABLE,Spatial Temporal dithering enable for the VP output Shadow bit-field" "0,1"
bitfld.long 0x04 6. "DPIENABLE,Enable the DPI output" "0,1"
newline
bitfld.long 0x04 5. "GOBIT,GO Command for the VP output" "0,1"
bitfld.long 0x04 4. "M8B,Deprecated" "0,1"
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bitfld.long 0x04 3. "STN,Deprecated" "0,1"
bitfld.long 0x04 2. "MONOCOLOR,Deprecated" "0,1"
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bitfld.long 0x04 1. "VPPROGLINENUMBERMODULO,Enable the modulo of the line number interrupt generation" "0,1"
bitfld.long 0x04 0. "ENABLE,Enable the video port output" "0,1"
line.long 0x08 "VP1_CSC_COEF0,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x08 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x08 16.--26. 1. "C01,C01 Coefficient"
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rbitfld.long 0x08 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x08 0.--10. 1. "C00,C00 Coefficient"
line.long 0x0C "VP1_CSC_COEF1,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x0C 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x0C 16.--26. 1. "C10,C10 Coefficient"
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rbitfld.long 0x0C 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x0C 0.--10. 1. "C02,C02 Coefficient"
line.long 0x10 "VP1_CSC_COEF2,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x10 27.--31. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x10 16.--26. 1. "C12,C12 Coefficient"
newline
rbitfld.long 0x10 11.--15. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x10 0.--10. 1. "C11,C11 Coefficient"
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
group.long ($2+0x14)++0x03
line.long 0x00 "VP1_DATA_CYCLE_$1,The control register configures the output data format over up to 3 cycles"
rbitfld.long 0x00 28.--31. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 12.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
group.long 0x44++0x03
line.long 0x00 "VP1_LINE_NUMBER,The control register indicates the panel display line number for the interrupt and the DMA request"
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,"
hexmask.long.word 0x00 0.--11. 1. "LINENUMBER,LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs"
group.long 0x4C++0x23
line.long 0x00 "VP1_POL_FREQ,The register configures the signal configuration"
hexmask.long.word 0x00 19.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0"
bitfld.long 0x00 18. "ALIGN,Defines the alignment between HSYNC and VSYNC assertion" "0,1"
newline
bitfld.long 0x00 17. "ONOFF,HSYNC/VSYNC Pixel clock Control On/Off" "0,1"
bitfld.long 0x00 16. "RF,Program HSYNC/VSYNC Rise or Fall" "0,1"
newline
bitfld.long 0x00 15. "IEO,Invert output enable" "0,1"
bitfld.long 0x00 14. "IPC,Invert pixel clock" "0,1"
newline
bitfld.long 0x00 13. "IHS,Invert HSYNC" "0,1"
bitfld.long 0x00 12. "IVS,Invert VSYNC" "0,1"
newline
bitfld.long 0x00 8.--11. "ACBI,AC Bias Pin transitions per interrupt Value [from 0 to 15] used to specify the number of AC Bias pin transitions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "ACB,AC Bias Pin Frequency Value [from 0 to 255] used to specify the number of line clocks to count before transitioning the AC Bias pin"
line.long 0x04 "VP1_SIZE_SCREEN,The register configures the panel size horizontal and vertical"
rbitfld.long 0x04 28.--31. "RESERVED1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 16.--27. 1. "LPP,Lines per panel Encoded value [from 1 to 4096] to specify the number of lines per panel [program to value minus one]"
newline
bitfld.long 0x04 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field" "0,1,2,3"
rbitfld.long 0x04 12.--13. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x04 0.--11. 1. "PPL,Pixels per line Encoded value [from 1 to 4096] to specify the number of pixels contains within each line on the display [program to value minus one]"
line.long 0x08 "VP1_TIMING_H,The register configures the timing logic for the HSYNC signal"
hexmask.long.word 0x08 20.--31. 1. "HBP,Horizontal Back Porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display [program to value minus one] When in BT mode and.."
hexmask.long.word 0x08 8.--19. 1. "HFP,Horizontal front porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted display [program to value minus one] When in BT mode and interlaced this field.."
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hexmask.long.byte 0x08 0.--7. 1. "HSW,Horizontal synchronization pulse width Encoded value [from 1 to 256] to specify the number of pixel clock periods to pulse the line clock at the end of each line display [program to value minus one] When in BT mode this field corresponds to the LSB.."
line.long 0x0C "VP1_TIMING_V,The register configures the timing logic for the VSYNC signal"
hexmask.long.word 0x0C 20.--31. 1. "VBP,Vertical back porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the beginning of a frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 2 for Odd Field When in BT and.."
hexmask.long.word 0x0C 8.--19. 1. "VFP,Vertical front porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the end of each frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 1 for Odd Field When in BT and in.."
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hexmask.long.byte 0x0C 0.--7. 1. "VSW,Vertical synchronization pulse width Encoded value [from 1 to 256] to specify the number of line clock periods to pulse the frame clock [VSYNC] pin at the end of each frame after the end of frame wait [VFP] period elapses Frame clock uses as VSYNC.."
line.long 0x10 "VP1_CSC_COEF3,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x10 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient"
newline
rbitfld.long 0x10 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient"
line.long 0x14 "VP1_CSC_COEF4,The register configures the color space conversion matrix coefficients"
hexmask.long.tbyte 0x14 11.--31. 1. "RESERVED,Write 0's for future compatibility"
hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient"
line.long 0x18 "VP1_CSC_COEF5,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset"
rbitfld.long 0x18 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset"
rbitfld.long 0x18 0.--2. "RESERVED," "0,1,2,3,4,5,6,7"
line.long 0x1C "VP1_CSC_COEF6,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset"
rbitfld.long 0x1C 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset"
rbitfld.long 0x1C 0.--2. "RESERVED," "0,1,2,3,4,5,6,7"
line.long 0x20 "VP1_CSC_COEF7,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x20 19.--31. 1. "POSTOFFSET3,Row-3 post-offset"
rbitfld.long 0x20 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x20 3.--15. 1. "POSTOFFSET2,Row-2 post-offset"
rbitfld.long 0x20 0.--2. "RESERVED," "0,1,2,3,4,5,6,7"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x70)++0x03
line.long 0x00 "VP1_SAFETY_ATTRIBUTES_$1,The register configures the safety sub-region n"
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,"
bitfld.long 0x00 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]" "No frames are skipped,Even Frames are skipped starting from second..,Odd Frames are skipped starting from first frame..,Reserved"
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hexmask.long.byte 0x00 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.."
bitfld.long 0x00 2. "SEEDSELECT,Initial seed selection control" "0,1"
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bitfld.long 0x00 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1"
bitfld.long 0x00 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0x90)++0x03
line.long 0x00 "VP1_SAFETY_CAPT_SIGNATURE_$1,The register captures the signature from the MISR of the safety sub-region n"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xB0)++0x03
line.long 0x00 "VP1_SAFETY_POSITION_$1,The register configures the position of the safety sub-region n"
rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 16.--27. 1. "POSY,Y position of the safety sub-region n"
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rbitfld.long 0x00 12.--15. "RESERVED1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "POSX,X position of the safety sub-region n"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xD0)++0x03
line.long 0x00 "VP1_SAFETY_REF_SIGNATURE_$1,The register configures the reference signature of the safety sub-region n"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xF0)++0x03
line.long 0x00 "VP1_SAFETY_SIZE_$1,The register configures the size of the safety sub-region n Shadow register"
rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 16.--27. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen One line height region has value of 0"
newline
rbitfld.long 0x00 12.--15. "RESERVED1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen One pixel wide region has value of 0"
repeat.end
group.long 0x110++0x03
line.long 0x00 "VP1_SAFETY_LFSR_SEED,The register configures the seed initial signature value of MISRs that are to be initialized with a user programmed initial value"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x120)++0x03
line.long 0x00 "VP1_GAMMA_TABLE_$1,The register configures the gamma table on VP output"
hexmask.long.byte 0x00 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table"
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hexmask.long.byte 0x00 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table"
repeat.end
group.long 0x160++0x0B
line.long 0x00 "VP1_DSS_OLDI_CFG,This register configures the OLDI[N:0] modules connected to the DSS"
bitfld.long 0x00 13. "TPATCFG,Test pattern Config" "0,1"
bitfld.long 0x00 12. "SOFTRST,SoftWare Reset" "0,1"
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bitfld.long 0x00 11. "DUALMODESYNC,DualMode Sync" "0,1"
bitfld.long 0x00 10. "LBDATA,LoopBack Data" "0,1"
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bitfld.long 0x00 9. "LBEN,LoopBack Enable" "0,1"
bitfld.long 0x00 8. "MSB,DSS bit-depth [for 18b LVDS only]" "0,1"
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bitfld.long 0x00 7. "DEPOL,Polarity of the DE signal" "0,1"
bitfld.long 0x00 6. "MASTERSLAVE,Master selection in Dual mode only [typically tied off in the SoC]" "0,1"
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bitfld.long 0x00 5. "MODE,Single mode or duplicate mode" "0,1"
bitfld.long 0x00 4. "SRC,Source Channel" "0,1"
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bitfld.long 0x00 1.--3. "MAP,Configuration of OLDI mapping Also indicates dual mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "ENABLE,OLDI Enable" "0,1"
line.long 0x04 "VP1_DSS_OLDI_STATUS,This register captures the PID from the OLDI[N:0] modules connected to the DSS"
hexmask.long.word 0x04 16.--31. 1. "MODID,Module ID Field"
bitfld.long 0x04 11.--15. "REVRTL,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 8.--10. "REVMAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 6.--7. "CUSTOM,Custom" "0,1,2,3"
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bitfld.long 0x04 0.--5. "REVMIN,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "VP1_DSS_OLDI_LB,This register captures the Loopback data from OLDI"
hexmask.long.word 0x08 0.--9. 1. "LBRDATA,Returned Data from Loopback"
tree.end
tree "DSS0_VP2"
base ad:0x3020B000
group.long 0x00++0x13
line.long 0x00 "VP2_CONFIG,The control register configures the Display Controller module for the VP output"
rbitfld.long 0x00 27.--31. "RESERVED3," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "COLORCONVPOS,Determines the position of the COLORCONV module" "0,1"
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bitfld.long 0x00 25. "FULLRANGE,Color Space Conversion full range setting" "0,1"
bitfld.long 0x00 24. "COLORCONVENABLE,Enable the color space conversion" "0,1"
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bitfld.long 0x00 23. "FIDFIRST,Selects the first field to output in case of interlace mode" "0,1"
bitfld.long 0x00 22. "OUTPUTMODEENABLE,Selects between progressive and interlace mode for the VP output" "0,1"
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bitfld.long 0x00 21. "BT1120ENABLE,Selects BT-1120 format on the VP output" "0,1"
bitfld.long 0x00 20. "BT656ENABLE,Selects BT-656 format on the VP output" "0,1"
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rbitfld.long 0x00 17.--19. "RESERVED2,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16. "BUFFERHANDSHAKE,Deprecated" "0,1"
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bitfld.long 0x00 15. "CPR,Deprecated" "0,1"
rbitfld.long 0x00 9.--14. "RESERVED1,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8. "EXTERNALSYNCEN,Deprecated" "0,1"
bitfld.long 0x00 7. "VSYNCGATED,VSYNC Gated Enabled [VP output]" "0,1"
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bitfld.long 0x00 6. "HSYNCGATED,HSYNC Gated Enabled [VP output]" "0,1"
bitfld.long 0x00 5. "PIXELCLOCKGATED,Pixel Clock Gated Enabled [VP output]" "0,1"
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bitfld.long 0x00 4. "PIXELDATAGATED,Pixel Data Gated Enabled [VP output]" "0,1"
bitfld.long 0x00 3. "HDMIMODE,Deprecated" "0,1"
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bitfld.long 0x00 2. "GAMMAENABLE,Enable the gamma Shadow bit-field" "0,1"
bitfld.long 0x00 1. "DATAENABLEGATED,DE Gated Enable Shadow bit-field" "0,1"
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bitfld.long 0x00 0. "PIXELGATED,Pixel Gated Enable" "0,1"
line.long 0x04 "VP2_CONTROL,The control register configures the Display Controller module for the VP output"
bitfld.long 0x04 30.--31. "SPATIALTEMPORALDITHERINGFRAMES,Spatial/Temporal dithering number of frames for the VP output Shadow bit-field" "0,1,2,3"
rbitfld.long 0x04 27.--29. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 25.--26. "TDMUNUSEDBITS,State of unused bits [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3"
bitfld.long 0x04 23.--24. "TDMCYCLEFORMAT,Cycle format [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3"
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bitfld.long 0x04 21.--22. "TDMPARALLELMODE,Output Interface width [TDM mode only] for the VP output Shadow bit-field" "0,1,2,3"
bitfld.long 0x04 20. "TDMENABLE,Enable the multiple cycle format for the VP output Shadow bit-field" "0,1"
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rbitfld.long 0x04 17.--19. "RESERVED1," "0,1,2,3,4,5,6,7"
bitfld.long 0x04 14.--16. "HT,Hold Time for output" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 13. "RESERVED3," "0,1"
rbitfld.long 0x04 12. "RESERVED6," "0,1"
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bitfld.long 0x04 11. "STALLMODE,Deprecated" "0,1"
bitfld.long 0x04 8.--10. "DATALINES,Width of the data bus on VP output Shadow bit-field" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 7. "STDITHERENABLE,Spatial Temporal dithering enable for the VP output Shadow bit-field" "0,1"
bitfld.long 0x04 6. "DPIENABLE,Enable the DPI output" "0,1"
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bitfld.long 0x04 5. "GOBIT,GO Command for the VP output" "0,1"
bitfld.long 0x04 4. "M8B,Deprecated" "0,1"
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bitfld.long 0x04 3. "STN,Deprecated" "0,1"
bitfld.long 0x04 2. "MONOCOLOR,Deprecated" "0,1"
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bitfld.long 0x04 1. "VPPROGLINENUMBERMODULO,Enable the modulo of the line number interrupt generation" "0,1"
bitfld.long 0x04 0. "ENABLE,Enable the video port output" "0,1"
line.long 0x08 "VP2_CSC_COEF0,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x08 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x08 16.--26. 1. "C01,C01 Coefficient"
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rbitfld.long 0x08 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x08 0.--10. 1. "C00,C00 Coefficient"
line.long 0x0C "VP2_CSC_COEF1,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x0C 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x0C 16.--26. 1. "C10,C10 Coefficient"
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rbitfld.long 0x0C 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x0C 0.--10. 1. "C02,C02 Coefficient"
line.long 0x10 "VP2_CSC_COEF2,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x10 27.--31. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x10 16.--26. 1. "C12,C12 Coefficient"
newline
rbitfld.long 0x10 11.--15. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x10 0.--10. 1. "C11,C11 Coefficient"
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
group.long ($2+0x14)++0x03
line.long 0x00 "VP2_DATA_CYCLE_$1,The control register configures the output data format over up to 3 cycles"
rbitfld.long 0x00 28.--31. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "BITALIGNMENTPIXEL2,Bit alignment Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 21.--23. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "NBBITSPIXEL2,Number of bits Number of bits from the pixel 2 [value from 0 to 16 bits]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 12.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "BITALIGNMENTPIXEL1,Bit alignment Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 5.--7. "RESERVED,Write 0's for future compatibility Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "NBBITSPIXEL1,Number of bits Number of bits from the pixel 1 [value from 0 to 16 bits]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
group.long 0x44++0x03
line.long 0x00 "VP2_LINE_NUMBER,The control register indicates the panel display line number for the interrupt and the DMA request"
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,"
hexmask.long.word 0x00 0.--11. 1. "LINENUMBER,LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs"
group.long 0x4C++0x23
line.long 0x00 "VP2_POL_FREQ,The register configures the signal configuration"
hexmask.long.word 0x00 19.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0"
bitfld.long 0x00 18. "ALIGN,Defines the alignment between HSYNC and VSYNC assertion" "0,1"
newline
bitfld.long 0x00 17. "ONOFF,HSYNC/VSYNC Pixel clock Control On/Off" "0,1"
bitfld.long 0x00 16. "RF,Program HSYNC/VSYNC Rise or Fall" "0,1"
newline
bitfld.long 0x00 15. "IEO,Invert output enable" "0,1"
bitfld.long 0x00 14. "IPC,Invert pixel clock" "0,1"
newline
bitfld.long 0x00 13. "IHS,Invert HSYNC" "0,1"
bitfld.long 0x00 12. "IVS,Invert VSYNC" "0,1"
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bitfld.long 0x00 8.--11. "ACBI,AC Bias Pin transitions per interrupt Value [from 0 to 15] used to specify the number of AC Bias pin transitions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 0.--7. 1. "ACB,AC Bias Pin Frequency Value [from 0 to 255] used to specify the number of line clocks to count before transitioning the AC Bias pin"
line.long 0x04 "VP2_SIZE_SCREEN,The register configures the panel size horizontal and vertical"
rbitfld.long 0x04 28.--31. "RESERVED1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x04 16.--27. 1. "LPP,Lines per panel Encoded value [from 1 to 4096] to specify the number of lines per panel [program to value minus one]"
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bitfld.long 0x04 14.--15. "DELTA_LPP,Indicates the delta size value of the odd field compared to the even field" "0,1,2,3"
rbitfld.long 0x04 12.--13. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x04 0.--11. 1. "PPL,Pixels per line Encoded value [from 1 to 4096] to specify the number of pixels contains within each line on the display [program to value minus one]"
line.long 0x08 "VP2_TIMING_H,The register configures the timing logic for the HSYNC signal"
hexmask.long.word 0x08 20.--31. 1. "HBP,Horizontal Back Porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display [program to value minus one] When in BT mode and.."
hexmask.long.word 0x08 8.--19. 1. "HFP,Horizontal front porch Encoded value [from 1 to 4096] to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted display [program to value minus one] When in BT mode and interlaced this field.."
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hexmask.long.byte 0x08 0.--7. 1. "HSW,Horizontal synchronization pulse width Encoded value [from 1 to 256] to specify the number of pixel clock periods to pulse the line clock at the end of each line display [program to value minus one] When in BT mode this field corresponds to the LSB.."
line.long 0x0C "VP2_TIMING_V,The register configures the timing logic for the VSYNC signal"
hexmask.long.word 0x0C 20.--31. 1. "VBP,Vertical back porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the beginning of a frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 2 for Odd Field When in BT and.."
hexmask.long.word 0x0C 8.--19. 1. "VFP,Vertical front porch Encoded value [from 0 to 4095] to specify the number of line clock periods to add to the end of each frame When in BT mode and interlaced this field corresponds to the vertical field blanking No 1 for Odd Field When in BT and in.."
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hexmask.long.byte 0x0C 0.--7. 1. "VSW,Vertical synchronization pulse width Encoded value [from 1 to 256] to specify the number of line clock periods to pulse the frame clock [VSYNC] pin at the end of each frame after the end of frame wait [VFP] period elapses Frame clock uses as VSYNC.."
line.long 0x10 "VP2_CSC_COEF3,The register configures the color space conversion matrix coefficients"
rbitfld.long 0x10 27.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x10 16.--26. 1. "C21,C21 coefficient"
newline
rbitfld.long 0x10 11.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x10 0.--10. 1. "C20,C20 coefficient"
line.long 0x14 "VP2_CSC_COEF4,The register configures the color space conversion matrix coefficients"
hexmask.long.tbyte 0x14 11.--31. 1. "RESERVED,Write 0's for future compatibility"
hexmask.long.word 0x14 0.--10. 1. "C22,C22 Coefficient"
line.long 0x18 "VP2_CSC_COEF5,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x18 19.--31. 1. "PREOFFSET2,Row-2 pre-offset"
rbitfld.long 0x18 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x18 3.--15. 1. "PREOFFSET1,Row1 pre-offset"
rbitfld.long 0x18 0.--2. "RESERVED," "0,1,2,3,4,5,6,7"
line.long 0x1C "VP2_CSC_COEF6,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x1C 19.--31. 1. "POSTOFFSET1,Row-1 post-offset"
rbitfld.long 0x1C 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x1C 3.--15. 1. "PREOFFSET3,Row-3 pre-offset"
rbitfld.long 0x1C 0.--2. "RESERVED," "0,1,2,3,4,5,6,7"
line.long 0x20 "VP2_CSC_COEF7,The register configures the color space conversion matrix coefficients"
hexmask.long.word 0x20 19.--31. 1. "POSTOFFSET3,Row-3 post-offset"
rbitfld.long 0x20 16.--18. "RESERVED1," "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x20 3.--15. 1. "POSTOFFSET2,Row-2 post-offset"
rbitfld.long 0x20 0.--2. "RESERVED," "0,1,2,3,4,5,6,7"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x70)++0x03
line.long 0x00 "VP2_SAFETY_ATTRIBUTES_$1,The register configures the safety sub-region n"
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,"
bitfld.long 0x00 11.--12. "FRAMESKIP,Indicates which frames to be skipped while doing FRAMEFREEZE or DATACHECK [Useful for interlaced displays]" "No frames are skipped,Even Frames are skipped starting from second..,Odd Frames are skipped starting from first frame..,Reserved"
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hexmask.long.byte 0x00 3.--10. 1. "THRESHOLD,Allowed maximum number of frames with the same frame signature When the freeze frame counter reaches 1 over this value [freeze_frame_thold+1] a freeze frame detection will occur Note: The freeze frame counter is cleared on reset -OR- MISR not.."
bitfld.long 0x00 2. "SEEDSELECT,Initial seed selection control" "0,1"
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bitfld.long 0x00 1. "CAPTUREMODE,Mode of operation of the safety check module" "0,1"
bitfld.long 0x00 0. "ENABLE,Safety check Enable for the region Note: Transition from 0 to 1 clears the signature register" "0,1"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0x90)++0x03
line.long 0x00 "VP2_SAFETY_CAPT_SIGNATURE_$1,The register captures the signature from the MISR of the safety sub-region n"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xB0)++0x03
line.long 0x00 "VP2_SAFETY_POSITION_$1,The register configures the position of the safety sub-region n"
rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 16.--27. 1. "POSY,Y position of the safety sub-region n"
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rbitfld.long 0x00 12.--15. "RESERVED1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "POSX,X position of the safety sub-region n"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xD0)++0x03
line.long 0x00 "VP2_SAFETY_REF_SIGNATURE_$1,The register configures the reference signature of the safety sub-region n"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xF0)++0x03
line.long 0x00 "VP2_SAFETY_SIZE_$1,The register configures the size of the safety sub-region n Shadow register"
rbitfld.long 0x00 28.--31. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 16.--27. 1. "SIZEY,Height of the safety sub-region n Encoded value [from 0 to 4095] to specify the height of the sub-region on the screen One line height region has value of 0"
newline
rbitfld.long 0x00 12.--15. "RESERVED1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "SIZEX,Width of the safety sub-region n Encoded value [from 0 to 4095] to specify the width of the sub-region on the screen One pixel wide region has value of 0"
repeat.end
group.long 0x110++0x03
line.long 0x00 "VP2_SAFETY_LFSR_SEED,The register configures the seed initial signature value of MISRs that are to be initialized with a user programmed initial value"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x120)++0x03
line.long 0x00 "VP2_GAMMA_TABLE_$1,The register configures the gamma table on VP output"
hexmask.long.byte 0x00 24.--31. 1. "INDEX,Defines the location in the table where the bit-fields VALUE_{R G B} is stored"
hexmask.long.byte 0x00 16.--23. 1. "VALUE_R,8-bit R value to be stored in the gamma table"
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hexmask.long.byte 0x00 8.--15. 1. "VALUE_G,8-bit G value to be stored in the gamma table"
hexmask.long.byte 0x00 0.--7. 1. "VALUE_B,8-bit B value to be stored in the gamma table"
repeat.end
group.long 0x160++0x0B
line.long 0x00 "VP2_DSS_OLDI_CFG,This register configures the OLDI[N:0] modules connected to the DSS"
bitfld.long 0x00 13. "TPATCFG,Test pattern Config" "0,1"
bitfld.long 0x00 12. "SOFTRST,SoftWare Reset" "0,1"
newline
bitfld.long 0x00 11. "DUALMODESYNC,DualMode Sync" "0,1"
bitfld.long 0x00 10. "LBDATA,LoopBack Data" "0,1"
newline
bitfld.long 0x00 9. "LBEN,LoopBack Enable" "0,1"
bitfld.long 0x00 8. "MSB,DSS bit-depth [for 18b LVDS only]" "0,1"
newline
bitfld.long 0x00 7. "DEPOL,Polarity of the DE signal" "0,1"
bitfld.long 0x00 6. "MASTERSLAVE,Master selection in Dual mode only [typically tied off in the SoC]" "0,1"
newline
bitfld.long 0x00 5. "MODE,Single mode or duplicate mode" "0,1"
bitfld.long 0x00 4. "SRC,Source Channel" "0,1"
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bitfld.long 0x00 1.--3. "MAP,Configuration of OLDI mapping Also indicates dual mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "ENABLE,OLDI Enable" "0,1"
line.long 0x04 "VP2_DSS_OLDI_STATUS,This register captures the PID from the OLDI[N:0] modules connected to the DSS"
hexmask.long.word 0x04 16.--31. 1. "MODID,Module ID Field"
bitfld.long 0x04 11.--15. "REVRTL,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 8.--10. "REVMAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x04 0.--5. "REVMIN,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "VP2_DSS_OLDI_LB,This register captures the Loopback data from OLDI"
hexmask.long.word 0x08 0.--9. 1. "LBRDATA,Returned Data from Loopback"
tree.end
tree "ECAP0_CTL_STS"
base ad:0x23100000
group.long 0x00++0x17
line.long 0x00 "CTL_STS_TSCNT,"
line.long 0x04 "CTL_STS_CNTPHS,"
line.long 0x08 "CTL_STS_CAP1,"
line.long 0x0C "CTL_STS_CAP2,"
line.long 0x10 "CTL_STS_CAP3,"
line.long 0x14 "CTL_STS_CAP4,"
group.long 0x28++0x0B
line.long 0x00 "CTL_STS_ECCTL,"
rbitfld.long 0x00 27.--31. "FILTER," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "APWMPOL,APWM output polarity select: 1'b0 Output is Active High (i.e. Compare value defines High time); 1'b1 Output is Active Low (i.e. Compare value defines Low time); Note: This is applicable only in APWM operating mode" "0,1"
bitfld.long 0x00 25. "CAP_APWM,CAP/APWM operating mode select: 1'b0 ECAP module operates in Capture mode This mode forces the following configuration: 1- Inhibits TSCNT resets via PRD_eq event 2- Inhibits Shadow loads on CAP1 & 2 registers 3- Permits User to enable CAP1-4.." "0,1"
bitfld.long 0x00 24. "SWSYNC,Software forced Counter (TSCNT) sync'ing: 1'b0 Writing a Zero has no effect Reading will always return a zero; 1'b1 Writing a One will force a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits.." "0,1"
bitfld.long 0x00 22.--23. "SYNCO_SEL,Sync-Out select: 2'b00 Select Sync-In event to be the Sync-Out signal (pass through); 2'b01 Select PRD_eq event to be the Sync-Out signal; 2'b10 DISABLE Sync Out Signal; 2'b11 DISABLE Sync Out Signal; Note: Selection PRD_eq is meaningful only.." "0,1,2,3"
bitfld.long 0x00 21. "SYNCI_EN,Counter (TSCNT) Sync-In select mode: 1'b0 Disable Sync-In option 1'b1 Enable Counter (TSCNT) to be loaded from CNTPHS register upon either a SYNCI signal or a S/W force event" "0,1"
bitfld.long 0x00 20. "TSCNTSTP,Counter Stop (freeze) Control: 1'b0 Counter Stopped; 1'b1 Counter Free Running" "0,1"
bitfld.long 0x00 19. "REARM_RESET,One-Shot Re-arming i.e" "0,1"
newline
bitfld.long 0x00 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1-4) of Captures allowed to occur before the CAP(1-4) registers are frozen i.e.Capture sequence is stopped" "0,1,2,3"
bitfld.long 0x00 16. "CONT_ONESHT,Continuous or Oneshot mode control: (applicable only in Capture mode) 1'b0 Operate in Continuous mode 1'b1 Operate in One-Shot mode" "0,1"
bitfld.long 0x00 14.--15. "FREE_SOFT,Emulation Control 2'b00 TSCNT Counter stops immediately on emulation suspend; 2'b01 TSCNT Counter runs until = 0; 2'b1X TSCNT Counter is unaffected by emulation suspend (Run Free)" "0,1,2,3"
bitfld.long 0x00 9.--13. "EVTFLTPS,Event Filter prescale select: 5'b00000 divide by 1 (i.e. no prescale by-pass the prescaler); 5'b00001 divide by 2; 5'b00010 divide by 4; 5'b00011 divide by 6; 5'b00100 divide by 8; 5'b00101 divide by 10;" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a Capture Event: 1'b0 Disable CAP1-4 register loads at capture Event time; 1'b1 Enable CAP1-4 register loads at capture Event time" "0,1"
bitfld.long 0x00 7. "CTRRST4,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 6. "CAP4POL,Capture Event 4 Polarity select: 1'b0 Capture event 4 triggered on a Rising Edge (FE); 1'b1 Capture event 4 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 5. "CTRRST3,Counter Reset on Capture Event" "0,1"
newline
bitfld.long 0x00 4. "CAP3POL,Capture Event 3 Polarity select: 1'b0 Capture event 3 triggered on a Rising Edge (FE); 1'b1 Capture event 3 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 3. "CTRRST2,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 2. "CAP2POL,Capture Event 2 Polarity select: 1'b0 Capture event 2 triggered on a Rising Edge (FE); 1'b1 Capture event 2 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 1. "CTRRST1,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 0. "CAP1POL,Capture Event 1 Polarity select: 1'b0 Capture event 1 triggered on a Rising Edge (FE); 1'b1 Capture event 1 triggered on a Falling Edge (FE)" "0,1"
line.long 0x04 "CTL_STS_ECINT_EN_FLG,"
rbitfld.long 0x04 23. "CMPEQ_FLG,Compare Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Compare register value (ACMP) Reading a 0 indicates no event occurred Note: This flag is only active in APWM mode" "0,1"
rbitfld.long 0x04 22. "PRDEQ_FLG,Period Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Period register value (APER) and was reset" "0,1"
rbitfld.long 0x04 21. "CNTOVF_FLG,Counter Overflow Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) has made the transition from 0xFFFFFFFF 0x00000000 Reading a 0 indicates no event occurred" "0,1"
rbitfld.long 0x04 20. "CEVT4_FLG,Capture Event 4 Status Flag: Reading a 1 on this bit indicates the fourth event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 19. "CEVT3_FLG,Capture Event 3 Status Flag: Reading a 1 on this bit indicates the third event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 18. "CEVT2_FLG,Capture Event 2 Status Flag: Reading a 1 on this bit indicates the second event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 17. "CEVT1_FLG,Capture Event 1 Status Flag: Reading a 1 on this bit indicates the first event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events" "0,1"
newline
bitfld.long 0x04 7. "CMPEQ_EN,Compare Equal Interrupt Enable: 1'b0 Disabled Compare Equal as an Interrupt source; 1'b1 Enable Compare Equal as an Interrupt source" "0,1"
bitfld.long 0x04 6. "PRDEQ_EN,Period Equal Interrupt Enable: 1'b0 Disabled Period Equal as an Interrupt source; 1'b1 Enable Period Equal as an Interrupt source" "0,1"
bitfld.long 0x04 5. "CNTOVF_EN,Counter Overflow Interrupt Enable: 1'b0 Disabled Counter Overflow as an Interrupt source; 1'b1 Enable Counter Overflow as an Interrupt source" "0,1"
bitfld.long 0x04 4. "CEVT4_EN,Capture Event 4 Interrupt Enable: 1'b0 Disabled Capture Event 4 as an Interrupt source: 1'b1 Enable Capture Event 4 as an Interrupt source" "0,1"
bitfld.long 0x04 3. "CEVT3_EN,Capture Event 3 Interrupt Enable: 1'b0 Disabled Capture Event 3 as an Interrupt source: 1'b1 Enable Capture Event 3 as an Interrupt source" "0,1"
bitfld.long 0x04 2. "CEVT2_EN,Capture Event 2 Interrupt Enable: 1'b0 Disabled Capture Event 2 as an Interrupt source: 1'b1 Enable Capture Event 2 as an Interrupt source" "0,1"
bitfld.long 0x04 1. "CEVT1_EN,Capture Event 1 Interrupt Enable: 1'b0 Disabled Capture Event 1 as an Interrupt source: 1'b1 Enable Capture Event 1 as an Interrupt source" "0,1"
line.long 0x08 "CTL_STS_ECINT_CLR_FRC,"
bitfld.long 0x08 23. "CMPEQ_FRC,Force Compare Equal: Writing a 1 to this bit will set the CMPEQ flag bit" "0,1"
bitfld.long 0x08 22. "PRDEQ_FRC,Force Period Equal: Writing a 1 to this bit will set the PRDEQ flag bit" "0,1"
bitfld.long 0x08 21. "CNTOVF_FRC,Force Counter Overflow: Writing a 1 to this bit will set the CNTOVF flag bit" "0,1"
bitfld.long 0x08 20. "CEVT4_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 19. "CEVT3_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 18. "CEVT2_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 17. "CEVT1_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 7. "CMPEQ_CLR,Compare Equal Status Flag: Writing a 1 will clear the CMPEQ flag condition" "0,1"
newline
bitfld.long 0x08 6. "PRDEQ_CLR,Period Equal Status Flag: Writing a 1 will clear the PRDEQ flag condition" "0,1"
bitfld.long 0x08 5. "CNTOVF_CLR,Counter Overflow Status Flag: Writing a 1 will clear the CNTOVF flag condition" "0,1"
bitfld.long 0x08 4. "CEVT4_CLR,Capture Event 4 Status Flag: Writing a 1 will clear the CEVT4 flag condition" "0,1"
bitfld.long 0x08 3. "CEVT3_CLR,Capture Event 3 Status Flag: Writing a 1 will clear the CEVT3 flag condition" "0,1"
bitfld.long 0x08 2. "CEVT2_CLR,Capture Event 2 Status Flag: Writing a 1 will clear the CEVT2 flag condition" "0,1"
bitfld.long 0x08 1. "CEVT1_CLR,Capture Event 1 Status Flag: Writing a 1 will clear the CEVT1 flag condition" "0,1"
bitfld.long 0x08 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "CTL_STS_PID,"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,"
bitfld.long 0x00 11.--15. "RTL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "ECAP1_CTL_STS"
base ad:0x23110000
group.long 0x00++0x17
line.long 0x00 "CTL_STS_TSCNT,"
line.long 0x04 "CTL_STS_CNTPHS,"
line.long 0x08 "CTL_STS_CAP1,"
line.long 0x0C "CTL_STS_CAP2,"
line.long 0x10 "CTL_STS_CAP3,"
line.long 0x14 "CTL_STS_CAP4,"
group.long 0x28++0x0B
line.long 0x00 "CTL_STS_ECCTL,"
rbitfld.long 0x00 27.--31. "FILTER," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "APWMPOL,APWM output polarity select: 1'b0 Output is Active High (i.e. Compare value defines High time); 1'b1 Output is Active Low (i.e. Compare value defines Low time); Note: This is applicable only in APWM operating mode" "0,1"
bitfld.long 0x00 25. "CAP_APWM,CAP/APWM operating mode select: 1'b0 ECAP module operates in Capture mode This mode forces the following configuration: 1- Inhibits TSCNT resets via PRD_eq event 2- Inhibits Shadow loads on CAP1 & 2 registers 3- Permits User to enable CAP1-4.." "0,1"
bitfld.long 0x00 24. "SWSYNC,Software forced Counter (TSCNT) sync'ing: 1'b0 Writing a Zero has no effect Reading will always return a zero; 1'b1 Writing a One will force a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits.." "0,1"
bitfld.long 0x00 22.--23. "SYNCO_SEL,Sync-Out select: 2'b00 Select Sync-In event to be the Sync-Out signal (pass through); 2'b01 Select PRD_eq event to be the Sync-Out signal; 2'b10 DISABLE Sync Out Signal; 2'b11 DISABLE Sync Out Signal; Note: Selection PRD_eq is meaningful only.." "0,1,2,3"
bitfld.long 0x00 21. "SYNCI_EN,Counter (TSCNT) Sync-In select mode: 1'b0 Disable Sync-In option 1'b1 Enable Counter (TSCNT) to be loaded from CNTPHS register upon either a SYNCI signal or a S/W force event" "0,1"
bitfld.long 0x00 20. "TSCNTSTP,Counter Stop (freeze) Control: 1'b0 Counter Stopped; 1'b1 Counter Free Running" "0,1"
bitfld.long 0x00 19. "REARM_RESET,One-Shot Re-arming i.e" "0,1"
newline
bitfld.long 0x00 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1-4) of Captures allowed to occur before the CAP(1-4) registers are frozen i.e.Capture sequence is stopped" "0,1,2,3"
bitfld.long 0x00 16. "CONT_ONESHT,Continuous or Oneshot mode control: (applicable only in Capture mode) 1'b0 Operate in Continuous mode 1'b1 Operate in One-Shot mode" "0,1"
bitfld.long 0x00 14.--15. "FREE_SOFT,Emulation Control 2'b00 TSCNT Counter stops immediately on emulation suspend; 2'b01 TSCNT Counter runs until = 0; 2'b1X TSCNT Counter is unaffected by emulation suspend (Run Free)" "0,1,2,3"
bitfld.long 0x00 9.--13. "EVTFLTPS,Event Filter prescale select: 5'b00000 divide by 1 (i.e. no prescale by-pass the prescaler); 5'b00001 divide by 2; 5'b00010 divide by 4; 5'b00011 divide by 6; 5'b00100 divide by 8; 5'b00101 divide by 10;" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a Capture Event: 1'b0 Disable CAP1-4 register loads at capture Event time; 1'b1 Enable CAP1-4 register loads at capture Event time" "0,1"
bitfld.long 0x00 7. "CTRRST4,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 6. "CAP4POL,Capture Event 4 Polarity select: 1'b0 Capture event 4 triggered on a Rising Edge (FE); 1'b1 Capture event 4 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 5. "CTRRST3,Counter Reset on Capture Event" "0,1"
newline
bitfld.long 0x00 4. "CAP3POL,Capture Event 3 Polarity select: 1'b0 Capture event 3 triggered on a Rising Edge (FE); 1'b1 Capture event 3 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 3. "CTRRST2,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 2. "CAP2POL,Capture Event 2 Polarity select: 1'b0 Capture event 2 triggered on a Rising Edge (FE); 1'b1 Capture event 2 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 1. "CTRRST1,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 0. "CAP1POL,Capture Event 1 Polarity select: 1'b0 Capture event 1 triggered on a Rising Edge (FE); 1'b1 Capture event 1 triggered on a Falling Edge (FE)" "0,1"
line.long 0x04 "CTL_STS_ECINT_EN_FLG,"
rbitfld.long 0x04 23. "CMPEQ_FLG,Compare Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Compare register value (ACMP) Reading a 0 indicates no event occurred Note: This flag is only active in APWM mode" "0,1"
rbitfld.long 0x04 22. "PRDEQ_FLG,Period Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Period register value (APER) and was reset" "0,1"
rbitfld.long 0x04 21. "CNTOVF_FLG,Counter Overflow Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) has made the transition from 0xFFFFFFFF 0x00000000 Reading a 0 indicates no event occurred" "0,1"
rbitfld.long 0x04 20. "CEVT4_FLG,Capture Event 4 Status Flag: Reading a 1 on this bit indicates the fourth event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 19. "CEVT3_FLG,Capture Event 3 Status Flag: Reading a 1 on this bit indicates the third event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 18. "CEVT2_FLG,Capture Event 2 Status Flag: Reading a 1 on this bit indicates the second event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 17. "CEVT1_FLG,Capture Event 1 Status Flag: Reading a 1 on this bit indicates the first event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events" "0,1"
newline
bitfld.long 0x04 7. "CMPEQ_EN,Compare Equal Interrupt Enable: 1'b0 Disabled Compare Equal as an Interrupt source; 1'b1 Enable Compare Equal as an Interrupt source" "0,1"
bitfld.long 0x04 6. "PRDEQ_EN,Period Equal Interrupt Enable: 1'b0 Disabled Period Equal as an Interrupt source; 1'b1 Enable Period Equal as an Interrupt source" "0,1"
bitfld.long 0x04 5. "CNTOVF_EN,Counter Overflow Interrupt Enable: 1'b0 Disabled Counter Overflow as an Interrupt source; 1'b1 Enable Counter Overflow as an Interrupt source" "0,1"
bitfld.long 0x04 4. "CEVT4_EN,Capture Event 4 Interrupt Enable: 1'b0 Disabled Capture Event 4 as an Interrupt source: 1'b1 Enable Capture Event 4 as an Interrupt source" "0,1"
bitfld.long 0x04 3. "CEVT3_EN,Capture Event 3 Interrupt Enable: 1'b0 Disabled Capture Event 3 as an Interrupt source: 1'b1 Enable Capture Event 3 as an Interrupt source" "0,1"
bitfld.long 0x04 2. "CEVT2_EN,Capture Event 2 Interrupt Enable: 1'b0 Disabled Capture Event 2 as an Interrupt source: 1'b1 Enable Capture Event 2 as an Interrupt source" "0,1"
bitfld.long 0x04 1. "CEVT1_EN,Capture Event 1 Interrupt Enable: 1'b0 Disabled Capture Event 1 as an Interrupt source: 1'b1 Enable Capture Event 1 as an Interrupt source" "0,1"
line.long 0x08 "CTL_STS_ECINT_CLR_FRC,"
bitfld.long 0x08 23. "CMPEQ_FRC,Force Compare Equal: Writing a 1 to this bit will set the CMPEQ flag bit" "0,1"
bitfld.long 0x08 22. "PRDEQ_FRC,Force Period Equal: Writing a 1 to this bit will set the PRDEQ flag bit" "0,1"
bitfld.long 0x08 21. "CNTOVF_FRC,Force Counter Overflow: Writing a 1 to this bit will set the CNTOVF flag bit" "0,1"
bitfld.long 0x08 20. "CEVT4_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 19. "CEVT3_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 18. "CEVT2_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 17. "CEVT1_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 7. "CMPEQ_CLR,Compare Equal Status Flag: Writing a 1 will clear the CMPEQ flag condition" "0,1"
newline
bitfld.long 0x08 6. "PRDEQ_CLR,Period Equal Status Flag: Writing a 1 will clear the PRDEQ flag condition" "0,1"
bitfld.long 0x08 5. "CNTOVF_CLR,Counter Overflow Status Flag: Writing a 1 will clear the CNTOVF flag condition" "0,1"
bitfld.long 0x08 4. "CEVT4_CLR,Capture Event 4 Status Flag: Writing a 1 will clear the CEVT4 flag condition" "0,1"
bitfld.long 0x08 3. "CEVT3_CLR,Capture Event 3 Status Flag: Writing a 1 will clear the CEVT3 flag condition" "0,1"
bitfld.long 0x08 2. "CEVT2_CLR,Capture Event 2 Status Flag: Writing a 1 will clear the CEVT2 flag condition" "0,1"
bitfld.long 0x08 1. "CEVT1_CLR,Capture Event 1 Status Flag: Writing a 1 will clear the CEVT1 flag condition" "0,1"
bitfld.long 0x08 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "CTL_STS_PID,"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,"
bitfld.long 0x00 11.--15. "RTL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "ECAP2_CTL_STS"
base ad:0x23120000
group.long 0x00++0x17
line.long 0x00 "CTL_STS_TSCNT,"
line.long 0x04 "CTL_STS_CNTPHS,"
line.long 0x08 "CTL_STS_CAP1,"
line.long 0x0C "CTL_STS_CAP2,"
line.long 0x10 "CTL_STS_CAP3,"
line.long 0x14 "CTL_STS_CAP4,"
group.long 0x28++0x0B
line.long 0x00 "CTL_STS_ECCTL,"
rbitfld.long 0x00 27.--31. "FILTER," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "APWMPOL,APWM output polarity select: 1'b0 Output is Active High (i.e. Compare value defines High time); 1'b1 Output is Active Low (i.e. Compare value defines Low time); Note: This is applicable only in APWM operating mode" "0,1"
bitfld.long 0x00 25. "CAP_APWM,CAP/APWM operating mode select: 1'b0 ECAP module operates in Capture mode This mode forces the following configuration: 1- Inhibits TSCNT resets via PRD_eq event 2- Inhibits Shadow loads on CAP1 & 2 registers 3- Permits User to enable CAP1-4.." "0,1"
bitfld.long 0x00 24. "SWSYNC,Software forced Counter (TSCNT) sync'ing: 1'b0 Writing a Zero has no effect Reading will always return a zero; 1'b1 Writing a One will force a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits.." "0,1"
bitfld.long 0x00 22.--23. "SYNCO_SEL,Sync-Out select: 2'b00 Select Sync-In event to be the Sync-Out signal (pass through); 2'b01 Select PRD_eq event to be the Sync-Out signal; 2'b10 DISABLE Sync Out Signal; 2'b11 DISABLE Sync Out Signal; Note: Selection PRD_eq is meaningful only.." "0,1,2,3"
bitfld.long 0x00 21. "SYNCI_EN,Counter (TSCNT) Sync-In select mode: 1'b0 Disable Sync-In option 1'b1 Enable Counter (TSCNT) to be loaded from CNTPHS register upon either a SYNCI signal or a S/W force event" "0,1"
bitfld.long 0x00 20. "TSCNTSTP,Counter Stop (freeze) Control: 1'b0 Counter Stopped; 1'b1 Counter Free Running" "0,1"
bitfld.long 0x00 19. "REARM_RESET,One-Shot Re-arming i.e" "0,1"
newline
bitfld.long 0x00 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1-4) of Captures allowed to occur before the CAP(1-4) registers are frozen i.e.Capture sequence is stopped" "0,1,2,3"
bitfld.long 0x00 16. "CONT_ONESHT,Continuous or Oneshot mode control: (applicable only in Capture mode) 1'b0 Operate in Continuous mode 1'b1 Operate in One-Shot mode" "0,1"
bitfld.long 0x00 14.--15. "FREE_SOFT,Emulation Control 2'b00 TSCNT Counter stops immediately on emulation suspend; 2'b01 TSCNT Counter runs until = 0; 2'b1X TSCNT Counter is unaffected by emulation suspend (Run Free)" "0,1,2,3"
bitfld.long 0x00 9.--13. "EVTFLTPS,Event Filter prescale select: 5'b00000 divide by 1 (i.e. no prescale by-pass the prescaler); 5'b00001 divide by 2; 5'b00010 divide by 4; 5'b00011 divide by 6; 5'b00100 divide by 8; 5'b00101 divide by 10;" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a Capture Event: 1'b0 Disable CAP1-4 register loads at capture Event time; 1'b1 Enable CAP1-4 register loads at capture Event time" "0,1"
bitfld.long 0x00 7. "CTRRST4,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 6. "CAP4POL,Capture Event 4 Polarity select: 1'b0 Capture event 4 triggered on a Rising Edge (FE); 1'b1 Capture event 4 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 5. "CTRRST3,Counter Reset on Capture Event" "0,1"
newline
bitfld.long 0x00 4. "CAP3POL,Capture Event 3 Polarity select: 1'b0 Capture event 3 triggered on a Rising Edge (FE); 1'b1 Capture event 3 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 3. "CTRRST2,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 2. "CAP2POL,Capture Event 2 Polarity select: 1'b0 Capture event 2 triggered on a Rising Edge (FE); 1'b1 Capture event 2 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 1. "CTRRST1,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 0. "CAP1POL,Capture Event 1 Polarity select: 1'b0 Capture event 1 triggered on a Rising Edge (FE); 1'b1 Capture event 1 triggered on a Falling Edge (FE)" "0,1"
line.long 0x04 "CTL_STS_ECINT_EN_FLG,"
rbitfld.long 0x04 23. "CMPEQ_FLG,Compare Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Compare register value (ACMP) Reading a 0 indicates no event occurred Note: This flag is only active in APWM mode" "0,1"
rbitfld.long 0x04 22. "PRDEQ_FLG,Period Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Period register value (APER) and was reset" "0,1"
rbitfld.long 0x04 21. "CNTOVF_FLG,Counter Overflow Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) has made the transition from 0xFFFFFFFF 0x00000000 Reading a 0 indicates no event occurred" "0,1"
rbitfld.long 0x04 20. "CEVT4_FLG,Capture Event 4 Status Flag: Reading a 1 on this bit indicates the fourth event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 19. "CEVT3_FLG,Capture Event 3 Status Flag: Reading a 1 on this bit indicates the third event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 18. "CEVT2_FLG,Capture Event 2 Status Flag: Reading a 1 on this bit indicates the second event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 17. "CEVT1_FLG,Capture Event 1 Status Flag: Reading a 1 on this bit indicates the first event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events" "0,1"
newline
bitfld.long 0x04 7. "CMPEQ_EN,Compare Equal Interrupt Enable: 1'b0 Disabled Compare Equal as an Interrupt source; 1'b1 Enable Compare Equal as an Interrupt source" "0,1"
bitfld.long 0x04 6. "PRDEQ_EN,Period Equal Interrupt Enable: 1'b0 Disabled Period Equal as an Interrupt source; 1'b1 Enable Period Equal as an Interrupt source" "0,1"
bitfld.long 0x04 5. "CNTOVF_EN,Counter Overflow Interrupt Enable: 1'b0 Disabled Counter Overflow as an Interrupt source; 1'b1 Enable Counter Overflow as an Interrupt source" "0,1"
bitfld.long 0x04 4. "CEVT4_EN,Capture Event 4 Interrupt Enable: 1'b0 Disabled Capture Event 4 as an Interrupt source: 1'b1 Enable Capture Event 4 as an Interrupt source" "0,1"
bitfld.long 0x04 3. "CEVT3_EN,Capture Event 3 Interrupt Enable: 1'b0 Disabled Capture Event 3 as an Interrupt source: 1'b1 Enable Capture Event 3 as an Interrupt source" "0,1"
bitfld.long 0x04 2. "CEVT2_EN,Capture Event 2 Interrupt Enable: 1'b0 Disabled Capture Event 2 as an Interrupt source: 1'b1 Enable Capture Event 2 as an Interrupt source" "0,1"
bitfld.long 0x04 1. "CEVT1_EN,Capture Event 1 Interrupt Enable: 1'b0 Disabled Capture Event 1 as an Interrupt source: 1'b1 Enable Capture Event 1 as an Interrupt source" "0,1"
line.long 0x08 "CTL_STS_ECINT_CLR_FRC,"
bitfld.long 0x08 23. "CMPEQ_FRC,Force Compare Equal: Writing a 1 to this bit will set the CMPEQ flag bit" "0,1"
bitfld.long 0x08 22. "PRDEQ_FRC,Force Period Equal: Writing a 1 to this bit will set the PRDEQ flag bit" "0,1"
bitfld.long 0x08 21. "CNTOVF_FRC,Force Counter Overflow: Writing a 1 to this bit will set the CNTOVF flag bit" "0,1"
bitfld.long 0x08 20. "CEVT4_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 19. "CEVT3_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 18. "CEVT2_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 17. "CEVT1_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 7. "CMPEQ_CLR,Compare Equal Status Flag: Writing a 1 will clear the CMPEQ flag condition" "0,1"
newline
bitfld.long 0x08 6. "PRDEQ_CLR,Period Equal Status Flag: Writing a 1 will clear the PRDEQ flag condition" "0,1"
bitfld.long 0x08 5. "CNTOVF_CLR,Counter Overflow Status Flag: Writing a 1 will clear the CNTOVF flag condition" "0,1"
bitfld.long 0x08 4. "CEVT4_CLR,Capture Event 4 Status Flag: Writing a 1 will clear the CEVT4 flag condition" "0,1"
bitfld.long 0x08 3. "CEVT3_CLR,Capture Event 3 Status Flag: Writing a 1 will clear the CEVT3 flag condition" "0,1"
bitfld.long 0x08 2. "CEVT2_CLR,Capture Event 2 Status Flag: Writing a 1 will clear the CEVT2 flag condition" "0,1"
bitfld.long 0x08 1. "CEVT1_CLR,Capture Event 1 Status Flag: Writing a 1 will clear the CEVT1 flag condition" "0,1"
bitfld.long 0x08 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "CTL_STS_PID,"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,"
bitfld.long 0x00 11.--15. "RTL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "EFUSE0"
base ad:0x300000
group.long 0x00++0x0B
line.long 0x00 "MEM_SYS_STATUS,efuse system_status"
line.long 0x04 "MEM_OCP_CTRL_LOWER,OCP control"
line.long 0x08 "MEM_OCP_CTRL_UPPER,OCP control"
group.long 0x10++0x03
line.long 0x00 "MEM_SYS_CONFIG,System config"
tree.end
tree "ELM0"
base ad:0x25010000
rgroup.long 0x00++0x03
line.long 0x00 "MEM_ELM_REVISION,This register contains the IP revision code.(A write to this register has no effect. the same as the reset)"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_0,Read returns 0"
hexmask.long.byte 0x00 0.--7. 1. "REV_NUMBER,IP revision number [RTL] [7:4] Major revision [3:0] Minor revision"
group.long 0x10++0x13
line.long 0x00 "MEM_ELM_SYSCONFIG,This register allows controlling various parameters of the OCP interface"
bitfld.long 0x00 8. "CLOCKACTIVITYOCP,OCP Clock activity when module is in IDLE mode [during wake up mode period]" "0,1"
bitfld.long 0x00 3.--4. "SIDLEMODE,Slave interface power management [IDLE req/ack control]" "0,1,2,3"
newline
bitfld.long 0x00 1. "SOFTRESET,Module Software Reset The bit is automatically reset by the hardware [During reads it always returns 0] It has same effect as the OCP Hardware reset" "0,1"
bitfld.long 0x00 0. "AUTOGATING,Internal OCP clock gating strategy [no module visible impact other than saving power]" "0,1"
line.long 0x04 "MEM_ELM_SYSSTATUS,Internal Reset monitoring (OCP domain)Undefined since:on HW perspective reset state is 0on SW user perspective when module is accessible is 1"
bitfld.long 0x04 0. "RESETDONE,Internal Reset monitoring [OCP domain] Undefined since: on HW perspective reset state is 0 on SW user perspective when module is accessible is 1" "0,1"
line.long 0x08 "MEM_ELM_IRQSTATUS,Interrupt status"
bitfld.long 0x08 8. "PAGE_VALID,Error location status for a full page based on the mask definition Read" "no effect,clear interrupt"
bitfld.long 0x08 7. "LOC_VALID_7,Error location status for syndrome polynomial 7" "no effect,clear interrupt"
newline
bitfld.long 0x08 6. "LOC_VALID_6,Error location status for syndrome polynomial 6" "0,1"
bitfld.long 0x08 5. "LOC_VALID_5,Error location status for syndrome polynomial 5" "0,1"
newline
bitfld.long 0x08 4. "LOC_VALID_4,Error location status for syndrome polynomial 4" "0,1"
bitfld.long 0x08 3. "LOC_VALID_3,Error location status for syndrome polynomial 3" "0,1"
newline
bitfld.long 0x08 2. "LOC_VALID_2,Error location status for syndrome polynomial 2" "0,1"
bitfld.long 0x08 1. "LOC_VALID_1,Error location status for syndrome polynomial 1" "0,1"
newline
bitfld.long 0x08 0. "LOC_VALID_0,Error location status for syndrome polynomial 0" "0,1"
line.long 0x0C "MEM_ELM_IRQENABLE,Interrupt enable"
bitfld.long 0x0C 8. "PAGE_MASK,Page interrupt mask bit" "disable interrupt,enable interrupt"
bitfld.long 0x0C 7. "LOCATION_MASK_7,Error location interrupt mask bit for syndrome polynomial 7" "0,1"
newline
bitfld.long 0x0C 6. "LOCATION_MASK_6,Error location interrupt mask bit for syndrome polynomial 6" "0,1"
bitfld.long 0x0C 5. "LOCATION_MASK_5,Error location interrupt mask bit for syndrome polynomial 5" "0,1"
newline
bitfld.long 0x0C 4. "LOCATION_MASK_4,Error location interrupt mask bit for syndrome polynomial 4" "0,1"
bitfld.long 0x0C 3. "LOCATION_MASK_3,Error location interrupt mask bit for syndrome polynomial 3" "0,1"
newline
bitfld.long 0x0C 2. "LOCATION_MASK_2,Error location interrupt mask bit for syndrome polynomial 2" "0,1"
bitfld.long 0x0C 1. "LOCATION_MASK_1,Error location interrupt mask bit for syndrome polynomial 1" "0,1"
newline
bitfld.long 0x0C 0. "LOCATION_MASK_0,Error location interrupt mask bit for syndrome polynomial 0" "disable interrupt,enable interrupt"
line.long 0x10 "MEM_ELM_LOCATION_CONFIG,ECC algorithm parameters"
hexmask.long.word 0x10 16.--26. 1. "ECC_SIZE,Maximum size of the buffers for which the error location engine is used in number of nibbles [4-bits entities]"
bitfld.long 0x10 0.--1. "ECC_BCH_LEVEL,Error correction level" "4 bits,8 bits,16 bits,reserved"
group.long 0x80++0x03
line.long 0x00 "MEM_ELM_PAGE_CTRL,Page definition"
bitfld.long 0x00 7. "SECTOR_7,Set to 1 if syndrome polynomial 7 is part of the page in page mode Must be 0 in continuous mode" "0,1"
bitfld.long 0x00 6. "SECTOR_6,Set to 1 if syndrome polynomial 6 is part of the page in page mode Must be 0 in continuous mode" "0,1"
newline
bitfld.long 0x00 5. "SECTOR_5,Set to 1 if syndrome polynomial 5 is part of the page in page mode Must be 0 in continuous mode" "0,1"
bitfld.long 0x00 4. "SECTOR_4,Set to 1 if syndrome polynomial 4 is part of the page in page mode Must be 0 in continuous mode" "0,1"
newline
bitfld.long 0x00 3. "SECTOR_3,Set to 1 if syndrome polynomial 3 is part of the page in page mode Must be 0 in continuous mode" "0,1"
bitfld.long 0x00 2. "SECTOR_2,Set to 1 if syndrome polynomial 2 is part of the page in page mode Must be 0 in continuous mode" "0,1"
newline
bitfld.long 0x00 1. "SECTOR_1,Set to 1 if syndrome polynomial 1 is part of the page in page mode Must be 0 in continuous mode" "0,1"
bitfld.long 0x00 0. "SECTOR_0,Set to 1 if syndrome polynomial 0 is part of the page in page mode Must be 0 in continuous mode" "0,1"
group.long 0x400++0x1B
line.long 0x00 "MEM_ELM_SYNDROME_FRAGMENT_0,Input syndrome polynomial bits 0 to 31"
line.long 0x04 "MEM_ELM_SYNDROME_FRAGMENT_1,Input syndrome polynomial bits 32 to 63"
line.long 0x08 "MEM_ELM_SYNDROME_FRAGMENT_2,Input syndrome polynomial bits 64 to 95"
line.long 0x0C "MEM_ELM_SYNDROME_FRAGMENT_3,Input syndrome polynomial bits 96 to 127"
line.long 0x10 "MEM_ELM_SYNDROME_FRAGMENT_4,Input syndrome polynomial bits 128 to 159"
line.long 0x14 "MEM_ELM_SYNDROME_FRAGMENT_5,Input syndrome polynomial bits 160 to 191"
line.long 0x18 "MEM_ELM_SYNDROME_FRAGMENT_6,Input syndrome polynomial bits 192 to 207"
bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit" "this syndrome polynomial should not be processed,this syndrome polynomial must be processed"
hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207"
rgroup.long 0x800++0x03
line.long 0x00 "MEM_ELM_LOCATION_STATUS,Exit status for the syndrome polynomial processing"
bitfld.long 0x00 8. "ECC_CORRECTABLE,Error location process exit status" "ECC error location process failed Number of..,all errors were successfully located Number of.."
bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x880)++0x03
line.long 0x00 "MEM_ELM_ERROR_LOCATION_$1,Error location register"
hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
repeat.end
tree.end
tree "EPWM0_EPWM"
base ad:0x23000000
group.word 0x00++0x0B
line.word 0x00 "EPWM_REGS_TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events" "0,1,2,3"
bitfld.word 0x00 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase.." "0,1"
bitfld.word 0x00 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7"
bitfld.word 0x00 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1"
bitfld.word 0x00 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3"
bitfld.word 0x00 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1"
bitfld.word 0x00 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1"
bitfld.word 0x00 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3"
line.word 0x02 "EPWM_REGS_TBSTS,Time-Base Status Register"
bitfld.word 0x02 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1"
bitfld.word 0x02 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1"
rbitfld.word 0x02 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1"
line.word 0x04 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register"
hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x06 "EPWM_REGS_TBPHS,Time Base Phase Register"
line.word 0x08 "EPWM_REGS_TBCNT,Time Base Counter Register"
line.word 0x0A "EPWM_REGS_TBPRD,Time Base Period Register"
group.word 0x0E++0x17
line.word 0x00 "EPWM_REGS_CMPCTL,Counter Compare Control Register"
rbitfld.word 0x00 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
rbitfld.word 0x00 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self.." "0,1"
bitfld.word 0x00 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1"
bitfld.word 0x00 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1"
bitfld.word 0x00 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3"
bitfld.word 0x00 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3"
line.word 0x02 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register"
hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h"
line.word 0x04 "EPWM_REGS_CMPA,Counter Compare A Register"
line.word 0x06 "EPWM_REGS_CMPB,Counter Compare B Register"
line.word 0x08 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A"
bitfld.word 0x08 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x08 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x08 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x08 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x08 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x08 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0x0A "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B"
bitfld.word 0x0A 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x0A 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x0A 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x0A 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x0A 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x0A 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0x0C "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register"
bitfld.word 0x0C 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3"
bitfld.word 0x0C 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1"
bitfld.word 0x0C 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3"
bitfld.word 0x0C 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1"
bitfld.word 0x0C 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3"
line.word 0x0E "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register"
bitfld.word 0x0E 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3"
bitfld.word 0x0E 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3"
line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms the default is EPWMxA In is.." "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3"
bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3"
line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter"
line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter"
line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register"
hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low a one-shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA and.."
hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low a cycle-by-cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA.."
group.word 0x28++0x15
line.word 0x00 "EPWM_REGS_TZCTL,Trip Zone Control Register"
bitfld.word 0x00 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
bitfld.word 0x00 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
line.word 0x02 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register"
bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1"
bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1"
line.word 0x04 "EPWM_REGS_TZFLG,Trip Zone Flag Register"
bitfld.word 0x04 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1"
bitfld.word 0x04 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1"
bitfld.word 0x04 0. "INT,Latched Trip Interrupt Status Flag" "0,1"
line.word 0x06 "EPWM_REGS_TZCLR,Trip Zone Clear Register"
bitfld.word 0x06 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1"
bitfld.word 0x06 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1"
bitfld.word 0x06 0. "INT,Global Interrupt Clear Flag" "0,1"
line.word 0x08 "EPWM_REGS_TZFRC,Trip Zone Force Register"
bitfld.word 0x08 2. "OST,Force a One-Shot Trip Event via Software" "0,1"
bitfld.word 0x08 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1"
line.word 0x0A "EPWM_REGS_ETSEL,Event Trigger Selection Register"
bitfld.word 0x0A 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1"
bitfld.word 0x0A 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7"
line.word 0x0C "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register"
rbitfld.word 0x0C 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled ETSEL[INT] = 0 or the.." "0,1,2,3"
bitfld.word 0x0C 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3"
line.word 0x0E "EPWM_REGS_ETFLG,Event Trigger Flag Register"
bitfld.word 0x0E 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1"
line.word 0x10 "EPWM_REGS_ETCLR,Event Trigger Clear Register"
bitfld.word 0x10 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x12 "EPWM_REGS_ETFRC,Event Trigger Force Register"
bitfld.word 0x12 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1"
line.word 0x14 "EPWM_REGS_PCCTL,PWM Chopper Control Register"
bitfld.word 0x14 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x14 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7"
bitfld.word 0x14 1.--4. "OSHTWTH,One-Shot Pulse Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x14 0. "CHPEN,PWM-chopping Enable" "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "EPWM_REGS_PID,EHRPWM Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,FUNC"
bitfld.long 0x00 11.--15. "R_RTL,RTL version [R] maintained by IP design owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,CUSTOM" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor revision [Y]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "EPWM1_EPWM"
base ad:0x23010000
group.word 0x00++0x0B
line.word 0x00 "EPWM_REGS_TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events" "0,1,2,3"
bitfld.word 0x00 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase.." "0,1"
bitfld.word 0x00 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7"
bitfld.word 0x00 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1"
bitfld.word 0x00 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3"
bitfld.word 0x00 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1"
bitfld.word 0x00 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1"
bitfld.word 0x00 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3"
line.word 0x02 "EPWM_REGS_TBSTS,Time-Base Status Register"
bitfld.word 0x02 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1"
bitfld.word 0x02 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1"
rbitfld.word 0x02 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1"
line.word 0x04 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register"
hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x06 "EPWM_REGS_TBPHS,Time Base Phase Register"
line.word 0x08 "EPWM_REGS_TBCNT,Time Base Counter Register"
line.word 0x0A "EPWM_REGS_TBPRD,Time Base Period Register"
group.word 0x0E++0x17
line.word 0x00 "EPWM_REGS_CMPCTL,Counter Compare Control Register"
rbitfld.word 0x00 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
rbitfld.word 0x00 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self.." "0,1"
bitfld.word 0x00 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1"
bitfld.word 0x00 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1"
bitfld.word 0x00 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3"
bitfld.word 0x00 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3"
line.word 0x02 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register"
hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h"
line.word 0x04 "EPWM_REGS_CMPA,Counter Compare A Register"
line.word 0x06 "EPWM_REGS_CMPB,Counter Compare B Register"
line.word 0x08 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A"
bitfld.word 0x08 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x08 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x08 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x08 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x08 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x08 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0x0A "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B"
bitfld.word 0x0A 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x0A 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x0A 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x0A 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x0A 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x0A 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0x0C "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register"
bitfld.word 0x0C 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3"
bitfld.word 0x0C 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1"
bitfld.word 0x0C 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3"
bitfld.word 0x0C 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1"
bitfld.word 0x0C 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3"
line.word 0x0E "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register"
bitfld.word 0x0E 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3"
bitfld.word 0x0E 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3"
line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms the default is EPWMxA In is.." "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3"
bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3"
line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter"
line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter"
line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register"
hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low a one-shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA and.."
hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low a cycle-by-cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA.."
group.word 0x28++0x15
line.word 0x00 "EPWM_REGS_TZCTL,Trip Zone Control Register"
bitfld.word 0x00 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
bitfld.word 0x00 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
line.word 0x02 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register"
bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1"
bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1"
line.word 0x04 "EPWM_REGS_TZFLG,Trip Zone Flag Register"
bitfld.word 0x04 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1"
bitfld.word 0x04 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1"
bitfld.word 0x04 0. "INT,Latched Trip Interrupt Status Flag" "0,1"
line.word 0x06 "EPWM_REGS_TZCLR,Trip Zone Clear Register"
bitfld.word 0x06 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1"
bitfld.word 0x06 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1"
bitfld.word 0x06 0. "INT,Global Interrupt Clear Flag" "0,1"
line.word 0x08 "EPWM_REGS_TZFRC,Trip Zone Force Register"
bitfld.word 0x08 2. "OST,Force a One-Shot Trip Event via Software" "0,1"
bitfld.word 0x08 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1"
line.word 0x0A "EPWM_REGS_ETSEL,Event Trigger Selection Register"
bitfld.word 0x0A 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1"
bitfld.word 0x0A 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7"
line.word 0x0C "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register"
rbitfld.word 0x0C 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled ETSEL[INT] = 0 or the.." "0,1,2,3"
bitfld.word 0x0C 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3"
line.word 0x0E "EPWM_REGS_ETFLG,Event Trigger Flag Register"
bitfld.word 0x0E 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1"
line.word 0x10 "EPWM_REGS_ETCLR,Event Trigger Clear Register"
bitfld.word 0x10 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x12 "EPWM_REGS_ETFRC,Event Trigger Force Register"
bitfld.word 0x12 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1"
line.word 0x14 "EPWM_REGS_PCCTL,PWM Chopper Control Register"
bitfld.word 0x14 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x14 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7"
bitfld.word 0x14 1.--4. "OSHTWTH,One-Shot Pulse Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x14 0. "CHPEN,PWM-chopping Enable" "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "EPWM_REGS_PID,EHRPWM Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,FUNC"
bitfld.long 0x00 11.--15. "R_RTL,RTL version [R] maintained by IP design owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,CUSTOM" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor revision [Y]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "EPWM2_EPWM"
base ad:0x23020000
group.word 0x00++0x0B
line.word 0x00 "EPWM_REGS_TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events" "0,1,2,3"
bitfld.word 0x00 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase.." "0,1"
bitfld.word 0x00 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7"
bitfld.word 0x00 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1"
bitfld.word 0x00 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3"
bitfld.word 0x00 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1"
bitfld.word 0x00 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1"
bitfld.word 0x00 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3"
line.word 0x02 "EPWM_REGS_TBSTS,Time-Base Status Register"
bitfld.word 0x02 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1"
bitfld.word 0x02 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1"
rbitfld.word 0x02 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1"
line.word 0x04 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register"
hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x06 "EPWM_REGS_TBPHS,Time Base Phase Register"
line.word 0x08 "EPWM_REGS_TBCNT,Time Base Counter Register"
line.word 0x0A "EPWM_REGS_TBPRD,Time Base Period Register"
group.word 0x0E++0x17
line.word 0x00 "EPWM_REGS_CMPCTL,Counter Compare Control Register"
rbitfld.word 0x00 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
rbitfld.word 0x00 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self.." "0,1"
bitfld.word 0x00 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1"
bitfld.word 0x00 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1"
bitfld.word 0x00 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3"
bitfld.word 0x00 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3"
line.word 0x02 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register"
hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h"
line.word 0x04 "EPWM_REGS_CMPA,Counter Compare A Register"
line.word 0x06 "EPWM_REGS_CMPB,Counter Compare B Register"
line.word 0x08 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A"
bitfld.word 0x08 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x08 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x08 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x08 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x08 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x08 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0x0A "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B"
bitfld.word 0x0A 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x0A 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x0A 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x0A 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x0A 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x0A 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0x0C "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register"
bitfld.word 0x0C 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3"
bitfld.word 0x0C 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1"
bitfld.word 0x0C 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3"
bitfld.word 0x0C 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1"
bitfld.word 0x0C 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3"
line.word 0x0E "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register"
bitfld.word 0x0E 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3"
bitfld.word 0x0E 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3"
line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms the default is EPWMxA In is.." "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3"
bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3"
line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter"
line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter"
line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register"
hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low a one-shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA and.."
hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low a cycle-by-cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA.."
group.word 0x28++0x15
line.word 0x00 "EPWM_REGS_TZCTL,Trip Zone Control Register"
bitfld.word 0x00 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
bitfld.word 0x00 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
line.word 0x02 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register"
bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1"
bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1"
line.word 0x04 "EPWM_REGS_TZFLG,Trip Zone Flag Register"
bitfld.word 0x04 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1"
bitfld.word 0x04 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1"
bitfld.word 0x04 0. "INT,Latched Trip Interrupt Status Flag" "0,1"
line.word 0x06 "EPWM_REGS_TZCLR,Trip Zone Clear Register"
bitfld.word 0x06 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1"
bitfld.word 0x06 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1"
bitfld.word 0x06 0. "INT,Global Interrupt Clear Flag" "0,1"
line.word 0x08 "EPWM_REGS_TZFRC,Trip Zone Force Register"
bitfld.word 0x08 2. "OST,Force a One-Shot Trip Event via Software" "0,1"
bitfld.word 0x08 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1"
line.word 0x0A "EPWM_REGS_ETSEL,Event Trigger Selection Register"
bitfld.word 0x0A 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1"
bitfld.word 0x0A 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7"
line.word 0x0C "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register"
rbitfld.word 0x0C 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled ETSEL[INT] = 0 or the.." "0,1,2,3"
bitfld.word 0x0C 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3"
line.word 0x0E "EPWM_REGS_ETFLG,Event Trigger Flag Register"
bitfld.word 0x0E 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1"
line.word 0x10 "EPWM_REGS_ETCLR,Event Trigger Clear Register"
bitfld.word 0x10 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x12 "EPWM_REGS_ETFRC,Event Trigger Force Register"
bitfld.word 0x12 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1"
line.word 0x14 "EPWM_REGS_PCCTL,PWM Chopper Control Register"
bitfld.word 0x14 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x14 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7"
bitfld.word 0x14 1.--4. "OSHTWTH,One-Shot Pulse Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x14 0. "CHPEN,PWM-chopping Enable" "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "EPWM_REGS_PID,EHRPWM Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,FUNC"
bitfld.long 0x00 11.--15. "R_RTL,RTL version [R] maintained by IP design owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,CUSTOM" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor revision [Y]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "EQEP0_REG"
base ad:0x23200000
group.long 0x00++0x23
line.long 0x00 "REG_QPOSCNT,Position Counter"
line.long 0x04 "REG_QPOSINIT,Position Counter Init"
line.long 0x08 "REG_QPOSMAX,Maximum Position Count"
line.long 0x0C "REG_QPOSCMP,Position Compare"
line.long 0x10 "REG_QPOSILAT,Index Position Latch"
line.long 0x14 "REG_QPOSSLAT,Strobe Position Latch"
line.long 0x18 "REG_QPOSLAT,Position Latch"
line.long 0x1C "REG_QUTMR,QEP Unit Timer"
line.long 0x20 "REG_QUPRD,QEP Unit Period"
group.word 0x24++0x1D
line.word 0x00 "REG_QWDTMR,QEP Watchdog Timer"
line.word 0x02 "REG_QWDPRD,QEP Watchdog Period"
line.word 0x04 "REG_QDECCTL_TYPE2,Quadrature Decoder Control"
bitfld.word 0x04 14.--15. "QSRC,Position-counter source selection" "0,1,2,3"
bitfld.word 0x04 13. "SOEN,Sync output-enable" "0,1"
bitfld.word 0x04 12. "SPSEL,Sync output pin selection" "0,1"
bitfld.word 0x04 11. "XCR,External Clock Rate" "0,1"
bitfld.word 0x04 10. "SWAP,CLK/DIR Signal Source for Position Counter" "0,1"
bitfld.word 0x04 9. "IGATE,Index pulse gating option" "0,1"
bitfld.word 0x04 8. "QAP,QEPA input polarity" "0,1"
bitfld.word 0x04 7. "QBP,QEPB input polarity" "0,1"
bitfld.word 0x04 6. "QIP,QEPI input polarity" "0,1"
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bitfld.word 0x04 5. "QSP,QEPS input polarity" "0,1"
bitfld.word 0x04 0. "QIDIRE," "0,1"
line.word 0x06 "REG_QEPCTL,QEP Control"
bitfld.word 0x06 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
bitfld.word 0x06 12.--13. "PCRM,Postion counter reset" "0,1,2,3"
bitfld.word 0x06 10.--11. "SEI,Strobe event initialization of position counter" "0,1,2,3"
bitfld.word 0x06 8.--9. "IEI,Index event init of position count" "0,1,2,3"
bitfld.word 0x06 7. "SWI,Software init position counter" "0,1"
bitfld.word 0x06 6. "SEL,Strobe event latch of position counter" "0,1"
bitfld.word 0x06 4.--5. "IEL,Index event latch of position counter [software index marker]" "0,1,2,3"
bitfld.word 0x06 3. "QPEN,Quadrature position counter enable/software reset" "0,1"
bitfld.word 0x06 2. "QCLM,QEP capture latch mode" "0,1"
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bitfld.word 0x06 1. "UTE,QEP unit timer enable" "0,1"
bitfld.word 0x06 0. "WDE,QEP watchdog enable" "0,1"
line.word 0x08 "REG_QCAPCTL,Qaudrature Capture Control"
bitfld.word 0x08 15. "CEN,Enable eQEP capture" "0,1"
bitfld.word 0x08 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7"
bitfld.word 0x08 0.--3. "UPPS,Unit position event prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x0A "REG_QPOSCTL,Position Compare Control"
bitfld.word 0x0A 15. "PCSHDW,Position compare of shadow enable" "0,1"
bitfld.word 0x0A 14. "PCLOAD,Position compare of shadow load" "0,1"
bitfld.word 0x0A 13. "PCPOL,Polarity of sync output" "0,1"
bitfld.word 0x0A 12. "PCE,Position compare enable/disable" "0,1"
hexmask.word 0x0A 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width"
line.word 0x0C "REG_QEINT_TYPE1,QEP Interrupt Control"
bitfld.word 0x0C 12. "QMAE,QMA Error Interrupt enable" "0,1"
bitfld.word 0x0C 11. "UTO,Unit time out interrupt enable" "0,1"
bitfld.word 0x0C 10. "IEL,Index event latch interrupt enable" "0,1"
bitfld.word 0x0C 9. "SEL,Strobe event latch interrupt enable" "0,1"
bitfld.word 0x0C 8. "PCM,Position-compare match interrupt enable" "0,1"
bitfld.word 0x0C 7. "PCR,Position-compare ready interrupt enable" "0,1"
bitfld.word 0x0C 6. "PCO,Position counter overflow interrupt enable" "0,1"
bitfld.word 0x0C 5. "PCU,Position counter underflow interrupt enable" "0,1"
bitfld.word 0x0C 4. "WTO,Watchdog time out interrupt enable" "0,1"
newline
bitfld.word 0x0C 3. "QDC,Quadrature direction change interrupt enable" "0,1"
bitfld.word 0x0C 2. "QPE,Quadrature phase error interrupt enable" "0,1"
bitfld.word 0x0C 1. "PCE,Position counter error interrupt enable" "0,1"
line.word 0x0E "REG_QFLG_TYPE1,QEP Interrupt Flag"
bitfld.word 0x0E 12. "QMAE,QMA Error interrupt flag" "0,1"
bitfld.word 0x0E 11. "UTO,Unit time out interrupt flag" "0,1"
bitfld.word 0x0E 10. "IEL,Index event latch interrupt flag" "0,1"
bitfld.word 0x0E 9. "SEL,Strobe event latch interrupt flag" "0,1"
bitfld.word 0x0E 8. "PCM,eQEP compare match event interrupt flag" "0,1"
bitfld.word 0x0E 7. "PCR,Position-compare ready interrupt flag" "0,1"
bitfld.word 0x0E 6. "PCO,Position counter overflow interrupt flag" "0,1"
bitfld.word 0x0E 5. "PCU,Position counter underflow interrupt flag" "0,1"
bitfld.word 0x0E 4. "WTO,Watchdog timeout interrupt flag" "0,1"
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bitfld.word 0x0E 3. "QDC,Quadrature direction change interrupt flag" "0,1"
bitfld.word 0x0E 2. "PHE,Quadrature phase error interrupt flag" "0,1"
bitfld.word 0x0E 1. "PCE,Position counter error interrupt flag" "0,1"
bitfld.word 0x0E 0. "INT,Global interrupt status flag" "0,1"
line.word 0x10 "REG_QCLR_TYPE1,QEP Interrupt Clear"
bitfld.word 0x10 12. "QMAE,Clear QMA Error interrupt flag" "0,1"
bitfld.word 0x10 11. "UTO,Clear unit time out interrupt flag" "0,1"
bitfld.word 0x10 10. "IEL,Clear index event latch interrupt flag" "0,1"
bitfld.word 0x10 9. "SEL,Clear strobe event latch interrupt flag" "0,1"
bitfld.word 0x10 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1"
bitfld.word 0x10 7. "PCR,Clear position-compare ready interrupt flag" "0,1"
bitfld.word 0x10 6. "PCO,Clear position counter overflow interrupt flag" "0,1"
bitfld.word 0x10 5. "PCU,Clear position counter underflow interrupt flag" "0,1"
bitfld.word 0x10 4. "WTO,Clear watchdog timeout interrupt flag" "0,1"
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bitfld.word 0x10 3. "QDC,Clear quadrature direction change interrupt flag" "0,1"
bitfld.word 0x10 2. "PHE,Clear quadrature phase error interrupt flag" "0,1"
bitfld.word 0x10 1. "PCE,Clear position counter error interrupt flag" "0,1"
bitfld.word 0x10 0. "INT,Global interrupt clear flag" "0,1"
line.word 0x12 "REG_QFRC_TYPE1,QEP Interrupt Force"
bitfld.word 0x12 12. "QMAE,Force QMA error interrupt" "0,1"
bitfld.word 0x12 11. "UTO,Force unit time out interrupt" "0,1"
bitfld.word 0x12 10. "IEL,Force index event latch interrupt" "0,1"
bitfld.word 0x12 9. "SEL,Force strobe event latch interrupt" "0,1"
bitfld.word 0x12 8. "PCM,Force position-compare match interrupt" "0,1"
bitfld.word 0x12 7. "PCR,Force position-compare ready interrupt" "0,1"
bitfld.word 0x12 6. "PCO,Force position counter overflow interrupt" "0,1"
bitfld.word 0x12 5. "PCU,Force position counter underflow interrupt" "0,1"
bitfld.word 0x12 4. "WTO,Force watchdog time out interrupt" "0,1"
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bitfld.word 0x12 3. "QDC,Force quadrature direction change interrupt" "0,1"
bitfld.word 0x12 2. "PHE,Force quadrature phase error interrupt" "0,1"
bitfld.word 0x12 1. "PCE,Force position counter error interrupt" "0,1"
line.word 0x14 "REG_QEPSTS_TYPE1,QEP Status"
bitfld.word 0x14 7. "UPEVNT,Unit position event flag" "0,1"
rbitfld.word 0x14 6. "FIDF,Direction on the first index markerStatus of the direction is latched on the first index event marker" "0,1"
rbitfld.word 0x14 5. "QDF,Quadrature direction flag" "0,1"
rbitfld.word 0x14 4. "QDLF,eQEP direction latch flag" "0,1"
bitfld.word 0x14 3. "COEF,Capture overflow error flag" "0,1"
bitfld.word 0x14 2. "CDEF,Capture direction error flag" "0,1"
bitfld.word 0x14 1. "FIMF,First index marker flag" "0,1"
rbitfld.word 0x14 0. "PCEF,Position counter error flag" "0,1"
line.word 0x16 "REG_QCTMR,QEP Capture Timer"
line.word 0x18 "REG_QCPRD,QEP Capture Period"
line.word 0x1A "REG_QCTMRLAT,QEP Capture Latch"
line.word 0x1C "REG_QCPRDLAT,QEP Capture Period Latch"
repeat 2. (list 1. 2. )(list 0x00 0x2E )
hgroup.word ($2+0x42)++0x01
hide.word 0x00 "REG_Reserved_$1,"
repeat.end
rgroup.long 0x60++0x0F
line.long 0x00 "REG_REV_TYPE2,QEP Revision Number"
bitfld.long 0x00 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP" "0,1,2,3,4,5,6,7"
line.long 0x04 "REG_QEPSTROBESEL,QEP Strobe select register"
bitfld.long 0x04 0.--1. "STROBESEL,Strobe source select" "0,1,2,3"
line.long 0x08 "REG_QMACTRL,QMA Control register"
bitfld.long 0x08 0.--2. "MODE,Select Mode for QMA mode:000 : QMA Module is bypassed" "0,1,2,3,4,5,6,7"
line.long 0x0C "REG_QEPSRCSEL,QEP Source Select Register"
bitfld.long 0x0C 12.--15. "QEPSSEL,QEP Strobe source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 8.--11. "QEPISEL,QEP Index source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 4.--7. "QEPBSEL,QEPB source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "QEPASEL,QEPA source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EQEP1_REG"
base ad:0x23210000
group.long 0x00++0x23
line.long 0x00 "REG_QPOSCNT,Position Counter"
line.long 0x04 "REG_QPOSINIT,Position Counter Init"
line.long 0x08 "REG_QPOSMAX,Maximum Position Count"
line.long 0x0C "REG_QPOSCMP,Position Compare"
line.long 0x10 "REG_QPOSILAT,Index Position Latch"
line.long 0x14 "REG_QPOSSLAT,Strobe Position Latch"
line.long 0x18 "REG_QPOSLAT,Position Latch"
line.long 0x1C "REG_QUTMR,QEP Unit Timer"
line.long 0x20 "REG_QUPRD,QEP Unit Period"
group.word 0x24++0x1D
line.word 0x00 "REG_QWDTMR,QEP Watchdog Timer"
line.word 0x02 "REG_QWDPRD,QEP Watchdog Period"
line.word 0x04 "REG_QDECCTL_TYPE2,Quadrature Decoder Control"
bitfld.word 0x04 14.--15. "QSRC,Position-counter source selection" "0,1,2,3"
bitfld.word 0x04 13. "SOEN,Sync output-enable" "0,1"
bitfld.word 0x04 12. "SPSEL,Sync output pin selection" "0,1"
bitfld.word 0x04 11. "XCR,External Clock Rate" "0,1"
bitfld.word 0x04 10. "SWAP,CLK/DIR Signal Source for Position Counter" "0,1"
bitfld.word 0x04 9. "IGATE,Index pulse gating option" "0,1"
bitfld.word 0x04 8. "QAP,QEPA input polarity" "0,1"
bitfld.word 0x04 7. "QBP,QEPB input polarity" "0,1"
bitfld.word 0x04 6. "QIP,QEPI input polarity" "0,1"
newline
bitfld.word 0x04 5. "QSP,QEPS input polarity" "0,1"
bitfld.word 0x04 0. "QIDIRE," "0,1"
line.word 0x06 "REG_QEPCTL,QEP Control"
bitfld.word 0x06 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
bitfld.word 0x06 12.--13. "PCRM,Postion counter reset" "0,1,2,3"
bitfld.word 0x06 10.--11. "SEI,Strobe event initialization of position counter" "0,1,2,3"
bitfld.word 0x06 8.--9. "IEI,Index event init of position count" "0,1,2,3"
bitfld.word 0x06 7. "SWI,Software init position counter" "0,1"
bitfld.word 0x06 6. "SEL,Strobe event latch of position counter" "0,1"
bitfld.word 0x06 4.--5. "IEL,Index event latch of position counter [software index marker]" "0,1,2,3"
bitfld.word 0x06 3. "QPEN,Quadrature position counter enable/software reset" "0,1"
bitfld.word 0x06 2. "QCLM,QEP capture latch mode" "0,1"
newline
bitfld.word 0x06 1. "UTE,QEP unit timer enable" "0,1"
bitfld.word 0x06 0. "WDE,QEP watchdog enable" "0,1"
line.word 0x08 "REG_QCAPCTL,Qaudrature Capture Control"
bitfld.word 0x08 15. "CEN,Enable eQEP capture" "0,1"
bitfld.word 0x08 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7"
bitfld.word 0x08 0.--3. "UPPS,Unit position event prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x0A "REG_QPOSCTL,Position Compare Control"
bitfld.word 0x0A 15. "PCSHDW,Position compare of shadow enable" "0,1"
bitfld.word 0x0A 14. "PCLOAD,Position compare of shadow load" "0,1"
bitfld.word 0x0A 13. "PCPOL,Polarity of sync output" "0,1"
bitfld.word 0x0A 12. "PCE,Position compare enable/disable" "0,1"
hexmask.word 0x0A 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width"
line.word 0x0C "REG_QEINT_TYPE1,QEP Interrupt Control"
bitfld.word 0x0C 12. "QMAE,QMA Error Interrupt enable" "0,1"
bitfld.word 0x0C 11. "UTO,Unit time out interrupt enable" "0,1"
bitfld.word 0x0C 10. "IEL,Index event latch interrupt enable" "0,1"
bitfld.word 0x0C 9. "SEL,Strobe event latch interrupt enable" "0,1"
bitfld.word 0x0C 8. "PCM,Position-compare match interrupt enable" "0,1"
bitfld.word 0x0C 7. "PCR,Position-compare ready interrupt enable" "0,1"
bitfld.word 0x0C 6. "PCO,Position counter overflow interrupt enable" "0,1"
bitfld.word 0x0C 5. "PCU,Position counter underflow interrupt enable" "0,1"
bitfld.word 0x0C 4. "WTO,Watchdog time out interrupt enable" "0,1"
newline
bitfld.word 0x0C 3. "QDC,Quadrature direction change interrupt enable" "0,1"
bitfld.word 0x0C 2. "QPE,Quadrature phase error interrupt enable" "0,1"
bitfld.word 0x0C 1. "PCE,Position counter error interrupt enable" "0,1"
line.word 0x0E "REG_QFLG_TYPE1,QEP Interrupt Flag"
bitfld.word 0x0E 12. "QMAE,QMA Error interrupt flag" "0,1"
bitfld.word 0x0E 11. "UTO,Unit time out interrupt flag" "0,1"
bitfld.word 0x0E 10. "IEL,Index event latch interrupt flag" "0,1"
bitfld.word 0x0E 9. "SEL,Strobe event latch interrupt flag" "0,1"
bitfld.word 0x0E 8. "PCM,eQEP compare match event interrupt flag" "0,1"
bitfld.word 0x0E 7. "PCR,Position-compare ready interrupt flag" "0,1"
bitfld.word 0x0E 6. "PCO,Position counter overflow interrupt flag" "0,1"
bitfld.word 0x0E 5. "PCU,Position counter underflow interrupt flag" "0,1"
bitfld.word 0x0E 4. "WTO,Watchdog timeout interrupt flag" "0,1"
newline
bitfld.word 0x0E 3. "QDC,Quadrature direction change interrupt flag" "0,1"
bitfld.word 0x0E 2. "PHE,Quadrature phase error interrupt flag" "0,1"
bitfld.word 0x0E 1. "PCE,Position counter error interrupt flag" "0,1"
bitfld.word 0x0E 0. "INT,Global interrupt status flag" "0,1"
line.word 0x10 "REG_QCLR_TYPE1,QEP Interrupt Clear"
bitfld.word 0x10 12. "QMAE,Clear QMA Error interrupt flag" "0,1"
bitfld.word 0x10 11. "UTO,Clear unit time out interrupt flag" "0,1"
bitfld.word 0x10 10. "IEL,Clear index event latch interrupt flag" "0,1"
bitfld.word 0x10 9. "SEL,Clear strobe event latch interrupt flag" "0,1"
bitfld.word 0x10 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1"
bitfld.word 0x10 7. "PCR,Clear position-compare ready interrupt flag" "0,1"
bitfld.word 0x10 6. "PCO,Clear position counter overflow interrupt flag" "0,1"
bitfld.word 0x10 5. "PCU,Clear position counter underflow interrupt flag" "0,1"
bitfld.word 0x10 4. "WTO,Clear watchdog timeout interrupt flag" "0,1"
newline
bitfld.word 0x10 3. "QDC,Clear quadrature direction change interrupt flag" "0,1"
bitfld.word 0x10 2. "PHE,Clear quadrature phase error interrupt flag" "0,1"
bitfld.word 0x10 1. "PCE,Clear position counter error interrupt flag" "0,1"
bitfld.word 0x10 0. "INT,Global interrupt clear flag" "0,1"
line.word 0x12 "REG_QFRC_TYPE1,QEP Interrupt Force"
bitfld.word 0x12 12. "QMAE,Force QMA error interrupt" "0,1"
bitfld.word 0x12 11. "UTO,Force unit time out interrupt" "0,1"
bitfld.word 0x12 10. "IEL,Force index event latch interrupt" "0,1"
bitfld.word 0x12 9. "SEL,Force strobe event latch interrupt" "0,1"
bitfld.word 0x12 8. "PCM,Force position-compare match interrupt" "0,1"
bitfld.word 0x12 7. "PCR,Force position-compare ready interrupt" "0,1"
bitfld.word 0x12 6. "PCO,Force position counter overflow interrupt" "0,1"
bitfld.word 0x12 5. "PCU,Force position counter underflow interrupt" "0,1"
bitfld.word 0x12 4. "WTO,Force watchdog time out interrupt" "0,1"
newline
bitfld.word 0x12 3. "QDC,Force quadrature direction change interrupt" "0,1"
bitfld.word 0x12 2. "PHE,Force quadrature phase error interrupt" "0,1"
bitfld.word 0x12 1. "PCE,Force position counter error interrupt" "0,1"
line.word 0x14 "REG_QEPSTS_TYPE1,QEP Status"
bitfld.word 0x14 7. "UPEVNT,Unit position event flag" "0,1"
rbitfld.word 0x14 6. "FIDF,Direction on the first index markerStatus of the direction is latched on the first index event marker" "0,1"
rbitfld.word 0x14 5. "QDF,Quadrature direction flag" "0,1"
rbitfld.word 0x14 4. "QDLF,eQEP direction latch flag" "0,1"
bitfld.word 0x14 3. "COEF,Capture overflow error flag" "0,1"
bitfld.word 0x14 2. "CDEF,Capture direction error flag" "0,1"
bitfld.word 0x14 1. "FIMF,First index marker flag" "0,1"
rbitfld.word 0x14 0. "PCEF,Position counter error flag" "0,1"
line.word 0x16 "REG_QCTMR,QEP Capture Timer"
line.word 0x18 "REG_QCPRD,QEP Capture Period"
line.word 0x1A "REG_QCTMRLAT,QEP Capture Latch"
line.word 0x1C "REG_QCPRDLAT,QEP Capture Period Latch"
repeat 2. (list 1. 2. )(list 0x00 0x2E )
hgroup.word ($2+0x42)++0x01
hide.word 0x00 "REG_Reserved_$1,"
repeat.end
rgroup.long 0x60++0x0F
line.long 0x00 "REG_REV_TYPE2,QEP Revision Number"
bitfld.long 0x00 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP" "0,1,2,3,4,5,6,7"
line.long 0x04 "REG_QEPSTROBESEL,QEP Strobe select register"
bitfld.long 0x04 0.--1. "STROBESEL,Strobe source select" "0,1,2,3"
line.long 0x08 "REG_QMACTRL,QMA Control register"
bitfld.long 0x08 0.--2. "MODE,Select Mode for QMA mode:000 : QMA Module is bypassed" "0,1,2,3,4,5,6,7"
line.long 0x0C "REG_QEPSRCSEL,QEP Source Select Register"
bitfld.long 0x0C 12.--15. "QEPSSEL,QEP Strobe source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 8.--11. "QEPISEL,QEP Index source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 4.--7. "QEPBSEL,QEPB source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "QEPASEL,QEPA source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EQEP2_REG"
base ad:0x23220000
group.long 0x00++0x23
line.long 0x00 "REG_QPOSCNT,Position Counter"
line.long 0x04 "REG_QPOSINIT,Position Counter Init"
line.long 0x08 "REG_QPOSMAX,Maximum Position Count"
line.long 0x0C "REG_QPOSCMP,Position Compare"
line.long 0x10 "REG_QPOSILAT,Index Position Latch"
line.long 0x14 "REG_QPOSSLAT,Strobe Position Latch"
line.long 0x18 "REG_QPOSLAT,Position Latch"
line.long 0x1C "REG_QUTMR,QEP Unit Timer"
line.long 0x20 "REG_QUPRD,QEP Unit Period"
group.word 0x24++0x1D
line.word 0x00 "REG_QWDTMR,QEP Watchdog Timer"
line.word 0x02 "REG_QWDPRD,QEP Watchdog Period"
line.word 0x04 "REG_QDECCTL_TYPE2,Quadrature Decoder Control"
bitfld.word 0x04 14.--15. "QSRC,Position-counter source selection" "0,1,2,3"
bitfld.word 0x04 13. "SOEN,Sync output-enable" "0,1"
bitfld.word 0x04 12. "SPSEL,Sync output pin selection" "0,1"
bitfld.word 0x04 11. "XCR,External Clock Rate" "0,1"
bitfld.word 0x04 10. "SWAP,CLK/DIR Signal Source for Position Counter" "0,1"
bitfld.word 0x04 9. "IGATE,Index pulse gating option" "0,1"
bitfld.word 0x04 8. "QAP,QEPA input polarity" "0,1"
bitfld.word 0x04 7. "QBP,QEPB input polarity" "0,1"
bitfld.word 0x04 6. "QIP,QEPI input polarity" "0,1"
newline
bitfld.word 0x04 5. "QSP,QEPS input polarity" "0,1"
bitfld.word 0x04 0. "QIDIRE," "0,1"
line.word 0x06 "REG_QEPCTL,QEP Control"
bitfld.word 0x06 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
bitfld.word 0x06 12.--13. "PCRM,Postion counter reset" "0,1,2,3"
bitfld.word 0x06 10.--11. "SEI,Strobe event initialization of position counter" "0,1,2,3"
bitfld.word 0x06 8.--9. "IEI,Index event init of position count" "0,1,2,3"
bitfld.word 0x06 7. "SWI,Software init position counter" "0,1"
bitfld.word 0x06 6. "SEL,Strobe event latch of position counter" "0,1"
bitfld.word 0x06 4.--5. "IEL,Index event latch of position counter [software index marker]" "0,1,2,3"
bitfld.word 0x06 3. "QPEN,Quadrature position counter enable/software reset" "0,1"
bitfld.word 0x06 2. "QCLM,QEP capture latch mode" "0,1"
newline
bitfld.word 0x06 1. "UTE,QEP unit timer enable" "0,1"
bitfld.word 0x06 0. "WDE,QEP watchdog enable" "0,1"
line.word 0x08 "REG_QCAPCTL,Qaudrature Capture Control"
bitfld.word 0x08 15. "CEN,Enable eQEP capture" "0,1"
bitfld.word 0x08 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7"
bitfld.word 0x08 0.--3. "UPPS,Unit position event prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x0A "REG_QPOSCTL,Position Compare Control"
bitfld.word 0x0A 15. "PCSHDW,Position compare of shadow enable" "0,1"
bitfld.word 0x0A 14. "PCLOAD,Position compare of shadow load" "0,1"
bitfld.word 0x0A 13. "PCPOL,Polarity of sync output" "0,1"
bitfld.word 0x0A 12. "PCE,Position compare enable/disable" "0,1"
hexmask.word 0x0A 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width"
line.word 0x0C "REG_QEINT_TYPE1,QEP Interrupt Control"
bitfld.word 0x0C 12. "QMAE,QMA Error Interrupt enable" "0,1"
bitfld.word 0x0C 11. "UTO,Unit time out interrupt enable" "0,1"
bitfld.word 0x0C 10. "IEL,Index event latch interrupt enable" "0,1"
bitfld.word 0x0C 9. "SEL,Strobe event latch interrupt enable" "0,1"
bitfld.word 0x0C 8. "PCM,Position-compare match interrupt enable" "0,1"
bitfld.word 0x0C 7. "PCR,Position-compare ready interrupt enable" "0,1"
bitfld.word 0x0C 6. "PCO,Position counter overflow interrupt enable" "0,1"
bitfld.word 0x0C 5. "PCU,Position counter underflow interrupt enable" "0,1"
bitfld.word 0x0C 4. "WTO,Watchdog time out interrupt enable" "0,1"
newline
bitfld.word 0x0C 3. "QDC,Quadrature direction change interrupt enable" "0,1"
bitfld.word 0x0C 2. "QPE,Quadrature phase error interrupt enable" "0,1"
bitfld.word 0x0C 1. "PCE,Position counter error interrupt enable" "0,1"
line.word 0x0E "REG_QFLG_TYPE1,QEP Interrupt Flag"
bitfld.word 0x0E 12. "QMAE,QMA Error interrupt flag" "0,1"
bitfld.word 0x0E 11. "UTO,Unit time out interrupt flag" "0,1"
bitfld.word 0x0E 10. "IEL,Index event latch interrupt flag" "0,1"
bitfld.word 0x0E 9. "SEL,Strobe event latch interrupt flag" "0,1"
bitfld.word 0x0E 8. "PCM,eQEP compare match event interrupt flag" "0,1"
bitfld.word 0x0E 7. "PCR,Position-compare ready interrupt flag" "0,1"
bitfld.word 0x0E 6. "PCO,Position counter overflow interrupt flag" "0,1"
bitfld.word 0x0E 5. "PCU,Position counter underflow interrupt flag" "0,1"
bitfld.word 0x0E 4. "WTO,Watchdog timeout interrupt flag" "0,1"
newline
bitfld.word 0x0E 3. "QDC,Quadrature direction change interrupt flag" "0,1"
bitfld.word 0x0E 2. "PHE,Quadrature phase error interrupt flag" "0,1"
bitfld.word 0x0E 1. "PCE,Position counter error interrupt flag" "0,1"
bitfld.word 0x0E 0. "INT,Global interrupt status flag" "0,1"
line.word 0x10 "REG_QCLR_TYPE1,QEP Interrupt Clear"
bitfld.word 0x10 12. "QMAE,Clear QMA Error interrupt flag" "0,1"
bitfld.word 0x10 11. "UTO,Clear unit time out interrupt flag" "0,1"
bitfld.word 0x10 10. "IEL,Clear index event latch interrupt flag" "0,1"
bitfld.word 0x10 9. "SEL,Clear strobe event latch interrupt flag" "0,1"
bitfld.word 0x10 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1"
bitfld.word 0x10 7. "PCR,Clear position-compare ready interrupt flag" "0,1"
bitfld.word 0x10 6. "PCO,Clear position counter overflow interrupt flag" "0,1"
bitfld.word 0x10 5. "PCU,Clear position counter underflow interrupt flag" "0,1"
bitfld.word 0x10 4. "WTO,Clear watchdog timeout interrupt flag" "0,1"
newline
bitfld.word 0x10 3. "QDC,Clear quadrature direction change interrupt flag" "0,1"
bitfld.word 0x10 2. "PHE,Clear quadrature phase error interrupt flag" "0,1"
bitfld.word 0x10 1. "PCE,Clear position counter error interrupt flag" "0,1"
bitfld.word 0x10 0. "INT,Global interrupt clear flag" "0,1"
line.word 0x12 "REG_QFRC_TYPE1,QEP Interrupt Force"
bitfld.word 0x12 12. "QMAE,Force QMA error interrupt" "0,1"
bitfld.word 0x12 11. "UTO,Force unit time out interrupt" "0,1"
bitfld.word 0x12 10. "IEL,Force index event latch interrupt" "0,1"
bitfld.word 0x12 9. "SEL,Force strobe event latch interrupt" "0,1"
bitfld.word 0x12 8. "PCM,Force position-compare match interrupt" "0,1"
bitfld.word 0x12 7. "PCR,Force position-compare ready interrupt" "0,1"
bitfld.word 0x12 6. "PCO,Force position counter overflow interrupt" "0,1"
bitfld.word 0x12 5. "PCU,Force position counter underflow interrupt" "0,1"
bitfld.word 0x12 4. "WTO,Force watchdog time out interrupt" "0,1"
newline
bitfld.word 0x12 3. "QDC,Force quadrature direction change interrupt" "0,1"
bitfld.word 0x12 2. "PHE,Force quadrature phase error interrupt" "0,1"
bitfld.word 0x12 1. "PCE,Force position counter error interrupt" "0,1"
line.word 0x14 "REG_QEPSTS_TYPE1,QEP Status"
bitfld.word 0x14 7. "UPEVNT,Unit position event flag" "0,1"
rbitfld.word 0x14 6. "FIDF,Direction on the first index markerStatus of the direction is latched on the first index event marker" "0,1"
rbitfld.word 0x14 5. "QDF,Quadrature direction flag" "0,1"
rbitfld.word 0x14 4. "QDLF,eQEP direction latch flag" "0,1"
bitfld.word 0x14 3. "COEF,Capture overflow error flag" "0,1"
bitfld.word 0x14 2. "CDEF,Capture direction error flag" "0,1"
bitfld.word 0x14 1. "FIMF,First index marker flag" "0,1"
rbitfld.word 0x14 0. "PCEF,Position counter error flag" "0,1"
line.word 0x16 "REG_QCTMR,QEP Capture Timer"
line.word 0x18 "REG_QCPRD,QEP Capture Period"
line.word 0x1A "REG_QCTMRLAT,QEP Capture Latch"
line.word 0x1C "REG_QCPRDLAT,QEP Capture Period Latch"
repeat 2. (list 1. 2. )(list 0x00 0x2E )
hgroup.word ($2+0x42)++0x01
hide.word 0x00 "REG_Reserved_$1,"
repeat.end
rgroup.long 0x60++0x0F
line.long 0x00 "REG_REV_TYPE2,QEP Revision Number"
bitfld.long 0x00 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP" "0,1,2,3,4,5,6,7"
line.long 0x04 "REG_QEPSTROBESEL,QEP Strobe select register"
bitfld.long 0x04 0.--1. "STROBESEL,Strobe source select" "0,1,2,3"
line.long 0x08 "REG_QMACTRL,QMA Control register"
bitfld.long 0x08 0.--2. "MODE,Select Mode for QMA mode:000 : QMA Module is bypassed" "0,1,2,3,4,5,6,7"
line.long 0x0C "REG_QEPSRCSEL,QEP Source Select Register"
bitfld.long 0x0C 12.--15. "QEPSSEL,QEP Strobe source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 8.--11. "QEPISEL,QEP Index source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 4.--7. "QEPBSEL,QEPB source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "QEPASEL,QEPA source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "ESM0_CFG"
base ad:0x420000
rgroup.long 0x00++0x33
line.long 0x00 "CFG_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_INFO,The Info Register gives the configuration Inforrmation of this ESM"
bitfld.long 0x04 31. "LAST_RESET,Indicates the Source of the last Reset" "0,1"
hexmask.long.byte 0x04 8.--15. 1. "PULSE_GROUPS,Number of Pulse Error Groups"
hexmask.long.byte 0x04 0.--7. 1. "GROUPS,Total number of Error Groups"
line.long 0x08 "CFG_EN,The Global Enable Register has the master interrupt mask"
bitfld.long 0x08 0.--3. "KEY,Global Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CFG_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables"
bitfld.long 0x0C 0.--3. "KEY,Global Soft Reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CFG_ERR_RAW,Raw Status/Set Register for Configuration Errors"
bitfld.long 0x10 0.--5. "STS,This is the raw status for config errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "CFG_ERR_STS,Config Error Enable and Clear Register"
bitfld.long 0x14 0.--5. "MSK,This is the masked status/clear for config errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "CFG_ERR_EN_SET,Config Error Enable Set Register"
bitfld.long 0x18 0.--5. "MSK,This is the mask enable set for config errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "CFG_ERR_EN_CLR,Config Error Interrupt Enabled Clear register"
bitfld.long 0x1C 0.--5. "MSK,This is the mask enable clear for config errors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "CFG_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt"
hexmask.long.word 0x20 16.--31. 1. "PLS,This is the highest priority outstanding low priority pulse interrupt"
hexmask.long.word 0x20 0.--15. 1. "LVL,This is the highest priority outstanding low priority level interrupt"
line.long 0x24 "CFG_HI_PRI,Shows which is the highest priority outstanding high priority interrupt"
hexmask.long.word 0x24 16.--31. 1. "PLS,This is the highest priority outstanding high priority pulse interrupt"
hexmask.long.word 0x24 0.--15. 1. "LVL,This is the highest priority outstanding high priority level interrupt"
line.long 0x28 "CFG_LOW,Shows which groups have oustanding low priority interrupts"
line.long 0x2C "CFG_HI,Shows which groups have oustanding high priority interrupts"
line.long 0x30 "CFG_EOI,End of Interrupt Register"
hexmask.long.word 0x30 0.--10. 1. "KEY,This is the interrupt being serviced"
group.long 0x40++0x1F
line.long 0x00 "CFG_PIN_CTRL,This register controls the error_pin_n output"
bitfld.long 0x00 4.--7. "PWM_EN,PWM enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "KEY,Pin Control Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CFG_PIN_STS,This register reflects the status of the error_pin_n output"
bitfld.long 0x04 0. "VAL,Value of the error_pin_n" "0,1"
line.long 0x08 "CFG_PIN_CNTR,This register shows the current value of the error pin counter"
hexmask.long.tbyte 0x08 0.--23. 1. "COUNT,Current Counter Value"
line.long 0x0C "CFG_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter"
hexmask.long.tbyte 0x0C 0.--23. 1. "COUNT,Counter Pre-Load Value"
line.long 0x10 "CFG_PWMH_PIN_CNTR,This register shows the current value of the error pin PWM high counter"
hexmask.long.tbyte 0x10 0.--23. 1. "COUNT,Current Counter Value"
line.long 0x14 "CFG_PWMH_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM High Counter"
hexmask.long.tbyte 0x14 0.--23. 1. "COUNT,Counter Pre-Load Value"
line.long 0x18 "CFG_PWML_PIN_CNTR,This register shows the current value of the error pin PWM low counter"
hexmask.long.tbyte 0x18 0.--23. 1. "COUNT,Current Counter Value"
line.long 0x1C "CFG_PWML_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM Low Counter"
hexmask.long.tbyte 0x1C 0.--23. 1. "COUNT,Counter Pre-Load Value"
group.long 0x400++0x1B
line.long 0x00 "CFG_RAW,Raw Status/Set Register for Group A Errors"
line.long 0x04 "CFG_STS,Error Enable and Clear Register"
line.long 0x08 "CFG_INTR_EN_SET,Level Error Enable Set Register"
line.long 0x0C "CFG_INTR_EN_CLR,Level Error Interrupt Enabled Clear register"
line.long 0x10 "CFG_INT_PRIO,Level Error Interrupt Enabled Clear register"
line.long 0x14 "CFG_PIN_EN_SET,Level Error Interrupt Enabled Clear register"
line.long 0x18 "CFG_PIN_EN_CLR,Level Error Interrupt Enabled Clear register"
tree.end
tree "FSS0_CFG"
base ad:0xFC00000
rgroup.long 0x00++0x03
line.long 0x00 "FSS_MMR__FSS_MMR_CFG__FSS_GENREGS_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "FSS0_FSAS_0_DAT_REG0"
base ad:0x400000000
group.long 0x00++0x03
line.long 0x00 "DAT_REG0_hpb_data_mem,FSAS data region0"
tree.end
tree "FSS0_FSAS_0_DAT_REG1"
base ad:0x60000000
group.long 0x00++0x03
line.long 0x00 "DAT_REG1_hpb_data_mem,FSAS boot data region1"
tree.end
tree "FSS0_FSAS_0_DAT_REG3"
base ad:0x500000000
group.long 0x00++0x03
line.long 0x00 "DAT_REG3_hpb_data_mem,FSAS bypass data region3"
tree.end
tree "FSS0_FSAS_0_FSAS_CFG"
base ad:0xFC10000
rgroup.long 0x00++0x23
line.long 0x00 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_REVISION,IP Revision Identifier (X.Y.R) Used by software to track features. bugs. and compatibility"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID field"
bitfld.long 0x00 11.--15. "REVRTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_SYSCONFIG,Controls various parameters of the cotroller state"
bitfld.long 0x04 8. "OSPI_32B_DISABLE_MODE,0 OSPI 32bit mode enabled" "0,1"
bitfld.long 0x04 7. "DISXIP,0 XIP Prefetch Enabled" "0,1"
bitfld.long 0x04 6. "OSPI_DDR_DISABLE_MODE,0 OSPI DDR mode enabled" "0,1"
newline
bitfld.long 0x04 3. "ECC_DISABLE_ADR,0 Block address within ECC calculation 1 Block address not within ECC calculation" "0,1"
rbitfld.long 0x04 2. "FSS_AES_EN_IPCFG,1 select security 0 disable security" "0,1"
bitfld.long 0x04 0. "ECC_EN,0 ECC disabled" "0,1"
line.long 0x08 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_FRAG_ADR,This FRAG_ADR is the address of a request that frag_hi or frag_lo boundary occurs"
line.long 0x0C "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_FRAG_CTL,The FRAG_CTL determins which frag region is fragmented"
bitfld.long 0x0C 1. "FRAG_HI,When set any address greater than or equal to frag_addr will be fragmented to 16 bits" "0,1"
bitfld.long 0x0C 0. "FRAG_LO,When set any address less than frag_addr will be fragmented to 16 bits" "0,1"
line.long 0x10 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_EOI,The End of Interrupt (EOI) MISC Register allows the CPU to acknowledge completion of an interrupt by writing to the EOI for MISC interrupt sources"
bitfld.long 0x10 0. "EOI_VECTOR,Write with bit position of targeted interrupt" "0,1"
line.long 0x14 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_STATUS_RAW,The IRQ_STATUS_RAW register allows the interrupt sources to be manually set when writing a 1 to a specific bit"
bitfld.long 0x14 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1"
bitfld.long 0x14 1. "ECC_ERROR_2BIT,ECC error on 2 bits" "0,1"
bitfld.long 0x14 0. "ECC_ERROR_1BIT,ECC error on 1 bits" "0,1"
line.long 0x18 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_STATUS,The IRQ_STATUS register allows the interrupt sources to be manually cleared when writing a 1 to a specific bit"
bitfld.long 0x18 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1"
bitfld.long 0x18 1. "ECC_ERROR_2BIT,ECC error on 2 bits" "0,1"
bitfld.long 0x18 0. "ECC_ERROR_1BIT,ECC error on 1 bits" "0,1"
line.long 0x1C "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ENABLE_SET,The IRQ_ENABLE_SET register allows the interrupt sources to be manually enabled when writing a 1 to a specific bit"
bitfld.long 0x1C 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1"
bitfld.long 0x1C 1. "ECC_ERROR_2BIT,ECC error on 2 bits" "0,1"
bitfld.long 0x1C 0. "ECC_ERROR_1BIT,ECC error on 1 bits" "0,1"
line.long 0x20 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ENABLE_CLR,The IRQ_ENABLE_CLR register allows the interrupt sources to be manually disabled when writing a 1 to a specific bit"
bitfld.long 0x20 2. "ECC_WRITE_NONALIGN,Write is not aligned to 32B boundary or not a multiple of 32B" "0,1"
bitfld.long 0x20 1. "ECC_ERROR_2BIT,ECC error on 2 bits" "0,1"
bitfld.long 0x20 0. "ECC_ERROR_1BIT,ECC error on 1 bits" "0,1"
group.long 0x30++0x07
line.long 0x00 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_RGSTRT,This defines the start of the ECC region in 4KBytes steps"
hexmask.long.tbyte 0x00 0.--19. 1. "R_START,This defines the start of the ECC region in 4KBytes steps"
line.long 0x04 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_RGSIZ,This defines the size of the ECC region in 4KBytes steps"
hexmask.long.tbyte 0x04 0.--19. 1. "R_SIZE,This defines the size of the ECC region in 4KBytes steps 0x0 means the size is zero and disabled 0x1 means the size is 4KBytes 0xA means the size is 40KBytes 0xF_FFFF means the size is 4GBytes Note the offset + size should be <= 4GBytes wrap.."
rgroup.long 0x70++0x0B
line.long 0x00 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_BLOCK_ADR,The ERR_ECC_BLOCK_ADR register holds the current top of stack ECC error block address. this is only valid when the ecc_err_valid is set"
hexmask.long 0x00 5.--31. 1. "ECC_ERROR_BLOCK_ADDR,ECC 32 byte aligned block address"
line.long 0x04 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_ECC_TYPE,The ERR_ECC_TYPE register holds the current top of stack ECC error info. this is only valid when the ecc_err_valid is set"
bitfld.long 0x04 31. "ECC_ERR_VALID,When set indicates that there is valid ECC error information available Writing a one to this register will pop the top of the stack" "0,1"
rbitfld.long 0x04 5. "ECC_ERR_ADR,When set indicates that there was a single error detected within the address field" "0,1"
rbitfld.long 0x04 4. "ECC_ERR_MAC,When set indicates that there was a single error detected within the MAC field" "0,1"
newline
rbitfld.long 0x04 3. "ECC_ERR_DA1,When set indicates that there was a single error detected within the High Data word" "0,1"
rbitfld.long 0x04 2. "ECC_ERR_DA0,When set indicates that there was a single error detected within the Low Data word" "0,1"
rbitfld.long 0x04 1. "ECC_ERR_DED,When set indicates that there was a double error detected for the block" "0,1"
newline
rbitfld.long 0x04 0. "ECC_ERR_SEC,hen set indicates that there was a single error detected for the block" "0,1"
line.long 0x08 "FSAS__FSAS_MMR_CFG__FSAS_GENREGS_WRT_TYPE,The ERR_WRT_TYPE register holds the current top of stack write error info"
bitfld.long 0x08 31. "WRT_ERR_VALID,When set indicates that there is valid write error information available Writing a one to this register will pop the top of the stack" "0,1"
rbitfld.long 0x08 13. "WRT_ERR_BEN,When set indicates that there was a write error due to a non-contiguous byte enables" "0,1"
rbitfld.long 0x08 12. "WRT_ERR_ADR,When set indicates that there was a write error due to a non-aligned address" "0,1"
newline
hexmask.long.word 0x08 0.--11. 1. "WRT_ERR_ROUTEID,Indicates the Route ID for the Master that caused the write error"
tree.end
tree "FSS0_FSAS_0_OTFA_CFG"
base ad:0xFC20000
rgroup.long 0x00++0x1F
line.long 0x00 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_revid,"
line.long 0x04 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_scfg,"
bitfld.long 0x04 0.--1. "IDLE_MODE,IDLE MODE" "0,1,2,3"
line.long 0x08 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_isr,"
bitfld.long 0x08 12.--15. "MAC_ERR,MAC error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 8.--11. "WRT_ERR,Write error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 4.--7. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0.--3. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_is,"
bitfld.long 0x0C 12.--15. "MAC_ERR,MAC error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 8.--11. "WRT_ERR,Write error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 4.--7. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0.--3. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_ies,"
bitfld.long 0x10 12.--15. "MAC_ERR,MAC error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 8.--11. "WRT_ERR,Write error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 4.--7. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 0.--3. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_iec,"
bitfld.long 0x14 12.--15. "MAC_ERR,MAC error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 8.--11. "WRT_ERR,Write error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 4.--7. "REGION_BV,Region overflow boundary event caused by a burst transaction crossed a start or end of a region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 0.--3. "CTR_WKV,AES mode 0 enabled region violated Wrt Once Per Wrt Key rule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_ccfg,"
bitfld.long 0x18 31. "MASTER_EN_RD,This register controls the enabling the functionality of this IP Disabled and Bypass mode active" "0,1"
bitfld.long 0x18 9. "ERROR_RESP_EN,This register controls the enabling the the ocp error response for mac errors" "0,1"
bitfld.long 0x18 8. "OTFA_WAIT,This register allows the ability to stop accepting any new transactions from getting accepted and allow the current transactions to complete" "0,1"
newline
bitfld.long 0x18 6. "CACHE_ENABLE,MAC cache enable" "0,1"
bitfld.long 0x18 5. "CACHE_EVICT_MODE,cache evict mode" "0,1"
bitfld.long 0x18 4. "KEY_SIZE,Key Size 0 128 Bit 1 256 Bit" "0,1"
newline
bitfld.long 0x18 0.--3. "RD_WRT_OPT,This register defines the static allocation of the AES cores to read transactions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_cstatus,"
rbitfld.long 0x1C 31. "BUSY,0 No transactions are active crypto or none crypto 1 One or more transactions are active crypto or none crypto" "0,1"
rbitfld.long 0x1C 30. "CRYPTO_BUSY,0 No transactions are active crypto or none crypto 1 One or more transactions are active crypto or none crypto" "0,1"
hexmask.long.word 0x1C 16.--29. 1. "RD_STALL_EVENT_CNT,rd stall event do to lack of eng"
newline
hexmask.long.word 0x1C 0.--13. 1. "WRT_STALL_EVENT_CNT,wrt stall event do to lack of eng"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x80 0x100 0x180 )
group.long ($2+0x20)++0x03
line.long 0x00 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgcfg$1,"
bitfld.long 0x00 4. "WRT_PROTECT0,WRT protect" "0,1"
bitfld.long 0x00 2.--3. "MAC_MODE0,MAC mode" "0,1,2,3"
bitfld.long 0x00 0.--1. "AES_MODE0,AES mode" "0,1,2,3"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x80 0x100 0x180 )
group.long ($2+0x24)++0x03
line.long 0x00 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgmacst$1,"
hexmask.long.tbyte 0x00 0.--19. 1. "M_START0,This defines the start of the mac buffer in 4KBytes steps"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x80 0x100 0x180 )
group.long ($2+0x28)++0x03
line.long 0x00 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgst$1,"
hexmask.long.tbyte 0x00 0.--19. 1. "R_START0,This defines the start of the crypto region in 4KBytes steps"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x80 0x100 0x180 )
group.long ($2+0x2C)++0x03
line.long 0x00 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rgsi$1,"
hexmask.long.tbyte 0x00 0.--19. 1. "R_SIZE0,This defines the size of the crypto region in 4KBytes steps"
repeat.end
repeat 16. (list 00. 01. 02. 03. 04. 05. 06. 07. 10. 11. 12. 13. 14. 15. 16. 17. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C )
group.long ($2+0x30)++0x03
line.long 0x00 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye$1,"
repeat.end
repeat 16. (list 00. 01. 02. 03. 04. 05. 06. 07. 10. 11. 12. 13. 14. 15. 16. 17. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C )
group.long ($2+0x50)++0x03
line.long 0x00 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep$1,"
repeat.end
repeat 16. (list 00. 01. 02. 03. 10. 11. 12. 13. 20. 21. 22. 23. 30. 31. 32. 33. )(list 0x00 0x04 0x08 0x0C 0x80 0x84 0x88 0x8C 0x100 0x104 0x108 0x10C 0x180 0x184 0x188 0x18C )
group.long ($2+0x70)++0x03
line.long 0x00 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeya$1,"
repeat.end
repeat 16. (list 00. 01. 02. 03. 10. 11. 12. 13. 20. 21. 22. 23. 30. 31. 32. 33. )(list 0x00 0x04 0x08 0x0C 0x80 0x84 0x88 0x8C 0x100 0x104 0x108 0x10C 0x180 0x184 0x188 0x18C )
group.long ($2+0x80)++0x03
line.long 0x00 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyap$1,"
repeat.end
repeat 16. (list 00. 01. 02. 03. 10. 11. 12. 13. 20. 21. 22. 23. 30. 31. 32. 33. )(list 0x00 0x04 0x08 0x0C 0x80 0x84 0x88 0x8C 0x100 0x104 0x108 0x10C 0x180 0x184 0x188 0x18C )
group.long ($2+0x90)++0x03
line.long 0x00 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_riv$1,"
repeat.end
repeat 16. (list 20. 21. 22. 23. 24. 25. 26. 27. 30. 31. 32. 33. 34. 35. 36. 37. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C )
group.long ($2+0x130)++0x03
line.long 0x00 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeye$1,"
repeat.end
repeat 16. (list 20. 21. 22. 23. 24. 25. 26. 27. 30. 31. 32. 33. 34. 35. 36. 37. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C )
group.long ($2+0x150)++0x03
line.long 0x00 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rkeyep$1,"
repeat.end
rgroup.long 0x220++0x0F
line.long 0x00 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_irqaddinfo0,"
line.long 0x04 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_irqaddinfo1,"
bitfld.long 0x04 14.--17. "IRQ_MLEN,Master LENGTH which caused the event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11.--13. "IRQ_MSEQ,Master SEQ which caused the event" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 8.--10. "IRQ_MCMD,Master CMD which caused the event" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x04 0.--7. 1. "IRQ_MID,Master TAG ID which caused the event"
line.long 0x08 "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_maccacheinfo,"
hexmask.long.word 0x08 0.--15. 1. "CACHE_MISS_EVENT_CNT,MAC Cache Miss event cnt"
line.long 0x0C "FSAS__FSAS_OTFA_CFG__FSAS_OTFA_REGS_rmwrmcnt,"
hexmask.long.word 0x0C 16.--31. 1. "RM_EVENT_CNT,RM event cnt"
hexmask.long.word 0x0C 0.--15. 1. "RMW_EVENT_CNT,RMW event cnt"
tree.end
tree "FSS0_OSPI_0_OSPI0_CTRL"
base ad:0xFC40000
group.long 0x00++0x47
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_config_reg,Octal-SPI Configuration Register"
rbitfld.long 0x00 31. "IDLE_FLD,Serial interface and low level SPI pipeline is IDLE: This is a STATUS read-only bit" "0,1"
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bitfld.long 0x00 30. "DUAL_BYTE_OPCODE_EN_FLD,Dual-byte Opcode Mode enable bit This bit is to be set in case the target Flash Device supports dual byte opcode [i.e. Macronix MX25]" "0,1"
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bitfld.long 0x00 29. "CRC_ENABLE_FLD,CRC enable bit This bit is to be set in case the target Flash Device supports CRC [Macronix MX25]" "0,1"
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bitfld.long 0x00 25. "PIPELINE_PHY_FLD,Pipeline PHY Mode enable: This bit is relevant only for configuration with PHY Module" "0,1"
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bitfld.long 0x00 24. "ENABLE_DTR_PROTOCOL_FLD,Enable DTR Protocol: This bit should be set if device is configured to work in DTR protocol" "0,1"
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bitfld.long 0x00 23. "ENABLE_AHB_DECODER_FLD,Enable AHB Decoder: Value=0 : Active slave is selected based on Peripheral Chip Select Lines [bits [13:10]]" "0,1"
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bitfld.long 0x00 19.--22. "MSTR_BAUD_DIV_FLD,Master Mode Baud Rate Divisor: SPI baud rate = [master reference clock] baud_rate_divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 18. "ENTER_XIP_MODE_IMM_FLD,Enter XIP Mode immediately: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction" "0,1"
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bitfld.long 0x00 17. "ENTER_XIP_MODE_FLD,Enter XIP Mode on next READ: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction" "0,1"
newline
bitfld.long 0x00 16. "ENB_AHB_ADDR_REMAP_FLD,Enable AHB Address Re-mapping: [Direct Access Mode Only] When set to 1 the incoming AHB address will be adapted and sent to the FLASH device as [address + N] where N is the value stored in the remap address register" "0,1"
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bitfld.long 0x00 15. "ENB_DMA_IF_FLD,Enable DMA Peripheral Interface: Set to 1 to enable the DMA handshaking logic" "0,1"
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bitfld.long 0x00 14. "WR_PROT_FLASH_FLD,Write Protect Flash Pin: Set to drive the Write Protect pin of the FLASH device" "0,1"
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bitfld.long 0x00 10.--13. "PERIPH_CS_LINES_FLD,Peripheral Chip Select Lines: Peripheral chip select lines If pdec = 0 ss[3:0] are output thus: ss[3:0] n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 [no peripheral selected] else ss[3:0] directly drives n_ss_out[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 9. "PERIPH_SEL_DEC_FLD,Peripheral select decode" "only 1 of 4 selects n_ss_out[3:0] is active,allow external 4-to-16 decode [n_ss_out = ss]"
newline
bitfld.long 0x00 8. "ENB_LEGACY_IP_MODE_FLD,Legacy IP Mode Enable" "Use Direct Access Controller/Indirect Access..,legacy Mode is enabled"
newline
bitfld.long 0x00 7. "ENB_DIR_ACC_CTLR_FLD,Enable Direct Access Controller" "disable the Direct Access Controller once..,enable the Direct Access Controller When the.."
newline
bitfld.long 0x00 6. "RESET_CFG_FLD,RESET pin configuration" "RESET feature on DQ3 pin of the device,RESET feature on dedicated pin of the device.."
newline
bitfld.long 0x00 5. "RESET_PIN_FLD,Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature" "0,1"
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bitfld.long 0x00 4. "HOLD_PIN_FLD,Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature" "0,1"
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bitfld.long 0x00 3. "PHY_MODE_ENABLE_FLD,PHY mode enable: When enabled the controller is informed that PHY Module is to be used for handling SPI transfers" "0,1"
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bitfld.long 0x00 2. "SEL_CLK_PHASE_FLD,Select Clock Phase: Selects whether the clock is in an active or inactive phase outside the SPI word" "the SPI clock is active outside the word,the SPI clock is inactive outside the word"
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bitfld.long 0x00 1. "SEL_CLK_POL_FLD,Clock polarity outside SPI word" "the SPI clock is quiescent low,the SPI clock is quiescent high"
newline
bitfld.long 0x00 0. "ENB_SPI_FLD,Octal-SPI Enable" "disable the Octal-SPI once current transfer of..,enable the Octal-SPI when spi_enable = 0 all.."
line.long 0x04 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_rd_config_reg,Device Read Instruction Configuration Register"
bitfld.long 0x04 24.--28. "DUMMY_RD_CLK_CYCLES_FLD,Dummy Read Clock Cycles: Number of dummy clock cycles required by device for read instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 20. "MODE_BIT_ENABLE_FLD,Mode Bit Enable: Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes" "0,1"
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bitfld.long 0x04 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes" "SIO mode data is shifted to the device on DQ0..,Used for Dual Input/Output instructions,Used for Quad Input/Output instructions,Used for Quad Input/Output instructions"
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bitfld.long 0x04 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes" "Addresses can be shifted to the device on DQ0 only,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ[7:0]"
newline
bitfld.long 0x04 10. "DDR_EN_FLD,DDR Enable: This is to inform that opcode from rd_opcode_non_xip_fld is compliant with one of the DDR READ Commands" "0,1"
newline
bitfld.long 0x04 8.--9. "INSTR_TYPE_FLD,Instruction Type" "Use Standard SPI mode [instruction always..,Use DIO-SPI mode [Instructions Address and Data..,Use QIO-SPI mode [Instructions Address and Data..,Use Octal-IO-SPI mode [Instructions Address and.."
newline
hexmask.long.byte 0x04 0.--7. 1. "RD_OPCODE_NON_XIP_FLD,Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode"
line.long 0x08 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_instr_wr_config_reg,Device Write Instruction Configuration Register"
bitfld.long 0x08 24.--28. "DUMMY_WR_CLK_CYCLES_FLD,Dummy Write Clock Cycles: Number of dummy clock cycles required by device for write instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes" "SIO mode data is shifted to the device on DQ0..,Used for Dual Input/Output instructions,Used for Quad Input/Output instructions,Used for Quad Input/Output instructions"
newline
bitfld.long 0x08 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes" "Addresses can be shifted to the device on DQ0 only,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ[7:0]"
newline
bitfld.long 0x08 8. "WEL_DIS_FLD,WEL Disable: This is to turn off automatic issuing of WEL Command before write operation for DAC or INDAC" "0,1"
newline
hexmask.long.byte 0x08 0.--7. 1. "WR_OPCODE_FLD,Write Opcode"
line.long 0x0C "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_delay_reg,Octal-SPI Device Delay Register: This register is used to introduce relative delays into the generation of the master output signals"
hexmask.long.byte 0x0C 24.--31. 1. "D_NSS_FLD,Clock Delay for Chip Select Deassert: Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions"
newline
hexmask.long.byte 0x0C 16.--23. 1. "D_BTWN_FLD,Clock Delay for Chip Select Deactivation: Delay in master reference clocks between one chip select being de-activated and the activation of another"
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hexmask.long.byte 0x0C 8.--15. 1. "D_AFTER_FLD,Clock Delay for Last Transaction Bit: Delay in master reference clocks between last bit of current transaction and deasserting the device chip select [n_ss_out]"
newline
hexmask.long.byte 0x0C 0.--7. 1. "D_INIT_FLD,Clock Delay with n_ss_out: Delay in master reference clocks between setting n_ss_out low and first bit transfer"
line.long 0x10 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_rd_data_capture_reg,Read Data Capture Register"
bitfld.long 0x10 16.--19. "DDR_READ_DELAY_FLD,DDR read delay: Delay the transmitted data by the programmed number of ref_clk cycles.This field is only relevant when DDR Read Command is executed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 8. "DQS_ENABLE_FLD,DQS enable bit: If enabled signal from DQS input is driven into RX DLL and is used for data capturing in PHY Mode rather than internally generated gated ref_clk" "0,1"
newline
bitfld.long 0x10 5. "SAMPLE_EDGE_SEL_FLD,Sample edge selection: Choose edge on which data outputs from flash memory will be sampled" "0,1"
newline
bitfld.long 0x10 1.--4. "DELAY_FLD,Read Delay: Delay the read data capturing logic by the programmed number of ref_clk cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 0. "BYPASS_FLD,Bypass the adapted loopback clock circuit" "0,1"
line.long 0x14 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dev_size_config_reg,Device Size Configuration Register"
bitfld.long 0x14 27.--28. "MEM_SIZE_ON_CS3_FLD,Size of Flash Device connected to CS[3] pin: Value=00 : size of 512Mb" "0,1,2,3"
newline
bitfld.long 0x14 25.--26. "MEM_SIZE_ON_CS2_FLD,Size of Flash Device connected to CS[2] pin: Value=00 : size of 512Mb" "0,1,2,3"
newline
bitfld.long 0x14 23.--24. "MEM_SIZE_ON_CS1_FLD,Size of Flash Device connected to CS[1] pin: Value=00 : size of 512Mb" "0,1,2,3"
newline
bitfld.long 0x14 21.--22. "MEM_SIZE_ON_CS0_FLD,Size of Flash Device connected to CS[0] pin: Value=00 : size of 512Mb" "0,1,2,3"
newline
bitfld.long 0x14 16.--20. "BYTES_PER_SUBSECTOR_FLD,Number of bytes per Block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x14 4.--15. 1. "BYTES_PER_DEVICE_PAGE_FLD,Number of bytes per device page"
newline
bitfld.long 0x14 0.--3. "NUM_ADDR_BYTES_FLD,Number of address bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_sram_partition_cfg_reg,SRAM Partition Configuration Register"
hexmask.long.byte 0x18 0.--7. 1. "ADDR_FLD,Indirect Read Partition Size: Defines the size of the indirect read partition in the SRAM in units of SRAM locations"
line.long 0x1C "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_ind_AHB_addr_trigger_reg,Indirect AHB Address Trigger Register"
line.long 0x20 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dma_periph_config_reg,DMA Peripheral Configuration Register"
bitfld.long 0x20 8.--11. "NUM_BURST_REQ_BYTES_FLD,Number of Burst Bytes: Number of bytes in a burst type request on the DMA peripheral request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 0.--3. "NUM_SINGLE_REQ_BYTES_FLD,Number of Single Bytes: Number of bytes in a single type request on the DMA peripheral request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_remap_addr_reg,Remap Address Register"
line.long 0x28 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_mode_bit_config_reg,Mode Bit Configuration Register"
hexmask.long.byte 0x28 24.--31. 1. "RX_CRC_DATA_LOW_FLD,RX CRC data [lower] The first CRC byte returned after RX data chunk"
newline
hexmask.long.byte 0x28 16.--23. 1. "RX_CRC_DATA_UP_FLD,RX CRC data [upper] The second CRC byte returned after RX data chunk"
newline
bitfld.long 0x28 15. "CRC_OUT_ENABLE_FLD,CRC# output enable bit When enabled the controller expects the Flash Device to toggle CRC data on both SPI clock edges in CRC->CRC# sequence and calculates CRC compliance accordingly" "0,1"
newline
bitfld.long 0x28 8.--10. "CHUNK_SIZE_FLD,It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x28 0.--7. 1. "MODE_FLD,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled"
line.long 0x2C "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_sram_fill_reg,SRAM Fill Register"
hexmask.long.word 0x2C 16.--31. 1. "SRAM_FILL_INDAC_WRITE_FLD,SRAM Fill Level [Indirect Write Partition]: Identifies the current fill level of the SRAM Indirect Write partition"
newline
hexmask.long.word 0x2C 0.--15. 1. "SRAM_FILL_INDAC_READ_FLD,SRAM Fill Level [Indirect Read Partition]: Identifies the current fill level of the SRAM Indirect Read partition"
line.long 0x30 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_tx_thresh_reg,TX Threshold Register"
bitfld.long 0x30 0.--4. "LEVEL_FLD,Defines the level at which the small TX FIFO not full interrupt is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_rx_thresh_reg,RX Threshold Register"
bitfld.long 0x34 0.--4. "LEVEL_FLD,Defines the level at which the small RX FIFO not empty interrupt is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x38 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_write_completion_ctrl_reg,Write Completion Control Register: This register defines how the controller will poll the device following a write transfer"
hexmask.long.byte 0x38 24.--31. 1. "POLL_REP_DELAY_FLD,Defines additional delay for maintain Chip Select de-asserted during auto-polling phase"
newline
hexmask.long.byte 0x38 16.--23. 1. "POLL_COUNT_FLD,Defines the number of times the controller should expect to see a true result from the polling in successive reads of the device register"
newline
bitfld.long 0x38 15. "ENABLE_POLLING_EXP_FLD,Set to '1' for enabling auto-polling expiration" "0,1"
newline
bitfld.long 0x38 14. "DISABLE_POLLING_FLD,This switches off the automatic polling function" "0,1"
newline
bitfld.long 0x38 13. "POLLING_POLARITY_FLD,Defines the polling polarity" "0,1"
newline
bitfld.long 0x38 8.--10. "POLLING_BIT_INDEX_FLD,Defines the bit index that should be polled" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x38 0.--7. 1. "OPCODE_FLD,Defines the opcode that should be issued by the controller when it is automatically polling for device program completion"
line.long 0x3C "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_no_of_polls_bef_exp_reg,Polling Expiration Register"
line.long 0x40 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_irq_status_reg,Interrupt Status Register: The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register"
bitfld.long 0x40 19. "ECC_FAIL_FLD,ECC failure This interrupt informs the system that Flash Device reported ECC error" "0,1"
newline
bitfld.long 0x40 18. "TX_CRC_CHUNK_BRK_FLD,TX CRC chunk was broken This interrupt informs the system that program page SPI transfer was discontinued somewhere inside the chunk" "0,1"
newline
bitfld.long 0x40 17. "RX_CRC_DATA_VAL_FLD,RX CRC data valid New RX CRC data was captured from Flash Device" "0,1"
newline
bitfld.long 0x40 16. "RX_CRC_DATA_ERR_FLD,RX CRC data error CRC data from Flash Device does not correspond to the one dynamically calculated by the controller" "0,1"
newline
bitfld.long 0x40 14. "STIG_REQ_INT_FLD,The controller is ready for getting another STIG request" "0,1"
newline
bitfld.long 0x40 13. "POLL_EXP_INT_FLD,The maximum number of programmed polls cycles is expired" "0,1"
newline
bitfld.long 0x40 12. "INDRD_SRAM_FULL_FLD,Indirect Read Partition overflow: Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation" "0,1"
newline
bitfld.long 0x40 11. "RX_FIFO_FULL_FLD,Small RX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode" "FIFO is not full,FIFO is full"
newline
bitfld.long 0x40 10. "RX_FIFO_NOT_EMPTY_FLD,Small RX FIFO not empty: Current FIFO status can be ignored in non-SPI legacy mode" "FIFO has less than RX THRESHOLD entries,FIFO has >= THRESHOLD entries"
newline
bitfld.long 0x40 9. "TX_FIFO_FULL_FLD,Small TX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode" "FIFO is not full,FIFO is full"
newline
bitfld.long 0x40 8. "TX_FIFO_NOT_FULL_FLD,Small TX FIFO not full: Current FIFO status can be ignored in non-SPI legacy mode" "FIFO has >= THRESHOLD entries,FIFO has less than THRESHOLD entries"
newline
bitfld.long 0x40 7. "RECV_OVERFLOW_FLD,Receive Overflow: This should only occur in Legacy SPI mode" "no overflow has been detected,an overflow has occurred"
newline
bitfld.long 0x40 6. "INDIRECT_XFER_LEVEL_BREACH_FLD,Indirect Transfer Watermark Level Breached" "0,1"
newline
bitfld.long 0x40 5. "ILLEGAL_ACCESS_DET_FLD,Illegal AHB access has been detected" "0,1"
newline
bitfld.long 0x40 4. "PROT_WR_ATTEMPT_FLD,Write to protected area was attempted and rejected" "0,1"
newline
bitfld.long 0x40 3. "INDIRECT_READ_REJECT_FLD,Indirect operation was requested but could not be accepted" "0,1"
newline
bitfld.long 0x40 2. "INDIRECT_OP_DONE_FLD,Indirect Operation Complete: Controller has completed last triggered indirect operation" "0,1"
newline
bitfld.long 0x40 1. "UNDERFLOW_DET_FLD,Underflow Detected" "no underflow has been detected,underflow is detected and an attempt to transfer.."
newline
bitfld.long 0x40 0. "MODE_M_FAIL_FLD,Mode M Failure: Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode" "no mode fault has been detected,a mode fault has occurred"
line.long 0x44 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_irq_mask_reg,Interrupt Mask"
bitfld.long 0x44 19. "ECC_FAIL_MASK_FLD,ECC failure Mask" "0,1"
newline
bitfld.long 0x44 18. "TX_CRC_CHUNK_BRK_MASK_FLD,TX CRC chunk was broken Mask" "0,1"
newline
bitfld.long 0x44 17. "RX_CRC_DATA_VAL_MASK_FLD,RX CRC data valid Mask" "0,1"
newline
bitfld.long 0x44 16. "RX_CRC_DATA_ERR_MASK_FLD,RX CRC data error Mask" "0,1"
newline
bitfld.long 0x44 14. "STIG_REQ_MASK_FLD,STIG request completion Mask" "0,1"
newline
bitfld.long 0x44 13. "POLL_EXP_INT_MASK_FLD,Polling expiration detected Mask" "0,1"
newline
bitfld.long 0x44 12. "INDRD_SRAM_FULL_MASK_FLD,Indirect Read Partition overflow mask" "0,1"
newline
bitfld.long 0x44 11. "RX_FIFO_FULL_MASK_FLD,Small RX FIFO full Mask" "0,1"
newline
bitfld.long 0x44 10. "RX_FIFO_NOT_EMPTY_MASK_FLD,Small RX FIFO not empty Mask" "0,1"
newline
bitfld.long 0x44 9. "TX_FIFO_FULL_MASK_FLD,Small TX FIFO full Mask" "0,1"
newline
bitfld.long 0x44 8. "TX_FIFO_NOT_FULL_MASK_FLD,Small TX FIFO not full Mask" "0,1"
newline
bitfld.long 0x44 7. "RECV_OVERFLOW_MASK_FLD,Receive Overflow Mask" "0,1"
newline
bitfld.long 0x44 6. "INDIRECT_XFER_LEVEL_BREACH_MASK_FLD,Transfer Watermark Breach Mask" "0,1"
newline
bitfld.long 0x44 5. "ILLEGAL_ACCESS_DET_MASK_FLD,Illegal Access Detected Mask" "0,1"
newline
bitfld.long 0x44 4. "PROT_WR_ATTEMPT_MASK_FLD,Protected Area Write Attempt Mask" "0,1"
newline
bitfld.long 0x44 3. "INDIRECT_READ_REJECT_MASK_FLD,Indirect Read Reject Mask" "0,1"
newline
bitfld.long 0x44 2. "INDIRECT_OP_DONE_MASK_FLD,Indirect Complete Mask" "0,1"
newline
bitfld.long 0x44 1. "UNDERFLOW_DET_MASK_FLD,Underflow Detected Mask" "0,1"
newline
bitfld.long 0x44 0. "MODE_M_FAIL_MASK_FLD,Mode M Failure Mask" "0,1"
group.long 0x50++0x0B
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_lower_wr_prot_reg,Lower Write Protection Register"
line.long 0x04 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_upper_wr_prot_reg,Upper Write Protection Register"
line.long 0x08 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_wr_prot_ctrl_reg,Write Protection Control Register"
bitfld.long 0x08 1. "ENB_FLD,Write Protection Enable Bit: When set to 1 any AHB write access with an address within the protection region defined in the lower and upper write protection registers is rejected" "0,1"
newline
bitfld.long 0x08 0. "INV_FLD,Write Protection Inversion Bit: When set to 1 the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to" "0,1"
group.long 0x60++0x23
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_ctrl_reg,Indirect Read Transfer Control Register"
rbitfld.long 0x00 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed" "0,1,2,3"
newline
bitfld.long 0x00 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed" "0,1"
newline
rbitfld.long 0x00 4. "RD_QUEUED_FLD,Two indirect read operations have been queued" "0,1"
newline
bitfld.long 0x00 3. "SRAM_FULL_FLD,SRAM Full: SRAM full and unable to immediately complete an indirect operation" "0,1"
newline
rbitfld.long 0x00 2. "RD_STATUS_FLD,Indirect Read Status: Indirect read operation in progress [status]" "0,1"
newline
bitfld.long 0x00 1. "CANCEL_FLD,Cancel Indirect Read: Writing a 1 to this bit will cancel all ongoing indirect read operations" "0,1"
newline
bitfld.long 0x00 0. "START_FLD,Start Indirect Read: Writing a 1 to this bit will trigger an indirect read operation" "0,1"
line.long 0x04 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_watermark_reg,Indirect Read Transfer Watermark Register"
line.long 0x08 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_start_reg,Indirect Read Transfer Start Address Register"
line.long 0x0C "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_read_xfer_num_bytes_reg,Indirect Read Transfer Number Bytes Register"
line.long 0x10 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_ctrl_reg,Indirect Write Transfer Control Register"
rbitfld.long 0x10 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed" "0,1,2,3"
newline
bitfld.long 0x10 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed" "0,1"
newline
rbitfld.long 0x10 4. "WR_QUEUED_FLD,Two indirect write operations have been queued" "0,1"
newline
rbitfld.long 0x10 2. "WR_STATUS_FLD,Indirect Write Status: Indirect write operation in progress [status]" "0,1"
newline
bitfld.long 0x10 1. "CANCEL_FLD,Cancel Indirect Write: Writing a 1 to this bit will cancel all ongoing indirect write operations" "0,1"
newline
bitfld.long 0x10 0. "START_FLD,Start Indirect Write: Writing a 1 to this bit will trigger an indirect write operation" "0,1"
line.long 0x14 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_watermark_reg,Indirect Write Transfer Watermark Register"
line.long 0x18 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_start_reg,Indirect Write Transfer Start Address Register"
line.long 0x1C "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_write_xfer_num_bytes_reg,Indirect Write Transfer Number Bytes Register"
line.long 0x20 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_indirect_trigger_addr_range_reg,Indirect Trigger Address Range Register"
bitfld.long 0x20 0.--3. "IND_RANGE_WIDTH_FLD,This is the address offset of Indirect Trigger Address Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x8C++0x0B
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_command_ctrl_mem_reg,Flash Command Control Memory Register"
hexmask.long.word 0x00 20.--28. 1. "MEM_BANK_ADDR_FLD,The address of the Memory Bank which data will be read from"
newline
bitfld.long 0x00 16.--18. "NB_OF_STIG_READ_BYTES_FLD,It defines the number of read bytes for the extended STIG" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 8.--15. 1. "MEM_BANK_READ_DATA_FLD,Last requested data from the STIG Memory Bank"
newline
rbitfld.long 0x00 1. "MEM_BANK_REQ_IN_PROGRESS_FLD,Memory Bank data request in progress" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER_MEM_BANK_REQ_FLD,Trigger the Memory Bank data request" "0,1"
line.long 0x04 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_cmd_ctrl_reg,Flash Command Control Register"
hexmask.long.byte 0x04 24.--31. 1. "CMD_OPCODE_FLD,Command Opcode: The command opcode field should be setup before triggering the command"
newline
bitfld.long 0x04 23. "ENB_READ_DATA_FLD,Read Data Enable: Set to 1 if the command specified in the command opcode field [bits 31:24] requires read data bytes to be received from the device" "0,1"
newline
bitfld.long 0x04 20.--22. "NUM_RD_DATA_BYTES_FLD,Number of Read Data Bytes: Up to 8 data bytes may be read using this command" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 19. "ENB_COMD_ADDR_FLD,Command Address Enable: Set to 1 if the command specified in bits 31:24 requires an address" "0,1"
newline
bitfld.long 0x04 18. "ENB_MODE_BIT_FLD,Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes" "0,1"
newline
bitfld.long 0x04 16.--17. "NUM_ADDR_BYTES_FLD,Number of Address Bytes: Set to the number of address bytes required [the address itself is programmed in the FLASH COMMAND ADDRESS REGISTERS]" "1 address byte,2 address bytes,3 address bytes,4 address bytes"
newline
bitfld.long 0x04 15. "ENB_WRITE_DATA_FLD,Write Data Enable: Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device" "0,1"
newline
bitfld.long 0x04 12.--14. "NUM_WR_DATA_BYTES_FLD,Number of Write Data Bytes: Up to 8 Data bytes may be written using this command Set to 0 for 1 byte 7 for 8 bytes" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 7.--11. "NUM_DUMMY_CYCLES_FLD,Number of Dummy cycles: Set to the number of dummy cycles required" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 2. "STIG_MEM_BANK_EN_FLD,STIG Memory Bank enable bit" "0,1"
newline
rbitfld.long 0x04 1. "CMD_EXEC_STATUS_FLD,Command execution in progress" "0,1"
newline
bitfld.long 0x04 0. "CMD_EXEC_FLD,Execute the command" "0,1"
line.long 0x08 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_cmd_addr_reg,Flash Command Address Register"
rgroup.long 0xA0++0x23
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_rd_data_lower_reg,Flash Command Read Data Register (Lower)"
line.long 0x04 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_rd_data_upper_reg,Flash Command Read Data Register (Upper)"
line.long 0x08 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_wr_data_lower_reg,Flash Command Write Data Register (Lower)"
line.long 0x0C "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_flash_wr_data_upper_reg,Flash Command Write Data Register (Upper)"
line.long 0x10 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_polling_flash_status_reg,Polling Flash Status Register"
bitfld.long 0x10 16.--19. "DEVICE_STATUS_NB_DUMMY,Number of dummy cycles for auto-polling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x10 8. "DEVICE_STATUS_VALID_FLD,Device Status Valid: This should be set when value in bits from 7 to 0 is valid" "0,1"
newline
hexmask.long.byte 0x10 0.--7. 1. "DEVICE_STATUS_FLD,Defines actual Status Register of Device"
line.long 0x14 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_phy_configuration_reg,PHY Configuration Register"
bitfld.long 0x14 31. "PHY_CONFIG_RESYNC_FLD,This bit is used for re-synchronisation delay lines to update them with values from TX DLL Delay and RX DLL Delay fields" "0,1"
newline
bitfld.long 0x14 30. "PHY_CONFIG_RESET_FLD,DLL Reset bit: This bit is used for reset of Delay Lines by software" "0,1"
newline
bitfld.long 0x14 29. "PHY_CONFIG_RX_DLL_BYPASS_FLD,RX DLL Bypass: This field determines id RX DLL is bypassed" "0,1"
newline
hexmask.long.byte 0x14 16.--22. 1. "PHY_CONFIG_TX_DLL_DELAY_FLD,TX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and spi_clk"
newline
hexmask.long.byte 0x14 0.--6. 1. "PHY_CONFIG_RX_DLL_DELAY_FLD,RX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and rx_dll_clk"
line.long 0x18 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_phy_master_control_reg,PHY DLL Master Control Register"
bitfld.long 0x18 24. "PHY_MASTER_LOCK_MODE_FLD,Determines if the master delay line locks on a full cycle or half cycle of delay" "0,1"
newline
bitfld.long 0x18 23. "PHY_MASTER_BYPASS_MODE_FLD,Controls the bypass mode of the master and slave DLLs" "0,1"
newline
bitfld.long 0x18 20.--22. "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD,Selects the number of delay elements to be inserted between the phase detect flip-flops" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 16.--18. "PHY_MASTER_NB_INDICATIONS_FLD,Holds the number of consecutive increment or decrement indications" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x18 0.--6. 1. "PHY_MASTER_INITIAL_DELAY_FLD,This value is the initial delay value for the DLL"
line.long 0x1C "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dll_observable_lower_reg,DLL Observable Register Lower"
hexmask.long.byte 0x1C 24.--31. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD,Holds the state of the cumulative dll_lock_inc register"
newline
hexmask.long.byte 0x1C 16.--23. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD,Holds the state of the cumulative dll_lock_dec register"
newline
bitfld.long 0x1C 15. "DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD,This bit indicates that lock of loopback is done" "0,1"
newline
hexmask.long.byte 0x1C 8.--14. 1. "DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD,Reports the DLL encoder value from the master DLL to the slave DLLs"
newline
bitfld.long 0x1C 3.--7. "DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD,Reports the number of increments or decrements required for the master DLL to complete the locking process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 1.--2. "DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD,Defines the mode in which the DLL has achieved the lock" "0,1,2,3"
newline
bitfld.long 0x1C 0. "DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD,Indicates status of DLL" "0,1"
line.long 0x20 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_dll_observable_upper_reg,DLL Observable Register Upper"
hexmask.long.byte 0x20 16.--22. 1. "DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD,Holds the encoded value for the TX delay line for this slice"
newline
hexmask.long.byte 0x20 0.--6. 1. "DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD,Holds the encoded value for the RX delay line for this slice"
group.long 0xE0++0x07
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_lower_reg,Opcode Extension Register (Lower)"
hexmask.long.byte 0x00 24.--31. 1. "EXT_READ_OPCODE_FLD,Supplement byte of any Read Opcode"
newline
hexmask.long.byte 0x00 16.--23. 1. "EXT_WRITE_OPCODE_FLD,Supplement byte of any Write Opcode"
newline
hexmask.long.byte 0x00 8.--15. 1. "EXT_POLL_OPCODE_FLD,Supplement byte of any Polling Opcode"
newline
hexmask.long.byte 0x00 0.--7. 1. "EXT_STIG_OPCODE_FLD,Supplement byte of any STIG Opcode"
line.long 0x04 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_opcode_ext_upper_reg,Opcode Extension Register (Upper)"
hexmask.long.byte 0x04 24.--31. 1. "WEL_OPCODE_FLD,First byte of any WEL Opcode"
newline
hexmask.long.byte 0x04 16.--23. 1. "EXT_WEL_OPCODE_FLD,Supplement byte of any WEL Opcode"
rgroup.long 0xFC++0x03
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__VBP2APB_WRAP__OSPI_CFG_VBP__OSPI_FLASH_APB_REGS_module_id_reg,Module ID Register"
hexmask.long.byte 0x00 24.--31. 1. "FIX_PATCH_FLD,Fix/path number related to revision described by 3 LSBs of this register"
newline
hexmask.long.word 0x00 8.--23. 1. "MODULE_ID_FLD,Module/Revision ID number"
newline
bitfld.long 0x00 0.--1. "CONF_FLD,Configuration ID number" "OCTAL + PHY Configuration,OCTAL Configuration,QUAD + PHY Configuration,QUAD Configuration"
tree.end
tree "FSS0_OSPI_0_OSPI0_ECC_AGGR"
base ad:0x716000
rgroup.long 0x00++0x03
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "OSPI0__OSPI_CFG_VBUSP__OSPI_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "FSS0_OSPI_0_OSPI0_SS_CFG"
base ad:0xFC44000
rgroup.long 0x00++0x0B
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_CTRL,The Control Register contains general control bits for the ospi"
bitfld.long 0x04 3. "PIPELINE_MODE_FLUSH," "0,1"
line.long 0x08 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_STAT,The Status register provide general status bits for the ospi"
bitfld.long 0x08 1. "MEM_INIT_DONE," "0,1"
group.long 0x20++0x03
line.long 0x00 "OSPI0__OSPI_CFG_VBUSP__MMR__MMRVBP__REGS_EOI,End of Interrupt Register"
hexmask.long.byte 0x00 0.--7. 1. "EOI,Write with bit position of targetted interrupt"
tree.end
tree "GICSS0_GIC"
base ad:0x1800000
group.long 0x00++0x0B
line.long 0x00 "GIC_REGS_Distributor__1_GICD_CTLR,GICD_CTLR"
bitfld.long 0x00 31. "DISTRIBUTOR__1_GICD_CTLR__31_1,Register Write Pending" "0,1"
newline
bitfld.long 0x00 6. "DISTRIBUTOR__1_GICD_CTLR__6_1,S: DS" "0,1"
newline
bitfld.long 0x00 5. "DISTRIBUTOR__1_GICD_CTLR__5_1,S: ARE_NS" "0,1"
newline
bitfld.long 0x00 4. "DISTRIBUTOR__1_GICD_CTLR__4_1,NS: ARE_NS S: ARE_S" "0,1"
newline
bitfld.long 0x00 2. "DISTRIBUTOR__1_GICD_CTLR__2_1,S: EnableGrp1_S" "0,1"
newline
bitfld.long 0x00 1. "DISTRIBUTOR__1_GICD_CTLR__1_1,NS: EnableGrp1A S: EnableGrp1_NS" "0,1"
newline
bitfld.long 0x00 0. "DISTRIBUTOR__1_GICD_CTLR__0_1,NS: EnableGrp1 S: EnableGrp0" "0,1"
line.long 0x04 "GIC_REGS_Distributor__3_GICD_TYPER,GICD_TYPER"
bitfld.long 0x04 24. "DISTRIBUTOR__3_GICD_TYPER__24_1,A3V" "0,1"
newline
bitfld.long 0x04 19.--23. "DISTRIBUTOR__3_GICD_TYPER__19_5,IDbits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 18. "DISTRIBUTOR__3_GICD_TYPER__18_1,DVIS" "0,1"
newline
bitfld.long 0x04 17. "DISTRIBUTOR__3_GICD_TYPER__17_1,LPIS" "0,1"
newline
bitfld.long 0x04 16. "DISTRIBUTOR__3_GICD_TYPER__16_1,MBIS" "0,1"
newline
bitfld.long 0x04 11.--15. "DISTRIBUTOR__3_GICD_TYPER__11_5,LSPI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 10. "DISTRIBUTOR__3_GICD_TYPER__10_1,SecurityExtn" "0,1"
newline
bitfld.long 0x04 5.--7. "DISTRIBUTOR__3_GICD_TYPER__5_3,CPUNumber" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0.--4. "DISTRIBUTOR__3_GICD_TYPER__0_5,ITLinesNumber" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "GIC_REGS_Distributor__4_GICD_IIDR,GICD_IIDR"
hexmask.long.byte 0x08 24.--31. 1. "DISTRIBUTOR__4_GICD_IIDR__24_8,ProductID"
newline
bitfld.long 0x08 16.--19. "DISTRIBUTOR__4_GICD_IIDR__16_4,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 12.--15. "DISTRIBUTOR__4_GICD_IIDR__12_4,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x08 0.--11. 1. "DISTRIBUTOR__4_GICD_IIDR__0_12,Implementer"
group.long 0x40++0x03
line.long 0x00 "GIC_REGS_Distributor__5_GICD_SETSPI_NSR,GICD_SETSPI_NSR"
hexmask.long.word 0x00 0.--9. 1. "DISTRIBUTOR__5_GICD_SETSPI_NSR__0_10,SPI ID"
group.long 0x48++0x03
line.long 0x00 "GIC_REGS_Distributor__6_GICD_CLRSPI_NSR,GICD_CLRSPI_NSR"
hexmask.long.word 0x00 0.--9. 1. "DISTRIBUTOR__6_GICD_CLRSPI_NSR__0_10,SPI ID"
group.long 0x50++0x03
line.long 0x00 "GIC_REGS_Distributor__7_GICD_SETSPI_SR,GICD_SETSPI_SR"
hexmask.long.word 0x00 0.--9. 1. "DISTRIBUTOR__7_GICD_SETSPI_SR__0_10,SPI ID"
group.long 0x58++0x03
line.long 0x00 "GIC_REGS_Distributor__8_GICD_CLRSPI_SR,GICD_CLRSPI_SR"
hexmask.long.word 0x00 0.--9. 1. "DISTRIBUTOR__8_GICD_CLRSPI_SR__0_10,SPI ID"
hgroup.long 0x80++0x03
hide.long 0x00 "GIC_REGS_Distributor__9_GICD_IGROUPR0,GICD_IGROUPR0"
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
hgroup.long ($2+0x84)++0x03
hide.long 0x00 "GIC_REGS_Distributor__10_GICD_IGROUPR$1,GICD_IGROUPR1"
repeat.end
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
hgroup.long ($2+0x104)++0x03
hide.long 0x00 "GIC_REGS_Distributor__12_GICD_ISENABLER$1,GICD_ISENABLER1"
repeat.end
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
hgroup.long ($2+0x184)++0x03
hide.long 0x00 "GIC_REGS_Distributor__14_GICD_ICENABLER$1,GICD_ICENABLER1"
repeat.end
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
hgroup.long ($2+0x204)++0x03
hide.long 0x00 "GIC_REGS_Distributor__16_GICD_ISPENDR$1,GICD_ISPENDR1"
repeat.end
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
hgroup.long ($2+0x284)++0x03
hide.long 0x00 "GIC_REGS_Distributor__18_GICD_ICPENDR$1,GICD_ICPENDR1"
repeat.end
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
hgroup.long ($2+0x304)++0x03
hide.long 0x00 "GIC_REGS_Distributor__20_GICD_ISACTIVER$1,GICD_ISACTIVER1"
repeat.end
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
hgroup.long ($2+0x384)++0x03
hide.long 0x00 "GIC_REGS_Distributor__22_GICD_ICACTIVER$1,GICD_ICACTIVER1"
repeat.end
repeat 16. (list 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
hgroup.long ($2+0x420)++0x03
hide.long 0x00 "GIC_REGS_Distributor__24_GICD_IPRIORITYR$1,GICD_IPRIORITYR8"
repeat.end
repeat 16. (list 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
hgroup.long ($2+0x460)++0x03
hide.long 0x00 "GIC_REGS_Distributor__24_GICD_IPRIORITYR$1,GICD_IPRIORITYR24"
repeat.end
repeat 16. (list 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
hgroup.long ($2+0x4A0)++0x03
hide.long 0x00 "GIC_REGS_Distributor__24_GICD_IPRIORITYR$1,GICD_IPRIORITYR40"
repeat.end
repeat 16. (list 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
hgroup.long ($2+0x4E0)++0x03
hide.long 0x00 "GIC_REGS_Distributor__24_GICD_IPRIORITYR$1,GICD_IPRIORITYR56"
repeat.end
repeat 16. (list 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
hgroup.long ($2+0x820)++0x03
hide.long 0x00 "GIC_REGS_Distributor__26_GICD_ITARGETSR$1,GICD_ITARGETSR8"
repeat.end
repeat 16. (list 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
hgroup.long ($2+0x860)++0x03
hide.long 0x00 "GIC_REGS_Distributor__26_GICD_ITARGETSR$1,GICD_ITARGETSR24"
repeat.end
repeat 16. (list 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
hgroup.long ($2+0x8A0)++0x03
hide.long 0x00 "GIC_REGS_Distributor__26_GICD_ITARGETSR$1,GICD_ITARGETSR40"
repeat.end
repeat 16. (list 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
hgroup.long ($2+0x8E0)++0x03
hide.long 0x00 "GIC_REGS_Distributor__26_GICD_ITARGETSR$1,GICD_ITARGETSR56"
repeat.end
repeat 16. (list 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
hgroup.long ($2+0xC08)++0x03
hide.long 0x00 "GIC_REGS_Distributor__29_GICD_ICFGR$1,GICD_ICFGR2"
repeat.end
hgroup.long 0xD00++0x03
hide.long 0x00 "GIC_REGS_Distributor__30_GICD_IGRPMODR0,GICD_IGRPMODR0"
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
hgroup.long ($2+0xD04)++0x03
hide.long 0x00 "GIC_REGS_Distributor__31_GICD_IGRPMODR$1,GICD_IGRPMODR1"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
hgroup.long ($2+0xE00)++0x03
hide.long 0x00 "GIC_REGS_Distributor__32_GICD_NSACR$1,GICD_NSACR0"
repeat.end
repeat 16. (list 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
hgroup.long ($2+0xE08)++0x03
hide.long 0x00 "GIC_REGS_Distributor__33_GICD_NSACR$1,GICD_NSACR2"
repeat.end
group.long 0x6100++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER32_lower,GICD_IROUTER32_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER32_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER32_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER32_LOWER__0_8,A0"
hgroup.long 0x6104++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER32_upper,GICD_IROUTER32_upper"
group.long 0x6108++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER33_lower,GICD_IROUTER33_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER33_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER33_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER33_LOWER__0_8,A0"
hgroup.long 0x610C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER33_upper,GICD_IROUTER33_upper"
group.long 0x6110++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER34_lower,GICD_IROUTER34_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER34_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER34_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER34_LOWER__0_8,A0"
hgroup.long 0x6114++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER34_upper,GICD_IROUTER34_upper"
group.long 0x6118++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER35_lower,GICD_IROUTER35_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER35_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER35_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER35_LOWER__0_8,A0"
hgroup.long 0x611C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER35_upper,GICD_IROUTER35_upper"
group.long 0x6120++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER36_lower,GICD_IROUTER36_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER36_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER36_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER36_LOWER__0_8,A0"
hgroup.long 0x6124++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER36_upper,GICD_IROUTER36_upper"
group.long 0x6128++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER37_lower,GICD_IROUTER37_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER37_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER37_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER37_LOWER__0_8,A0"
hgroup.long 0x612C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER37_upper,GICD_IROUTER37_upper"
group.long 0x6130++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER38_lower,GICD_IROUTER38_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER38_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER38_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER38_LOWER__0_8,A0"
hgroup.long 0x6134++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER38_upper,GICD_IROUTER38_upper"
group.long 0x6138++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER39_lower,GICD_IROUTER39_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER39_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER39_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER39_LOWER__0_8,A0"
hgroup.long 0x613C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER39_upper,GICD_IROUTER39_upper"
group.long 0x6140++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER40_lower,GICD_IROUTER40_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER40_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER40_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER40_LOWER__0_8,A0"
hgroup.long 0x6144++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER40_upper,GICD_IROUTER40_upper"
group.long 0x6148++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER41_lower,GICD_IROUTER41_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER41_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER41_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER41_LOWER__0_8,A0"
hgroup.long 0x614C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER41_upper,GICD_IROUTER41_upper"
group.long 0x6150++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER42_lower,GICD_IROUTER42_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER42_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER42_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER42_LOWER__0_8,A0"
hgroup.long 0x6154++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER42_upper,GICD_IROUTER42_upper"
group.long 0x6158++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER43_lower,GICD_IROUTER43_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER43_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER43_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER43_LOWER__0_8,A0"
hgroup.long 0x615C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER43_upper,GICD_IROUTER43_upper"
group.long 0x6160++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER44_lower,GICD_IROUTER44_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER44_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER44_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER44_LOWER__0_8,A0"
hgroup.long 0x6164++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER44_upper,GICD_IROUTER44_upper"
group.long 0x6168++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER45_lower,GICD_IROUTER45_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER45_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER45_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER45_LOWER__0_8,A0"
hgroup.long 0x616C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER45_upper,GICD_IROUTER45_upper"
group.long 0x6170++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER46_lower,GICD_IROUTER46_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER46_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER46_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER46_LOWER__0_8,A0"
hgroup.long 0x6174++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER46_upper,GICD_IROUTER46_upper"
group.long 0x6178++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER47_lower,GICD_IROUTER47_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER47_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER47_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER47_LOWER__0_8,A0"
hgroup.long 0x617C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER47_upper,GICD_IROUTER47_upper"
group.long 0x6180++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER48_lower,GICD_IROUTER48_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER48_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER48_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER48_LOWER__0_8,A0"
hgroup.long 0x6184++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER48_upper,GICD_IROUTER48_upper"
group.long 0x6188++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER49_lower,GICD_IROUTER49_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER49_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER49_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER49_LOWER__0_8,A0"
hgroup.long 0x618C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER49_upper,GICD_IROUTER49_upper"
group.long 0x6190++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER50_lower,GICD_IROUTER50_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER50_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER50_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER50_LOWER__0_8,A0"
hgroup.long 0x6194++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER50_upper,GICD_IROUTER50_upper"
group.long 0x6198++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER51_lower,GICD_IROUTER51_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER51_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER51_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER51_LOWER__0_8,A0"
hgroup.long 0x619C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER51_upper,GICD_IROUTER51_upper"
group.long 0x61A0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER52_lower,GICD_IROUTER52_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER52_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER52_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER52_LOWER__0_8,A0"
hgroup.long 0x61A4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER52_upper,GICD_IROUTER52_upper"
group.long 0x61A8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER53_lower,GICD_IROUTER53_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER53_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER53_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER53_LOWER__0_8,A0"
hgroup.long 0x61AC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER53_upper,GICD_IROUTER53_upper"
group.long 0x61B0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER54_lower,GICD_IROUTER54_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER54_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER54_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER54_LOWER__0_8,A0"
hgroup.long 0x61B4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER54_upper,GICD_IROUTER54_upper"
group.long 0x61B8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER55_lower,GICD_IROUTER55_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER55_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER55_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER55_LOWER__0_8,A0"
hgroup.long 0x61BC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER55_upper,GICD_IROUTER55_upper"
group.long 0x61C0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER56_lower,GICD_IROUTER56_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER56_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER56_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER56_LOWER__0_8,A0"
hgroup.long 0x61C4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER56_upper,GICD_IROUTER56_upper"
group.long 0x61C8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER57_lower,GICD_IROUTER57_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER57_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER57_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER57_LOWER__0_8,A0"
hgroup.long 0x61CC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER57_upper,GICD_IROUTER57_upper"
group.long 0x61D0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER58_lower,GICD_IROUTER58_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER58_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER58_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER58_LOWER__0_8,A0"
hgroup.long 0x61D4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER58_upper,GICD_IROUTER58_upper"
group.long 0x61D8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER59_lower,GICD_IROUTER59_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER59_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER59_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER59_LOWER__0_8,A0"
hgroup.long 0x61DC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER59_upper,GICD_IROUTER59_upper"
group.long 0x61E0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER60_lower,GICD_IROUTER60_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER60_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER60_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER60_LOWER__0_8,A0"
hgroup.long 0x61E4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER60_upper,GICD_IROUTER60_upper"
group.long 0x61E8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER61_lower,GICD_IROUTER61_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER61_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER61_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER61_LOWER__0_8,A0"
hgroup.long 0x61EC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER61_upper,GICD_IROUTER61_upper"
group.long 0x61F0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER62_lower,GICD_IROUTER62_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER62_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER62_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER62_LOWER__0_8,A0"
hgroup.long 0x61F4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER62_upper,GICD_IROUTER62_upper"
group.long 0x61F8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER63_lower,GICD_IROUTER63_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER63_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER63_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER63_LOWER__0_8,A0"
hgroup.long 0x61FC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER63_upper,GICD_IROUTER63_upper"
group.long 0x6200++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER64_lower,GICD_IROUTER64_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER64_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER64_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER64_LOWER__0_8,A0"
hgroup.long 0x6204++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER64_upper,GICD_IROUTER64_upper"
group.long 0x6208++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER65_lower,GICD_IROUTER65_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER65_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER65_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER65_LOWER__0_8,A0"
hgroup.long 0x620C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER65_upper,GICD_IROUTER65_upper"
group.long 0x6210++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER66_lower,GICD_IROUTER66_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER66_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER66_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER66_LOWER__0_8,A0"
hgroup.long 0x6214++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER66_upper,GICD_IROUTER66_upper"
group.long 0x6218++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER67_lower,GICD_IROUTER67_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER67_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER67_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER67_LOWER__0_8,A0"
hgroup.long 0x621C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER67_upper,GICD_IROUTER67_upper"
group.long 0x6220++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER68_lower,GICD_IROUTER68_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER68_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER68_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER68_LOWER__0_8,A0"
hgroup.long 0x6224++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER68_upper,GICD_IROUTER68_upper"
group.long 0x6228++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER69_lower,GICD_IROUTER69_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER69_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER69_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER69_LOWER__0_8,A0"
hgroup.long 0x622C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER69_upper,GICD_IROUTER69_upper"
group.long 0x6230++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER70_lower,GICD_IROUTER70_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER70_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER70_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER70_LOWER__0_8,A0"
hgroup.long 0x6234++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER70_upper,GICD_IROUTER70_upper"
group.long 0x6238++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER71_lower,GICD_IROUTER71_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER71_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER71_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER71_LOWER__0_8,A0"
hgroup.long 0x623C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER71_upper,GICD_IROUTER71_upper"
group.long 0x6240++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER72_lower,GICD_IROUTER72_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER72_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER72_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER72_LOWER__0_8,A0"
hgroup.long 0x6244++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER72_upper,GICD_IROUTER72_upper"
group.long 0x6248++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER73_lower,GICD_IROUTER73_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER73_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER73_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER73_LOWER__0_8,A0"
hgroup.long 0x624C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER73_upper,GICD_IROUTER73_upper"
group.long 0x6250++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER74_lower,GICD_IROUTER74_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER74_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER74_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER74_LOWER__0_8,A0"
hgroup.long 0x6254++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER74_upper,GICD_IROUTER74_upper"
group.long 0x6258++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER75_lower,GICD_IROUTER75_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER75_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER75_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER75_LOWER__0_8,A0"
hgroup.long 0x625C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER75_upper,GICD_IROUTER75_upper"
group.long 0x6260++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER76_lower,GICD_IROUTER76_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER76_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER76_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER76_LOWER__0_8,A0"
hgroup.long 0x6264++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER76_upper,GICD_IROUTER76_upper"
group.long 0x6268++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER77_lower,GICD_IROUTER77_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER77_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER77_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER77_LOWER__0_8,A0"
hgroup.long 0x626C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER77_upper,GICD_IROUTER77_upper"
group.long 0x6270++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER78_lower,GICD_IROUTER78_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER78_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER78_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER78_LOWER__0_8,A0"
hgroup.long 0x6274++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER78_upper,GICD_IROUTER78_upper"
group.long 0x6278++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER79_lower,GICD_IROUTER79_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER79_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER79_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER79_LOWER__0_8,A0"
hgroup.long 0x627C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER79_upper,GICD_IROUTER79_upper"
group.long 0x6280++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER80_lower,GICD_IROUTER80_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER80_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER80_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER80_LOWER__0_8,A0"
hgroup.long 0x6284++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER80_upper,GICD_IROUTER80_upper"
group.long 0x6288++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER81_lower,GICD_IROUTER81_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER81_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER81_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER81_LOWER__0_8,A0"
hgroup.long 0x628C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER81_upper,GICD_IROUTER81_upper"
group.long 0x6290++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER82_lower,GICD_IROUTER82_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER82_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER82_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER82_LOWER__0_8,A0"
hgroup.long 0x6294++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER82_upper,GICD_IROUTER82_upper"
group.long 0x6298++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER83_lower,GICD_IROUTER83_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER83_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER83_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER83_LOWER__0_8,A0"
hgroup.long 0x629C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER83_upper,GICD_IROUTER83_upper"
group.long 0x62A0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER84_lower,GICD_IROUTER84_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER84_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER84_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER84_LOWER__0_8,A0"
hgroup.long 0x62A4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER84_upper,GICD_IROUTER84_upper"
group.long 0x62A8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER85_lower,GICD_IROUTER85_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER85_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER85_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER85_LOWER__0_8,A0"
hgroup.long 0x62AC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER85_upper,GICD_IROUTER85_upper"
group.long 0x62B0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER86_lower,GICD_IROUTER86_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER86_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER86_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER86_LOWER__0_8,A0"
hgroup.long 0x62B4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER86_upper,GICD_IROUTER86_upper"
group.long 0x62B8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER87_lower,GICD_IROUTER87_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER87_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER87_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER87_LOWER__0_8,A0"
hgroup.long 0x62BC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER87_upper,GICD_IROUTER87_upper"
group.long 0x62C0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER88_lower,GICD_IROUTER88_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER88_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER88_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER88_LOWER__0_8,A0"
hgroup.long 0x62C4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER88_upper,GICD_IROUTER88_upper"
group.long 0x62C8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER89_lower,GICD_IROUTER89_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER89_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER89_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER89_LOWER__0_8,A0"
hgroup.long 0x62CC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER89_upper,GICD_IROUTER89_upper"
group.long 0x62D0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER90_lower,GICD_IROUTER90_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER90_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER90_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER90_LOWER__0_8,A0"
hgroup.long 0x62D4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER90_upper,GICD_IROUTER90_upper"
group.long 0x62D8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER91_lower,GICD_IROUTER91_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER91_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER91_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER91_LOWER__0_8,A0"
hgroup.long 0x62DC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER91_upper,GICD_IROUTER91_upper"
group.long 0x62E0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER92_lower,GICD_IROUTER92_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER92_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER92_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER92_LOWER__0_8,A0"
hgroup.long 0x62E4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER92_upper,GICD_IROUTER92_upper"
group.long 0x62E8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER93_lower,GICD_IROUTER93_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER93_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER93_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER93_LOWER__0_8,A0"
hgroup.long 0x62EC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER93_upper,GICD_IROUTER93_upper"
group.long 0x62F0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER94_lower,GICD_IROUTER94_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER94_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER94_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER94_LOWER__0_8,A0"
hgroup.long 0x62F4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER94_upper,GICD_IROUTER94_upper"
group.long 0x62F8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER95_lower,GICD_IROUTER95_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER95_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER95_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER95_LOWER__0_8,A0"
hgroup.long 0x62FC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER95_upper,GICD_IROUTER95_upper"
group.long 0x6300++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER96_lower,GICD_IROUTER96_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER96_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER96_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER96_LOWER__0_8,A0"
hgroup.long 0x6304++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER96_upper,GICD_IROUTER96_upper"
group.long 0x6308++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER97_lower,GICD_IROUTER97_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER97_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER97_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER97_LOWER__0_8,A0"
hgroup.long 0x630C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER97_upper,GICD_IROUTER97_upper"
group.long 0x6310++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER98_lower,GICD_IROUTER98_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER98_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER98_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER98_LOWER__0_8,A0"
hgroup.long 0x6314++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER98_upper,GICD_IROUTER98_upper"
group.long 0x6318++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER99_lower,GICD_IROUTER99_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER99_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER99_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER99_LOWER__0_8,A0"
hgroup.long 0x631C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER99_upper,GICD_IROUTER99_upper"
group.long 0x6320++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER100_lower,GICD_IROUTER100_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER100_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER100_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER100_LOWER__0_8,A0"
hgroup.long 0x6324++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER100_upper,GICD_IROUTER100_upper"
group.long 0x6328++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER101_lower,GICD_IROUTER101_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER101_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER101_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER101_LOWER__0_8,A0"
hgroup.long 0x632C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER101_upper,GICD_IROUTER101_upper"
group.long 0x6330++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER102_lower,GICD_IROUTER102_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER102_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER102_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER102_LOWER__0_8,A0"
hgroup.long 0x6334++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER102_upper,GICD_IROUTER102_upper"
group.long 0x6338++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER103_lower,GICD_IROUTER103_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER103_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER103_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER103_LOWER__0_8,A0"
hgroup.long 0x633C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER103_upper,GICD_IROUTER103_upper"
group.long 0x6340++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER104_lower,GICD_IROUTER104_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER104_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER104_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER104_LOWER__0_8,A0"
hgroup.long 0x6344++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER104_upper,GICD_IROUTER104_upper"
group.long 0x6348++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER105_lower,GICD_IROUTER105_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER105_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER105_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER105_LOWER__0_8,A0"
hgroup.long 0x634C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER105_upper,GICD_IROUTER105_upper"
group.long 0x6350++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER106_lower,GICD_IROUTER106_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER106_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER106_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER106_LOWER__0_8,A0"
hgroup.long 0x6354++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER106_upper,GICD_IROUTER106_upper"
group.long 0x6358++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER107_lower,GICD_IROUTER107_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER107_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER107_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER107_LOWER__0_8,A0"
hgroup.long 0x635C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER107_upper,GICD_IROUTER107_upper"
group.long 0x6360++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER108_lower,GICD_IROUTER108_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER108_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER108_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER108_LOWER__0_8,A0"
hgroup.long 0x6364++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER108_upper,GICD_IROUTER108_upper"
group.long 0x6368++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER109_lower,GICD_IROUTER109_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER109_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER109_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER109_LOWER__0_8,A0"
hgroup.long 0x636C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER109_upper,GICD_IROUTER109_upper"
group.long 0x6370++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER110_lower,GICD_IROUTER110_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER110_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER110_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER110_LOWER__0_8,A0"
hgroup.long 0x6374++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER110_upper,GICD_IROUTER110_upper"
group.long 0x6378++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER111_lower,GICD_IROUTER111_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER111_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER111_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER111_LOWER__0_8,A0"
hgroup.long 0x637C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER111_upper,GICD_IROUTER111_upper"
group.long 0x6380++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER112_lower,GICD_IROUTER112_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER112_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER112_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER112_LOWER__0_8,A0"
hgroup.long 0x6384++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER112_upper,GICD_IROUTER112_upper"
group.long 0x6388++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER113_lower,GICD_IROUTER113_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER113_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER113_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER113_LOWER__0_8,A0"
hgroup.long 0x638C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER113_upper,GICD_IROUTER113_upper"
group.long 0x6390++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER114_lower,GICD_IROUTER114_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER114_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER114_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER114_LOWER__0_8,A0"
hgroup.long 0x6394++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER114_upper,GICD_IROUTER114_upper"
group.long 0x6398++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER115_lower,GICD_IROUTER115_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER115_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER115_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER115_LOWER__0_8,A0"
hgroup.long 0x639C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER115_upper,GICD_IROUTER115_upper"
group.long 0x63A0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER116_lower,GICD_IROUTER116_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER116_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER116_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER116_LOWER__0_8,A0"
hgroup.long 0x63A4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER116_upper,GICD_IROUTER116_upper"
group.long 0x63A8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER117_lower,GICD_IROUTER117_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER117_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER117_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER117_LOWER__0_8,A0"
hgroup.long 0x63AC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER117_upper,GICD_IROUTER117_upper"
group.long 0x63B0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER118_lower,GICD_IROUTER118_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER118_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER118_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER118_LOWER__0_8,A0"
hgroup.long 0x63B4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER118_upper,GICD_IROUTER118_upper"
group.long 0x63B8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER119_lower,GICD_IROUTER119_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER119_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER119_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER119_LOWER__0_8,A0"
hgroup.long 0x63BC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER119_upper,GICD_IROUTER119_upper"
group.long 0x63C0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER120_lower,GICD_IROUTER120_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER120_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER120_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER120_LOWER__0_8,A0"
hgroup.long 0x63C4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER120_upper,GICD_IROUTER120_upper"
group.long 0x63C8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER121_lower,GICD_IROUTER121_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER121_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER121_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER121_LOWER__0_8,A0"
hgroup.long 0x63CC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER121_upper,GICD_IROUTER121_upper"
group.long 0x63D0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER122_lower,GICD_IROUTER122_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER122_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER122_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER122_LOWER__0_8,A0"
hgroup.long 0x63D4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER122_upper,GICD_IROUTER122_upper"
group.long 0x63D8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER123_lower,GICD_IROUTER123_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER123_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER123_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER123_LOWER__0_8,A0"
hgroup.long 0x63DC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER123_upper,GICD_IROUTER123_upper"
group.long 0x63E0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER124_lower,GICD_IROUTER124_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER124_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER124_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER124_LOWER__0_8,A0"
hgroup.long 0x63E4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER124_upper,GICD_IROUTER124_upper"
group.long 0x63E8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER125_lower,GICD_IROUTER125_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER125_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER125_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER125_LOWER__0_8,A0"
hgroup.long 0x63EC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER125_upper,GICD_IROUTER125_upper"
group.long 0x63F0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER126_lower,GICD_IROUTER126_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER126_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER126_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER126_LOWER__0_8,A0"
hgroup.long 0x63F4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER126_upper,GICD_IROUTER126_upper"
group.long 0x63F8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER127_lower,GICD_IROUTER127_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER127_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER127_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER127_LOWER__0_8,A0"
hgroup.long 0x63FC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER127_upper,GICD_IROUTER127_upper"
group.long 0x6400++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER128_lower,GICD_IROUTER128_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER128_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER128_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER128_LOWER__0_8,A0"
hgroup.long 0x6404++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER128_upper,GICD_IROUTER128_upper"
group.long 0x6408++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER129_lower,GICD_IROUTER129_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER129_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER129_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER129_LOWER__0_8,A0"
hgroup.long 0x640C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER129_upper,GICD_IROUTER129_upper"
group.long 0x6410++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER130_lower,GICD_IROUTER130_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER130_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER130_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER130_LOWER__0_8,A0"
hgroup.long 0x6414++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER130_upper,GICD_IROUTER130_upper"
group.long 0x6418++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER131_lower,GICD_IROUTER131_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER131_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER131_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER131_LOWER__0_8,A0"
hgroup.long 0x641C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER131_upper,GICD_IROUTER131_upper"
group.long 0x6420++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER132_lower,GICD_IROUTER132_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER132_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER132_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER132_LOWER__0_8,A0"
hgroup.long 0x6424++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER132_upper,GICD_IROUTER132_upper"
group.long 0x6428++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER133_lower,GICD_IROUTER133_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER133_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER133_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER133_LOWER__0_8,A0"
hgroup.long 0x642C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER133_upper,GICD_IROUTER133_upper"
group.long 0x6430++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER134_lower,GICD_IROUTER134_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER134_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER134_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER134_LOWER__0_8,A0"
hgroup.long 0x6434++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER134_upper,GICD_IROUTER134_upper"
group.long 0x6438++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER135_lower,GICD_IROUTER135_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER135_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER135_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER135_LOWER__0_8,A0"
hgroup.long 0x643C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER135_upper,GICD_IROUTER135_upper"
group.long 0x6440++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER136_lower,GICD_IROUTER136_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER136_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER136_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER136_LOWER__0_8,A0"
hgroup.long 0x6444++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER136_upper,GICD_IROUTER136_upper"
group.long 0x6448++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER137_lower,GICD_IROUTER137_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER137_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER137_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER137_LOWER__0_8,A0"
hgroup.long 0x644C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER137_upper,GICD_IROUTER137_upper"
group.long 0x6450++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER138_lower,GICD_IROUTER138_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER138_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER138_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER138_LOWER__0_8,A0"
hgroup.long 0x6454++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER138_upper,GICD_IROUTER138_upper"
group.long 0x6458++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER139_lower,GICD_IROUTER139_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER139_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER139_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER139_LOWER__0_8,A0"
hgroup.long 0x645C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER139_upper,GICD_IROUTER139_upper"
group.long 0x6460++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER140_lower,GICD_IROUTER140_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER140_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER140_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER140_LOWER__0_8,A0"
hgroup.long 0x6464++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER140_upper,GICD_IROUTER140_upper"
group.long 0x6468++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER141_lower,GICD_IROUTER141_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER141_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER141_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER141_LOWER__0_8,A0"
hgroup.long 0x646C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER141_upper,GICD_IROUTER141_upper"
group.long 0x6470++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER142_lower,GICD_IROUTER142_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER142_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER142_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER142_LOWER__0_8,A0"
hgroup.long 0x6474++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER142_upper,GICD_IROUTER142_upper"
group.long 0x6478++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER143_lower,GICD_IROUTER143_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER143_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER143_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER143_LOWER__0_8,A0"
hgroup.long 0x647C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER143_upper,GICD_IROUTER143_upper"
group.long 0x6480++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER144_lower,GICD_IROUTER144_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER144_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER144_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER144_LOWER__0_8,A0"
hgroup.long 0x6484++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER144_upper,GICD_IROUTER144_upper"
group.long 0x6488++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER145_lower,GICD_IROUTER145_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER145_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER145_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER145_LOWER__0_8,A0"
hgroup.long 0x648C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER145_upper,GICD_IROUTER145_upper"
group.long 0x6490++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER146_lower,GICD_IROUTER146_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER146_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER146_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER146_LOWER__0_8,A0"
hgroup.long 0x6494++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER146_upper,GICD_IROUTER146_upper"
group.long 0x6498++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER147_lower,GICD_IROUTER147_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER147_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER147_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER147_LOWER__0_8,A0"
hgroup.long 0x649C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER147_upper,GICD_IROUTER147_upper"
group.long 0x64A0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER148_lower,GICD_IROUTER148_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER148_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER148_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER148_LOWER__0_8,A0"
hgroup.long 0x64A4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER148_upper,GICD_IROUTER148_upper"
group.long 0x64A8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER149_lower,GICD_IROUTER149_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER149_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER149_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER149_LOWER__0_8,A0"
hgroup.long 0x64AC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER149_upper,GICD_IROUTER149_upper"
group.long 0x64B0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER150_lower,GICD_IROUTER150_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER150_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER150_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER150_LOWER__0_8,A0"
hgroup.long 0x64B4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER150_upper,GICD_IROUTER150_upper"
group.long 0x64B8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER151_lower,GICD_IROUTER151_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER151_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER151_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER151_LOWER__0_8,A0"
hgroup.long 0x64BC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER151_upper,GICD_IROUTER151_upper"
group.long 0x64C0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER152_lower,GICD_IROUTER152_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER152_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER152_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER152_LOWER__0_8,A0"
hgroup.long 0x64C4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER152_upper,GICD_IROUTER152_upper"
group.long 0x64C8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER153_lower,GICD_IROUTER153_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER153_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER153_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER153_LOWER__0_8,A0"
hgroup.long 0x64CC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER153_upper,GICD_IROUTER153_upper"
group.long 0x64D0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER154_lower,GICD_IROUTER154_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER154_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER154_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER154_LOWER__0_8,A0"
hgroup.long 0x64D4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER154_upper,GICD_IROUTER154_upper"
group.long 0x64D8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER155_lower,GICD_IROUTER155_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER155_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER155_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER155_LOWER__0_8,A0"
hgroup.long 0x64DC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER155_upper,GICD_IROUTER155_upper"
group.long 0x64E0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER156_lower,GICD_IROUTER156_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER156_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER156_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER156_LOWER__0_8,A0"
hgroup.long 0x64E4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER156_upper,GICD_IROUTER156_upper"
group.long 0x64E8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER157_lower,GICD_IROUTER157_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER157_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER157_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER157_LOWER__0_8,A0"
hgroup.long 0x64EC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER157_upper,GICD_IROUTER157_upper"
group.long 0x64F0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER158_lower,GICD_IROUTER158_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER158_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER158_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER158_LOWER__0_8,A0"
hgroup.long 0x64F4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER158_upper,GICD_IROUTER158_upper"
group.long 0x64F8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER159_lower,GICD_IROUTER159_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER159_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER159_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER159_LOWER__0_8,A0"
hgroup.long 0x64FC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER159_upper,GICD_IROUTER159_upper"
group.long 0x6500++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER160_lower,GICD_IROUTER160_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER160_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER160_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER160_LOWER__0_8,A0"
hgroup.long 0x6504++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER160_upper,GICD_IROUTER160_upper"
group.long 0x6508++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER161_lower,GICD_IROUTER161_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER161_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER161_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER161_LOWER__0_8,A0"
hgroup.long 0x650C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER161_upper,GICD_IROUTER161_upper"
group.long 0x6510++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER162_lower,GICD_IROUTER162_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER162_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER162_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER162_LOWER__0_8,A0"
hgroup.long 0x6514++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER162_upper,GICD_IROUTER162_upper"
group.long 0x6518++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER163_lower,GICD_IROUTER163_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER163_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER163_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER163_LOWER__0_8,A0"
hgroup.long 0x651C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER163_upper,GICD_IROUTER163_upper"
group.long 0x6520++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER164_lower,GICD_IROUTER164_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER164_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER164_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER164_LOWER__0_8,A0"
hgroup.long 0x6524++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER164_upper,GICD_IROUTER164_upper"
group.long 0x6528++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER165_lower,GICD_IROUTER165_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER165_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER165_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER165_LOWER__0_8,A0"
hgroup.long 0x652C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER165_upper,GICD_IROUTER165_upper"
group.long 0x6530++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER166_lower,GICD_IROUTER166_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER166_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER166_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER166_LOWER__0_8,A0"
hgroup.long 0x6534++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER166_upper,GICD_IROUTER166_upper"
group.long 0x6538++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER167_lower,GICD_IROUTER167_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER167_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER167_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER167_LOWER__0_8,A0"
hgroup.long 0x653C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER167_upper,GICD_IROUTER167_upper"
group.long 0x6540++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER168_lower,GICD_IROUTER168_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER168_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER168_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER168_LOWER__0_8,A0"
hgroup.long 0x6544++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER168_upper,GICD_IROUTER168_upper"
group.long 0x6548++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER169_lower,GICD_IROUTER169_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER169_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER169_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER169_LOWER__0_8,A0"
hgroup.long 0x654C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER169_upper,GICD_IROUTER169_upper"
group.long 0x6550++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER170_lower,GICD_IROUTER170_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER170_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER170_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER170_LOWER__0_8,A0"
hgroup.long 0x6554++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER170_upper,GICD_IROUTER170_upper"
group.long 0x6558++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER171_lower,GICD_IROUTER171_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER171_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER171_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER171_LOWER__0_8,A0"
hgroup.long 0x655C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER171_upper,GICD_IROUTER171_upper"
group.long 0x6560++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER172_lower,GICD_IROUTER172_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER172_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER172_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER172_LOWER__0_8,A0"
hgroup.long 0x6564++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER172_upper,GICD_IROUTER172_upper"
group.long 0x6568++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER173_lower,GICD_IROUTER173_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER173_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER173_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER173_LOWER__0_8,A0"
hgroup.long 0x656C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER173_upper,GICD_IROUTER173_upper"
group.long 0x6570++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER174_lower,GICD_IROUTER174_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER174_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER174_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER174_LOWER__0_8,A0"
hgroup.long 0x6574++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER174_upper,GICD_IROUTER174_upper"
group.long 0x6578++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER175_lower,GICD_IROUTER175_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER175_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER175_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER175_LOWER__0_8,A0"
hgroup.long 0x657C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER175_upper,GICD_IROUTER175_upper"
group.long 0x6580++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER176_lower,GICD_IROUTER176_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER176_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER176_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER176_LOWER__0_8,A0"
hgroup.long 0x6584++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER176_upper,GICD_IROUTER176_upper"
group.long 0x6588++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER177_lower,GICD_IROUTER177_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER177_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER177_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER177_LOWER__0_8,A0"
hgroup.long 0x658C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER177_upper,GICD_IROUTER177_upper"
group.long 0x6590++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER178_lower,GICD_IROUTER178_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER178_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER178_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER178_LOWER__0_8,A0"
hgroup.long 0x6594++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER178_upper,GICD_IROUTER178_upper"
group.long 0x6598++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER179_lower,GICD_IROUTER179_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER179_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER179_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER179_LOWER__0_8,A0"
hgroup.long 0x659C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER179_upper,GICD_IROUTER179_upper"
group.long 0x65A0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER180_lower,GICD_IROUTER180_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER180_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER180_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER180_LOWER__0_8,A0"
hgroup.long 0x65A4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER180_upper,GICD_IROUTER180_upper"
group.long 0x65A8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER181_lower,GICD_IROUTER181_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER181_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER181_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER181_LOWER__0_8,A0"
hgroup.long 0x65AC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER181_upper,GICD_IROUTER181_upper"
group.long 0x65B0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER182_lower,GICD_IROUTER182_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER182_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER182_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER182_LOWER__0_8,A0"
hgroup.long 0x65B4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER182_upper,GICD_IROUTER182_upper"
group.long 0x65B8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER183_lower,GICD_IROUTER183_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER183_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER183_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER183_LOWER__0_8,A0"
hgroup.long 0x65BC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER183_upper,GICD_IROUTER183_upper"
group.long 0x65C0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER184_lower,GICD_IROUTER184_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER184_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER184_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER184_LOWER__0_8,A0"
hgroup.long 0x65C4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER184_upper,GICD_IROUTER184_upper"
group.long 0x65C8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER185_lower,GICD_IROUTER185_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER185_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER185_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER185_LOWER__0_8,A0"
hgroup.long 0x65CC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER185_upper,GICD_IROUTER185_upper"
group.long 0x65D0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER186_lower,GICD_IROUTER186_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER186_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER186_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER186_LOWER__0_8,A0"
hgroup.long 0x65D4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER186_upper,GICD_IROUTER186_upper"
group.long 0x65D8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER187_lower,GICD_IROUTER187_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER187_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER187_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER187_LOWER__0_8,A0"
hgroup.long 0x65DC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER187_upper,GICD_IROUTER187_upper"
group.long 0x65E0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER188_lower,GICD_IROUTER188_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER188_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER188_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER188_LOWER__0_8,A0"
hgroup.long 0x65E4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER188_upper,GICD_IROUTER188_upper"
group.long 0x65E8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER189_lower,GICD_IROUTER189_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER189_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER189_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER189_LOWER__0_8,A0"
hgroup.long 0x65EC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER189_upper,GICD_IROUTER189_upper"
group.long 0x65F0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER190_lower,GICD_IROUTER190_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER190_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER190_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER190_LOWER__0_8,A0"
hgroup.long 0x65F4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER190_upper,GICD_IROUTER190_upper"
group.long 0x65F8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER191_lower,GICD_IROUTER191_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER191_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER191_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER191_LOWER__0_8,A0"
hgroup.long 0x65FC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER191_upper,GICD_IROUTER191_upper"
group.long 0x6600++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER192_lower,GICD_IROUTER192_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER192_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER192_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER192_LOWER__0_8,A0"
hgroup.long 0x6604++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER192_upper,GICD_IROUTER192_upper"
group.long 0x6608++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER193_lower,GICD_IROUTER193_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER193_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER193_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER193_LOWER__0_8,A0"
hgroup.long 0x660C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER193_upper,GICD_IROUTER193_upper"
group.long 0x6610++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER194_lower,GICD_IROUTER194_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER194_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER194_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER194_LOWER__0_8,A0"
hgroup.long 0x6614++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER194_upper,GICD_IROUTER194_upper"
group.long 0x6618++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER195_lower,GICD_IROUTER195_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER195_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER195_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER195_LOWER__0_8,A0"
hgroup.long 0x661C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER195_upper,GICD_IROUTER195_upper"
group.long 0x6620++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER196_lower,GICD_IROUTER196_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER196_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER196_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER196_LOWER__0_8,A0"
hgroup.long 0x6624++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER196_upper,GICD_IROUTER196_upper"
group.long 0x6628++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER197_lower,GICD_IROUTER197_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER197_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER197_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER197_LOWER__0_8,A0"
hgroup.long 0x662C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER197_upper,GICD_IROUTER197_upper"
group.long 0x6630++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER198_lower,GICD_IROUTER198_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER198_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER198_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER198_LOWER__0_8,A0"
hgroup.long 0x6634++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER198_upper,GICD_IROUTER198_upper"
group.long 0x6638++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER199_lower,GICD_IROUTER199_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER199_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER199_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER199_LOWER__0_8,A0"
hgroup.long 0x663C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER199_upper,GICD_IROUTER199_upper"
group.long 0x6640++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER200_lower,GICD_IROUTER200_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER200_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER200_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER200_LOWER__0_8,A0"
hgroup.long 0x6644++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER200_upper,GICD_IROUTER200_upper"
group.long 0x6648++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER201_lower,GICD_IROUTER201_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER201_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER201_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER201_LOWER__0_8,A0"
hgroup.long 0x664C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER201_upper,GICD_IROUTER201_upper"
group.long 0x6650++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER202_lower,GICD_IROUTER202_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER202_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER202_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER202_LOWER__0_8,A0"
hgroup.long 0x6654++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER202_upper,GICD_IROUTER202_upper"
group.long 0x6658++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER203_lower,GICD_IROUTER203_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER203_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER203_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER203_LOWER__0_8,A0"
hgroup.long 0x665C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER203_upper,GICD_IROUTER203_upper"
group.long 0x6660++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER204_lower,GICD_IROUTER204_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER204_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER204_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER204_LOWER__0_8,A0"
hgroup.long 0x6664++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER204_upper,GICD_IROUTER204_upper"
group.long 0x6668++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER205_lower,GICD_IROUTER205_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER205_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER205_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER205_LOWER__0_8,A0"
hgroup.long 0x666C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER205_upper,GICD_IROUTER205_upper"
group.long 0x6670++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER206_lower,GICD_IROUTER206_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER206_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER206_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER206_LOWER__0_8,A0"
hgroup.long 0x6674++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER206_upper,GICD_IROUTER206_upper"
group.long 0x6678++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER207_lower,GICD_IROUTER207_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER207_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER207_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER207_LOWER__0_8,A0"
hgroup.long 0x667C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER207_upper,GICD_IROUTER207_upper"
group.long 0x6680++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER208_lower,GICD_IROUTER208_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER208_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER208_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER208_LOWER__0_8,A0"
hgroup.long 0x6684++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER208_upper,GICD_IROUTER208_upper"
group.long 0x6688++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER209_lower,GICD_IROUTER209_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER209_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER209_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER209_LOWER__0_8,A0"
hgroup.long 0x668C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER209_upper,GICD_IROUTER209_upper"
group.long 0x6690++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER210_lower,GICD_IROUTER210_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER210_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER210_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER210_LOWER__0_8,A0"
hgroup.long 0x6694++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER210_upper,GICD_IROUTER210_upper"
group.long 0x6698++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER211_lower,GICD_IROUTER211_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER211_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER211_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER211_LOWER__0_8,A0"
hgroup.long 0x669C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER211_upper,GICD_IROUTER211_upper"
group.long 0x66A0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER212_lower,GICD_IROUTER212_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER212_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER212_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER212_LOWER__0_8,A0"
hgroup.long 0x66A4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER212_upper,GICD_IROUTER212_upper"
group.long 0x66A8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER213_lower,GICD_IROUTER213_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER213_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER213_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER213_LOWER__0_8,A0"
hgroup.long 0x66AC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER213_upper,GICD_IROUTER213_upper"
group.long 0x66B0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER214_lower,GICD_IROUTER214_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER214_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER214_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER214_LOWER__0_8,A0"
hgroup.long 0x66B4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER214_upper,GICD_IROUTER214_upper"
group.long 0x66B8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER215_lower,GICD_IROUTER215_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER215_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER215_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER215_LOWER__0_8,A0"
hgroup.long 0x66BC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER215_upper,GICD_IROUTER215_upper"
group.long 0x66C0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER216_lower,GICD_IROUTER216_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER216_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER216_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER216_LOWER__0_8,A0"
hgroup.long 0x66C4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER216_upper,GICD_IROUTER216_upper"
group.long 0x66C8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER217_lower,GICD_IROUTER217_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER217_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER217_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER217_LOWER__0_8,A0"
hgroup.long 0x66CC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER217_upper,GICD_IROUTER217_upper"
group.long 0x66D0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER218_lower,GICD_IROUTER218_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER218_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER218_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER218_LOWER__0_8,A0"
hgroup.long 0x66D4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER218_upper,GICD_IROUTER218_upper"
group.long 0x66D8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER219_lower,GICD_IROUTER219_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER219_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER219_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER219_LOWER__0_8,A0"
hgroup.long 0x66DC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER219_upper,GICD_IROUTER219_upper"
group.long 0x66E0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER220_lower,GICD_IROUTER220_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER220_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER220_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER220_LOWER__0_8,A0"
hgroup.long 0x66E4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER220_upper,GICD_IROUTER220_upper"
group.long 0x66E8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER221_lower,GICD_IROUTER221_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER221_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER221_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER221_LOWER__0_8,A0"
hgroup.long 0x66EC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER221_upper,GICD_IROUTER221_upper"
group.long 0x66F0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER222_lower,GICD_IROUTER222_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER222_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER222_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER222_LOWER__0_8,A0"
hgroup.long 0x66F4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER222_upper,GICD_IROUTER222_upper"
group.long 0x66F8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER223_lower,GICD_IROUTER223_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER223_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER223_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER223_LOWER__0_8,A0"
hgroup.long 0x66FC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER223_upper,GICD_IROUTER223_upper"
group.long 0x6700++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER224_lower,GICD_IROUTER224_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER224_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER224_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER224_LOWER__0_8,A0"
hgroup.long 0x6704++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER224_upper,GICD_IROUTER224_upper"
group.long 0x6708++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER225_lower,GICD_IROUTER225_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER225_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER225_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER225_LOWER__0_8,A0"
hgroup.long 0x670C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER225_upper,GICD_IROUTER225_upper"
group.long 0x6710++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER226_lower,GICD_IROUTER226_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER226_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER226_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER226_LOWER__0_8,A0"
hgroup.long 0x6714++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER226_upper,GICD_IROUTER226_upper"
group.long 0x6718++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER227_lower,GICD_IROUTER227_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER227_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER227_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER227_LOWER__0_8,A0"
hgroup.long 0x671C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER227_upper,GICD_IROUTER227_upper"
group.long 0x6720++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER228_lower,GICD_IROUTER228_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER228_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER228_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER228_LOWER__0_8,A0"
hgroup.long 0x6724++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER228_upper,GICD_IROUTER228_upper"
group.long 0x6728++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER229_lower,GICD_IROUTER229_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER229_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER229_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER229_LOWER__0_8,A0"
hgroup.long 0x672C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER229_upper,GICD_IROUTER229_upper"
group.long 0x6730++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER230_lower,GICD_IROUTER230_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER230_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER230_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER230_LOWER__0_8,A0"
hgroup.long 0x6734++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER230_upper,GICD_IROUTER230_upper"
group.long 0x6738++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER231_lower,GICD_IROUTER231_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER231_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER231_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER231_LOWER__0_8,A0"
hgroup.long 0x673C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER231_upper,GICD_IROUTER231_upper"
group.long 0x6740++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER232_lower,GICD_IROUTER232_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER232_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER232_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER232_LOWER__0_8,A0"
hgroup.long 0x6744++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER232_upper,GICD_IROUTER232_upper"
group.long 0x6748++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER233_lower,GICD_IROUTER233_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER233_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER233_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER233_LOWER__0_8,A0"
hgroup.long 0x674C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER233_upper,GICD_IROUTER233_upper"
group.long 0x6750++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER234_lower,GICD_IROUTER234_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER234_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER234_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER234_LOWER__0_8,A0"
hgroup.long 0x6754++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER234_upper,GICD_IROUTER234_upper"
group.long 0x6758++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER235_lower,GICD_IROUTER235_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER235_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER235_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER235_LOWER__0_8,A0"
hgroup.long 0x675C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER235_upper,GICD_IROUTER235_upper"
group.long 0x6760++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER236_lower,GICD_IROUTER236_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER236_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER236_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER236_LOWER__0_8,A0"
hgroup.long 0x6764++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER236_upper,GICD_IROUTER236_upper"
group.long 0x6768++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER237_lower,GICD_IROUTER237_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER237_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER237_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER237_LOWER__0_8,A0"
hgroup.long 0x676C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER237_upper,GICD_IROUTER237_upper"
group.long 0x6770++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER238_lower,GICD_IROUTER238_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER238_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER238_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER238_LOWER__0_8,A0"
hgroup.long 0x6774++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER238_upper,GICD_IROUTER238_upper"
group.long 0x6778++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER239_lower,GICD_IROUTER239_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER239_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER239_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER239_LOWER__0_8,A0"
hgroup.long 0x677C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER239_upper,GICD_IROUTER239_upper"
group.long 0x6780++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER240_lower,GICD_IROUTER240_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER240_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER240_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER240_LOWER__0_8,A0"
hgroup.long 0x6784++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER240_upper,GICD_IROUTER240_upper"
group.long 0x6788++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER241_lower,GICD_IROUTER241_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER241_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER241_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER241_LOWER__0_8,A0"
hgroup.long 0x678C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER241_upper,GICD_IROUTER241_upper"
group.long 0x6790++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER242_lower,GICD_IROUTER242_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER242_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER242_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER242_LOWER__0_8,A0"
hgroup.long 0x6794++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER242_upper,GICD_IROUTER242_upper"
group.long 0x6798++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER243_lower,GICD_IROUTER243_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER243_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER243_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER243_LOWER__0_8,A0"
hgroup.long 0x679C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER243_upper,GICD_IROUTER243_upper"
group.long 0x67A0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER244_lower,GICD_IROUTER244_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER244_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER244_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER244_LOWER__0_8,A0"
hgroup.long 0x67A4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER244_upper,GICD_IROUTER244_upper"
group.long 0x67A8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER245_lower,GICD_IROUTER245_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER245_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER245_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER245_LOWER__0_8,A0"
hgroup.long 0x67AC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER245_upper,GICD_IROUTER245_upper"
group.long 0x67B0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER246_lower,GICD_IROUTER246_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER246_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER246_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER246_LOWER__0_8,A0"
hgroup.long 0x67B4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER246_upper,GICD_IROUTER246_upper"
group.long 0x67B8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER247_lower,GICD_IROUTER247_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER247_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER247_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER247_LOWER__0_8,A0"
hgroup.long 0x67BC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER247_upper,GICD_IROUTER247_upper"
group.long 0x67C0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER248_lower,GICD_IROUTER248_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER248_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER248_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER248_LOWER__0_8,A0"
hgroup.long 0x67C4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER248_upper,GICD_IROUTER248_upper"
group.long 0x67C8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER249_lower,GICD_IROUTER249_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER249_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER249_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER249_LOWER__0_8,A0"
hgroup.long 0x67CC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER249_upper,GICD_IROUTER249_upper"
group.long 0x67D0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER250_lower,GICD_IROUTER250_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER250_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER250_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER250_LOWER__0_8,A0"
hgroup.long 0x67D4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER250_upper,GICD_IROUTER250_upper"
group.long 0x67D8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER251_lower,GICD_IROUTER251_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER251_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER251_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER251_LOWER__0_8,A0"
hgroup.long 0x67DC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER251_upper,GICD_IROUTER251_upper"
group.long 0x67E0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER252_lower,GICD_IROUTER252_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER252_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER252_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER252_LOWER__0_8,A0"
hgroup.long 0x67E4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER252_upper,GICD_IROUTER252_upper"
group.long 0x67E8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER253_lower,GICD_IROUTER253_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER253_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER253_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER253_LOWER__0_8,A0"
hgroup.long 0x67EC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER253_upper,GICD_IROUTER253_upper"
group.long 0x67F0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER254_lower,GICD_IROUTER254_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER254_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER254_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER254_LOWER__0_8,A0"
hgroup.long 0x67F4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER254_upper,GICD_IROUTER254_upper"
group.long 0x67F8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER255_lower,GICD_IROUTER255_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER255_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER255_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER255_LOWER__0_8,A0"
hgroup.long 0x67FC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER255_upper,GICD_IROUTER255_upper"
group.long 0x6800++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER256_lower,GICD_IROUTER256_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER256_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER256_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER256_LOWER__0_8,A0"
hgroup.long 0x6804++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER256_upper,GICD_IROUTER256_upper"
group.long 0x6808++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER257_lower,GICD_IROUTER257_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER257_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER257_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER257_LOWER__0_8,A0"
hgroup.long 0x680C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER257_upper,GICD_IROUTER257_upper"
group.long 0x6810++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER258_lower,GICD_IROUTER258_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER258_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER258_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER258_LOWER__0_8,A0"
hgroup.long 0x6814++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER258_upper,GICD_IROUTER258_upper"
group.long 0x6818++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER259_lower,GICD_IROUTER259_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER259_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER259_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER259_LOWER__0_8,A0"
hgroup.long 0x681C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER259_upper,GICD_IROUTER259_upper"
group.long 0x6820++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER260_lower,GICD_IROUTER260_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER260_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER260_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER260_LOWER__0_8,A0"
hgroup.long 0x6824++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER260_upper,GICD_IROUTER260_upper"
group.long 0x6828++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER261_lower,GICD_IROUTER261_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER261_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER261_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER261_LOWER__0_8,A0"
hgroup.long 0x682C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER261_upper,GICD_IROUTER261_upper"
group.long 0x6830++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER262_lower,GICD_IROUTER262_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER262_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER262_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER262_LOWER__0_8,A0"
hgroup.long 0x6834++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER262_upper,GICD_IROUTER262_upper"
group.long 0x6838++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER263_lower,GICD_IROUTER263_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER263_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER263_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER263_LOWER__0_8,A0"
hgroup.long 0x683C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER263_upper,GICD_IROUTER263_upper"
group.long 0x6840++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER264_lower,GICD_IROUTER264_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER264_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER264_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER264_LOWER__0_8,A0"
hgroup.long 0x6844++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER264_upper,GICD_IROUTER264_upper"
group.long 0x6848++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER265_lower,GICD_IROUTER265_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER265_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER265_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER265_LOWER__0_8,A0"
hgroup.long 0x684C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER265_upper,GICD_IROUTER265_upper"
group.long 0x6850++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER266_lower,GICD_IROUTER266_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER266_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER266_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER266_LOWER__0_8,A0"
hgroup.long 0x6854++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER266_upper,GICD_IROUTER266_upper"
group.long 0x6858++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER267_lower,GICD_IROUTER267_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER267_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER267_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER267_LOWER__0_8,A0"
hgroup.long 0x685C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER267_upper,GICD_IROUTER267_upper"
group.long 0x6860++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER268_lower,GICD_IROUTER268_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER268_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER268_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER268_LOWER__0_8,A0"
hgroup.long 0x6864++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER268_upper,GICD_IROUTER268_upper"
group.long 0x6868++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER269_lower,GICD_IROUTER269_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER269_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER269_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER269_LOWER__0_8,A0"
hgroup.long 0x686C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER269_upper,GICD_IROUTER269_upper"
group.long 0x6870++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER270_lower,GICD_IROUTER270_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER270_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER270_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER270_LOWER__0_8,A0"
hgroup.long 0x6874++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER270_upper,GICD_IROUTER270_upper"
group.long 0x6878++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER271_lower,GICD_IROUTER271_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER271_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER271_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER271_LOWER__0_8,A0"
hgroup.long 0x687C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER271_upper,GICD_IROUTER271_upper"
group.long 0x6880++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER272_lower,GICD_IROUTER272_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER272_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER272_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER272_LOWER__0_8,A0"
hgroup.long 0x6884++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER272_upper,GICD_IROUTER272_upper"
group.long 0x6888++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER273_lower,GICD_IROUTER273_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER273_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER273_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER273_LOWER__0_8,A0"
hgroup.long 0x688C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER273_upper,GICD_IROUTER273_upper"
group.long 0x6890++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER274_lower,GICD_IROUTER274_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER274_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER274_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER274_LOWER__0_8,A0"
hgroup.long 0x6894++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER274_upper,GICD_IROUTER274_upper"
group.long 0x6898++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER275_lower,GICD_IROUTER275_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER275_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER275_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER275_LOWER__0_8,A0"
hgroup.long 0x689C++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER275_upper,GICD_IROUTER275_upper"
group.long 0x68A0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER276_lower,GICD_IROUTER276_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER276_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER276_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER276_LOWER__0_8,A0"
hgroup.long 0x68A4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER276_upper,GICD_IROUTER276_upper"
group.long 0x68A8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER277_lower,GICD_IROUTER277_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER277_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER277_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER277_LOWER__0_8,A0"
hgroup.long 0x68AC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER277_upper,GICD_IROUTER277_upper"
group.long 0x68B0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER278_lower,GICD_IROUTER278_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER278_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER278_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER278_LOWER__0_8,A0"
hgroup.long 0x68B4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER278_upper,GICD_IROUTER278_upper"
group.long 0x68B8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER279_lower,GICD_IROUTER279_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER279_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER279_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER279_LOWER__0_8,A0"
hgroup.long 0x68BC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER279_upper,GICD_IROUTER279_upper"
group.long 0x68C0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER280_lower,GICD_IROUTER280_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER280_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER280_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER280_LOWER__0_8,A0"
hgroup.long 0x68C4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER280_upper,GICD_IROUTER280_upper"
group.long 0x68C8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER281_lower,GICD_IROUTER281_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER281_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER281_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER281_LOWER__0_8,A0"
hgroup.long 0x68CC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER281_upper,GICD_IROUTER281_upper"
group.long 0x68D0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER282_lower,GICD_IROUTER282_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER282_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER282_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER282_LOWER__0_8,A0"
hgroup.long 0x68D4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER282_upper,GICD_IROUTER282_upper"
group.long 0x68D8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER283_lower,GICD_IROUTER283_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER283_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER283_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER283_LOWER__0_8,A0"
hgroup.long 0x68DC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER283_upper,GICD_IROUTER283_upper"
group.long 0x68E0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER284_lower,GICD_IROUTER284_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER284_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER284_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER284_LOWER__0_8,A0"
hgroup.long 0x68E4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER284_upper,GICD_IROUTER284_upper"
group.long 0x68E8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER285_lower,GICD_IROUTER285_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER285_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER285_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER285_LOWER__0_8,A0"
hgroup.long 0x68EC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER285_upper,GICD_IROUTER285_upper"
group.long 0x68F0++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER286_lower,GICD_IROUTER286_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER286_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER286_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER286_LOWER__0_8,A0"
hgroup.long 0x68F4++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER286_upper,GICD_IROUTER286_upper"
group.long 0x68F8++0x03
line.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER287_lower,GICD_IROUTER287_lower"
bitfld.long 0x00 31. "DISTRIBUTOR__37_GICD_IROUTER287_LOWER__31_1,IRM" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "DISTRIBUTOR__37_GICD_IROUTER287_LOWER__8_8,A1"
newline
hexmask.long.byte 0x00 0.--7. 1. "DISTRIBUTOR__37_GICD_IROUTER287_LOWER__0_8,A0"
hgroup.long 0x68FC++0x03
hide.long 0x00 "GIC_REGS_Distributor__37_GICD_IROUTER287_upper,GICD_IROUTER287_upper"
group.long 0xC000++0x07
line.long 0x00 "GIC_REGS_Distributor__38_GICD_ESTATUSR,GICD_ESTATUSR"
bitfld.long 0x00 31. "DISTRIBUTOR__38_GICD_ESTATUSR__31_1,SWRP" "0,1"
line.long 0x04 "GIC_REGS_Distributor__39_GICD_ERRTESTR,GICD_ERRTESTR"
bitfld.long 0x04 1. "DISTRIBUTOR__39_GICD_ERRTESTR__1_1,AXIM_err" "0,1"
newline
bitfld.long 0x04 0. "DISTRIBUTOR__39_GICD_ERRTESTR__0_1,ECC_fatal" "0,1"
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
hgroup.long ($2+0xC084)++0x03
hide.long 0x00 "GIC_REGS_Distributor__40_GICD_SPISR$1,GICD_SPISR0"
repeat.end
hgroup.long 0xFFD0++0x2F
hide.long 0x00 "GIC_REGS_Distributor__41_GICD_PIDR4,GICD_PIDR4"
hide.long 0x04 "GIC_REGS_Distributor__42_GICD_PIDR5,GICD_PIDR5"
hide.long 0x08 "GIC_REGS_Distributor__43_GICD_PIDR6,GICD_PIDR6"
hide.long 0x0C "GIC_REGS_Distributor__44_GICD_PIDR7,GICD_PIDR7"
hide.long 0x10 "GIC_REGS_Distributor__45_GICD_PIDR0,GICD_PIDR0"
hide.long 0x14 "GIC_REGS_Distributor__46_GICD_PIDR1,GICD_PIDR1"
hide.long 0x18 "GIC_REGS_Distributor__47_GICD_PIDR2,GICD_PIDR2"
hide.long 0x1C "GIC_REGS_Distributor__48_GICD_PIDR3,GICD_PIDR3"
hide.long 0x20 "GIC_REGS_Distributor__49_GICD_CIDR0,GICD_CIDR0"
hide.long 0x24 "GIC_REGS_Distributor__50_GICD_CIDR1,GICD_CIDR1"
hide.long 0x28 "GIC_REGS_Distributor__51_GICD_CIDR2,GICD_CIDR2"
hide.long 0x2C "GIC_REGS_Distributor__52_GICD_CIDR3,GICD_CIDR3"
group.long 0x10040++0x03
line.long 0x00 "GIC_REGS_Message_based_SPIs__1_GICD_SETSPI_NSR,GICD_SETSPI_NSR"
hexmask.long.word 0x00 0.--9. 1. "MESSAGE_BASED_SPIS__1_GICD_SETSPI_NSR__0_10,SPI ID"
group.long 0x10048++0x03
line.long 0x00 "GIC_REGS_Message_based_SPIs__2_GICD_CLRSPI_NSR,GICD_CLRSPI_NSR"
hexmask.long.word 0x00 0.--9. 1. "MESSAGE_BASED_SPIS__2_GICD_CLRSPI_NSR__0_10,SPI ID"
group.long 0x10050++0x03
line.long 0x00 "GIC_REGS_Message_based_SPIs__3_GICD_SETSPI_SR,GICD_SETSPI_SR"
hexmask.long.word 0x00 0.--9. 1. "MESSAGE_BASED_SPIS__3_GICD_SETSPI_SR__0_10,SPI ID"
group.long 0x10058++0x03
line.long 0x00 "GIC_REGS_Message_based_SPIs__4_GICD_CLRSPI_SR,GICD_CLRSPI_SR"
hexmask.long.word 0x00 0.--9. 1. "MESSAGE_BASED_SPIS__4_GICD_CLRSPI_SR__0_10,SPI ID"
group.long 0x20000++0x0B
line.long 0x00 "GIC_REGS_ITS__1_GITS_CTLR,GITS_CTLR"
bitfld.long 0x00 31. "ITS__1_GITS_CTLR__31_1,Quiescent" "0,1"
newline
bitfld.long 0x00 0. "ITS__1_GITS_CTLR__0_1,Enabled" "0,1"
line.long 0x04 "GIC_REGS_ITS__2_GITS_IIDR,GITS_IIDR"
hexmask.long.byte 0x04 24.--31. 1. "ITS__2_GITS_IIDR__24_8,ProductID"
newline
bitfld.long 0x04 16.--19. "ITS__2_GITS_IIDR__16_4,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 12.--15. "ITS__2_GITS_IIDR__12_4,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 0.--11. 1. "ITS__2_GITS_IIDR__0_12,Implementer"
line.long 0x08 "GIC_REGS_ITS__3_GITS_TYPER_lower,GITS_TYPER_lower"
hexmask.long.byte 0x08 24.--31. 1. "ITS__3_GITS_TYPER_LOWER__24_8,HCC"
newline
bitfld.long 0x08 19. "ITS__3_GITS_TYPER_LOWER__19_1,PTA" "0,1"
newline
bitfld.long 0x08 13.--17. "ITS__3_GITS_TYPER_LOWER__13_5,Devbits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 8.--12. "ITS__3_GITS_TYPER_LOWER__8_5,IDbits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 4.--7. "ITS__3_GITS_TYPER_LOWER__4_4,ITT Entry Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 3. "ITS__3_GITS_TYPER_LOWER__3_1,Distributed" "0,1"
newline
bitfld.long 0x08 1. "ITS__3_GITS_TYPER_LOWER__1_1,VLPIS" "0,1"
newline
bitfld.long 0x08 0. "ITS__3_GITS_TYPER_LOWER__0_1,PLPIS" "0,1"
hgroup.long 0x2000C++0x03
hide.long 0x00 "GIC_REGS_ITS__4_GITS_TYPER_upper,GITS_TYPER_upper"
group.long 0x20080++0x0B
line.long 0x00 "GIC_REGS_ITS__5_GITS_CBASER_lower,GITS_CBASER_lower"
hexmask.long.tbyte 0x00 12.--31. 1. "ITS__5_GITS_CBASER_LOWER__12_20,Physical Address [31:12]"
newline
hexmask.long.byte 0x00 0.--7. 1. "ITS__5_GITS_CBASER_LOWER__0_8,Size"
line.long 0x04 "GIC_REGS_ITS__6_GITS_CBASER_upper,GITS_CBASER_upper"
bitfld.long 0x04 31. "ITS__6_GITS_CBASER_UPPER__31_1,Valid" "0,1"
newline
bitfld.long 0x04 27.--29. "ITS__6_GITS_CBASER_UPPER__27_3,Cacheability" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x04 0.--15. 1. "ITS__6_GITS_CBASER_UPPER__0_16,Physical Address [47:32]"
line.long 0x08 "GIC_REGS_ITS__7_GITS_CWRITER_lower,GITS_CWRITER_lower"
hexmask.long.word 0x08 5.--19. 1. "ITS__7_GITS_CWRITER_LOWER__5_15,Offset"
hgroup.long 0x2008C++0x03
hide.long 0x00 "GIC_REGS_ITS__8_GITS_CWRITER_upper,GITS_CWRITER_upper"
group.long 0x20090++0x03
line.long 0x00 "GIC_REGS_ITS__9_GITS_CREADR_lower,GITS_CREADR_lower"
hexmask.long.word 0x00 5.--19. 1. "ITS__9_GITS_CREADR_LOWER__5_15,Offset"
hgroup.long 0x20094++0x03
hide.long 0x00 "GIC_REGS_ITS__10_GITS_CREADR_upper,GITS_CREADR_upper"
group.long 0x20100++0x07
line.long 0x00 "GIC_REGS_ITS__11_GITS_BASER0_lower,GITS_BASER0_lower"
hexmask.long.tbyte 0x00 12.--31. 1. "ITS__11_GITS_BASER0_LOWER__12_20,Physical Address [31:12]"
newline
bitfld.long 0x00 8.--9. "ITS__11_GITS_BASER0_LOWER__8_2,Page Size" "0,1,2,3"
newline
hexmask.long.byte 0x00 0.--7. 1. "ITS__11_GITS_BASER0_LOWER__0_8,Size"
line.long 0x04 "GIC_REGS_ITS__12_GITS_BASER0_upper,GITS_BASER0_upper"
bitfld.long 0x04 24.--26. "ITS__12_GITS_BASER0_UPPER__24_3,Type" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x04 16.--23. 1. "ITS__12_GITS_BASER0_UPPER__16_8,Entry Size"
newline
hexmask.long.word 0x04 0.--15. 1. "ITS__12_GITS_BASER0_UPPER__0_16,Physical Address [47:32]"
group.long 0x2C000++0x1F
line.long 0x00 "GIC_REGS_ITS__13_GITS_TRKCTLR,GITS_TRKCTLR"
bitfld.long 0x00 1. "ITS__13_GITS_TRKCTLR__1_1,ITS track" "0,1"
newline
bitfld.long 0x00 0. "ITS__13_GITS_TRKCTLR__0_1,Cache count reset" "0,1"
line.long 0x04 "GIC_REGS_ITS__14_GITS_TRKR,GITS_TRKR"
bitfld.long 0x04 5. "ITS__14_GITS_TRKR__5_1,Translated ID out of range" "0,1"
newline
bitfld.long 0x04 4. "ITS__14_GITS_TRKR__4_1,Target CPU out of range" "0,1"
newline
bitfld.long 0x04 3. "ITS__14_GITS_TRKR__3_1,DID/ID not mapped" "0,1"
newline
bitfld.long 0x04 2. "ITS__14_GITS_TRKR__2_1,Input ID out of range" "0,1"
newline
bitfld.long 0x04 1. "ITS__14_GITS_TRKR__1_1,DID unmapped" "0,1"
newline
bitfld.long 0x04 0. "ITS__14_GITS_TRKR__0_1,DID out of range" "0,1"
line.long 0x08 "GIC_REGS_ITS__15_GITS_TRKDIDR,GITS_TRKDIDR"
hexmask.long.tbyte 0x08 0.--19. 1. "ITS__15_GITS_TRKDIDR__0_20,DID"
line.long 0x0C "GIC_REGS_ITS__16_GITS_TRKPIDR,GITS_TRKPIDR"
hexmask.long.word 0x0C 0.--15. 1. "ITS__16_GITS_TRKPIDR__0_16,Translated ID"
line.long 0x10 "GIC_REGS_ITS__17_GITS_TRKVIDR,GITS_TRKVIDR"
hexmask.long.word 0x10 0.--15. 1. "ITS__17_GITS_TRKVIDR__0_16,Input ID"
line.long 0x14 "GIC_REGS_ITS__18_GITS_TRKTGTR,GITS_TRKTGTR"
hexmask.long.byte 0x14 0.--6. 1. "ITS__18_GITS_TRKTGTR__0_7,Target CPU"
line.long 0x18 "GIC_REGS_ITS__19_GITS_TRKICR,GITS_TRKICR"
hexmask.long.word 0x18 16.--31. 1. "ITS__19_GITS_TRKICR__16_16,ITE cache hits"
newline
hexmask.long.word 0x18 0.--15. 1. "ITS__19_GITS_TRKICR__0_16,ITE cache misses"
line.long 0x1C "GIC_REGS_ITS__20_GITS_TRKLCR,GITS_TRKLCR"
hexmask.long.word 0x1C 16.--31. 1. "ITS__20_GITS_TRKLCR__16_16,LPI cache hits"
newline
hexmask.long.word 0x1C 0.--15. 1. "ITS__20_GITS_TRKLCR__0_16,LPI cache misses"
hgroup.long 0x2FFD0++0x2F
hide.long 0x00 "GIC_REGS_ITS__21_GITS_PIDR4,GITS_PIDR4"
hide.long 0x04 "GIC_REGS_ITS__22_GITS_PIDR5,GITS_PIDR5"
hide.long 0x08 "GIC_REGS_ITS__23_GITS_PIDR6,GITS_PIDR6"
hide.long 0x0C "GIC_REGS_ITS__24_GITS_PIDR7,GITS_PIDR7"
hide.long 0x10 "GIC_REGS_ITS__25_GITS_PIDR0,GITS_PIDR0"
hide.long 0x14 "GIC_REGS_ITS__26_GITS_PIDR1,GITS_PIDR1"
hide.long 0x18 "GIC_REGS_ITS__27_GITS_PIDR2,GITS_PIDR2"
hide.long 0x1C "GIC_REGS_ITS__28_GITS_PIDR3,GITS_PIDR3"
hide.long 0x20 "GIC_REGS_ITS__29_GITS_CIDR0,GITS_CIDR0"
hide.long 0x24 "GIC_REGS_ITS__30_GITS_CIDR1,GITS_CIDR1"
hide.long 0x28 "GIC_REGS_ITS__31_GITS_CIDR2,GITS_CIDR2"
hide.long 0x2C "GIC_REGS_ITS__32_GITS_CIDR3,GITS_CIDR3"
group.long 0x40000++0x0F
line.long 0x00 "GIC_REGS_Redistributor_control_LPI_0__2_GICR_CTLR,GICR_CTLR"
bitfld.long 0x00 31. "REDISTRIBUTOR_CONTROL_LPI_0__2_GICR_CTLR__31_1,Upstream Write Pending" "0,1"
newline
bitfld.long 0x00 3. "REDISTRIBUTOR_CONTROL_LPI_0__2_GICR_CTLR__3_1,Register Write Pending" "0,1"
newline
bitfld.long 0x00 0. "REDISTRIBUTOR_CONTROL_LPI_0__2_GICR_CTLR__0_1,Enable LPIs" "0,1"
line.long 0x04 "GIC_REGS_Redistributor_control_LPI_0__3_GICR_IIDR,GICR_IIDR"
hexmask.long.byte 0x04 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_0__3_GICR_IIDR__24_8,ProductID"
newline
bitfld.long 0x04 16.--19. "REDISTRIBUTOR_CONTROL_LPI_0__3_GICR_IIDR__16_4,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 12.--15. "REDISTRIBUTOR_CONTROL_LPI_0__3_GICR_IIDR__12_4,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 0.--11. 1. "REDISTRIBUTOR_CONTROL_LPI_0__3_GICR_IIDR__0_12,Implementer"
line.long 0x08 "GIC_REGS_Redistributor_control_LPI_0__4_GICR_TYPER_lower,GICR_TYPER_lower"
hexmask.long.word 0x08 8.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_0__4_GICR_TYPER_LOWER__8_16,Processor Number"
newline
bitfld.long 0x08 4. "REDISTRIBUTOR_CONTROL_LPI_0__4_GICR_TYPER_LOWER__4_1,Last" "0,1"
newline
bitfld.long 0x08 3. "REDISTRIBUTOR_CONTROL_LPI_0__4_GICR_TYPER_LOWER__3_1,Distributed" "0,1"
newline
bitfld.long 0x08 1. "REDISTRIBUTOR_CONTROL_LPI_0__4_GICR_TYPER_LOWER__1_1,VLPIS" "0,1"
newline
bitfld.long 0x08 0. "REDISTRIBUTOR_CONTROL_LPI_0__4_GICR_TYPER_LOWER__0_1,PLPIS" "0,1"
line.long 0x0C "GIC_REGS_Redistributor_control_LPI_0__5_GICR_TYPER_upper,GICR_TYPER_upper"
hexmask.long.byte 0x0C 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_0__5_GICR_TYPER_UPPER__24_8,A3"
newline
hexmask.long.byte 0x0C 16.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_0__5_GICR_TYPER_UPPER__16_8,A2"
newline
hexmask.long.byte 0x0C 8.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_0__5_GICR_TYPER_UPPER__8_8,A1"
newline
hexmask.long.byte 0x0C 0.--7. 1. "REDISTRIBUTOR_CONTROL_LPI_0__5_GICR_TYPER_UPPER__0_8,A0"
group.long 0x40014++0x03
line.long 0x00 "GIC_REGS_Redistributor_control_LPI_0__6_GICR_WAKER,GICR_WAKER"
bitfld.long 0x00 31. "REDISTRIBUTOR_CONTROL_LPI_0__6_GICR_WAKER__31_1,Quiescent" "0,1"
newline
bitfld.long 0x00 2. "REDISTRIBUTOR_CONTROL_LPI_0__6_GICR_WAKER__2_1,ChildrenAsleep" "0,1"
newline
bitfld.long 0x00 1. "REDISTRIBUTOR_CONTROL_LPI_0__6_GICR_WAKER__1_1,ProcessorSleep" "0,1"
newline
bitfld.long 0x00 0. "REDISTRIBUTOR_CONTROL_LPI_0__6_GICR_WAKER__0_1,Sleep" "0,1"
group.long 0x40070++0x0F
line.long 0x00 "GIC_REGS_Redistributor_control_LPI_0__7_GICR_PROPBASER_lower,GICR_PROPBASER_lower"
hexmask.long.tbyte 0x00 12.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_0__7_GICR_PROPBASER_LOWER__12_20,Physical Address [31:12]"
newline
bitfld.long 0x00 7.--9. "REDISTRIBUTOR_CONTROL_LPI_0__7_GICR_PROPBASER_LOWER__7_3,Cacheability" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "REDISTRIBUTOR_CONTROL_LPI_0__7_GICR_PROPBASER_LOWER__0_5,Idbits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "GIC_REGS_Redistributor_control_LPI_0__8_GICR_PROPBASER_upper,GICR_PROPBASER_upper"
hexmask.long.word 0x04 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_0__8_GICR_PROPBASER_UPPER__0_16,Physical Address [47:32]"
line.long 0x08 "GIC_REGS_Redistributor_control_LPI_0__9_GICR_PENDBASER_lower,GICR_PENDBASER_lower"
hexmask.long.word 0x08 16.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_0__9_GICR_PENDBASER_LOWER__16_16,Physical Address [31:16]"
newline
bitfld.long 0x08 7.--9. "REDISTRIBUTOR_CONTROL_LPI_0__9_GICR_PENDBASER_LOWER__7_3,Cacheability" "0,1,2,3,4,5,6,7"
line.long 0x0C "GIC_REGS_Redistributor_control_LPI_0__10_GICR_PENDBASER_upper,GICR_PENDBASER_upper"
bitfld.long 0x0C 30. "REDISTRIBUTOR_CONTROL_LPI_0__10_GICR_PENDBASER_UPPER__30_1,Pending Table Zero" "0,1"
newline
hexmask.long.word 0x0C 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_0__10_GICR_PENDBASER_UPPER__0_16,Physical Address [47:32]"
hgroup.long 0x4FFD0++0x2F
hide.long 0x00 "GIC_REGS_Redistributor_control_LPI_0__11_GICR_PIDR4,GICR_PIDR4"
hide.long 0x04 "GIC_REGS_Redistributor_control_LPI_0__12_GICR_PIDR5,GICR_PIDR5"
hide.long 0x08 "GIC_REGS_Redistributor_control_LPI_0__13_GICR_PIDR6,GICR_PIDR6"
hide.long 0x0C "GIC_REGS_Redistributor_control_LPI_0__14_GICR_PIDR7,GICR_PIDR7"
hide.long 0x10 "GIC_REGS_Redistributor_control_LPI_0__15_GICR_PIDR0,GICR_PIDR0"
hide.long 0x14 "GIC_REGS_Redistributor_control_LPI_0__16_GICR_PIDR1,GICR_PIDR1"
hide.long 0x18 "GIC_REGS_Redistributor_control_LPI_0__17_GICR_PIDR2,GICR_PIDR2"
hide.long 0x1C "GIC_REGS_Redistributor_control_LPI_0__18_GICR_PIDR3,GICR_PIDR3"
hide.long 0x20 "GIC_REGS_Redistributor_control_LPI_0__19_GICR_CIDR0,GICR_CIDR0"
hide.long 0x24 "GIC_REGS_Redistributor_control_LPI_0__20_GICR_CIDR1,GICR_CIDR1"
hide.long 0x28 "GIC_REGS_Redistributor_control_LPI_0__21_GICR_CIDR2,GICR_CIDR2"
hide.long 0x2C "GIC_REGS_Redistributor_control_LPI_0__22_GICR_CIDR3,GICR_CIDR3"
hgroup.long 0x50080++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_0__1_GICR_IGROUPR0,GICR_IGROUPR0"
hgroup.long 0x50100++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_0__2_GICR_ISENABLER0,GICR_ISENABLER0"
hgroup.long 0x50180++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_0__3_GICR_ICENABLER0,GICR_ICENABLER0"
hgroup.long 0x50200++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_0__4_GICR_ISPENDR0,GICR_ISPENDR0"
hgroup.long 0x50280++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_0__5_GICR_ICPENDR0,GICR_ICPENDR0"
hgroup.long 0x50300++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_0__6_GICR_ISACTIVER0,GICR_ISACTIVER0"
hgroup.long 0x50380++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_0__7_GICR_ICACTIVER0,GICR_ICACTIVER0"
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
hgroup.long ($2+0x50400)++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_0__8_GICR_IPRIORITYR$1,GICR_IPRIORITYR0"
repeat.end
hgroup.long 0x50C00++0x07
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_0__9_GICR_ICFGR0,GICR_ICFGR0"
hide.long 0x04 "GIC_REGS_Redistributor_SGI_PPI_0__10_GICR_ICFGR1,GICR_ICFGR1"
hgroup.long 0x50D00++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_0__11_GICR_IGRPMODR0,GICR_IGRPMODR0"
hgroup.long 0x50E00++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_0__12_GICR_NSACR,GICR_NSACR"
group.long 0x5C000++0x03
line.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_0__13_GICR_MISCSTATUSR,GICR_MISCSTATUSR"
bitfld.long 0x00 31. "REDISTRIBUTOR_SGI_PPI_0__13_GICR_MISCSTATUSR__31_1,cpu_active" "0,1"
newline
bitfld.long 0x00 2. "REDISTRIBUTOR_SGI_PPI_0__13_GICR_MISCSTATUSR__2_1,EnableGrp1_S" "0,1"
newline
bitfld.long 0x00 1. "REDISTRIBUTOR_SGI_PPI_0__13_GICR_MISCSTATUSR__1_1,EnableGrp1_NS" "0,1"
newline
bitfld.long 0x00 0. "REDISTRIBUTOR_SGI_PPI_0__13_GICR_MISCSTATUSR__0_1,EnableGrp0" "0,1"
group.long 0x5C080++0x03
line.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_0__14_GICR_PPISR,GICR_PPISR"
hexmask.long.word 0x00 16.--31. 1. "REDISTRIBUTOR_SGI_PPI_0__14_GICR_PPISR__16_16,PPI status"
group.long 0x60000++0x0F
line.long 0x00 "GIC_REGS_Redistributor_control_LPI_1__2_GICR_CTLR,GICR_CTLR"
bitfld.long 0x00 31. "REDISTRIBUTOR_CONTROL_LPI_1__2_GICR_CTLR__31_1,Upstream Write Pending" "0,1"
newline
bitfld.long 0x00 3. "REDISTRIBUTOR_CONTROL_LPI_1__2_GICR_CTLR__3_1,Register Write Pending" "0,1"
newline
bitfld.long 0x00 0. "REDISTRIBUTOR_CONTROL_LPI_1__2_GICR_CTLR__0_1,Enable LPIs" "0,1"
line.long 0x04 "GIC_REGS_Redistributor_control_LPI_1__3_GICR_IIDR,GICR_IIDR"
hexmask.long.byte 0x04 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_1__3_GICR_IIDR__24_8,ProductID"
newline
bitfld.long 0x04 16.--19. "REDISTRIBUTOR_CONTROL_LPI_1__3_GICR_IIDR__16_4,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 12.--15. "REDISTRIBUTOR_CONTROL_LPI_1__3_GICR_IIDR__12_4,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 0.--11. 1. "REDISTRIBUTOR_CONTROL_LPI_1__3_GICR_IIDR__0_12,Implementer"
line.long 0x08 "GIC_REGS_Redistributor_control_LPI_1__4_GICR_TYPER_lower,GICR_TYPER_lower"
hexmask.long.word 0x08 8.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_1__4_GICR_TYPER_LOWER__8_16,Processor Number"
newline
bitfld.long 0x08 4. "REDISTRIBUTOR_CONTROL_LPI_1__4_GICR_TYPER_LOWER__4_1,Last" "0,1"
newline
bitfld.long 0x08 3. "REDISTRIBUTOR_CONTROL_LPI_1__4_GICR_TYPER_LOWER__3_1,Distributed" "0,1"
newline
bitfld.long 0x08 1. "REDISTRIBUTOR_CONTROL_LPI_1__4_GICR_TYPER_LOWER__1_1,VLPIS" "0,1"
newline
bitfld.long 0x08 0. "REDISTRIBUTOR_CONTROL_LPI_1__4_GICR_TYPER_LOWER__0_1,PLPIS" "0,1"
line.long 0x0C "GIC_REGS_Redistributor_control_LPI_1__5_GICR_TYPER_upper,GICR_TYPER_upper"
hexmask.long.byte 0x0C 24.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_1__5_GICR_TYPER_UPPER__24_8,A3"
newline
hexmask.long.byte 0x0C 16.--23. 1. "REDISTRIBUTOR_CONTROL_LPI_1__5_GICR_TYPER_UPPER__16_8,A2"
newline
hexmask.long.byte 0x0C 8.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_1__5_GICR_TYPER_UPPER__8_8,A1"
newline
hexmask.long.byte 0x0C 0.--7. 1. "REDISTRIBUTOR_CONTROL_LPI_1__5_GICR_TYPER_UPPER__0_8,A0"
group.long 0x60014++0x03
line.long 0x00 "GIC_REGS_Redistributor_control_LPI_1__6_GICR_WAKER,GICR_WAKER"
bitfld.long 0x00 31. "REDISTRIBUTOR_CONTROL_LPI_1__6_GICR_WAKER__31_1,Quiescent" "0,1"
newline
bitfld.long 0x00 2. "REDISTRIBUTOR_CONTROL_LPI_1__6_GICR_WAKER__2_1,ChildrenAsleep" "0,1"
newline
bitfld.long 0x00 1. "REDISTRIBUTOR_CONTROL_LPI_1__6_GICR_WAKER__1_1,ProcessorSleep" "0,1"
newline
bitfld.long 0x00 0. "REDISTRIBUTOR_CONTROL_LPI_1__6_GICR_WAKER__0_1,Sleep" "0,1"
group.long 0x60070++0x0F
line.long 0x00 "GIC_REGS_Redistributor_control_LPI_1__7_GICR_PROPBASER_lower,GICR_PROPBASER_lower"
hexmask.long.tbyte 0x00 12.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_1__7_GICR_PROPBASER_LOWER__12_20,Physical Address [31:12]"
newline
bitfld.long 0x00 7.--9. "REDISTRIBUTOR_CONTROL_LPI_1__7_GICR_PROPBASER_LOWER__7_3,Cacheability" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "REDISTRIBUTOR_CONTROL_LPI_1__7_GICR_PROPBASER_LOWER__0_5,Idbits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "GIC_REGS_Redistributor_control_LPI_1__8_GICR_PROPBASER_upper,GICR_PROPBASER_upper"
hexmask.long.word 0x04 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_1__8_GICR_PROPBASER_UPPER__0_16,Physical Address [47:32]"
line.long 0x08 "GIC_REGS_Redistributor_control_LPI_1__9_GICR_PENDBASER_lower,GICR_PENDBASER_lower"
hexmask.long.word 0x08 16.--31. 1. "REDISTRIBUTOR_CONTROL_LPI_1__9_GICR_PENDBASER_LOWER__16_16,Physical Address [31:16]"
newline
bitfld.long 0x08 7.--9. "REDISTRIBUTOR_CONTROL_LPI_1__9_GICR_PENDBASER_LOWER__7_3,Cacheability" "0,1,2,3,4,5,6,7"
line.long 0x0C "GIC_REGS_Redistributor_control_LPI_1__10_GICR_PENDBASER_upper,GICR_PENDBASER_upper"
bitfld.long 0x0C 30. "REDISTRIBUTOR_CONTROL_LPI_1__10_GICR_PENDBASER_UPPER__30_1,Pending Table Zero" "0,1"
newline
hexmask.long.word 0x0C 0.--15. 1. "REDISTRIBUTOR_CONTROL_LPI_1__10_GICR_PENDBASER_UPPER__0_16,Physical Address [47:32]"
hgroup.long 0x6FFD0++0x2F
hide.long 0x00 "GIC_REGS_Redistributor_control_LPI_1__11_GICR_PIDR4,GICR_PIDR4"
hide.long 0x04 "GIC_REGS_Redistributor_control_LPI_1__12_GICR_PIDR5,GICR_PIDR5"
hide.long 0x08 "GIC_REGS_Redistributor_control_LPI_1__13_GICR_PIDR6,GICR_PIDR6"
hide.long 0x0C "GIC_REGS_Redistributor_control_LPI_1__14_GICR_PIDR7,GICR_PIDR7"
hide.long 0x10 "GIC_REGS_Redistributor_control_LPI_1__15_GICR_PIDR0,GICR_PIDR0"
hide.long 0x14 "GIC_REGS_Redistributor_control_LPI_1__16_GICR_PIDR1,GICR_PIDR1"
hide.long 0x18 "GIC_REGS_Redistributor_control_LPI_1__17_GICR_PIDR2,GICR_PIDR2"
hide.long 0x1C "GIC_REGS_Redistributor_control_LPI_1__18_GICR_PIDR3,GICR_PIDR3"
hide.long 0x20 "GIC_REGS_Redistributor_control_LPI_1__19_GICR_CIDR0,GICR_CIDR0"
hide.long 0x24 "GIC_REGS_Redistributor_control_LPI_1__20_GICR_CIDR1,GICR_CIDR1"
hide.long 0x28 "GIC_REGS_Redistributor_control_LPI_1__21_GICR_CIDR2,GICR_CIDR2"
hide.long 0x2C "GIC_REGS_Redistributor_control_LPI_1__22_GICR_CIDR3,GICR_CIDR3"
hgroup.long 0x70080++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_1__1_GICR_IGROUPR0,GICR_IGROUPR0"
hgroup.long 0x70100++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_1__2_GICR_ISENABLER0,GICR_ISENABLER0"
hgroup.long 0x70180++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_1__3_GICR_ICENABLER0,GICR_ICENABLER0"
hgroup.long 0x70200++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_1__4_GICR_ISPENDR0,GICR_ISPENDR0"
hgroup.long 0x70280++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_1__5_GICR_ICPENDR0,GICR_ICPENDR0"
hgroup.long 0x70300++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_1__6_GICR_ISACTIVER0,GICR_ISACTIVER0"
hgroup.long 0x70380++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_1__7_GICR_ICACTIVER0,GICR_ICACTIVER0"
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
hgroup.long ($2+0x70400)++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_1__8_GICR_IPRIORITYR$1,GICR_IPRIORITYR0"
repeat.end
hgroup.long 0x70C00++0x07
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_1__9_GICR_ICFGR0,GICR_ICFGR0"
hide.long 0x04 "GIC_REGS_Redistributor_SGI_PPI_1__10_GICR_ICFGR1,GICR_ICFGR1"
hgroup.long 0x70D00++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_1__11_GICR_IGRPMODR0,GICR_IGRPMODR0"
hgroup.long 0x70E00++0x03
hide.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_1__12_GICR_NSACR,GICR_NSACR"
group.long 0x7C000++0x03
line.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_1__13_GICR_MISCSTATUSR,GICR_MISCSTATUSR"
bitfld.long 0x00 31. "REDISTRIBUTOR_SGI_PPI_1__13_GICR_MISCSTATUSR__31_1,cpu_active" "0,1"
newline
bitfld.long 0x00 2. "REDISTRIBUTOR_SGI_PPI_1__13_GICR_MISCSTATUSR__2_1,EnableGrp1_S" "0,1"
newline
bitfld.long 0x00 1. "REDISTRIBUTOR_SGI_PPI_1__13_GICR_MISCSTATUSR__1_1,EnableGrp1_NS" "0,1"
newline
bitfld.long 0x00 0. "REDISTRIBUTOR_SGI_PPI_1__13_GICR_MISCSTATUSR__0_1,EnableGrp0" "0,1"
group.long 0x7C080++0x03
line.long 0x00 "GIC_REGS_Redistributor_SGI_PPI_1__14_GICR_PPISR,GICR_PPISR"
hexmask.long.word 0x00 16.--31. 1. "REDISTRIBUTOR_SGI_PPI_1__14_GICR_PPISR__16_16,PPI status"
tree.end
tree "GICSS0_GIC_TRANSLATER"
base ad:0x1000000
group.long 0x30040++0x03
line.long 0x00 "GIC_TRANSLATER_REGS_TRANSLATER__1_GITS_TRANSLATER,GITS_TRANSLATER"
tree.end
tree "GICSS0_REGS"
base ad:0x3F004000
rgroup.long 0x00++0x03
line.long 0x00 "REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 2. "LPI_RAMECC_PEND,Interrupt Pending Status for lpi_ramecc_pend" "0,1"
bitfld.long 0x04 1. "ITE_RAMECC_PEND,Interrupt Pending Status for ite_ramecc_pend" "0,1"
bitfld.long 0x04 0. "ICB_RAMECC_PEND,Interrupt Pending Status for icb_ramecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 2. "LPI_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lpi_ramecc_pend" "0,1"
bitfld.long 0x00 1. "ITE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for ite_ramecc_pend" "0,1"
bitfld.long 0x00 0. "ICB_RAMECC_ENABLE_SET,Interrupt Enable Set Register for icb_ramecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 2. "LPI_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lpi_ramecc_pend" "0,1"
bitfld.long 0x00 1. "ITE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ite_ramecc_pend" "0,1"
bitfld.long 0x00 0. "ICB_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for icb_ramecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 2. "LPI_RAMECC_PEND,Interrupt Pending Status for lpi_ramecc_pend" "0,1"
bitfld.long 0x04 1. "ITE_RAMECC_PEND,Interrupt Pending Status for ite_ramecc_pend" "0,1"
bitfld.long 0x04 0. "ICB_RAMECC_PEND,Interrupt Pending Status for icb_ramecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 2. "LPI_RAMECC_ENABLE_SET,Interrupt Enable Set Register for lpi_ramecc_pend" "0,1"
bitfld.long 0x00 1. "ITE_RAMECC_ENABLE_SET,Interrupt Enable Set Register for ite_ramecc_pend" "0,1"
bitfld.long 0x00 0. "ICB_RAMECC_ENABLE_SET,Interrupt Enable Set Register for icb_ramecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 2. "LPI_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for lpi_ramecc_pend" "0,1"
bitfld.long 0x00 1. "ITE_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for ite_ramecc_pend" "0,1"
bitfld.long 0x00 0. "ICB_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for icb_ramecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
repeat 2. (list 0. 1. )(list ad:0x600000 ad:0x601000 )
tree "GPIO$1"
base $2
rgroup.long 0x00++0x0B
line.long 0x00 "MEM_pid,GPIO Periperal ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Current scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function code assigned to TCP3"
bitfld.long 0x00 11.--15. "RTL,RTL Version R code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version code" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision Y code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MEM_PCR,Peripheral Control Register"
bitfld.long 0x04 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1"
bitfld.long 0x04 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend" "0,1"
line.long 0x08 "MEM_BINTEN,Bit Interrupt Enable Register"
abitfld.long 0x08 0.--15. "EN,Per bank interrupt enable" "0x0000=disable,0x0001=enable"
group.long 0x10++0x0B
line.long 0x00 "MEM_DIR01,Direction Register"
abitfld.long 0x00 16.--31. "DIR1,Direction of GPIO bank 1 bits " "0x0000=output,0x0001=input"
abitfld.long 0x00 0.--15. "DIR0,Direction of GPIO bank 0 bits " "0x0000=output,0x0001=input"
line.long 0x04 "MEM_OUT_DATA01,Output Drive State Register"
hexmask.long.word 0x04 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x04 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x08 "MEM_SET_DATA01,Set Output Drive State Register"
hexmask.long.word 0x08 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state"
hexmask.long.word 0x08 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state"
repeat 4. (list 01. 23. 45. 67. )(list 0x00 0x28 0x50 0x78 )
group.long ($2+0x1C)++0x03
line.long 0x00 "MEM_CLR_DATA$1,Clear Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
repeat.end
rgroup.long 0x20++0x23
line.long 0x00 "MEM_IN_DATA01,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN1,Status of GPIO bank 1 bits"
hexmask.long.word 0x00 0.--15. 1. "IN0,Status of GPIO bank 0 bits"
line.long 0x04 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits"
line.long 0x0C "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits"
line.long 0x14 "MEM_INTSTAT01,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT1,Status of GPIO bank 0 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT0,Status of GPIO bank 0 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR23,Direction Register"
abitfld.long 0x18 16.--31. "DIR3,Direction of GPIO bank 3 bits " "0x0000=output,0x0001=input"
abitfld.long 0x18 0.--15. "DIR2,Direction of GPIO bank 2 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA23,Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA23,Set Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state"
rgroup.long 0x48++0x23
line.long 0x00 "MEM_IN_DATA23,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN3,Status of GPIO bank 3 bits"
hexmask.long.word 0x00 0.--15. 1. "IN2,Status of GPIO bank 2 bits"
line.long 0x04 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits"
line.long 0x0C "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits"
line.long 0x14 "MEM_INTSTAT23,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT3,Status of GPIO bank 2 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT2,Status of GPIO bank 2 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR45,Direction Register"
abitfld.long 0x18 16.--31. "DIR5,Direction of GPIO bank 5 bits " "0x0000=output,0x0001=input"
abitfld.long 0x18 0.--15. "DIR4,Direction of GPIO bank 4 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA45,Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA45,Set Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state"
rgroup.long 0x70++0x23
line.long 0x00 "MEM_IN_DATA45,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN5,Status of GPIO bank 5 bits"
hexmask.long.word 0x00 0.--15. 1. "IN4,Status of GPIO bank 4 bits"
line.long 0x04 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits"
line.long 0x0C "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits"
line.long 0x14 "MEM_INTSTAT45,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT5,Status of GPIO bank 4 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT4,Status of GPIO bank 4 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR67,Direction Register"
abitfld.long 0x18 16.--31. "DIR7,Direction of GPIO bank 7 bits " "0x0000=output,0x0001=input"
abitfld.long 0x18 0.--15. "DIR6,Direction of GPIO bank 6 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA67,Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA67,Set Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state"
rgroup.long 0x98++0x3F
line.long 0x00 "MEM_IN_DATA67,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN7,Status of GPIO bank 7 bits"
hexmask.long.word 0x00 0.--15. 1. "IN6,Status of GPIO bank 6 bits"
line.long 0x04 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits"
line.long 0x0C "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits"
line.long 0x14 "MEM_INTSTAT67,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT7,Status of GPIO bank 6 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT6,Status of GPIO bank 6 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR8,Direction Register"
abitfld.long 0x18 0.--15. "DIR8,Direction of GPIO bank 8 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA8,Output Drive State Register"
hexmask.long.word 0x1C 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA8,Set Output Drive State Register"
hexmask.long.word 0x20 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state"
line.long 0x24 "MEM_CLR_DATA8,Clear Output Drive State Register"
hexmask.long.word 0x24 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
line.long 0x28 "MEM_IN_DATA8,Bank Status Register"
hexmask.long.word 0x28 0.--15. 1. "IN8,Status of GPIO bank 8 bits"
line.long 0x2C "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register"
hexmask.long.word 0x2C 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits"
line.long 0x30 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register"
hexmask.long.word 0x30 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits"
line.long 0x34 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register"
hexmask.long.word 0x34 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits"
line.long 0x38 "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register"
hexmask.long.word 0x38 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits"
line.long 0x3C "MEM_INTSTAT8,Bank Interrupt Status Register"
abitfld.long 0x3C 0.--15. "STAT8,Status of GPIO bank 8 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
tree.end
repeat.end
tree "GPMC0_CFG"
base ad:0x3B000000
group.long 0x00++0x03
line.long 0x00 "CFG_GPMC_REVISION,This register contains the IP revision code"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,Reads returns 0"
hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1"
group.long 0x10++0x0F
line.long 0x00 "CFG_GPMC_SYSCONFIG,This register controls the various parameters of the OCP interface"
hexmask.long 0x00 5.--31. 1. "RESERVED,Write 0's for future compatibility Reads return 0"
bitfld.long 0x00 3.--4. "IDLEMODE," "0,1,2,3"
newline
bitfld.long 0x00 2. "RESERVED,Write 0 for future compatibility Reads returns 0" "0,1"
bitfld.long 0x00 1. "RESERVED,This bit must be kept 0 for normal functioning of the IP" "0,1"
newline
bitfld.long 0x00 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
line.long 0x04 "CFG_GPMC_SYSSTATUS,This register provides status information about the module. excluding the interrupt status information"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,Reads returns 0"
hexmask.long.byte 0x04 1.--7. 1. "RESERVED,Reads returns 0 [reserved for OCP-socket status information]"
newline
rbitfld.long 0x04 0. "RESETDONE,Internal reset monitoring" "0,1"
line.long 0x08 "CFG_GPMC_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.tbyte 0x08 12.--31. 1. "RESERVED,Write 0's for future compatibility"
bitfld.long 0x08 11. "WAIT3EDGEDETECTIONSTATUS,Status of the Wait3 Edge Detection interrupt" "0,1"
newline
bitfld.long 0x08 10. "WAIT2EDGEDETECTIONSTATUS,Status of the Wait2 Edge Detection interrupt" "0,1"
bitfld.long 0x08 9. "WAIT1EDGEDETECTIONSTATUS,Status of the Wait1 Edge Detection interrupt" "0,1"
newline
bitfld.long 0x08 8. "WAIT0EDGEDETECTIONSTATUS,Status of the Wait0 Edge Detection interrupt" "0,1"
bitfld.long 0x08 2.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x08 1. "TERMINALCOUNTSTATUS,Status of the TerminalCountEvent interrupt" "0,1"
bitfld.long 0x08 0. "FIFOEVENTSTATUS,Status of the FIFOEvent interrupt" "0,1"
line.long 0x0C "CFG_GPMC_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt. on a event-by-event basis"
hexmask.long.tbyte 0x0C 12.--31. 1. "RESERVED,Write 0's for future compatibility"
bitfld.long 0x0C 11. "WAIT3EDGEDETECTIONENABLE,Enables the Wait3 Edge Detection interrupt" "0,1"
newline
bitfld.long 0x0C 10. "WAIT2EDGEDETECTIONENABLE,Enables the Wait2 Edge Detection interrupt" "0,1"
bitfld.long 0x0C 9. "WAIT1EDGEDETECTIONENABLE,Enables the Wait1 Edge Detection interrupt" "0,1"
newline
bitfld.long 0x0C 8. "WAIT0EDGEDETECTIONENABLE,Enables the Wait0 Edge Detection interrupt" "0,1"
bitfld.long 0x0C 2.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x0C 1. "TERMINALCOUNTEVENTENABLE,Enables TerminalCountEvent interrupt issuing in pre-fetch or write posting mode" "0,1"
bitfld.long 0x0C 0. "FIFOEVENTENABLE,Enables the FIFOEvent interrupt" "0,1"
group.long 0x40++0x0B
line.long 0x00 "CFG_GPMC_TIMEOUT_CONTROL,The GPMC_TIMEOUT_CONTROL register allows the user to set the start value of the timeout counter"
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED,Write 0's for future compatibility"
hexmask.long.word 0x00 4.--12. 1. "TIMEOUTSTARTVALUE,Start value of the time-out counter [0x000 corresponds to 0 GPMC.FCLK cycle 0x001 corresponds to 1 GmpcClk cycle & 0x1FF corresponds to 511 GPMC.FCLK cyles.]"
newline
bitfld.long 0x00 1.--3. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "TIMEOUTENABLE,Enable bit of the TimeOut feature" "0,1"
line.long 0x04 "CFG_GPMC_ERR_ADDRESS,The GPMC_ERR_ADDRESS register stores the address of the illegal access when an error occurs"
bitfld.long 0x04 31. "RESERVED,Write 0's for future compatibility" "0,1"
hexmask.long 0x04 0.--30. 1. "ILLEGALADD,Address of illegal access : A30[0 for memory region 1 for GPMC register region] and A29-A0[1 GBytes maximum]"
line.long 0x08 "CFG_GPMC_ERR_TYPE,The GPMC_ERR_TYPE register stores the type of error when an error occurs"
hexmask.long.tbyte 0x08 11.--31. 1. "RESERVED,Write 0's for future compatibility"
rbitfld.long 0x08 8.--10. "ILLEGALMCMD,System Command of the transaction that caused the error" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 5.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7"
rbitfld.long 0x08 4. "ERRORNOTSUPPADD,Not supported Address error" "0,1"
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rbitfld.long 0x08 3. "ERRORNOTSUPPMCMD,Not supported Command error" "0,1"
rbitfld.long 0x08 2. "ERRORTIMEOUT,Time-out error" "0,1"
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bitfld.long 0x08 1. "RESERVED,Write 0's for future compatibility" "0,1"
bitfld.long 0x08 0. "ERRORVALID,Error validity status - Must be explicitely cleared with a write 1 transaction" "0,1"
group.long 0x50++0x07
line.long 0x00 "CFG_GPMC_CONFIG,The configuration register allows global configuration of the GPMC"
hexmask.long.tbyte 0x00 12.--31. 1. "RESERVED,Write 0's for future compatibility"
bitfld.long 0x00 11. "WAIT3PINPOLARITY,Selects the polarity of input pin WAIT3" "0,1"
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bitfld.long 0x00 10. "WAIT2PINPOLARITY,Selects the polarity of input pin WAIT2" "0,1"
bitfld.long 0x00 9. "WAIT1PINPOLARITY,Selects the polarity of input pin WAIT1" "0,1"
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bitfld.long 0x00 8. "WAIT0PINPOLARITY,Selects the polarity of input pin WAIT0" "0,1"
bitfld.long 0x00 5.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "WRITEPROTECT,Controls the WP output pin level" "0,1"
bitfld.long 0x00 2.--3. "RESERVED,Write 0's for future compatibility" "0,1,2,3"
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bitfld.long 0x00 1. "LIMITEDADDRESS,Limited Address device support" "0,1"
bitfld.long 0x00 0. "NANDFORCEPOSTEDWRITE,Enables the Force Posted Write feature to NAND Cmd/Add/Data location" "0,1"
line.long 0x04 "CFG_GPMC_STATUS,The status register provides global status bits of the GPMC"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED,Write 0's for future compatibility"
rbitfld.long 0x04 11. "WAIT3STATUS,Is a copy of input pin WAIT3" "0,1"
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rbitfld.long 0x04 10. "WAIT2STATUS,Is a copy of input pin WAIT2" "0,1"
rbitfld.long 0x04 9. "WAIT1STATUS,Is a copy of input pin WAIT1" "0,1"
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rbitfld.long 0x04 8. "WAIT0STATUS,Is a copy of input pin WAIT0" "0,1"
hexmask.long.byte 0x04 1.--7. 1. "RESERVED,Write 0's for future compatibility Reads returns 0"
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rbitfld.long 0x04 0. "EMPTYWRITEBUFFERSTATUS,Stores the empty status of the write buffer" "0,1"
group.long 0x1E0++0x07
line.long 0x00 "CFG_GPMC_PREFETCH_CONFIG1,Prefetch engine configuration 1"
bitfld.long 0x00 31. "RESERVED,Write 0's for future compatibility" "0,1"
bitfld.long 0x00 28.--30. "CYCLEOPTIMIZATION,Define the number of GPMC.FCLK cycles to be substracted from RdCycleTime WrCycleTime AccessTime CSRdOffTime CSWrOffTime ADVRdOffTime ADVWrOffTime OEOffTime WEOffTime [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 27. "ENABLEOPTIMIZEDACCESS,Enables access cycle optimization" "0,1"
bitfld.long 0x00 24.--26. "ENGINECSSELECTOR,Selects the CS where Prefetch Postwrite engine is active [0x0 corresponds toCS0 0x1 corresponds to CS1 & 0x7 corresponds to CS7]" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 23. "PFPWENROUNDROBIN,Enables the PFPW RoundRobin arbitration" "0,1"
bitfld.long 0x00 20.--22. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--19. "PFPWWEIGHTEDPRIO,When an arbitration occurs between a direct memory access and a PFPW engine access the direct memory access is always serviced" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15. "RESERVED,Write 0's for future compatibility" "0,1"
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hexmask.long.byte 0x00 8.--14. 1. "FIFOTHRESHOLD,Selects the maximum number of bytes read from the FIFO or written to the FIFO by the host on a DMA or interrupt request [0x00 corresponds to 0 byte 0x01 corresponds to 1 byte & 0x40 corresponds to 64 bytes]"
bitfld.long 0x00 7. "ENABLEENGINE,Enables the Prefetch Postwite engine" "0,1"
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bitfld.long 0x00 6. "RESERVED,Write 0's for future compatibility" "0,1"
bitfld.long 0x00 4.--5. "WAITPINSELECTOR,Select which wait pin edge detector should start the engine in synchronized mode" "0,1,2,3"
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bitfld.long 0x00 3. "SYNCHROMODE,Selects when the engine starts the access to CS" "0,1"
bitfld.long 0x00 2. "DMAMODE,Selects interrupt synchronization or DMA request synchronization" "0,1"
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bitfld.long 0x00 1. "RESERVED,Write 0's for future compatibility" "0,1"
bitfld.long 0x00 0. "ACCESSMODE,Selects pre-fetch read or write posting accesses" "0,1"
line.long 0x04 "CFG_GPMC_PREFETCH_CONFIG2,Prefetch engine configuration 2"
hexmask.long.tbyte 0x04 14.--31. 1. "RESERVED,Write 0's for future compatibility"
hexmask.long.word 0x04 0.--13. 1. "TRANSFERCOUNT,Selects the number of bytes to be read or written by the engine to the selected CS [0x0000 corresponds to 0 byte 0x0001 corresponds to 1 byte & 0x2000 corresponds to 8 Kbytes]"
group.long 0x1EC++0x17
line.long 0x00 "CFG_GPMC_PREFETCH_CONTROL,Prefetch engine control"
hexmask.long 0x00 1.--31. 1. "RESERVED,Write 0's for future compatibility"
bitfld.long 0x00 0. "STARTENGINE,Resets the FIFO pointer and starts the engine" "0,1"
line.long 0x04 "CFG_GPMC_PREFETCH_STATUS,Prefetch engine status"
bitfld.long 0x04 31. "RESERVED,Write 0's for future compatibility" "0,1"
hexmask.long.byte 0x04 24.--30. 1. "FIFOPOINTER,Number of available bytes to be read or number of free empty byte places to be written [0x00 corresponds to 0 byte available to be read or 0 free empty place to be written & 0x40 corresponds to 64 bytes available to be read or 64 empty.."
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hexmask.long.byte 0x04 17.--23. 1. "RESERVED,Write 0's for future compatibility"
rbitfld.long 0x04 16. "FIFOTHRESHOLDSTATUS,Set when FIFOPointer exceeds FIFOThreshold value" "0,1"
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bitfld.long 0x04 14.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3"
hexmask.long.word 0x04 0.--13. 1. "COUNTVALUE,Number of remaining bytes to be read or to be written by the engine according to the TransferCount value [0x0000 corresponds to 0 byte remaining to be read or to be written 0x0001 corresponds to 1 byte remaining to be read or to be written &.."
line.long 0x08 "CFG_GPMC_ECC_CONFIG,ECC configuration"
hexmask.long.word 0x08 17.--31. 1. "RESERVED,Write 0's for future compatibility"
bitfld.long 0x08 16. "ECCALGORITHM,ECC algorithm used" "Hamming code,BCH code"
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bitfld.long 0x08 14.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3"
bitfld.long 0x08 12.--13. "ECCBCHTSEL,Error correction capability used for BCH" "up to 4 bits error correction [t = 4],up to 8 bits error correction [t=8],up to 16 bits error correction [t=16],reserved"
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bitfld.long 0x08 8.--11. "ECCWRAPMODE,Spare area organization definition for the BCH algorithm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 7. "ECC16B,Selects an ECC calculated on 16 columns" "0,1"
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bitfld.long 0x08 4.--6. "ECCTOPSECTOR,Number of sectors to process with the BCH algorithm" "1 sector [512kB page],2 sectors,?,4 sectors [2kB page],?,?,?,8 sectors [4kB page]"
bitfld.long 0x08 1.--3. "ECCCS,Selects the CS where ECC is computed" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 0. "ECCENABLE,Enables the ECC feature" "0,1"
line.long 0x0C "CFG_GPMC_ECC_CONTROL,ECC control"
hexmask.long.tbyte 0x0C 9.--31. 1. "RESERVED,Write 0's for future compatibility"
bitfld.long 0x0C 8. "ECCCLEAR,Clear all ECC result registers [Reads returns 0 - Writes 1 to this field clear all ECC result registers - Writes 0 are ignored]" "0,1"
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bitfld.long 0x0C 4.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "ECCPOINTER,Selects ECC result register [Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored]; Other enums: writing other values disables.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CFG_GPMC_ECC_SIZE_CONFIG,ECC size"
bitfld.long 0x10 30.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3"
hexmask.long.byte 0x10 22.--29. 1. "ECCSIZE1,Defines ECC size 1 [0x00 corresponds to 2 Bytes 0x01 corresponds to 4 Bytes 0x02 corresponds to 6 Bytes 0x03 corresponds to 8 Bytes & 0xFF corresponds to 512 Bytes]"
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bitfld.long 0x10 20.--21. "RESERVED,Write 0's for future compatibility" "0,1,2,3"
hexmask.long.byte 0x10 12.--19. 1. "ECCSIZE0,Defines ECC size 0 [0x00 corresponds to 2 Bytes 0x01 corresponds to 4 Bytes 0x02 corresponds to 6 Bytes 0x03 corresponds to 8 Bytes & 0xFF corresponds to 512 Bytes]"
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bitfld.long 0x10 9.--11. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 8. "ECC9RESULTSIZE,Selects ECC size for ECC 9 result register" "0,1"
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bitfld.long 0x10 7. "ECC8RESULTSIZE,Selects ECC size for ECC 8 result register" "0,1"
bitfld.long 0x10 6. "ECC7RESULTSIZE,Selects ECC size for ECC 7 result register" "0,1"
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bitfld.long 0x10 5. "ECC6RESULTSIZE,Selects ECC size for ECC 6 result register" "0,1"
bitfld.long 0x10 4. "ECC5RESULTSIZE,Selects ECC size for ECC 5 result register" "0,1"
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bitfld.long 0x10 3. "ECC4RESULTSIZE,Selects ECC size for ECC 4 result register" "0,1"
bitfld.long 0x10 2. "ECC3RESULTSIZE,Selects ECC size for ECC 3 result register" "0,1"
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bitfld.long 0x10 1. "ECC2RESULTSIZE,Selects ECC size for ECC 2 result register" "0,1"
bitfld.long 0x10 0. "ECC1RESULTSIZE,Selects ECC size for ECC 1 result register" "0,1"
line.long 0x14 "CFG_GPMC_ECC_RESULT,ECC result register"
bitfld.long 0x14 28.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x14 27. "P2048O,Odd Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1"
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rbitfld.long 0x14 26. "P1024O,Odd Row Parity bit 1024" "0,1"
rbitfld.long 0x14 25. "P512O,Odd Row Parity bit 512" "0,1"
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rbitfld.long 0x14 24. "P256O,Odd Row Parity bit 256" "0,1"
rbitfld.long 0x14 23. "P128O,Odd Row Parity bit 128" "0,1"
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rbitfld.long 0x14 22. "P64O,Odd Row Parity bit 64" "0,1"
rbitfld.long 0x14 21. "P32O,Odd Row Parity bit 32" "0,1"
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rbitfld.long 0x14 20. "P16O,Odd Row Parity bit 16" "0,1"
rbitfld.long 0x14 19. "P8O,Odd Row Parity bit 8" "0,1"
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rbitfld.long 0x14 18. "P4O,Odd Column Parity bit 4" "0,1"
rbitfld.long 0x14 17. "P2O,Odd Column Parity bit 2" "0,1"
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rbitfld.long 0x14 16. "P1O,Odd Column Parity bit 1" "0,1"
bitfld.long 0x14 12.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 11. "P2048E,Even Row Parity bit 2048 only used for ECC computed on 512 Bytes" "0,1"
rbitfld.long 0x14 10. "P1024E,Even Row Parity bit 1024" "0,1"
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rbitfld.long 0x14 9. "P512E,Even Row Parity bit 512" "0,1"
rbitfld.long 0x14 8. "P256E,Even Row Parity bit 256" "0,1"
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rbitfld.long 0x14 7. "P128E,Even Row Parity bit 128" "0,1"
rbitfld.long 0x14 6. "P64E,Even Row Parity bit 64" "0,1"
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rbitfld.long 0x14 5. "P32E,Even Row Parity bit 32" "0,1"
rbitfld.long 0x14 4. "P16E,Even Row Parity bit 16" "0,1"
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rbitfld.long 0x14 3. "P8E,Even Row Parity bit 8" "0,1"
rbitfld.long 0x14 2. "P4E,Even Column Parity bit 4" "0,1"
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rbitfld.long 0x14 1. "P2E,Even Column Parity bit 2" "0,1"
rbitfld.long 0x14 0. "P1E,Even Column Parity bit 1" "0,1"
group.long 0x2D0++0x03
line.long 0x00 "CFG_GPMC_BCH_SWDATA,This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface"
hexmask.long.word 0x00 0.--15. 1. "BCH_DATA,Data to be included in the BCH calculation"
group.long 0x60++0x27
line.long 0x00 "CFG_GPMC_CONFIG1,The configuration 1 register sets signal control parameters per chip select"
bitfld.long 0x00 31. "WRAPBURST,Enables the wrapping burst capability" "0,1"
bitfld.long 0x00 30. "READMULTIPLE,Selects the read single or multiple access" "0,1"
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bitfld.long 0x00 29. "READTYPE,Selects the read mode operation" "0,1"
bitfld.long 0x00 28. "WRITEMULTIPLE,Selects the write single or multiple access" "0,1"
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bitfld.long 0x00 27. "WRITETYPE,Selects the write mode operation" "0,1"
bitfld.long 0x00 25.--26. "CLKACTIVATIONTIME,Output GPMC.CLK activation time" "0,1,2,3"
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bitfld.long 0x00 23.--24. "ATTACHEDDEVICEPAGELENGTH,Specifies the attached device page [burst] length" "0,1,2,3"
bitfld.long 0x00 22. "WAITREADMONITORING,Selects the Wait monitoring configuration for Read accesses [Reset value is BOOTWAITEN input pin sampled at IC reset]" "0,1"
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bitfld.long 0x00 21. "WAITWRITEMONITORING,Selects the Wait monitoring configuration for Write accesses" "0,1"
bitfld.long 0x00 20. "RESERVED,Write 0's for future compatibility" "0,1"
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bitfld.long 0x00 18.--19. "WAITMONITORINGTIME,Selects input pin Wait monitoring time" "0,1,2,3"
bitfld.long 0x00 16.--17. "WAITPINSELECT,Selects the input WAIT pin for this chip select [Reset value is BOOTWAITSELECT input pin sampled at IC reset for CS0 and 0 for CS1-7]" "0,1,2,3"
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bitfld.long 0x00 14.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3"
bitfld.long 0x00 12.--13. "DEVICESIZE,Selects the device size attached [Reset value is BOOTDEVICESIZE input pin sampled at IC reset for CS0 and 01 for CS1-7]" "0,1,2,3"
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bitfld.long 0x00 10.--11. "DEVICETYPE,Selects the attached device type" "0,1,2,3"
bitfld.long 0x00 8.--9. "MUXADDDATA,Enables the Address and data multiplexed protocol [Reset value is CS0MUXDEVICE input pin sampled at IC reset for CS0 and 0 for CS1-7]" "0,1,2,3"
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bitfld.long 0x00 5.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "TIMEPARAGRANULARITY,Signals timing latencies scalar factor [Rd/WRCycleTime AccessTime PageBurstAccessTime CSOnTime CSRd/WrOffTime ADVOnTime ADVRd/WrOffTime OEOnTime OEOffTime WEOnTime WEOffTime Cycle2CycleDelay BusTurnAround TimeOutStartValue]" "0,1"
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bitfld.long 0x00 2.--3. "RESERVED,Write 0's for future compatibility" "0,1,2,3"
bitfld.long 0x00 0.--1. "GPMCFCLKDIVIDER,Divides the GPMC.FCLK clock" "0,1,2,3"
line.long 0x04 "CFG_GPMC_CONFIG2,Chip-select signal timing parameter configuration"
hexmask.long.word 0x04 21.--31. 1. "RESERVED,Write 0's for future compatibility Reads returns 0"
bitfld.long 0x04 16.--20. "CSWROFFTIME,CS# de-assertion time from start cycle time for write accesses [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 13.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 8.--12. "CSRDOFFTIME,CS# de-assertion time from start cycle time for read accesses [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 7. "CSEXTRADELAY,CS# Add Extra Half GPMC.FCLK cycle" "0,1"
bitfld.long 0x04 4.--6. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 0.--3. "CSONTIME,CS# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CFG_GPMC_CONFIG3,ADV# signal timing parameter configuration"
rbitfld.long 0x08 31. "RESERVED_1,Write 0's for future compatibility" "0,1"
bitfld.long 0x08 28.--30. "ADVAADMUXWROFFTIME,ADV# de-assertion for first address phase when using the AAD-Mux protocol" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x08 27. "RESERVED_0,Write 0's for future compatibility" "0,1"
bitfld.long 0x08 24.--26. "ADVAADMUXRDOFFTIME,ADV# assertion for first address phase when using the AAD-Mux protocol" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 21.--23. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--20. "ADVWROFFTIME,ADV# de-assertion time from start cycle time for write accesses [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 13.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 8.--12. "ADVRDOFFTIME,ADV# de-assertion time from start cycle time for read accesses[0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 7. "ADVEXTRADELAY,ADV# Add Extra Half GPMC.FCLK cycle" "0,1"
bitfld.long 0x08 4.--6. "ADVAADMUXONTIME,ADV# assertion for first address phase when using the AAD-Mux protocol" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 0.--3. "ADVONTIME,ADV# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CFG_GPMC_CONFIG4,WE# and OE# signals timing parameter configuration"
rbitfld.long 0x0C 29.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 24.--28. "WEOFFTIME,WE# de-assertion time from start cycle time [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 23. "WEEXTRADELAY,WE# Add Extra Half GPMC.FCLK cycle" "0,1"
bitfld.long 0x0C 20.--22. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 16.--19. "WEONTIME,WE# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 13.--15. "OEAADMUXOFFTIME,OE# de-assertion time for the first address phase in an AAD-Mux access" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 8.--12. "OEOFFTIME,OE# de-assertion time from start cycle time [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 7. "OEEXTRADELAY,OE# Add Extra Half GPMC.FCLK cycle" "0,1"
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bitfld.long 0x0C 4.--6. "OEAADMUXONTIME,OE# assertion time for the first address phase in an AAD-Mux access" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0.--3. "OEONTIME,OE# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CFG_GPMC_CONFIG5,RdAccessTime and CycleTime timing parameters configuration"
bitfld.long 0x10 28.--31. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 24.--27. "PAGEBURSTACCESSTIME,Delay between successive words in a multiple access [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 21.--23. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 16.--20. "RDACCESSTIME,Delay between start cycle time and first data valid [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 13.--15. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 8.--12. "WRCYCLETIME,Total write cycle time [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 5.--7. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7"
bitfld.long 0x10 0.--4. "RDCYCLETIME,Total read cycle time [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F corresponds to 31 GPMC.FCLK cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "CFG_GPMC_CONFIG6,WrAccessTime. WrDataOnADmuxBus. Cycle2Cycle and BusTurnAround parameters configuration"
bitfld.long 0x14 31. "RESERVED,TI Internal use - Do not modify" "0,1"
bitfld.long 0x14 29.--30. "RESERVED,Write 0's for future compatibility" "0,1,2,3"
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bitfld.long 0x14 24.--28. "WRACCESSTIME,Delay from StartAccessTime to the GPMC.FCLK rising edge corresponding the the GPMC.CLK rising edge used by the attached memory for the first data capture [0x00 corresponds to 0 GPMC.FCLK cycle 0x01 corresponds to 1 GPMC.FCLK cycle & 0x1F.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x14 20.--23. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "WRDATAONADMUXBUS,Specifies on which GPMC.FCLK rising edge the first data of the synchronous burst write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 12.--15. "RESERVED,Write 0's for future compatibility" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "CYCLE2CYCLEDELAY,Chip select high pulse delay between two successive accesses [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF corresponds to 15 GPMC.FCLK cycles]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 7. "CYCLE2CYCLESAMECSEN,Add Cycle2CycleDelay between two successive accesses to the same chip-select [any access type]" "0,1"
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bitfld.long 0x14 6. "CYCLE2CYCLEDIFFCSEN,Add Cycle2CycleDelay between two successive accesses to a different chip-select [any access type]" "0,1"
bitfld.long 0x14 4.--5. "RESERVED,Write 0's for future compatibility Reads returns 0" "0,1,2,3"
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bitfld.long 0x14 0.--3. "BUSTURNAROUND,Bus turn around latency between two successive accesses to the same chip-select [rd to wr] or to a different chip-select [read to read and read to write] [0x0 corresponds to 0 GPMC.FCLK cycle 0x1 corresponds to 1 GPMC.FCLK cycle & 0xF.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "CFG_GPMC_CONFIG7,Chip-select address mapping configuration Note: For CS0. the register reset is 0xf40 while for all the other instances CS1-CS7. the reset is 0xf00"
hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED,Write 0's for future compatibility"
bitfld.long 0x18 8.--11. "MASKADDRESS,Chip-select mask address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 7. "RESERVED,Write 0's for future compatibility" "0,1"
bitfld.long 0x18 6. "CSVALID,Chip-select enable [reset value is 1 for CS0 and 0 for CS1-7]" "0,1"
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bitfld.long 0x18 0.--5. "BASEADDRESS,Chip-select base address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "CFG_GPMC_NAND_COMMAND,This Register is not a true register. just a address location"
line.long 0x20 "CFG_GPMC_NAND_ADDRESS,This Register is not a true register. just a address location"
line.long 0x24 "CFG_GPMC_NAND_DATA,This Register is not a true register. just a address location"
rgroup.long 0x240++0x0F
line.long 0x00 "CFG_GPMC_BCH_RESULT_0,BCH ECC result. bits 0 to 31"
line.long 0x04 "CFG_GPMC_BCH_RESULT_1,BCH ECC result. bits 32 to 63"
line.long 0x08 "CFG_GPMC_BCH_RESULT_2,BCH ECC result. bits 64 to 95"
line.long 0x0C "CFG_GPMC_BCH_RESULT_3,BCH ECC result. bits 96 to 127"
rgroup.long 0x300++0x0B
line.long 0x00 "CFG_GPMC_BCH_RESULT_4,BCH ECC result. bits 128 to 159"
line.long 0x04 "CFG_GPMC_BCH_RESULT_5,BCH ECC result. bits 160 to 191"
line.long 0x08 "CFG_GPMC_BCH_RESULT_6,BCH ECC result. bits 192 to 207"
hexmask.long.word 0x08 0.--15. 1. "BCH_RESULT_6,BCH ECC result bits 192 to 207"
tree.end
tree "GPMC0_DATA"
base ad:0x50000000
tree.end
tree "I2C0_CFG"
base ad:0x20000000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x04 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x04 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x00 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
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bitfld.long 0x00 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Autoidle bit" "0,1"
group.long 0x20++0x2F
line.long 0x00 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
line.long 0x04 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
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bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
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bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x08 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x08 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x08 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x08 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x08 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x08 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x08 8. "BF,Bus Free IRQ enabled status" "0,1"
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bitfld.long 0x08 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x08 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x08 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
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bitfld.long 0x08 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x08 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x0C "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector"
bitfld.long 0x0C 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0C 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0C 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0C 11. "ROVR,Receive overrun enable set" "0,1"
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bitfld.long 0x0C 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0C 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0C 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0C 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x0C 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0C 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0C 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0C 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x0C 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0C 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0C 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector"
bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1"
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bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x14 "CFG_I2C_WE,I2C wakeup enable vector (legacy)"
bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x18 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set"
bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set"
bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x20 "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear"
bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear"
bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x28 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable"
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x2C "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable"
bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x07
line.long 0x00 "CFG_I2C_IE,I2C interrupt enable vector (legacy)"
bitfld.long 0x00 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x00 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x00 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x00 11. "ROVR,Receive overrun enable set" "0,1"
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bitfld.long 0x00 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x00 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x00 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x00 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x00 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x00 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x00 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x00 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x00 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x00 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x00 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x04 "CFG_I2C_STAT,I2C interrupt status vector (legacy)"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
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bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
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bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
rgroup.long 0x90++0x0F
line.long 0x00 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x00 0. "RDONE,Reset done bit" "0,1"
line.long 0x04 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x04 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x04 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
bitfld.long 0x04 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
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bitfld.long 0x04 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
bitfld.long 0x04 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x08 0.--15. 1. "DCOUNT,Data count"
line.long 0x0C "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x0C 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x33
line.long 0x00 "CFG_I2C_CON,I2C configuration register"
bitfld.long 0x00 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x00 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x00 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x00 10. "MST,Master/slave mode" "0,1"
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bitfld.long 0x00 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x00 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x00 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x00 6. "XOA1,Expand Own address 1" "0,1"
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bitfld.long 0x00 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x00 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x00 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x00 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x04 "CFG_I2C_OA,Own address register"
bitfld.long 0x04 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "OA,Own address"
line.long 0x08 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x08 0.--9. 1. "SA,Slave address"
line.long 0x0C "CFG_I2C_PSC,I2C Clock Prescaler Register"
abitfld.long 0x0C 0.--7. "PSC,Fast/Standard mode prescale sampling clock divider value" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
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rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
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bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
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bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
line.long 0x1C "CFG_I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x1C 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
bitfld.long 0x1C 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1C 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x20 0.--9. 1. "OA1,Own address 1"
line.long 0x24 "CFG_I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x24 0.--9. 1. "OA2,Own address 2"
line.long 0x28 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x28 0.--9. 1. "OA3,Own address 3"
line.long 0x2C "CFG_I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x2C 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x2C 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x2C 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x2C 0. "OA0_ACT,Own Address 0 active" "0,1"
line.long 0x30 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x30 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x30 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x30 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x30 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree "I2C1_CFG"
base ad:0x20010000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x04 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x04 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x00 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
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bitfld.long 0x00 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Autoidle bit" "0,1"
group.long 0x20++0x2F
line.long 0x00 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
line.long 0x04 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
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bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x08 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x08 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x08 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x08 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x08 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x08 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x08 8. "BF,Bus Free IRQ enabled status" "0,1"
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bitfld.long 0x08 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x08 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x08 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x08 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x08 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x0C "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector"
bitfld.long 0x0C 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0C 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0C 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0C 11. "ROVR,Receive overrun enable set" "0,1"
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bitfld.long 0x0C 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0C 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0C 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0C 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x0C 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0C 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0C 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0C 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x0C 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0C 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0C 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector"
bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1"
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bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x14 "CFG_I2C_WE,I2C wakeup enable vector (legacy)"
bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x18 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set"
bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set"
bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x20 "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear"
bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear"
bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x28 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable"
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x2C "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable"
bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x07
line.long 0x00 "CFG_I2C_IE,I2C interrupt enable vector (legacy)"
bitfld.long 0x00 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x00 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x00 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x00 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x00 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x00 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x00 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x00 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x00 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x00 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x00 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x00 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x00 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x00 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x00 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x04 "CFG_I2C_STAT,I2C interrupt status vector (legacy)"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
rgroup.long 0x90++0x0F
line.long 0x00 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x00 0. "RDONE,Reset done bit" "0,1"
line.long 0x04 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x04 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x04 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
bitfld.long 0x04 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
newline
bitfld.long 0x04 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
bitfld.long 0x04 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x08 0.--15. 1. "DCOUNT,Data count"
line.long 0x0C "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x0C 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x33
line.long 0x00 "CFG_I2C_CON,I2C configuration register"
bitfld.long 0x00 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x00 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x00 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x00 10. "MST,Master/slave mode" "0,1"
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bitfld.long 0x00 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x00 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x00 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x00 6. "XOA1,Expand Own address 1" "0,1"
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bitfld.long 0x00 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x00 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x00 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x00 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x04 "CFG_I2C_OA,Own address register"
bitfld.long 0x04 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "OA,Own address"
line.long 0x08 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x08 0.--9. 1. "SA,Slave address"
line.long 0x0C "CFG_I2C_PSC,I2C Clock Prescaler Register"
abitfld.long 0x0C 0.--7. "PSC,Fast/Standard mode prescale sampling clock divider value" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
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rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
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bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
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bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
line.long 0x1C "CFG_I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x1C 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
bitfld.long 0x1C 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1C 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x20 0.--9. 1. "OA1,Own address 1"
line.long 0x24 "CFG_I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x24 0.--9. 1. "OA2,Own address 2"
line.long 0x28 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x28 0.--9. 1. "OA3,Own address 3"
line.long 0x2C "CFG_I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x2C 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x2C 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x2C 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x2C 0. "OA0_ACT,Own Address 0 active" "0,1"
line.long 0x30 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x30 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x30 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x30 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x30 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree "I2C2_CFG"
base ad:0x20020000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x04 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x04 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x00 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
newline
bitfld.long 0x00 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Autoidle bit" "0,1"
group.long 0x20++0x2F
line.long 0x00 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
line.long 0x04 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x08 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x08 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x08 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x08 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x08 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x08 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x08 8. "BF,Bus Free IRQ enabled status" "0,1"
newline
bitfld.long 0x08 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x08 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x08 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x08 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x08 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x0C "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector"
bitfld.long 0x0C 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0C 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0C 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0C 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x0C 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0C 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0C 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0C 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x0C 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0C 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0C 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0C 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x0C 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0C 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0C 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector"
bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1"
newline
bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x14 "CFG_I2C_WE,I2C wakeup enable vector (legacy)"
bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x18 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set"
bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set"
bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x20 "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear"
bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear"
bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x28 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable"
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x2C "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable"
bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x07
line.long 0x00 "CFG_I2C_IE,I2C interrupt enable vector (legacy)"
bitfld.long 0x00 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x00 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x00 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x00 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x00 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x00 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x00 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x00 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x00 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x00 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x00 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x00 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x00 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x00 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x00 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x04 "CFG_I2C_STAT,I2C interrupt status vector (legacy)"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
rgroup.long 0x90++0x0F
line.long 0x00 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x00 0. "RDONE,Reset done bit" "0,1"
line.long 0x04 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x04 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x04 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
bitfld.long 0x04 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
newline
bitfld.long 0x04 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
bitfld.long 0x04 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x08 0.--15. 1. "DCOUNT,Data count"
line.long 0x0C "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x0C 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x33
line.long 0x00 "CFG_I2C_CON,I2C configuration register"
bitfld.long 0x00 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x00 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x00 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x00 10. "MST,Master/slave mode" "0,1"
newline
bitfld.long 0x00 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x00 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x00 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x00 6. "XOA1,Expand Own address 1" "0,1"
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bitfld.long 0x00 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x00 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x00 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x00 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x04 "CFG_I2C_OA,Own address register"
bitfld.long 0x04 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "OA,Own address"
line.long 0x08 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x08 0.--9. 1. "SA,Slave address"
line.long 0x0C "CFG_I2C_PSC,I2C Clock Prescaler Register"
abitfld.long 0x0C 0.--7. "PSC,Fast/Standard mode prescale sampling clock divider value" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
newline
rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
newline
bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
newline
bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
line.long 0x1C "CFG_I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x1C 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
bitfld.long 0x1C 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1C 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x20 0.--9. 1. "OA1,Own address 1"
line.long 0x24 "CFG_I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x24 0.--9. 1. "OA2,Own address 2"
line.long 0x28 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x28 0.--9. 1. "OA3,Own address 3"
line.long 0x2C "CFG_I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x2C 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x2C 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x2C 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x2C 0. "OA0_ACT,Own Address 0 active" "0,1"
line.long 0x30 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x30 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x30 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x30 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x30 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree "I2C3_CFG"
base ad:0x20030000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x04 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x04 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x00 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
newline
bitfld.long 0x00 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Autoidle bit" "0,1"
group.long 0x20++0x2F
line.long 0x00 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
line.long 0x04 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x08 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x08 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x08 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x08 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x08 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x08 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x08 8. "BF,Bus Free IRQ enabled status" "0,1"
newline
bitfld.long 0x08 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x08 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x08 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x08 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x08 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x0C "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector"
bitfld.long 0x0C 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0C 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0C 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0C 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x0C 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0C 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0C 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0C 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x0C 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0C 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0C 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0C 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x0C 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0C 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0C 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector"
bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1"
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bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x14 "CFG_I2C_WE,I2C wakeup enable vector (legacy)"
bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x18 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set"
bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set"
bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x20 "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear"
bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear"
bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x28 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable"
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x2C "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable"
bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x07
line.long 0x00 "CFG_I2C_IE,I2C interrupt enable vector (legacy)"
bitfld.long 0x00 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x00 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x00 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x00 11. "ROVR,Receive overrun enable set" "0,1"
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bitfld.long 0x00 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x00 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x00 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x00 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x00 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x00 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x00 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x00 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x00 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x00 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x00 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x04 "CFG_I2C_STAT,I2C interrupt status vector (legacy)"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
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bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
rgroup.long 0x90++0x0F
line.long 0x00 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x00 0. "RDONE,Reset done bit" "0,1"
line.long 0x04 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x04 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x04 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
bitfld.long 0x04 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
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bitfld.long 0x04 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
bitfld.long 0x04 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x08 0.--15. 1. "DCOUNT,Data count"
line.long 0x0C "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x0C 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x33
line.long 0x00 "CFG_I2C_CON,I2C configuration register"
bitfld.long 0x00 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x00 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x00 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x00 10. "MST,Master/slave mode" "0,1"
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bitfld.long 0x00 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x00 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x00 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x00 6. "XOA1,Expand Own address 1" "0,1"
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bitfld.long 0x00 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x00 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x00 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x00 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x04 "CFG_I2C_OA,Own address register"
bitfld.long 0x04 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "OA,Own address"
line.long 0x08 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x08 0.--9. 1. "SA,Slave address"
line.long 0x0C "CFG_I2C_PSC,I2C Clock Prescaler Register"
abitfld.long 0x0C 0.--7. "PSC,Fast/Standard mode prescale sampling clock divider value" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
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rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
newline
bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
newline
bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
line.long 0x1C "CFG_I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x1C 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
bitfld.long 0x1C 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1C 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x20 0.--9. 1. "OA1,Own address 1"
line.long 0x24 "CFG_I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x24 0.--9. 1. "OA2,Own address 2"
line.long 0x28 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x28 0.--9. 1. "OA3,Own address 3"
line.long 0x2C "CFG_I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x2C 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x2C 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x2C 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x2C 0. "OA0_ACT,Own Address 0 active" "0,1"
line.long 0x30 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x30 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x30 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x30 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x30 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree "ICSSM0_DRAM0_SLV_RAM"
base ad:0x30040000
group.long 0x00++0x03
line.long 0x00 "DRAM0__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "ICSSM0_DRAM1_SLV_RAM"
base ad:0x30042000
group.long 0x00++0x03
line.long 0x00 "DRAM1__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "ICSSM0_ECC_AGGR"
base ad:0x3F00C000
rgroup.long 0x00++0x03
line.long 0x00 "BORG_ECC_AGGR__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "BORG_ECC_AGGR__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "BORG_ECC_AGGR__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "BORG_ECC_AGGR__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "BORG_ECC_AGGR__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "BORG_ECC_AGGR__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 4. "PR1_RAM_PEND,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x04 3. "PR1_PDSP1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
bitfld.long 0x04 2. "PR1_PDSP0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
newline
bitfld.long 0x04 1. "PR1_DRAM1_PEND,Interrupt Pending Status for pr1_dram1_pend" "0,1"
bitfld.long 0x04 0. "PR1_DRAM0_PEND,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "BORG_ECC_AGGR__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 4. "PR1_RAM_ENABLE_SET,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "PR1_PDSP1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
bitfld.long 0x00 2. "PR1_PDSP0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
newline
bitfld.long 0x00 1. "PR1_DRAM1_ENABLE_SET,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
bitfld.long 0x00 0. "PR1_DRAM0_ENABLE_SET,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "BORG_ECC_AGGR__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 4. "PR1_RAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "PR1_PDSP1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp1_iram_pend" "0,1"
bitfld.long 0x00 2. "PR1_PDSP0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp0_iram_pend" "0,1"
newline
bitfld.long 0x00 1. "PR1_DRAM1_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram1_pend" "0,1"
bitfld.long 0x00 0. "PR1_DRAM0_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "BORG_ECC_AGGR__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "BORG_ECC_AGGR__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 4. "PR1_RAM_PEND,Interrupt Pending Status for pr1_ram_pend" "0,1"
bitfld.long 0x04 3. "PR1_PDSP1_IRAM_PEND,Interrupt Pending Status for pr1_pdsp1_iram_pend" "0,1"
bitfld.long 0x04 2. "PR1_PDSP0_IRAM_PEND,Interrupt Pending Status for pr1_pdsp0_iram_pend" "0,1"
newline
bitfld.long 0x04 1. "PR1_DRAM1_PEND,Interrupt Pending Status for pr1_dram1_pend" "0,1"
bitfld.long 0x04 0. "PR1_DRAM0_PEND,Interrupt Pending Status for pr1_dram0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "BORG_ECC_AGGR__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 4. "PR1_RAM_ENABLE_SET,Interrupt Enable Set Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "PR1_PDSP1_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp1_iram_pend" "0,1"
bitfld.long 0x00 2. "PR1_PDSP0_IRAM_ENABLE_SET,Interrupt Enable Set Register for pr1_pdsp0_iram_pend" "0,1"
newline
bitfld.long 0x00 1. "PR1_DRAM1_ENABLE_SET,Interrupt Enable Set Register for pr1_dram1_pend" "0,1"
bitfld.long 0x00 0. "PR1_DRAM0_ENABLE_SET,Interrupt Enable Set Register for pr1_dram0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "BORG_ECC_AGGR__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 4. "PR1_RAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_ram_pend" "0,1"
bitfld.long 0x00 3. "PR1_PDSP1_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp1_iram_pend" "0,1"
bitfld.long 0x00 2. "PR1_PDSP0_IRAM_ENABLE_CLR,Interrupt Enable Clear Register for pr1_pdsp0_iram_pend" "0,1"
newline
bitfld.long 0x00 1. "PR1_DRAM1_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram1_pend" "0,1"
bitfld.long 0x00 0. "PR1_DRAM0_ENABLE_CLR,Interrupt Enable Clear Register for pr1_dram0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "BORG_ECC_AGGR__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "BORG_ECC_AGGR__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "BORG_ECC_AGGR__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "BORG_ECC_AGGR__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "ICSSM0_IEP0"
base ad:0x3006E000
group.long 0x00++0x1F
line.long 0x00 "PR1_IEP0__SLV__REGS_global_cfg_reg,"
hexmask.long.word 0x00 8.--19. 1. "CMP_INC,"
bitfld.long 0x00 4.--7. "DEFAULT_INC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "CNT_ENABLE," "0,1"
line.long 0x04 "PR1_IEP0__SLV__REGS_global_status_reg,"
bitfld.long 0x04 0. "CNT_OVF," "0,1"
line.long 0x08 "PR1_IEP0__SLV__REGS_compen_reg,"
hexmask.long.tbyte 0x08 0.--22. 1. "COMPEN_CNT,"
line.long 0x0C "PR1_IEP0__SLV__REGS_slow_compen_reg,"
line.long 0x10 "PR1_IEP0__SLV__REGS_count_reg0,"
line.long 0x14 "PR1_IEP0__SLV__REGS_count_reg1,"
line.long 0x18 "PR1_IEP0__SLV__REGS_cap_cfg_reg,"
bitfld.long 0x18 18.--23. "EXT_CAP_EN," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x18 10.--17. 1. "CAP_ASYNC_EN,"
hexmask.long.word 0x18 0.--9. 1. "CAP_EN,"
line.long 0x1C "PR1_IEP0__SLV__REGS_cap_status_reg,"
hexmask.long.byte 0x1C 16.--23. 1. "CAP_RAW,"
hexmask.long.word 0x1C 0.--10. 1. "CAP_VALID,"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x20)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr0_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x28)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr1_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x30)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr2_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x38)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr3_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x40)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr4_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x48)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr5_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x50)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr6_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x58)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capf6_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x60)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr7_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x68)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capf7_reg$1,"
repeat.end
group.long 0x70++0x07
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp_cfg_reg,"
bitfld.long 0x00 17. "SHADOW_EN," "0,1"
hexmask.long.word 0x00 1.--16. 1. "CMP_EN,"
bitfld.long 0x00 0. "CMP0_RST_CNT_EN," "0,1"
line.long 0x04 "PR1_IEP0__SLV__REGS_cmp_status_reg,"
hexmask.long.word 0x04 0.--15. 1. "CMP_STATUS,"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x78)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp0_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x80)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp1_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x88)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp2_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x90)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp3_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x98)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp4_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xA0)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp5_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xA8)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp6_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xB0)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp7_reg$1,"
repeat.end
group.long 0xB8++0x07
line.long 0x00 "PR1_IEP0__SLV__REGS_rxipg0_reg,"
hexmask.long.word 0x00 16.--31. 1. "RX_MIN_IPG0,"
hexmask.long.word 0x00 0.--15. 1. "RX_IPG0,"
line.long 0x04 "PR1_IEP0__SLV__REGS_rxipg1_reg,"
hexmask.long.word 0x04 16.--31. 1. "RX_MIN_IPG1,"
hexmask.long.word 0x04 0.--15. 1. "RX_IPG1,"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xC0)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp8_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xC8)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp9_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xD0)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp10_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xD8)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp11_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xE0)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp12_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xE8)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp13_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xF0)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp14_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xF8)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp15_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x100)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_count_reset_val_reg$1,"
repeat.end
group.long 0x108++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_pwm_reg,"
bitfld.long 0x00 3. "PWM3_HIT," "0,1"
bitfld.long 0x00 2. "PWM3_RST_CNT_EN," "0,1"
bitfld.long 0x00 1. "PWM0_HIT," "0,1"
bitfld.long 0x00 0. "PWM0_RST_CNT_EN," "0,1"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x10C)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr0_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x114)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr1_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x11C)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr2_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x124)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr3_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x12C)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr4_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x134)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr5_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x13C)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr6_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x144)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capf6_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x14C)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr7_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x154)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capf7_bi_reg$1,"
repeat.end
group.long 0x180++0x1F
line.long 0x00 "PR1_IEP0__SLV__REGS_sync_ctrl_reg,"
bitfld.long 0x00 10. "SYNC1_OUT_NV_EN," "0,1"
bitfld.long 0x00 9. "SYNC0_OUT_NV_EN," "0,1"
bitfld.long 0x00 8. "SYNC1_IND_EN," "0,1"
bitfld.long 0x00 7. "SYNC1_CYCLIC_EN," "0,1"
bitfld.long 0x00 6. "SYNC1_ACK_EN," "0,1"
newline
bitfld.long 0x00 5. "SYNC0_CYCLIC_EN," "0,1"
bitfld.long 0x00 4. "SYNC0_ACK_EN," "0,1"
bitfld.long 0x00 2. "SYNC1_EN," "0,1"
bitfld.long 0x00 1. "SYNC0_EN," "0,1"
bitfld.long 0x00 0. "SYNC_EN," "0,1"
line.long 0x04 "PR1_IEP0__SLV__REGS_sync_first_stat_reg,"
bitfld.long 0x04 1. "FIRST_SYNC1," "0,1"
bitfld.long 0x04 0. "FIRST_SYNC0," "0,1"
line.long 0x08 "PR1_IEP0__SLV__REGS_sync0_stat_reg,"
bitfld.long 0x08 0. "SYNC0_PEND," "0,1"
line.long 0x0C "PR1_IEP0__SLV__REGS_sync1_stat_reg,"
bitfld.long 0x0C 0. "SYNC1_PEND," "0,1"
line.long 0x10 "PR1_IEP0__SLV__REGS_sync_pwidth_reg,"
line.long 0x14 "PR1_IEP0__SLV__REGS_sync0_period_reg,"
line.long 0x18 "PR1_IEP0__SLV__REGS_sync1_delay_reg,"
line.long 0x1C "PR1_IEP0__SLV__REGS_sync_start_reg,"
group.long 0x200++0x17
line.long 0x00 "PR1_IEP0__SLV__REGS_wd_prediv_reg,"
hexmask.long.word 0x00 0.--15. 1. "PRE_DIV,"
line.long 0x04 "PR1_IEP0__SLV__REGS_pdi_wd_tim_reg,"
hexmask.long.word 0x04 0.--15. 1. "PDI_WD_TIME,"
line.long 0x08 "PR1_IEP0__SLV__REGS_pd_wd_tim_reg,"
hexmask.long.word 0x08 0.--15. 1. "PD_WD_TIME,"
line.long 0x0C "PR1_IEP0__SLV__REGS_wd_status_reg,"
bitfld.long 0x0C 16. "PDI_WD_STAT," "0,1"
bitfld.long 0x0C 0. "PD_WD_STAT," "0,1"
line.long 0x10 "PR1_IEP0__SLV__REGS_wd_exp_cnt_reg,"
hexmask.long.byte 0x10 8.--15. 1. "PD_EXP_CNT,"
hexmask.long.byte 0x10 0.--7. 1. "PDI_EXP_CNT,"
line.long 0x14 "PR1_IEP0__SLV__REGS_wd_ctrl_reg,"
bitfld.long 0x14 16. "PDI_WD_EN," "0,1"
bitfld.long 0x14 0. "PD_WD_EN," "0,1"
group.long 0x300++0x1B
line.long 0x00 "PR1_IEP0__SLV__REGS_digio_ctrl_reg,"
bitfld.long 0x00 6.--7. "OUT_MODE," "0,1,2,3"
bitfld.long 0x00 4.--5. "IN_MODE," "0,1,2,3"
bitfld.long 0x00 3. "WD_MODE," "0,1"
rbitfld.long 0x00 2. "BIDI_MODE," "0,1"
bitfld.long 0x00 1. "OUTVALID_MODE," "0,1"
newline
rbitfld.long 0x00 0. "OUTVALID_POL," "0,1"
line.long 0x04 "PR1_IEP0__SLV__REGS_digio_status_reg,"
line.long 0x08 "PR1_IEP0__SLV__REGS_digio_data_in_reg,"
line.long 0x0C "PR1_IEP0__SLV__REGS_digio_data_in_raw_reg,"
line.long 0x10 "PR1_IEP0__SLV__REGS_digio_data_out_reg,"
line.long 0x14 "PR1_IEP0__SLV__REGS_digio_data_out_en_reg,"
line.long 0x18 "PR1_IEP0__SLV__REGS_digio_exp_reg,"
bitfld.long 0x18 13. "EOF_SEL," "0,1"
bitfld.long 0x18 12. "SOF_SEL," "0,1"
bitfld.long 0x18 8.--11. "SOF_DLY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 4.--7. "OUTVALID_DLY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 2. "SW_OUTVALID," "0,1"
newline
bitfld.long 0x18 1. "OUTVALID_OVR_EN," "0,1"
bitfld.long 0x18 0. "SW_DATA_OUT_UP," "0,1"
tree.end
tree "ICSSM0_PR1_CFG_SLV"
base ad:0x30066000
rgroup.long 0x00++0x1F
line.long 0x00 "PR1_CFG__SLV__REGS_pid_reg,"
line.long 0x04 "PR1_CFG__SLV__REGS_hwdis_reg,"
hexmask.long.byte 0x04 0.--7. 1. "HWDIS,HW Disable Observation"
line.long 0x08 "PR1_CFG__SLV__REGS_gpcfg0_reg,"
bitfld.long 0x08 26.--29. "PR1_PRU0_GP_MUX_SEL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x08 25. "PRU0_GPO_SH1_SEL," "0,1"
bitfld.long 0x08 20.--24. "PRU0_GPO_DIV1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 15.--19. "PRU0_GPO_DIV0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 14. "PRU0_GPO_MODE," "0,1"
bitfld.long 0x08 13. "PRU0_GPI_SB," "0,1"
newline
bitfld.long 0x08 8.--12. "PRU0_GPI_DIV1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 3.--7. "PRU0_GPI_DIV0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 2. "PRU0_GPI_CLK_MODE," "0,1"
newline
bitfld.long 0x08 0.--1. "PRU0_GPI_MODE," "0,1,2,3"
line.long 0x0C "PR1_CFG__SLV__REGS_gpcfg1_reg,"
bitfld.long 0x0C 26.--29. "PR1_PRU1_GP_MUX_SEL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x0C 25. "PRU1_GPO_SH1_SEL," "0,1"
bitfld.long 0x0C 20.--24. "PRU1_GPO_DIV1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 15.--19. "PRU1_GPO_DIV0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 14. "PRU1_GPO_MODE," "0,1"
bitfld.long 0x0C 13. "PRU1_GPI_SB," "0,1"
newline
bitfld.long 0x0C 8.--12. "PRU1_GPI_DIV1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 3.--7. "PRU1_GPI_DIV0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 2. "PRU1_GPI_CLK_MODE," "0,1"
newline
bitfld.long 0x0C 0.--1. "PRU1_GPI_MODE," "0,1,2,3"
line.long 0x10 "PR1_CFG__SLV__REGS_cgr_reg,"
bitfld.long 0x10 31. "ICSS_STOP_ACK," "0,1"
rbitfld.long 0x10 30. "ICSS_STOP_REQ," "0,1"
bitfld.long 0x10 29. "ICSS_PWR_IDLE," "0,1"
newline
bitfld.long 0x10 21. "BOTTOM_HALF_CLK_GATE_EN," "0,1"
bitfld.long 0x10 20. "TOP_HALF_CLK_GATE_EN," "0,1"
bitfld.long 0x10 19. "AUTO_SLICE1_CLK_GATE_EN," "0,1"
newline
bitfld.long 0x10 18. "AUTO_SLICE0_CLK_GATE_EN," "0,1"
bitfld.long 0x10 17. "IEP_CLK_EN," "0,1"
rbitfld.long 0x10 16. "IEP_CLK_STOP_ACK," "0,1"
newline
bitfld.long 0x10 15. "IEP_CLK_STOP_REQ," "0,1"
bitfld.long 0x10 14. "ECAP_CLK_EN," "0,1"
rbitfld.long 0x10 13. "ECAP_CLK_STOP_ACK," "0,1"
newline
bitfld.long 0x10 12. "ECAP_CLK_STOP_REQ," "0,1"
bitfld.long 0x10 11. "UART_CLK_EN," "0,1"
rbitfld.long 0x10 10. "UART_CLK_STOP_ACK," "0,1"
newline
bitfld.long 0x10 9. "UART_CLK_STOP_REQ," "0,1"
bitfld.long 0x10 8. "INTC_CLK_EN," "0,1"
rbitfld.long 0x10 7. "INTC_CLK_STOP_ACK," "0,1"
newline
bitfld.long 0x10 6. "INTC_CLK_STOP_REQ," "0,1"
line.long 0x14 "PR1_CFG__SLV__REGS_gpecfg0_reg,"
bitfld.long 0x14 17. "PRU0_GPO_SHIFT_CLK_DONE," "0,1"
bitfld.long 0x14 16. "PRU0_GPO_SHIFT_CLK_HIGH," "0,1"
hexmask.long.byte 0x14 8.--15. 1. "PRU0_GPO_SHIFT_CNT,"
newline
bitfld.long 0x14 6. "PRU0_GPO_SHIFT_GP_EN," "0,1"
bitfld.long 0x14 5. "PRU0_GPO_SHIFT_CLK_FREE," "0,1"
bitfld.long 0x14 4. "PRU0_GPO_SHIFT_SWAP," "0,1"
newline
bitfld.long 0x14 1. "PRU0_GPI_SHIFT_EN," "0,1"
bitfld.long 0x14 0. "PRU0_GPI_SB_P," "0,1"
line.long 0x18 "PR1_CFG__SLV__REGS_gpecfg1_reg,"
bitfld.long 0x18 17. "PRU1_GPO_SHIFT_CLK_DONE," "0,1"
bitfld.long 0x18 16. "PRU1_GPO_SHIFT_CLK_HIGH," "0,1"
hexmask.long.byte 0x18 8.--15. 1. "PRU1_GPO_SHIFT_CNT,"
newline
bitfld.long 0x18 6. "PRU1_GPO_SHIFT_GP_EN," "0,1"
bitfld.long 0x18 5. "PRU1_GPO_SHIFT_CLK_FREE," "0,1"
bitfld.long 0x18 4. "PRU1_GPO_SHIFT_SWAP," "0,1"
newline
bitfld.long 0x18 1. "PRU1_GPI_SHIFT_EN," "0,1"
bitfld.long 0x18 0. "PRU1_GPI_SB_P," "0,1"
line.long 0x1C "PR1_CFG__SLV__REGS_reset_iso_reg,"
bitfld.long 0x1C 2. "RESET_ISO_EDGE," "0,1"
bitfld.long 0x1C 1. "RESET_ISO_ACK," "0,1"
bitfld.long 0x1C 0. "RESET_ISO_REQ," "0,1"
group.long 0x2C++0x1B
line.long 0x00 "PR1_CFG__SLV__REGS_mii_rt_reg,"
bitfld.long 0x00 0. "MII_RT_EVENT_EN," "0,1"
line.long 0x04 "PR1_CFG__SLV__REGS_iepclk_reg,"
bitfld.long 0x04 1. "IEP1_SLV_EN," "0,1"
bitfld.long 0x04 0. "IEP_OCP_CLK_EN," "0,1"
line.long 0x08 "PR1_CFG__SLV__REGS_spp_reg,"
bitfld.long 0x08 3. "RTU_XFR_SHIFT_EN," "0,1"
bitfld.long 0x08 2. "XFR_BYTE_SHIFT_EN," "0,1"
bitfld.long 0x08 1. "XFR_SHIFT_EN," "0,1"
newline
bitfld.long 0x08 0. "PRU1_PAD_HP_EN," "0,1"
line.long 0x0C "PR1_CFG__SLV__REGS_spin_cfg_reg,"
bitfld.long 0x0C 0. "SPIN_CLOCK_TX_PRU_EN," "0,1"
line.long 0x10 "PR1_CFG__SLV__REGS_core_sync_reg,"
bitfld.long 0x10 0. "CORE_VBUSP_SYNC_EN," "0,1"
line.long 0x14 "PR1_CFG__SLV__REGS_sa_mx_reg,"
bitfld.long 0x14 16. "PWM_EFC_EN," "0,1"
bitfld.long 0x14 10.--11. "PWM3_REMAP_EN," "0,1,2,3"
bitfld.long 0x14 8.--9. "PWM0_REMAP_EN," "0,1,2,3"
newline
hexmask.long.byte 0x14 0.--7. 1. "SA_MUX_SEL,"
line.long 0x18 "PR1_CFG__SLV__REGS_pru0_sd_clk_div_reg,"
hexmask.long.byte 0x18 24.--31. 1. "PRU0_SD_MAN_REC_CLK_PERIOD,"
rbitfld.long 0x18 16. "PRU0_SD_MAN_CLK_CAL_DONE," "0,1"
rbitfld.long 0x18 15. "PRU0_SD_MAN_STATUS," "0,1"
newline
bitfld.long 0x18 11.--14. "PRU0_SD_CH_SEL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 10. "PRU0_SD_MAN_NV_DATA_EN," "0,1"
bitfld.long 0x18 9. "PRU0_SD_MAN_EN," "0,1"
newline
bitfld.long 0x18 8. "PRU0_SD_SHARE_EN," "0,1"
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 )
group.long ($2+0x48)++0x03
line.long 0x00 "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg$1,"
bitfld.long 0x00 22. "PRU0_FD_ZERO_MAX_0," "0,1"
bitfld.long 0x00 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "PRU0_FD_ZERO_MIN_0," "0,1"
newline
bitfld.long 0x00 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--5. "PRU0_SD_ACC_SEL0," "0,1,2,3"
bitfld.long 0x00 2. "PRU0_SD_CLK_INV0," "0,1"
newline
bitfld.long 0x00 0.--1. "PRU0_SD_CLK_SEL0," "0,1,2,3"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 )
group.long ($2+0x4C)++0x03
line.long 0x00 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg$1,"
bitfld.long 0x00 23. "PRU0_FD_EN_0," "0,1"
bitfld.long 0x00 22. "PRU0_FD_ONE_MAX_0," "0,1"
bitfld.long 0x00 17.--21. "PRU0_FD_ONE_MAX_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16. "PRU0_FD_ONE_MIN_0," "0,1"
bitfld.long 0x00 11.--15. "PRU0_FD_ONE_MIN_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "PRU0_FD_WINDOW_SIZE_0," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 0.--7. 1. "PRU0_SD_SAMPLE_SIZE0,"
repeat.end
group.long 0x90++0x03
line.long 0x00 "PR1_CFG__SLV__REGS_pru1_sd_clk_div_reg,"
hexmask.long.byte 0x00 24.--31. 1. "PRU1_SD_MAN_REC_CLK_PERIOD,"
rbitfld.long 0x00 16. "PRU1_SD_MAN_CLK_CAL_DONE," "0,1"
rbitfld.long 0x00 15. "PRU1_SD_MAN_STATUS," "0,1"
newline
bitfld.long 0x00 11.--14. "PRU1_SD_CH_SEL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10. "PRU1_SD_MAN_NV_DATA_EN," "0,1"
bitfld.long 0x00 9. "PRU1_SD_MAN_EN," "0,1"
newline
bitfld.long 0x00 8. "PRU1_SD_SHARE_EN," "0,1"
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 )
group.long ($2+0x94)++0x03
line.long 0x00 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg$1,"
bitfld.long 0x00 22. "PRU1_FD_ZERO_MAX_0," "0,1"
bitfld.long 0x00 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "PRU1_FD_ZERO_MIN_0," "0,1"
newline
bitfld.long 0x00 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--5. "PRU1_SD_ACC_SEL0," "0,1,2,3"
bitfld.long 0x00 2. "PRU1_SD_CLK_INV0," "0,1"
newline
bitfld.long 0x00 0.--1. "PRU1_SD_CLK_SEL0," "0,1,2,3"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 )
group.long ($2+0x98)++0x03
line.long 0x00 "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg$1,"
bitfld.long 0x00 23. "PRU1_FD_EN_0," "0,1"
bitfld.long 0x00 22. "PRU1_FD_ONE_MAX_0," "0,1"
bitfld.long 0x00 17.--21. "PRU1_FD_ONE_MAX_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16. "PRU1_FD_ONE_MIN_0," "0,1"
bitfld.long 0x00 11.--15. "PRU1_FD_ONE_MIN_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "PRU1_FD_WINDOW_SIZE_0," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 0.--7. 1. "PRU1_SD_SAMPLE_SIZE0,"
repeat.end
group.long 0xE0++0x3F
line.long 0x00 "PR1_CFG__SLV__REGS_pru0_ed_rx_cfg_reg,"
hexmask.long.word 0x00 16.--31. 1. "PRU0_ED_RX_DIV_FACTOR,"
bitfld.long 0x00 15. "PRU0_ED_RX_DIV_FACTOR_FRAC," "0,1"
bitfld.long 0x00 4. "PRU0_ED_RX_CLK_SEL," "0,1"
newline
bitfld.long 0x00 3. "PRU0_ED_RX_SB_POL," "0,1"
bitfld.long 0x00 0.--2. "PRU0_ED_RX_SAMPLE_SIZE," "0,1,2,3,4,5,6,7"
line.long 0x04 "PR1_CFG__SLV__REGS_pru0_ed_tx_cfg_reg,"
hexmask.long.word 0x04 16.--31. 1. "PRU0_ED_TX_DIV_FACTOR,"
bitfld.long 0x04 15. "PRU0_ED_TX_DIV_FACTOR_FRAC," "0,1"
bitfld.long 0x04 11. "PRU0_ENDAT_SHARE_EN," "0,1"
newline
rbitfld.long 0x04 10. "PRU0_ENDAT2_CLK_SYNC," "0,1"
rbitfld.long 0x04 9. "PRU0_ENDAT1_CLK_SYNC," "0,1"
rbitfld.long 0x04 8. "PRU0_ENDAT0_CLK_SYNC," "0,1"
newline
rbitfld.long 0x04 7. "PRU0_ED_BUSY_2," "0,1"
rbitfld.long 0x04 6. "PRU0_ED_BUSY_1," "0,1"
rbitfld.long 0x04 5. "PRU0_ED_BUSY_0," "0,1"
newline
bitfld.long 0x04 4. "PRU0_ED_TX_CLK_SEL," "0,1"
line.long 0x08 "PR1_CFG__SLV__REGS_pru0_ed_ch0_cfg0_reg,"
bitfld.long 0x08 31. "PRU0_ED_TX_FIFO_SWAP_BITS0," "0,1"
bitfld.long 0x08 30. "PRU0_ED_SW_CLK_OUT0," "0,1"
bitfld.long 0x08 29. "PRU0_ED_CLK_OUT_OVR_EN0," "0,1"
newline
rbitfld.long 0x08 28. "PRU0_ED_RX_SNOOP0," "0,1"
hexmask.long.word 0x08 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE0,"
bitfld.long 0x08 11.--15. "PRU0_ED_TX_FRAME_SIZE0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x08 0.--10. 1. "PRU0_ED_TX_WDLY0,"
line.long 0x0C "PR1_CFG__SLV__REGS_pru0_ed_ch0_cfg1_reg,"
hexmask.long.word 0x0C 16.--31. 1. "PRU0_ED_RX_EN_COUNTER0,"
hexmask.long.word 0x0C 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER0,"
line.long 0x10 "PR1_CFG__SLV__REGS_pru0_ed_ch1_cfg0_reg,"
bitfld.long 0x10 31. "PRU0_ED_TX_FIFO_SWAP_BITS1," "0,1"
bitfld.long 0x10 30. "PRU0_ED_SW_CLK_OUT1," "0,1"
bitfld.long 0x10 29. "PRU0_ED_CLK_OUT_OVR_EN1," "0,1"
newline
rbitfld.long 0x10 28. "PRU0_ED_RX_SNOOP1," "0,1"
hexmask.long.word 0x10 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE1,"
bitfld.long 0x10 11.--15. "PRU0_ED_TX_FRAME_SIZE1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x10 0.--10. 1. "PRU0_ED_TX_WDLY1,"
line.long 0x14 "PR1_CFG__SLV__REGS_pru0_ed_ch1_cfg1_reg,"
hexmask.long.word 0x14 16.--31. 1. "PRU0_ED_RX_EN_COUNTER1,"
hexmask.long.word 0x14 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER1,"
line.long 0x18 "PR1_CFG__SLV__REGS_pru0_ed_ch2_cfg0_reg,"
bitfld.long 0x18 31. "PRU0_ED_TX_FIFO_SWAP_BITS2," "0,1"
bitfld.long 0x18 30. "PRU0_ED_SW_CLK_OUT2," "0,1"
bitfld.long 0x18 29. "PRU0_ED_CLK_OUT_OVR_EN2," "0,1"
newline
rbitfld.long 0x18 28. "PRU0_ED_RX_SNOOP2," "0,1"
hexmask.long.word 0x18 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE2,"
bitfld.long 0x18 11.--15. "PRU0_ED_TX_FRAME_SIZE2," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x18 0.--10. 1. "PRU0_ED_TX_WDLY2,"
line.long 0x1C "PR1_CFG__SLV__REGS_pru0_ed_ch2_cfg1_reg,"
hexmask.long.word 0x1C 16.--31. 1. "PRU0_ED_RX_EN_COUNTER2,"
hexmask.long.word 0x1C 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER2,"
line.long 0x20 "PR1_CFG__SLV__REGS_pru1_ed_rx_cfg_reg,"
hexmask.long.word 0x20 16.--31. 1. "PRU1_ED_RX_DIV_FACTOR,"
bitfld.long 0x20 15. "PRU1_ED_RX_DIV_FACTOR_FRAC," "0,1"
bitfld.long 0x20 4. "PRU1_ED_RX_CLK_SEL," "0,1"
newline
bitfld.long 0x20 3. "PRU1_ED_RX_SB_POL," "0,1"
bitfld.long 0x20 0.--2. "PRU1_ED_RX_SAMPLE_SIZE," "0,1,2,3,4,5,6,7"
line.long 0x24 "PR1_CFG__SLV__REGS_pru1_ed_tx_cfg_reg,"
hexmask.long.word 0x24 16.--31. 1. "PRU1_ED_TX_DIV_FACTOR,"
bitfld.long 0x24 15. "PRU1_ED_TX_DIV_FACTOR_FRAC," "0,1"
bitfld.long 0x24 11. "PRU1_ENDAT_SHARE_EN," "0,1"
newline
rbitfld.long 0x24 10. "PRU1_ENDAT2_CLK_SYNC," "0,1"
rbitfld.long 0x24 9. "PRU1_ENDAT1_CLK_SYNC," "0,1"
rbitfld.long 0x24 8. "PRU1_ENDAT0_CLK_SYNC," "0,1"
newline
rbitfld.long 0x24 7. "PRU1_ED_BUSY_2," "0,1"
rbitfld.long 0x24 6. "PRU1_ED_BUSY_1," "0,1"
rbitfld.long 0x24 5. "PRU1_ED_BUSY_0," "0,1"
newline
bitfld.long 0x24 4. "PRU1_ED_TX_CLK_SEL," "0,1"
line.long 0x28 "PR1_CFG__SLV__REGS_pru1_ed_ch0_cfg0_reg,"
bitfld.long 0x28 31. "PRU1_ED_TX_FIFO_SWAP_BITS0," "0,1"
bitfld.long 0x28 30. "PRU1_ED_SW_CLK_OUT0," "0,1"
bitfld.long 0x28 29. "PRU1_ED_CLK_OUT_OVR_EN0," "0,1"
newline
rbitfld.long 0x28 28. "PRU1_ED_RX_SNOOP0," "0,1"
hexmask.long.word 0x28 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE0,"
bitfld.long 0x28 11.--15. "PRU1_ED_TX_FRAME_SIZE0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x28 0.--10. 1. "PRU1_ED_TX_WDLY0,"
line.long 0x2C "PR1_CFG__SLV__REGS_pru1_ed_ch0_cfg1_reg,"
hexmask.long.word 0x2C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER0,"
hexmask.long.word 0x2C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER0,"
line.long 0x30 "PR1_CFG__SLV__REGS_pru1_ed_ch1_cfg0_reg,"
bitfld.long 0x30 31. "PRU1_ED_TX_FIFO_SWAP_BITS1," "0,1"
bitfld.long 0x30 30. "PRU1_ED_SW_CLK_OUT1," "0,1"
bitfld.long 0x30 29. "PRU1_ED_CLK_OUT_OVR_EN1," "0,1"
newline
rbitfld.long 0x30 28. "PRU1_ED_RX_SNOOP1," "0,1"
hexmask.long.word 0x30 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE1,"
bitfld.long 0x30 11.--15. "PRU1_ED_TX_FRAME_SIZE1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x30 0.--10. 1. "PRU1_ED_TX_WDLY1,"
line.long 0x34 "PR1_CFG__SLV__REGS_pru1_ed_ch1_cfg1_reg,"
hexmask.long.word 0x34 16.--31. 1. "PRU1_ED_RX_EN_COUNTER1,"
hexmask.long.word 0x34 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER1,"
line.long 0x38 "PR1_CFG__SLV__REGS_pru1_ed_ch2_cfg0_reg,"
bitfld.long 0x38 31. "PRU1_ED_TX_FIFO_SWAP_BITS2," "0,1"
bitfld.long 0x38 30. "PRU1_ED_SW_CLK_OUT2," "0,1"
bitfld.long 0x38 29. "PRU1_ED_CLK_OUT_OVR_EN2," "0,1"
newline
rbitfld.long 0x38 28. "PRU1_ED_RX_SNOOP2," "0,1"
hexmask.long.word 0x38 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE2,"
bitfld.long 0x38 11.--15. "PRU1_ED_TX_FRAME_SIZE2," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x38 0.--10. 1. "PRU1_ED_TX_WDLY2,"
line.long 0x3C "PR1_CFG__SLV__REGS_pru1_ed_ch2_cfg1_reg,"
hexmask.long.word 0x3C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER2,"
hexmask.long.word 0x3C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER2,"
hgroup.long 0x124++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_rtu0_poke_en0_reg,"
hgroup.long 0x12C++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_rtu1_poke_en0_reg,"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x130)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_pwm$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
hgroup.long ($2+0x140)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_pwm0_$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
hgroup.long ($2+0x14C)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_pwm1_$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
hgroup.long ($2+0x158)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_pwm2_$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
hgroup.long ($2+0x164)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_pwm3_$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
hgroup.long ($2+0x170)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_spin_lock$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x08 0x10 0x18 )
hgroup.long ($2+0x178)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_pa_stat_pdsp_cfg$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x08 0x10 0x18 )
hgroup.long ($2+0x17C)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_pa_stat_pdsp_stat$1,"
repeat.end
tree.end
tree "ICSSM0_PR1_ICSS_ECAP0_ECAP_SLV"
base ad:0x30070000
group.long 0x00++0x17
line.long 0x00 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_TSCNT,TIME STAMP COUNTER REGISTER"
line.long 0x04 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CNTPHS,COUNTER PHASE CONTROL REGISTER"
line.long 0x08 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP1,CAPTURE-1 REGISTER"
line.long 0x0C "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP2,CAPTURE-2 REGISTER"
line.long 0x10 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP3,CAPTURE-3 REGISTER"
line.long 0x14 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP4,CAPTURE-4 REGISTER"
group.long 0x28++0x0F
line.long 0x00 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_ECCTL2_ECCTL1,ECAP CONTROL REGISTER 1"
rbitfld.long 0x00 27.--31. "FILTER," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "APWMPOL,APWM OUTPUT POLARITY SELECT:0OUTPUT IS ACTIVE HIGH [IE COMPARE VALUE DEFINES HIGH TIME]1OUTPUT IS ACTIVE LOW [IE COMPARE VALUE DEFINES LOW TIME]NOTE: THIS IS APPLICABLE ONLY IN APWM OPERATING MODE" "0,1"
bitfld.long 0x00 25. "CAP_APWM,CAP/APWM OPERATING MODE SELECT:0ECAP MODULE OPERATES IN CAPTURE MODETHIS MODE FORCES THE FOLLOWING CONFIGURATION:1] INHIBITS TSCNT RESETS VIA PRD_EQ EVENT2] INHIBITS SHADOW LOADS ON CAP1 &AMP" "0,1"
bitfld.long 0x00 24. "SWSYNC,SOFTWARE FORCED COUNTER [TSCNT] SYNCING:0WRITING A ZERO HAS NO EFFECT WILL ALWAYS RETURN A ZERO1WRITING A ONE WILL FORCE A TSCNT SHADOW LOAD OF CURRENT ECAP MODULE AND ANY ECAP MODULES DOWN-STREAM PROVIDING THE SYNCO_SEL BITS ARE 0 0 AFTER.." "0,1"
bitfld.long 0x00 22.--23. "SYNCO_SEL,SYNC-OUT SELECT:0 0SELECT SYNC-IN EVENT TO BE THE SYNC-OUT SIGNAL [PASS THROUGH]0 1SELECT PRD_EQ EVENT TO BE THE SYNC-OUT SIGNAL1 0DISABLE SYNC OUT SIGNAL1 1DISABLE SYNC OUT SIGNALNOTE: SELECTION PRD_EQ IS MEANINGFUL ONLY IN APWM MODE HOWEVER.." "0,1,2,3"
bitfld.long 0x00 21. "SYNCI_EN,COUNTER [TSCNT] SYNC-IN SELECT MODE:0DISABLE SYNC-IN OPTION1ENABLE COUNTER [TSCNT] TO BE LOADED FROM CNTPHS REGISTER UPON EITHER A SYNCI SIGNAL OR A S/W FORCE EVENT" "0,1"
newline
bitfld.long 0x00 20. "TSCNTSTP,COUNTER STOP [FREEZE] CONTROL:0COUNTER STOPPED1COUNTER FREE RUNNING" "0,1"
bitfld.long 0x00 19. "REARM_RESET,ONE-SHOT RE-ARMING IE WAIT FOR STOP TRIGGER:WRITING A ONE ARMS THE ONE-SHOT SEQUENCE IE:1] RESETS THE MOD4 COUNTER TO ZERO2] UN-FREEZES THE MOD4 COUNTER3] ENABLES CAPTURE REGISTER LOADSWRITING A ZERO HAS NO EFFECT ALWAYS RETURNS A 0NOTE: THE.." "0,1"
bitfld.long 0x00 17.--18. "STOPVALUE,STOP VALUE FOR ONE-SHOT MODE:THIS IS THE NUMBER [BETWEEN 1-4] OF CAPTURES ALLOWED TO OCCUR BEFORE THE CAP[1-4] REGISTERS ARE FROZEN IECAPTURE SEQUENCE IS STOPPED0 0STOP AFTER CAPTURE EVENT 10 1STOP AFTER CAPTURE EVENT 21 0STOP AFTER CAPTURE.." "0,1,2,3"
bitfld.long 0x00 16. "CONT_ONESHT,CONTINUOUS OR ONESHOT MODE CONTROL:[APPLICABLE ONLY IN CAPTURE MODE]0OPERATE IN CONTINUOUS MODE1OPERATE IN ONE-SHOT MODE" "0,1"
bitfld.long 0x00 15. "FREE,EMULATION CONTROL0 0 TSCNT COUNTER STOPS IMMEDIATELY ON EMULATION SUSPEND0 1 TSCNT COUNTER RUNS UNTIL = 01 X TSCNT COUNTER IS UNAFFECTED BY EMULATION SUSPEND [RUN FREE]" "0,1"
bitfld.long 0x00 14. "SOFT,EMULATION CONTROL0 0 TSCNT COUNTER STOPS IMMEDIATELY ON EMULATION SUSPEND0 1 TSCNT COUNTER RUNS UNTIL = 01 X TSCNT COUNTER IS UNAFFECTED BY EMULATION SUSPEND [RUN FREE]" "0,1"
newline
bitfld.long 0x00 9.--13. "EVTFLTPS,EVENT FILTER PRESCALE SELECT:0 0 0 0 0DIVIDE BY 1 [IE NO PRESCALE BY-PASS THE PRESCALER]0 0 0 0 1DIVIDE BY 20 0 0 1 0DIVIDE BY 40 0 0 1 1DIVIDE BY 60 0 1 0 0DIVIDE BY 80 0 1 0 1DIVIDE BY 10 1 1 1 1 0DIVIDE BY 601 1 1 1 1DIVIDE BY 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8. "CAPLDEN,ENABLE LOADING OF CAP1-4 REGISTERS ON A CAPTURE EVENT:0DISABLE CAP1-4 REGISTER LOADS AT CAPTURE EVENT TIME1ENABLE CAP1-4 REGISTER LOADS AT CAPTURE EVENT TIME" "0,1"
bitfld.long 0x00 7. "CTRRST4,COUNTER RESET ON CAPTURE EVENT 4:0DO NOT RESET COUNTER ON CAPTURE EVENT 4 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 4 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "0,1"
bitfld.long 0x00 6. "CAP4POL,CAPTURE EVENT 4 POLARITY SELECT:0CAPTURE EVENT 4 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 4 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
bitfld.long 0x00 5. "CTRRST3,COUNTER RESET ON CAPTURE EVENT 3:0DO NOT RESET COUNTER ON CAPTURE EVENT 3 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 3 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "0,1"
bitfld.long 0x00 4. "CAP3POL,CAPTURE EVENT 3 POLARITY SELECT:0CAPTURE EVENT 3 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 3 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
newline
bitfld.long 0x00 3. "CTRRST2,COUNTER RESET ON CAPTURE EVENT 2:0DO NOT RESET COUNTER ON CAPTURE EVENT 2 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 2 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "0,1"
bitfld.long 0x00 2. "CAP2POL,CAPTURE EVENT 2 POLARITY SELECT:0CAPTURE EVENT 2 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 2 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
bitfld.long 0x00 1. "CTRRST1,COUNTER RESET ON CAPTURE EVENT 1:0DO NOT RESET COUNTER ON CAPTURE EVENT 1 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 1 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "0,1"
bitfld.long 0x00 0. "CAP1POL,CAPTURE EVENT 1 POLARITY SELECT:0CAPTURE EVENT 1 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 1 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
line.long 0x04 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_ECFLG_ECEINT,ECAP INTERRUPT ENABLE REGISTER"
hexmask.long.byte 0x04 24.--31. 1. "FLAG_RESV0,"
rbitfld.long 0x04 23. "FLAG_CMPEQ,COMPARE EQUAL STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] REACHED THE COMPARE REGISTER VALUE [ACMP]READING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN APWM MODE" "0,1"
rbitfld.long 0x04 22. "FLAG_PRDEQ,PERIOD EQUAL STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] REACHED THE PERIOD REGISTER VALUE [APER] AND WAS RESETREADING A 0 INDICATES NO EVENT OCCURREDNOTES: THIS FLAG IS ONLY ACTIVE IN APWM MODE" "0,1"
rbitfld.long 0x04 21. "FLAG_CNTOVF,COUNTER OVERFLOW STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] HAS MADE THE TRANSITION FROM FFFFFFFF 00000000READING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ACTIVE IN CAP &AMP" "0,1"
rbitfld.long 0x04 20. "FLAG_CEVT4,CAPTURE EVENT 4 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE FOURTH EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
rbitfld.long 0x04 19. "FLAG_CEVT3,CAPTURE EVENT 3 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE THIRD EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
newline
rbitfld.long 0x04 18. "FLAG_CEVT2,CAPTURE EVENT 2 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE SECOND EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
rbitfld.long 0x04 17. "FLAG_CEVT1,CAPTURE EVENT 1 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE FIRST EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
rbitfld.long 0x04 16. "FLAG_INT,GLOBAL INTERRUPT STATUS FLAG: READING A 1 ON THIS BIT INDICATES THAT AN INTERRUPT WAS GENERATED FROM ONE OF THE FOLLOWING EVENTSREADING A 0 INDICATES NO INTERRUPT GENERATED" "0,1"
hexmask.long.byte 0x04 8.--15. 1. "EN__RESV1,"
bitfld.long 0x04 7. "EN_CMPEQ,COMPARE EQUAL INTERRUPT ENABLE: 0DISABLED COMPARE EQUAL AS AN INTERRUPT SOURCE1ENABLE COMPARE EQUAL AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x04 6. "EN_PRDEQ,PERIOD EQUAL INTERRUPT ENABLE: 0DISABLED PERIOD EQUAL AS AN INTERRUPT SOURCE1ENABLE PERIOD EQUAL AS AN INTERRUPT SOURCE" "0,1"
newline
bitfld.long 0x04 5. "EN_CNTOVF,COUNTER OVERFLOW INTERRUPT ENABLE: 0DISABLED COUNTER OVERFLOW AS AN INTERRUPT SOURCE1ENABLE COUNTER OVERFLOW AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x04 4. "EN_CEVT4,CAPTURE EVENT 4 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x04 3. "EN_CEVT3,CAPTURE EVENT 3 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x04 2. "EN_CEVT2,CAPTURE EVENT 2 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x04 1. "EN_CEVT1,CAPTURE EVENT 1 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
rbitfld.long 0x04 0. "EN_RESV0," "0,1"
line.long 0x08 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_ECCLR,ECAP INTERRUPT CLEAR REGISTER"
hexmask.long.byte 0x08 8.--15. 1. "_RESV0,"
bitfld.long 0x08 7. "CMPEQ,COMPARE EQUAL STATUS FLAG: WRITING A 1 WILL CLEAR THE CMPEQ FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
bitfld.long 0x08 6. "PRDEQ,PERIOD EQUAL STATUS FLAG: WRITING A 1 WILL CLEAR THE PRDEQ FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
bitfld.long 0x08 5. "CNTOVF,COUNTER OVERFLOW STATUS FLAG: WRITING A 1 WILL CLEAR THE CNTOVF FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
bitfld.long 0x08 4. "CEVT4,CAPTURE EVENT 4 STATUS FLAG: WRITING A 1 WILL CLEAR THE CEVT3 FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
bitfld.long 0x08 3. "CEVT3,CAPTURE EVENT 3 STATUS FLAG: WRITING A 1 WILL CLEAR THE CEVT3 FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
newline
bitfld.long 0x08 2. "CEVT2,CAPTURE EVENT 2 STATUS FLAG: WRITING A 1 WILL CLEAR THE CEVT2 FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
bitfld.long 0x08 1. "CEVT1,CAPTURE EVENT 1 STATUS FLAG: WRITING A 1 WILL CLEAR THE CEVT1 FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
bitfld.long 0x08 0. "INT,GLOBAL INTERRUPT CLEAR FLAG: WRITING A 1 WILL CLEAR THE INT FLAG AND ENABLE FURTHER INTERRUPTS TO BE GENERATED IF ANY OF THE EVENT FLAGS ARE SET TO 1WRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
line.long 0x0C "PR1_ICSS_ECAP0__ECAP_SLV__REGS_ECFRC,ECAP INTERRUPT FORCING REGISTER"
hexmask.long.byte 0x0C 8.--15. 1. "_RESV1,"
bitfld.long 0x0C 7. "CMPEQ,FORCE COMPARE EQUAL: WRITING A 1 TO THIS BIT WILL SET THE CMPEQ FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0" "0,1"
bitfld.long 0x0C 6. "PRDEQ,FORCE PERIOD EQUAL: WRITING A 1 TO THIS BIT WILL SET THE PRDEQ FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0" "0,1"
bitfld.long 0x0C 5. "CNTOVF,FORCE COUNTER OVERFLOW: WRITING A 1 TO THIS BIT WILL SET THE CNTOVF FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0" "0,1"
bitfld.long 0x0C 4. "CEVT4,FORCE CAPTURE EVENT" "0,1"
bitfld.long 0x0C 3. "CEVT3,FORCE CAPTURE EVENT" "0,1"
newline
bitfld.long 0x0C 2. "CEVT2,FORCE CAPTURE EVENT" "0,1"
bitfld.long 0x0C 1. "CEVT1,FORCE CAPTURE EVENT" "0,1"
rbitfld.long 0x0C 0. "_RESV0," "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_PID,ECAP PERIPHERAL ID REGISTER"
tree.end
tree "ICSSM0_PR1_ICSS_INTC_INTC_SLV"
base ad:0x30060000
rgroup.long 0x00++0x07
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_REVISION_REG,"
bitfld.long 0x00 30.--31. "REV_SCHEME,Scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "REV_MODULE,Module ID"
bitfld.long 0x00 11.--15. "REV_RTL,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REV_MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "REV_CUSTOM,Custom revision" "0,1,2,3"
bitfld.long 0x00 0.--5. "REV_MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_CONTROL_REG,"
bitfld.long 0x04 4. "PRIORITY_HOLD_MODE,Priority Holding Mode" "0,1"
bitfld.long 0x04 2.--3. "NEST_MODE,Nesting Mode" "0,1,2,3"
bitfld.long 0x04 1. "WAKEUP_MODE,Wakeup mode enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_GLOBAL_ENABLE_HINT_REG,"
bitfld.long 0x00 0. "ENABLE_HINT_ANY,Global Enable for all Host Ints" "0,1"
group.long 0x1C++0x13
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_GLB_NEST_LEVEL_REG,"
bitfld.long 0x00 31. "GLB_NEST_AUTO_OVR,Global Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "GLB_NEST_LEVEL,Global Nesting Level"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_STATUS_SET_INDEX_REG,"
hexmask.long.word 0x04 0.--9. 1. "STATUS_SET_INDEX,Status Set Index Register (write index to set status of)"
line.long 0x08 "PR1_ICSS_INTC__INTC_SLV__REGS_STATUS_CLR_INDEX_REG,"
hexmask.long.word 0x08 0.--9. 1. "STATUS_CLR_INDEX,Status Clear Index Register (write index to clear status of)"
line.long 0x0C "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_SET_INDEX_REG,"
hexmask.long.word 0x0C 0.--9. 1. "ENABLE_SET_INDEX,Enable Set Index Register (write index to set enable of)"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_INDEX_REG,"
hexmask.long.word 0x10 0.--9. 1. "ENABLE_CLR_INDEX,Enable Clear Index Register (write index to clear enable of)"
group.long 0x34++0x07
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_ENABLE_SET_INDEX_REG,"
hexmask.long.word 0x00 0.--9. 1. "HINT_ENABLE_SET_INDEX,Enable set for Host Interrupts"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_ENABLE_CLR_INDEX_REG,"
hexmask.long.word 0x04 0.--9. 1. "HINT_ENABLE_CLR_INDEX,Enable clear for Host Interrupts"
rgroup.long 0x80++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_GLB_PRI_INTR_REG,"
bitfld.long 0x00 31. "GLB_NONE,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "GLB_PRI_INTR,Prioritized Interrupt"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x200)++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG$1,"
bitfld.long 0x00 31. "RAW_STATUS_31,Raw Status (write 1 to set) for intr_in[31]" "0,1"
bitfld.long 0x00 30. "RAW_STATUS_30,Raw Status (write 1 to set) for intr_in[30]" "0,1"
bitfld.long 0x00 29. "RAW_STATUS_29,Raw Status (write 1 to set) for intr_in[29]" "0,1"
newline
bitfld.long 0x00 28. "RAW_STATUS_28,Raw Status (write 1 to set) for intr_in[28]" "0,1"
bitfld.long 0x00 27. "RAW_STATUS_27,Raw Status (write 1 to set) for intr_in[27]" "0,1"
bitfld.long 0x00 26. "RAW_STATUS_26,Raw Status (write 1 to set) for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "RAW_STATUS_25,Raw Status (write 1 to set) for intr_in[25]" "0,1"
bitfld.long 0x00 24. "RAW_STATUS_24,Raw Status (write 1 to set) for intr_in[24]" "0,1"
bitfld.long 0x00 23. "RAW_STATUS_23,Raw Status (write 1 to set) for intr_in[23]" "0,1"
newline
bitfld.long 0x00 22. "RAW_STATUS_22,Raw Status (write 1 to set) for intr_in[22]" "0,1"
bitfld.long 0x00 21. "RAW_STATUS_21,Raw Status (write 1 to set) for intr_in[21]" "0,1"
bitfld.long 0x00 20. "RAW_STATUS_20,Raw Status (write 1 to set) for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "RAW_STATUS_19,Raw Status (write 1 to set) for intr_in[19]" "0,1"
bitfld.long 0x00 18. "RAW_STATUS_18,Raw Status (write 1 to set) for intr_in[18]" "0,1"
bitfld.long 0x00 17. "RAW_STATUS_17,Raw Status (write 1 to set) for intr_in[17]" "0,1"
newline
bitfld.long 0x00 16. "RAW_STATUS_16,Raw Status (write 1 to set) for intr_in[16]" "0,1"
bitfld.long 0x00 15. "RAW_STATUS_15,Raw Status (write 1 to set) for intr_in[15]" "0,1"
bitfld.long 0x00 14. "RAW_STATUS_14,Raw Status (write 1 to set) for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "RAW_STATUS_13,Raw Status (write 1 to set) for intr_in[13]" "0,1"
bitfld.long 0x00 12. "RAW_STATUS_12,Raw Status (write 1 to set) for intr_in[12]" "0,1"
bitfld.long 0x00 11. "RAW_STATUS_11,Raw Status (write 1 to set) for intr_in[11]" "0,1"
newline
bitfld.long 0x00 10. "RAW_STATUS_10,Raw Status (write 1 to set) for intr_in[10]" "0,1"
bitfld.long 0x00 9. "RAW_STATUS_9,Raw Status (write 1 to set) for intr_in[9]" "0,1"
bitfld.long 0x00 8. "RAW_STATUS_8,Raw Status (write 1 to set) for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "RAW_STATUS_7,Raw Status (write 1 to set) for intr_in[7]" "0,1"
bitfld.long 0x00 6. "RAW_STATUS_6,Raw Status (write 1 to set) for intr_in[6]" "0,1"
bitfld.long 0x00 5. "RAW_STATUS_5,Raw Status (write 1 to set) for intr_in[5]" "0,1"
newline
bitfld.long 0x00 4. "RAW_STATUS_4,Raw Status (write 1 to set) for intr_in[4]" "0,1"
bitfld.long 0x00 3. "RAW_STATUS_3,Raw Status (write 1 to set) for intr_in[3]" "0,1"
bitfld.long 0x00 2. "RAW_STATUS_2,Raw Status (write 1 to set) for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "RAW_STATUS_1,Raw Status (write 1 to set) for intr_in[1]" "0,1"
bitfld.long 0x00 0. "RAW_STATUS_0,Raw Status (write 1 to set) for intr_in[0]" "0,1"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x280)++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG$1,"
bitfld.long 0x00 31. "ENA_STATUS_31,Enabled Status for intr_in[31]" "0,1"
bitfld.long 0x00 30. "ENA_STATUS_30,Enabled Status for intr_in[30]" "0,1"
bitfld.long 0x00 29. "ENA_STATUS_29,Enabled Status for intr_in[29]" "0,1"
newline
bitfld.long 0x00 28. "ENA_STATUS_28,Enabled Status for intr_in[28]" "0,1"
bitfld.long 0x00 27. "ENA_STATUS_27,Enabled Status for intr_in[27]" "0,1"
bitfld.long 0x00 26. "ENA_STATUS_26,Enabled Status for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "ENA_STATUS_25,Enabled Status for intr_in[25]" "0,1"
bitfld.long 0x00 24. "ENA_STATUS_24,Enabled Status for intr_in[24]" "0,1"
bitfld.long 0x00 23. "ENA_STATUS_23,Enabled Status for intr_in[23]" "0,1"
newline
bitfld.long 0x00 22. "ENA_STATUS_22,Enabled Status for intr_in[22]" "0,1"
bitfld.long 0x00 21. "ENA_STATUS_21,Enabled Status for intr_in[21]" "0,1"
bitfld.long 0x00 20. "ENA_STATUS_20,Enabled Status for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENA_STATUS_19,Enabled Status for intr_in[19]" "0,1"
bitfld.long 0x00 18. "ENA_STATUS_18,Enabled Status for intr_in[18]" "0,1"
bitfld.long 0x00 17. "ENA_STATUS_17,Enabled Status for intr_in[17]" "0,1"
newline
bitfld.long 0x00 16. "ENA_STATUS_16,Enabled Status for intr_in[16]" "0,1"
bitfld.long 0x00 15. "ENA_STATUS_15,Enabled Status for intr_in[15]" "0,1"
bitfld.long 0x00 14. "ENA_STATUS_14,Enabled Status for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "ENA_STATUS_13,Enabled Status for intr_in[13]" "0,1"
bitfld.long 0x00 12. "ENA_STATUS_12,Enabled Status for intr_in[12]" "0,1"
bitfld.long 0x00 11. "ENA_STATUS_11,Enabled Status for intr_in[11]" "0,1"
newline
bitfld.long 0x00 10. "ENA_STATUS_10,Enabled Status for intr_in[10]" "0,1"
bitfld.long 0x00 9. "ENA_STATUS_9,Enabled Status for intr_in[9]" "0,1"
bitfld.long 0x00 8. "ENA_STATUS_8,Enabled Status for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENA_STATUS_7,Enabled Status for intr_in[7]" "0,1"
bitfld.long 0x00 6. "ENA_STATUS_6,Enabled Status for intr_in[6]" "0,1"
bitfld.long 0x00 5. "ENA_STATUS_5,Enabled Status for intr_in[5]" "0,1"
newline
bitfld.long 0x00 4. "ENA_STATUS_4,Enabled Status for intr_in[4]" "0,1"
bitfld.long 0x00 3. "ENA_STATUS_3,Enabled Status for intr_in[3]" "0,1"
bitfld.long 0x00 2. "ENA_STATUS_2,Enabled Status for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "ENA_STATUS_1,Enabled Status for intr_in[1]" "0,1"
bitfld.long 0x00 0. "ENA_STATUS_0,Enabled Status for intr_in[0]" "0,1"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x300)++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG$1,"
bitfld.long 0x00 31. "ENABLE_31,Enable (set) for intr_in[31]" "0,1"
bitfld.long 0x00 30. "ENABLE_30,Enable (set) for intr_in[30]" "0,1"
bitfld.long 0x00 29. "ENABLE_29,Enable (set) for intr_in[29]" "0,1"
newline
bitfld.long 0x00 28. "ENABLE_28,Enable (set) for intr_in[28]" "0,1"
bitfld.long 0x00 27. "ENABLE_27,Enable (set) for intr_in[27]" "0,1"
bitfld.long 0x00 26. "ENABLE_26,Enable (set) for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_25,Enable (set) for intr_in[25]" "0,1"
bitfld.long 0x00 24. "ENABLE_24,Enable (set) for intr_in[24]" "0,1"
bitfld.long 0x00 23. "ENABLE_23,Enable (set) for intr_in[23]" "0,1"
newline
bitfld.long 0x00 22. "ENABLE_22,Enable (set) for intr_in[22]" "0,1"
bitfld.long 0x00 21. "ENABLE_21,Enable (set) for intr_in[21]" "0,1"
bitfld.long 0x00 20. "ENABLE_20,Enable (set) for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_19,Enable (set) for intr_in[19]" "0,1"
bitfld.long 0x00 18. "ENABLE_18,Enable (set) for intr_in[18]" "0,1"
bitfld.long 0x00 17. "ENABLE_17,Enable (set) for intr_in[17]" "0,1"
newline
bitfld.long 0x00 16. "ENABLE_16,Enable (set) for intr_in[16]" "0,1"
bitfld.long 0x00 15. "ENABLE_15,Enable (set) for intr_in[15]" "0,1"
bitfld.long 0x00 14. "ENABLE_14,Enable (set) for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_13,Enable (set) for intr_in[13]" "0,1"
bitfld.long 0x00 12. "ENABLE_12,Enable (set) for intr_in[12]" "0,1"
bitfld.long 0x00 11. "ENABLE_11,Enable (set) for intr_in[11]" "0,1"
newline
bitfld.long 0x00 10. "ENABLE_10,Enable (set) for intr_in[10]" "0,1"
bitfld.long 0x00 9. "ENABLE_9,Enable (set) for intr_in[9]" "0,1"
bitfld.long 0x00 8. "ENABLE_8,Enable (set) for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_7,Enable (set) for intr_in[7]" "0,1"
bitfld.long 0x00 6. "ENABLE_6,Enable (set) for intr_in[6]" "0,1"
bitfld.long 0x00 5. "ENABLE_5,Enable (set) for intr_in[5]" "0,1"
newline
bitfld.long 0x00 4. "ENABLE_4,Enable (set) for intr_in[4]" "0,1"
bitfld.long 0x00 3. "ENABLE_3,Enable (set) for intr_in[3]" "0,1"
bitfld.long 0x00 2. "ENABLE_2,Enable (set) for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_1,Enable (set) for intr_in[1]" "0,1"
bitfld.long 0x00 0. "ENABLE_0,Enable (set) for intr_in[0]" "0,1"
repeat.end
group.long 0x380++0x07
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG0,"
bitfld.long 0x00 31. "ENABLE_31_CLR,Enable clear for intr_in[31]" "0,1"
bitfld.long 0x00 30. "ENABLE_30_CLR,Enable clear for intr_in[30]" "0,1"
bitfld.long 0x00 29. "ENABLE_29_CLR,Enable clear for intr_in[29]" "0,1"
newline
bitfld.long 0x00 28. "ENABLE_28_CLR,Enable clear for intr_in[28]" "0,1"
bitfld.long 0x00 27. "ENABLE_27_CLR,Enable clear for intr_in[27]" "0,1"
bitfld.long 0x00 26. "ENABLE_26_CLR,Enable clear for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_25_CLR,Enable clear for intr_in[25]" "0,1"
bitfld.long 0x00 24. "ENABLE_24_CLR,Enable clear for intr_in[24]" "0,1"
bitfld.long 0x00 23. "ENABLE_23_CLR,Enable clear for intr_in[23]" "0,1"
newline
bitfld.long 0x00 22. "ENABLE_22_CLR,Enable clear for intr_in[22]" "0,1"
bitfld.long 0x00 21. "ENABLE_21_CLR,Enable clear for intr_in[21]" "0,1"
bitfld.long 0x00 20. "ENABLE_20_CLR,Enable clear for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_19_CLR,Enable clear for intr_in[19]" "0,1"
bitfld.long 0x00 18. "ENABLE_18_CLR,Enable clear for intr_in[18]" "0,1"
bitfld.long 0x00 17. "ENABLE_17_CLR,Enable clear for intr_in[17]" "0,1"
newline
bitfld.long 0x00 16. "ENABLE_16_CLR,Enable clear for intr_in[16]" "0,1"
bitfld.long 0x00 15. "ENABLE_15_CLR,Enable clear for intr_in[15]" "0,1"
bitfld.long 0x00 14. "ENABLE_14_CLR,Enable clear for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_13_CLR,Enable clear for intr_in[13]" "0,1"
bitfld.long 0x00 12. "ENABLE_12_CLR,Enable clear for intr_in[12]" "0,1"
bitfld.long 0x00 11. "ENABLE_11_CLR,Enable clear for intr_in[11]" "0,1"
newline
bitfld.long 0x00 10. "ENABLE_10_CLR,Enable clear for intr_in[10]" "0,1"
bitfld.long 0x00 9. "ENABLE_9_CLR,Enable clear for intr_in[9]" "0,1"
bitfld.long 0x00 8. "ENABLE_8_CLR,Enable clear for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_7_CLR,Enable clear for intr_in[7]" "0,1"
bitfld.long 0x00 6. "ENABLE_6_CLR,Enable clear for intr_in[6]" "0,1"
bitfld.long 0x00 5. "ENABLE_5_CLR,Enable clear for intr_in[5]" "0,1"
newline
bitfld.long 0x00 4. "ENABLE_4_CLR,Enable clear for intr_in[4]" "0,1"
bitfld.long 0x00 3. "ENABLE_3_CLR,Enable clear for intr_in[3]" "0,1"
bitfld.long 0x00 2. "ENABLE_2_CLR,Enable clear for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_1_CLR,Enable clear for intr_in[1]" "0,1"
bitfld.long 0x00 0. "ENABLE_0_CLR,Enable clear for intr_in[0]" "0,1"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG1,"
bitfld.long 0x04 31. "ENABLE_63_CLR,Enable clear for intr_in[63]" "0,1"
bitfld.long 0x04 30. "ENABLE_62_CLR,Enable clear for intr_in[62]" "0,1"
bitfld.long 0x04 29. "ENABLE_61_CLR,Enable clear for intr_in[61]" "0,1"
newline
bitfld.long 0x04 28. "ENABLE_60_CLR,Enable clear for intr_in[60]" "0,1"
bitfld.long 0x04 27. "ENABLE_59_CLR,Enable clear for intr_in[59]" "0,1"
bitfld.long 0x04 26. "ENABLE_58_CLR,Enable clear for intr_in[58]" "0,1"
newline
bitfld.long 0x04 25. "ENABLE_57_CLR,Enable clear for intr_in[57]" "0,1"
bitfld.long 0x04 24. "ENABLE_56_CLR,Enable clear for intr_in[56]" "0,1"
bitfld.long 0x04 23. "ENABLE_55_CLR,Enable clear for intr_in[55]" "0,1"
newline
bitfld.long 0x04 22. "ENABLE_54_CLR,Enable clear for intr_in[54]" "0,1"
bitfld.long 0x04 21. "ENABLE_53_CLR,Enable clear for intr_in[53]" "0,1"
bitfld.long 0x04 20. "ENABLE_52_CLR,Enable clear for intr_in[52]" "0,1"
newline
bitfld.long 0x04 19. "ENABLE_51_CLR,Enable clear for intr_in[51]" "0,1"
bitfld.long 0x04 18. "ENABLE_50_CLR,Enable clear for intr_in[50]" "0,1"
bitfld.long 0x04 17. "ENABLE_49_CLR,Enable clear for intr_in[49]" "0,1"
newline
bitfld.long 0x04 16. "ENABLE_48_CLR,Enable clear for intr_in[48]" "0,1"
bitfld.long 0x04 15. "ENABLE_47_CLR,Enable clear for intr_in[47]" "0,1"
bitfld.long 0x04 14. "ENABLE_46_CLR,Enable clear for intr_in[46]" "0,1"
newline
bitfld.long 0x04 13. "ENABLE_45_CLR,Enable clear for intr_in[45]" "0,1"
bitfld.long 0x04 12. "ENABLE_44_CLR,Enable clear for intr_in[44]" "0,1"
bitfld.long 0x04 11. "ENABLE_43_CLR,Enable clear for intr_in[43]" "0,1"
newline
bitfld.long 0x04 10. "ENABLE_42_CLR,Enable clear for intr_in[42]" "0,1"
bitfld.long 0x04 9. "ENABLE_41_CLR,Enable clear for intr_in[41]" "0,1"
bitfld.long 0x04 8. "ENABLE_40_CLR,Enable clear for intr_in[40]" "0,1"
newline
bitfld.long 0x04 7. "ENABLE_39_CLR,Enable clear for intr_in[39]" "0,1"
bitfld.long 0x04 6. "ENABLE_38_CLR,Enable clear for intr_in[38]" "0,1"
bitfld.long 0x04 5. "ENABLE_37_CLR,Enable clear for intr_in[37]" "0,1"
newline
bitfld.long 0x04 4. "ENABLE_36_CLR,Enable clear for intr_in[36]" "0,1"
bitfld.long 0x04 3. "ENABLE_35_CLR,Enable clear for intr_in[35]" "0,1"
bitfld.long 0x04 2. "ENABLE_34_CLR,Enable clear for intr_in[34]" "0,1"
newline
bitfld.long 0x04 1. "ENABLE_33_CLR,Enable clear for intr_in[33]" "0,1"
bitfld.long 0x04 0. "ENABLE_32_CLR,Enable clear for intr_in[32]" "0,1"
group.long 0x400++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG0,"
bitfld.long 0x00 24.--27. "CH_MAP_3,Interrupt Channel Map for intr_in[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "CH_MAP_2,Interrupt Channel Map for intr_in[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "CH_MAP_1,Interrupt Channel Map for intr_in[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "CH_MAP_0,Interrupt Channel Map for intr_in[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 15. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
group.long ($2+0x404)++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG$1,"
bitfld.long 0x00 24.--27. "CH_MAP_7,Interrupt Channel Map for intr_in[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "CH_MAP_6,Interrupt Channel Map for intr_in[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "CH_MAP_5,Interrupt Channel Map for intr_in[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "CH_MAP_4,Interrupt Channel Map for intr_in[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x800)++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG$1,"
bitfld.long 0x00 24.--27. "HINT_MAP_3,Host Interrupt Map for Channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "HINT_MAP_2,Host Interrupt Map for Channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "HINT_MAP_1,Host Interrupt Map for Channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "HINT_MAP_0,Host Interrupt Map for Channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
group.long 0x808++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG2,"
bitfld.long 0x00 8.--11. "HINT_MAP_9,Host Interrupt Map for Channel 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "HINT_MAP_8,Host Interrupt Map for Channel 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x900++0x27
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG0,"
bitfld.long 0x00 31. "NONE_HINT_0,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "PRI_HINT_0,Host Int 0 Prioritized Interrupt"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG1,"
bitfld.long 0x04 31. "NONE_HINT_1,No interrupt pending flag" "0,1"
hexmask.long.word 0x04 0.--9. 1. "PRI_HINT_1,Host Int 1 Prioritized Interrupt"
line.long 0x08 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG2,"
bitfld.long 0x08 31. "NONE_HINT_2,No interrupt pending flag" "0,1"
hexmask.long.word 0x08 0.--9. 1. "PRI_HINT_2,Host Int 2 Prioritized Interrupt"
line.long 0x0C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG3,"
bitfld.long 0x0C 31. "NONE_HINT_3,No interrupt pending flag" "0,1"
hexmask.long.word 0x0C 0.--9. 1. "PRI_HINT_3,Host Int 3 Prioritized Interrupt"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG4,"
bitfld.long 0x10 31. "NONE_HINT_4,No interrupt pending flag" "0,1"
hexmask.long.word 0x10 0.--9. 1. "PRI_HINT_4,Host Int 4 Prioritized Interrupt"
line.long 0x14 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG5,"
bitfld.long 0x14 31. "NONE_HINT_5,No interrupt pending flag" "0,1"
hexmask.long.word 0x14 0.--9. 1. "PRI_HINT_5,Host Int 5 Prioritized Interrupt"
line.long 0x18 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG6,"
bitfld.long 0x18 31. "NONE_HINT_6,No interrupt pending flag" "0,1"
hexmask.long.word 0x18 0.--9. 1. "PRI_HINT_6,Host Int 6 Prioritized Interrupt"
line.long 0x1C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG7,"
bitfld.long 0x1C 31. "NONE_HINT_7,No interrupt pending flag" "0,1"
hexmask.long.word 0x1C 0.--9. 1. "PRI_HINT_7,Host Int 7 Prioritized Interrupt"
line.long 0x20 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG8,"
bitfld.long 0x20 31. "NONE_HINT_8,No interrupt pending flag" "0,1"
hexmask.long.word 0x20 0.--9. 1. "PRI_HINT_8,Host Int 8 Prioritized Interrupt"
line.long 0x24 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG9,"
bitfld.long 0x24 31. "NONE_HINT_9,No interrupt pending flag" "0,1"
hexmask.long.word 0x24 0.--9. 1. "PRI_HINT_9,Host Int 9 Prioritized Interrupt"
group.long 0xD00++0x07
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG0,"
bitfld.long 0x00 31. "POLARITY_31,Polarity for intr_in[31]" "0,1"
bitfld.long 0x00 30. "POLARITY_30,Polarity for intr_in[30]" "0,1"
bitfld.long 0x00 29. "POLARITY_29,Polarity for intr_in[29]" "0,1"
newline
bitfld.long 0x00 28. "POLARITY_28,Polarity for intr_in[28]" "0,1"
bitfld.long 0x00 27. "POLARITY_27,Polarity for intr_in[27]" "0,1"
bitfld.long 0x00 26. "POLARITY_26,Polarity for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "POLARITY_25,Polarity for intr_in[25]" "0,1"
bitfld.long 0x00 24. "POLARITY_24,Polarity for intr_in[24]" "0,1"
bitfld.long 0x00 23. "POLARITY_23,Polarity for intr_in[23]" "0,1"
newline
bitfld.long 0x00 22. "POLARITY_22,Polarity for intr_in[22]" "0,1"
bitfld.long 0x00 21. "POLARITY_21,Polarity for intr_in[21]" "0,1"
bitfld.long 0x00 20. "POLARITY_20,Polarity for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "POLARITY_19,Polarity for intr_in[19]" "0,1"
bitfld.long 0x00 18. "POLARITY_18,Polarity for intr_in[18]" "0,1"
bitfld.long 0x00 17. "POLARITY_17,Polarity for intr_in[17]" "0,1"
newline
bitfld.long 0x00 16. "POLARITY_16,Polarity for intr_in[16]" "0,1"
bitfld.long 0x00 15. "POLARITY_15,Polarity for intr_in[15]" "0,1"
bitfld.long 0x00 14. "POLARITY_14,Polarity for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "POLARITY_13,Polarity for intr_in[13]" "0,1"
bitfld.long 0x00 12. "POLARITY_12,Polarity for intr_in[12]" "0,1"
bitfld.long 0x00 11. "POLARITY_11,Polarity for intr_in[11]" "0,1"
newline
bitfld.long 0x00 10. "POLARITY_10,Polarity for intr_in[10]" "0,1"
bitfld.long 0x00 9. "POLARITY_9,Polarity for intr_in[9]" "0,1"
bitfld.long 0x00 8. "POLARITY_8,Polarity for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "POLARITY_7,Polarity for intr_in[7]" "0,1"
bitfld.long 0x00 6. "POLARITY_6,Polarity for intr_in[6]" "0,1"
bitfld.long 0x00 5. "POLARITY_5,Polarity for intr_in[5]" "0,1"
newline
bitfld.long 0x00 4. "POLARITY_4,Polarity for intr_in[4]" "0,1"
bitfld.long 0x00 3. "POLARITY_3,Polarity for intr_in[3]" "0,1"
bitfld.long 0x00 2. "POLARITY_2,Polarity for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "POLARITY_1,Polarity for intr_in[1]" "0,1"
bitfld.long 0x00 0. "POLARITY_0,Polarity for intr_in[0]" "0,1"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG1,"
bitfld.long 0x04 31. "POLARITY_63,Polarity for intr_in[63]" "0,1"
bitfld.long 0x04 30. "POLARITY_62,Polarity for intr_in[62]" "0,1"
bitfld.long 0x04 29. "POLARITY_61,Polarity for intr_in[61]" "0,1"
newline
bitfld.long 0x04 28. "POLARITY_60,Polarity for intr_in[60]" "0,1"
bitfld.long 0x04 27. "POLARITY_59,Polarity for intr_in[59]" "0,1"
bitfld.long 0x04 26. "POLARITY_58,Polarity for intr_in[58]" "0,1"
newline
bitfld.long 0x04 25. "POLARITY_57,Polarity for intr_in[57]" "0,1"
bitfld.long 0x04 24. "POLARITY_56,Polarity for intr_in[56]" "0,1"
bitfld.long 0x04 23. "POLARITY_55,Polarity for intr_in[55]" "0,1"
newline
bitfld.long 0x04 22. "POLARITY_54,Polarity for intr_in[54]" "0,1"
bitfld.long 0x04 21. "POLARITY_53,Polarity for intr_in[53]" "0,1"
bitfld.long 0x04 20. "POLARITY_52,Polarity for intr_in[52]" "0,1"
newline
bitfld.long 0x04 19. "POLARITY_51,Polarity for intr_in[51]" "0,1"
bitfld.long 0x04 18. "POLARITY_50,Polarity for intr_in[50]" "0,1"
bitfld.long 0x04 17. "POLARITY_49,Polarity for intr_in[49]" "0,1"
newline
bitfld.long 0x04 16. "POLARITY_48,Polarity for intr_in[48]" "0,1"
bitfld.long 0x04 15. "POLARITY_47,Polarity for intr_in[47]" "0,1"
bitfld.long 0x04 14. "POLARITY_46,Polarity for intr_in[46]" "0,1"
newline
bitfld.long 0x04 13. "POLARITY_45,Polarity for intr_in[45]" "0,1"
bitfld.long 0x04 12. "POLARITY_44,Polarity for intr_in[44]" "0,1"
bitfld.long 0x04 11. "POLARITY_43,Polarity for intr_in[43]" "0,1"
newline
bitfld.long 0x04 10. "POLARITY_42,Polarity for intr_in[42]" "0,1"
bitfld.long 0x04 9. "POLARITY_41,Polarity for intr_in[41]" "0,1"
bitfld.long 0x04 8. "POLARITY_40,Polarity for intr_in[40]" "0,1"
newline
bitfld.long 0x04 7. "POLARITY_39,Polarity for intr_in[39]" "0,1"
bitfld.long 0x04 6. "POLARITY_38,Polarity for intr_in[38]" "0,1"
bitfld.long 0x04 5. "POLARITY_37,Polarity for intr_in[37]" "0,1"
newline
bitfld.long 0x04 4. "POLARITY_36,Polarity for intr_in[36]" "0,1"
bitfld.long 0x04 3. "POLARITY_35,Polarity for intr_in[35]" "0,1"
bitfld.long 0x04 2. "POLARITY_34,Polarity for intr_in[34]" "0,1"
newline
bitfld.long 0x04 1. "POLARITY_33,Polarity for intr_in[33]" "0,1"
bitfld.long 0x04 0. "POLARITY_32,Polarity for intr_in[32]" "0,1"
group.long 0xD80++0x07
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG0,"
bitfld.long 0x00 31. "TYPE_31,Type for intr_in[31]" "0,1"
bitfld.long 0x00 30. "TYPE_30,Type for intr_in[30]" "0,1"
bitfld.long 0x00 29. "TYPE_29,Type for intr_in[29]" "0,1"
newline
bitfld.long 0x00 28. "TYPE_28,Type for intr_in[28]" "0,1"
bitfld.long 0x00 27. "TYPE_27,Type for intr_in[27]" "0,1"
bitfld.long 0x00 26. "TYPE_26,Type for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "TYPE_25,Type for intr_in[25]" "0,1"
bitfld.long 0x00 24. "TYPE_24,Type for intr_in[24]" "0,1"
bitfld.long 0x00 23. "TYPE_23,Type for intr_in[23]" "0,1"
newline
bitfld.long 0x00 22. "TYPE_22,Type for intr_in[22]" "0,1"
bitfld.long 0x00 21. "TYPE_21,Type for intr_in[21]" "0,1"
bitfld.long 0x00 20. "TYPE_20,Type for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "TYPE_19,Type for intr_in[19]" "0,1"
bitfld.long 0x00 18. "TYPE_18,Type for intr_in[18]" "0,1"
bitfld.long 0x00 17. "TYPE_17,Type for intr_in[17]" "0,1"
newline
bitfld.long 0x00 16. "TYPE_16,Type for intr_in[16]" "0,1"
bitfld.long 0x00 15. "TYPE_15,Type for intr_in[15]" "0,1"
bitfld.long 0x00 14. "TYPE_14,Type for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "TYPE_13,Type for intr_in[13]" "0,1"
bitfld.long 0x00 12. "TYPE_12,Type for intr_in[12]" "0,1"
bitfld.long 0x00 11. "TYPE_11,Type for intr_in[11]" "0,1"
newline
bitfld.long 0x00 10. "TYPE_10,Type for intr_in[10]" "0,1"
bitfld.long 0x00 9. "TYPE_9,Type for intr_in[9]" "0,1"
bitfld.long 0x00 8. "TYPE_8,Type for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "TYPE_7,Type for intr_in[7]" "0,1"
bitfld.long 0x00 6. "TYPE_6,Type for intr_in[6]" "0,1"
bitfld.long 0x00 5. "TYPE_5,Type for intr_in[5]" "0,1"
newline
bitfld.long 0x00 4. "TYPE_4,Type for intr_in[4]" "0,1"
bitfld.long 0x00 3. "TYPE_3,Type for intr_in[3]" "0,1"
bitfld.long 0x00 2. "TYPE_2,Type for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "TYPE_1,Type for intr_in[1]" "0,1"
bitfld.long 0x00 0. "TYPE_0,Type for intr_in[0]" "0,1"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG1,"
bitfld.long 0x04 31. "TYPE_63,Type for intr_in[63]" "0,1"
bitfld.long 0x04 30. "TYPE_62,Type for intr_in[62]" "0,1"
bitfld.long 0x04 29. "TYPE_61,Type for intr_in[61]" "0,1"
newline
bitfld.long 0x04 28. "TYPE_60,Type for intr_in[60]" "0,1"
bitfld.long 0x04 27. "TYPE_59,Type for intr_in[59]" "0,1"
bitfld.long 0x04 26. "TYPE_58,Type for intr_in[58]" "0,1"
newline
bitfld.long 0x04 25. "TYPE_57,Type for intr_in[57]" "0,1"
bitfld.long 0x04 24. "TYPE_56,Type for intr_in[56]" "0,1"
bitfld.long 0x04 23. "TYPE_55,Type for intr_in[55]" "0,1"
newline
bitfld.long 0x04 22. "TYPE_54,Type for intr_in[54]" "0,1"
bitfld.long 0x04 21. "TYPE_53,Type for intr_in[53]" "0,1"
bitfld.long 0x04 20. "TYPE_52,Type for intr_in[52]" "0,1"
newline
bitfld.long 0x04 19. "TYPE_51,Type for intr_in[51]" "0,1"
bitfld.long 0x04 18. "TYPE_50,Type for intr_in[50]" "0,1"
bitfld.long 0x04 17. "TYPE_49,Type for intr_in[49]" "0,1"
newline
bitfld.long 0x04 16. "TYPE_48,Type for intr_in[48]" "0,1"
bitfld.long 0x04 15. "TYPE_47,Type for intr_in[47]" "0,1"
bitfld.long 0x04 14. "TYPE_46,Type for intr_in[46]" "0,1"
newline
bitfld.long 0x04 13. "TYPE_45,Type for intr_in[45]" "0,1"
bitfld.long 0x04 12. "TYPE_44,Type for intr_in[44]" "0,1"
bitfld.long 0x04 11. "TYPE_43,Type for intr_in[43]" "0,1"
newline
bitfld.long 0x04 10. "TYPE_42,Type for intr_in[42]" "0,1"
bitfld.long 0x04 9. "TYPE_41,Type for intr_in[41]" "0,1"
bitfld.long 0x04 8. "TYPE_40,Type for intr_in[40]" "0,1"
newline
bitfld.long 0x04 7. "TYPE_39,Type for intr_in[39]" "0,1"
bitfld.long 0x04 6. "TYPE_38,Type for intr_in[38]" "0,1"
bitfld.long 0x04 5. "TYPE_37,Type for intr_in[37]" "0,1"
newline
bitfld.long 0x04 4. "TYPE_36,Type for intr_in[36]" "0,1"
bitfld.long 0x04 3. "TYPE_35,Type for intr_in[35]" "0,1"
bitfld.long 0x04 2. "TYPE_34,Type for intr_in[34]" "0,1"
newline
bitfld.long 0x04 1. "TYPE_33,Type for intr_in[33]" "0,1"
bitfld.long 0x04 0. "TYPE_32,Type for intr_in[32]" "0,1"
group.long 0x1100++0x27
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG0,"
bitfld.long 0x00 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "NEST_HINT_0,Host Int 0 Nesting Level"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG1,"
bitfld.long 0x04 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x04 0.--8. 1. "NEST_HINT_1,Host Int 1 Nesting Level"
line.long 0x08 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG2,"
bitfld.long 0x08 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x08 0.--8. 1. "NEST_HINT_2,Host Int 2 Nesting Level"
line.long 0x0C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG3,"
bitfld.long 0x0C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x0C 0.--8. 1. "NEST_HINT_3,Host Int 3 Nesting Level"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG4,"
bitfld.long 0x10 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x10 0.--8. 1. "NEST_HINT_4,Host Int 4 Nesting Level"
line.long 0x14 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG5,"
bitfld.long 0x14 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x14 0.--8. 1. "NEST_HINT_5,Host Int 5 Nesting Level"
line.long 0x18 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG6,"
bitfld.long 0x18 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x18 0.--8. 1. "NEST_HINT_6,Host Int 6 Nesting Level"
line.long 0x1C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG7,"
bitfld.long 0x1C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x1C 0.--8. 1. "NEST_HINT_7,Host Int 7 Nesting Level"
line.long 0x20 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG8,"
bitfld.long 0x20 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x20 0.--8. 1. "NEST_HINT_8,Host Int 8 Nesting Level"
line.long 0x24 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG9,"
bitfld.long 0x24 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x24 0.--8. 1. "NEST_HINT_9,Host Int 9 Nesting Level"
group.long 0x1500++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_HINT_REG0,"
bitfld.long 0x00 9. "ENABLE_HINT_9,Enable for Host Int 9" "0,1"
bitfld.long 0x00 8. "ENABLE_HINT_8,Enable for Host Int 8" "0,1"
bitfld.long 0x00 7. "ENABLE_HINT_7,Enable for Host Int 7" "0,1"
newline
bitfld.long 0x00 6. "ENABLE_HINT_6,Enable for Host Int 6" "0,1"
bitfld.long 0x00 5. "ENABLE_HINT_5,Enable for Host Int 5" "0,1"
bitfld.long 0x00 4. "ENABLE_HINT_4,Enable for Host Int 4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_HINT_3,Enable for Host Int 3" "0,1"
bitfld.long 0x00 2. "ENABLE_HINT_2,Enable for Host Int 2" "0,1"
bitfld.long 0x00 1. "ENABLE_HINT_1,Enable for Host Int 1" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_HINT_0,Enable for Host Int 0" "0,1"
tree.end
tree "ICSSM0_PR1_ICSS_UART_UART_SLV"
base ad:0x30068000
group.long 0x00++0x2B
line.long 0x00 "PR1_ICSS_UART__UART_SLV__REGS_RBR_TBR,RBR_TBR Registers"
hexmask.long.word 0x00 8.--17. 1. "TBR_DATA,Transmit Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. "RBR_DATA,Receive Buffer Register"
line.long 0x04 "PR1_ICSS_UART__UART_SLV__REGS_INT_EN,UART Interrupt Enable Register"
bitfld.long 0x04 3. "EDSSI,Enable for Modem Status Interrupt" "0,1"
bitfld.long 0x04 2. "ELSI,Enable for Receiver Line Status Interrupt" "0,1"
bitfld.long 0x04 1. "ETBEI,Enable for Transmitter Holding Register Empty Interrupt" "0,1"
bitfld.long 0x04 0. "ERBI,Enable for Receiver Data Available Interrupt" "0,1"
line.long 0x08 "PR1_ICSS_UART__UART_SLV__REGS_INT_FIFO,Interrupt Identification Register / FIFO Control Register"
bitfld.long 0x08 14.--15. "FCR_RXFIFTL,Receiver Trigger Level" "0,1,2,3"
bitfld.long 0x08 11. "FCR_DMAMODE1,DMA Mode Select" "0,1"
bitfld.long 0x08 10. "FCR_TXCLR,Transmitter FIFO Reset" "0,1"
bitfld.long 0x08 9. "FCR_RXCLR,Receiver FIFO Reset" "0,1"
bitfld.long 0x08 8. "FCR_FIFOEN,FIFO Enable Register" "0,1"
rbitfld.long 0x08 6.--7. "IIR_FIFOEN,FIFOs enabled" "0,1,2,3"
newline
rbitfld.long 0x08 1.--3. "IIR_INTID,Interrupt Type" "0,1,2,3,4,5,6,7"
rbitfld.long 0x08 0. "IIR_IPEND,Receiver Data Available Interrupt Pending" "0,1"
line.long 0x0C "PR1_ICSS_UART__UART_SLV__REGS_LCTR,Line Control Register"
bitfld.long 0x0C 7. "DLAB,Divisor Latch Access Bit" "0,1"
bitfld.long 0x0C 6. "BC,Break Control" "0,1"
bitfld.long 0x0C 5. "SP,Stick Parity" "0,1"
bitfld.long 0x0C 4. "EPS,Even Parity Select" "0,1"
bitfld.long 0x0C 3. "PEN,Parity Enable" "0,1"
bitfld.long 0x0C 2. "STB,Number of Stop Bits" "0,1"
newline
bitfld.long 0x0C 1. "WLS1,Word Length Select Bit 1" "0,1"
bitfld.long 0x0C 0. "WLS0,Word Length Select Bit 0" "0,1"
line.long 0x10 "PR1_ICSS_UART__UART_SLV__REGS_MCTR,Modem Control Register"
bitfld.long 0x10 5. "AFE,Autoflow Control Enable" "0,1"
bitfld.long 0x10 4. "LOOP,LOOP Bit" "0,1"
bitfld.long 0x10 3. "OUT2,Out2 Bit" "0,1"
bitfld.long 0x10 2. "OUT1,Out1 Bit" "0,1"
bitfld.long 0x10 1. "RTS,Ready to Send" "0,1"
bitfld.long 0x10 0. "DTR,Data Terminal Ready" "0,1"
line.long 0x14 "PR1_ICSS_UART__UART_SLV__REGS_LSR1,Line Status Register1"
bitfld.long 0x14 7. "RXFIFOE,Receiver FIFO Error" "0,1"
bitfld.long 0x14 6. "TEMT,Transmitter Empty" "0,1"
bitfld.long 0x14 5. "THRE,Transmitter Holding Register" "0,1"
bitfld.long 0x14 4. "BI,Break Interrupt" "0,1"
bitfld.long 0x14 3. "FE,Framing Error" "0,1"
bitfld.long 0x14 2. "PE,Parity Error" "0,1"
newline
bitfld.long 0x14 1. "OE,Overrun Error" "0,1"
bitfld.long 0x14 0. "DR,Data Ready" "0,1"
line.long 0x18 "PR1_ICSS_UART__UART_SLV__REGS_MSR,Modem Status Register"
bitfld.long 0x18 7. "CD,Carrier Detect" "0,1"
bitfld.long 0x18 6. "RI,Ring Indicator" "0,1"
bitfld.long 0x18 5. "DSR,Data Set Ready" "0,1"
bitfld.long 0x18 4. "CTS,Clear To Send" "0,1"
bitfld.long 0x18 3. "DCD,Delta Carrier Detect" "0,1"
bitfld.long 0x18 2. "TERI,Trailing Edge Ring Indicator" "0,1"
newline
bitfld.long 0x18 1. "DDSR,Delta Set Ready" "0,1"
bitfld.long 0x18 0. "DCTS,Delta Clear To Send" "0,1"
line.long 0x1C "PR1_ICSS_UART__UART_SLV__REGS_SCRATCH,UART Scratch Register"
hexmask.long.byte 0x1C 0.--7. 1. "DATA,Scratch Register Bits"
line.long 0x20 "PR1_ICSS_UART__UART_SLV__REGS_DIVLSB,UART Divisor Register"
hexmask.long.byte 0x20 0.--7. 1. "DLL,Divisor Latch [LSB]"
line.long 0x24 "PR1_ICSS_UART__UART_SLV__REGS_DIVMSB,UART Divisor Register"
hexmask.long.byte 0x24 0.--7. 1. "DLH,Divisor Latch [MSB]"
line.long 0x28 "PR1_ICSS_UART__UART_SLV__REGS_PID,Peripheral ID Register"
group.long 0x30++0x07
line.long 0x00 "PR1_ICSS_UART__UART_SLV__REGS_PWR,UART PowerManagement and Emulation Register"
bitfld.long 0x00 15. "URST,UART Reset Bit" "0,1"
bitfld.long 0x00 14. "UTRST,UART Transmitter Reset Bit" "0,1"
bitfld.long 0x00 13. "URRST,UART Receiver Reset Bit" "0,1"
rbitfld.long 0x00 1. "RES,Free Bit" "0,1"
bitfld.long 0x00 0. "FREE,Free Bit" "0,1"
line.long 0x04 "PR1_ICSS_UART__UART_SLV__REGS_MODE,UART Mode Definition Register"
bitfld.long 0x04 0. "OSM_SEL,Oversampling Mode Select" "0,1"
tree.end
tree "ICSSM0_PR1_MDIO_V1P7_MDIO"
base ad:0x30072400
rgroup.long 0x00++0x47
line.long 0x00 "PR1_MDIO_V1P7__MDIO__REGS_MDIO_VERSION_REG,version_reg"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID"
hexmask.long.byte 0x00 8.--15. 1. "REVMAJ,Major revision value"
hexmask.long.byte 0x00 0.--7. 1. "REVMINOR,Minor revision value"
line.long 0x04 "PR1_MDIO_V1P7__MDIO__REGS_CONTROL_REG,control_reg"
rbitfld.long 0x04 31. "IDLE,MDIO state machine idle" "0,1"
bitfld.long 0x04 30. "ENABLE,Enable control" "0,1"
rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "0,1"
bitfld.long 0x04 19. "FAULT,Fault indicator" "0,1"
bitfld.long 0x04 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
newline
bitfld.long 0x04 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock divider"
line.long 0x08 "PR1_MDIO_V1P7__MDIO__REGS_ALIVE_REG,alive_reg"
line.long 0x0C "PR1_MDIO_V1P7__MDIO__REGS_LINK_REG,link_reg"
line.long 0x10 "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_RAW_REG,link_int_raw_reg"
bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
line.long 0x14 "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_MASKED_REG,link_int_masked_reg"
bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
line.long 0x18 "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_MASK_SET_REG,link_int_mask_set_reg"
bitfld.long 0x18 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1"
line.long 0x1C "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_MASK_CLEAR_REG,link_int_mask_clear_reg"
bitfld.long 0x1C 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1"
line.long 0x20 "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_RAW_REG,user_int_raw_reg"
bitfld.long 0x20 0.--1. "USERINTRAW,User interrupt raw" "0,1,2,3"
line.long 0x24 "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_MASKED_REG,user_int_masked_reg"
bitfld.long 0x24 0.--1. "USERINTMASKED,User interrupt masked" "0,1,2,3"
line.long 0x28 "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_MASK_SET_REG,user_int_mask_set_reg"
bitfld.long 0x28 0.--1. "USERINTMASKSET,MDIO user interrupt mask set" "0,1,2,3"
line.long 0x2C "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_MASK_CLEAR_REG,user_int_mask_clear_reg"
bitfld.long 0x2C 0.--1. "USERINTMASKCLR,MDIO user interrupt mask clear" "0,1,2,3"
line.long 0x30 "PR1_MDIO_V1P7__MDIO__REGS_MANUAL_IF_REG,manual_if_reg"
bitfld.long 0x30 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1"
bitfld.long 0x30 1. "MDIO_OE,MDIO Output Enable" "0,1"
bitfld.long 0x30 0. "MDIO_PIN,MDIO Pin" "0,1"
line.long 0x34 "PR1_MDIO_V1P7__MDIO__REGS_POLL_REG,poll_reg"
bitfld.long 0x34 31. "MANUALMODE,MDIO Manual Mode" "0,1"
bitfld.long 0x34 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1"
hexmask.long.byte 0x34 0.--7. 1. "IPG,MDIO IPG"
line.long 0x38 "PR1_MDIO_V1P7__MDIO__REGS_POLL_EN_REG,poll_en_reg"
line.long 0x3C "PR1_MDIO_V1P7__MDIO__REGS_CLAUS45_REG,"
line.long 0x40 "PR1_MDIO_V1P7__MDIO__REGS_USER_ADDR0_REG,MDIO USER Address 0"
hexmask.long.word 0x40 0.--15. 1. "USER_ADDR0,MDIO USER Address 0"
line.long 0x44 "PR1_MDIO_V1P7__MDIO__REGS_USER_ADDR1_REG,MDIO USER Address 1"
hexmask.long.word 0x44 0.--15. 1. "USER_ADDR1,MDIO USER Address 1"
group.long 0x80++0x07
line.long 0x00 "PR1_MDIO_V1P7__MDIO__REGS_USER_ACCESS_REG,user_access_reg"
bitfld.long 0x00 31. "GO,Go" "0,1"
bitfld.long 0x00 30. "WRITE," "0,1"
bitfld.long 0x00 29. "ACK,Acknowledge" "0,1"
newline
bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "DATA,User data"
line.long 0x04 "PR1_MDIO_V1P7__MDIO__REGS_USER_PHY_SEL_REG,user_phy_sel_reg"
bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1"
bitfld.long 0x04 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
bitfld.long 0x04 0.--4. "PHYADR_MON,PHY address whose link status is monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "ICSSM0_PR1_MII_RT_PR1_MII_RT_CFG"
base ad:0x30072000
group.long 0x00++0x07
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rxcfg0,MIIRXCFG0Register"
bitfld.long 0x00 9. "RX_EOF_SCLR_DIS0," "0,1"
bitfld.long 0x00 8. "RX_ERR_RAW0," "0,1"
bitfld.long 0x00 7. "RX_SFD_RAW0," "0,1"
bitfld.long 0x00 6. "RX_AUTO_FWD_PRE0," "0,1"
newline
bitfld.long 0x00 5. "RX_BYTE_SWAP0," "0,1"
bitfld.long 0x00 4. "RX_L2_EN0," "0,1"
bitfld.long 0x00 3. "RX_MUX_SEL0," "0,1"
bitfld.long 0x00 2. "RX_CUT_PREAMBLE0," "0,1"
newline
bitfld.long 0x00 1. "RX_DATA_RDY_MODE_DIS0," "0,1"
bitfld.long 0x00 0. "RX_ENABLE0," "0,1"
line.long 0x04 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rxcfg1,MIIRXCFG1Register"
bitfld.long 0x04 9. "RX_EOF_SCLR_DIS1," "0,1"
bitfld.long 0x04 8. "RX_ERR_RAW1," "0,1"
bitfld.long 0x04 7. "RX_SFD_RAW1," "0,1"
bitfld.long 0x04 6. "RX_AUTO_FWD_PRE1," "0,1"
newline
bitfld.long 0x04 5. "RX_BYTE_SWAP1," "0,1"
bitfld.long 0x04 4. "RX_L2_EN1," "0,1"
bitfld.long 0x04 3. "RX_MUX_SEL1," "0,1"
bitfld.long 0x04 2. "RX_CUT_PREAMBLE1," "0,1"
newline
bitfld.long 0x04 1. "RX_DATA_RDY_MODE_DIS1," "0,1"
bitfld.long 0x04 0. "RX_ENABLE1," "0,1"
group.long 0x10++0x07
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_txcfg0,MIITXCFG0Register"
bitfld.long 0x00 28.--30. "TX_CLK_DELAY0," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--25. 1. "TX_START_DELAY0,"
bitfld.long 0x00 12. "TX_IPG_WIRE_CLK_EN0," "0,1"
bitfld.long 0x00 11. "TX_32_MODE_EN0," "0,1"
newline
bitfld.long 0x00 10. "PRE_TX_AUTO_ESC_ERR0," "0,1"
bitfld.long 0x00 9. "PRE_TX_AUTO_SEQUENCE0," "0,1"
bitfld.long 0x00 8. "TX_MUX_SEL0," "0,1"
bitfld.long 0x00 3. "TX_BYTE_SWAP0," "0,1"
newline
bitfld.long 0x00 2. "TX_EN_MODE0," "0,1"
bitfld.long 0x00 1. "TX_AUTO_PREAMBLE0," "0,1"
bitfld.long 0x00 0. "TX_ENABLE0," "0,1"
line.long 0x04 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_txcfg1,MIITXCFG1Register"
bitfld.long 0x04 28.--30. "TX_CLK_DELAY1," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 16.--25. 1. "TX_START_DELAY1,"
bitfld.long 0x04 12. "TX_IPG_WIRE_CLK_EN1," "0,1"
bitfld.long 0x04 11. "TX_32_MODE_EN1," "0,1"
newline
bitfld.long 0x04 10. "PRE_TX_AUTO_ESC_ERR1," "0,1"
bitfld.long 0x04 9. "PRE_TX_AUTO_SEQUENCE1," "0,1"
bitfld.long 0x04 8. "TX_MUX_SEL1," "0,1"
bitfld.long 0x04 3. "TX_BYTE_SWAP1," "0,1"
newline
bitfld.long 0x04 2. "TX_EN_MODE1," "0,1"
bitfld.long 0x04 1. "TX_AUTO_PREAMBLE1," "0,1"
bitfld.long 0x04 0. "TX_ENABLE1," "0,1"
rgroup.long 0x20++0x07
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_crc0,MIITXCRC0Register"
line.long 0x04 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_crc1,MIITXCRC1Register"
group.long 0x30++0x27
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_ipg0,MIITXIPG0Register"
hexmask.long.word 0x00 0.--15. 1. "TX_IPG0,Transmit IPG"
line.long 0x04 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_ipg1,MIITXIPG1Register"
hexmask.long.word 0x04 0.--15. 1. "TX_IPG1,Transmit IPG"
line.long 0x08 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_prs0,MIIPortStatus0Register"
bitfld.long 0x08 1. "SYNC_PORT0_CRS,sync_port0_crs" "0,1"
bitfld.long 0x08 0. "SYNC_PORT0_COL,sync_port0_col" "0,1"
line.long 0x0C "PR1_MII_RT__PR1_MII_RT_CFG__REGS_prs1,MIIPortStatus1Register"
bitfld.long 0x0C 1. "SYNC_PORT1_CRS,sync_port1_crs" "0,1"
bitfld.long 0x0C 0. "SYNC_PORT1_COL,sync_port1_col" "0,1"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_frms0,MIIRXFRMS0Register"
hexmask.long.word 0x10 16.--31. 1. "RX_MAX_FRM0,rx_max_frm0"
hexmask.long.word 0x10 0.--15. 1. "RX_MIN_FRM0,rx_min_frm0"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_frms1,MIIRXFRMS1Register"
hexmask.long.word 0x14 16.--31. 1. "RX_MAX_FRM1,rx_max_frm1"
hexmask.long.word 0x14 0.--15. 1. "RX_MIN_FRM1,rx_min_frm1"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_pcnt0,MIIRXPCNT0Register"
bitfld.long 0x18 4.--8. "RX_MAX_PCNT0,rx_max_pcnt0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 0.--3. "RX_MIN_PCNT0,rx_min_pcnt0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_pcnt1,MIIRXPCNT1Register"
bitfld.long 0x1C 4.--8. "RX_MAX_PCNT1,rx_max_pcnt1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 0.--3. "RX_MIN_PCNT1,rx_min_pcnt1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_err0,MIIRXERR0Register"
bitfld.long 0x20 3. "RX_MAX_FRM_ERR0,rx_max_frm_err0" "0,1"
bitfld.long 0x20 2. "RX_MIN_FRM_ERR0,rx_min_frm_err0" "0,1"
bitfld.long 0x20 1. "RX_MAX_PCNT_ERR0,rx_max_pcnt_err0" "0,1"
bitfld.long 0x20 0. "RX_MIN_PCNT_ERR0,rx_min_pcnt_err0" "0,1"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_err1,MIIRXERR1Register"
bitfld.long 0x24 3. "RX_MAX_FRM_ERR1,rx_max_frm_err1" "0,1"
bitfld.long 0x24 2. "RX_MIN_FRM_ERR1,rx_min_frm_err1" "0,1"
bitfld.long 0x24 1. "RX_MAX_PCNT_ERR1,rx_max_pcnt_err1" "0,1"
bitfld.long 0x24 0. "RX_MIN_PCNT_ERR1,rx_min_pcnt_err1" "0,1"
rgroup.long 0x60++0x0F
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_fifo_level0,MIIRXFIFOLEVEL0Register"
hexmask.long.byte 0x00 0.--7. 1. "RX_FIFO_LEVEL0,rx_fifo_level0"
line.long 0x04 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_fifo_level1,MIIRXFIFOLEVEL1Register"
hexmask.long.byte 0x04 0.--7. 1. "RX_FIFO_LEVEL1,rx_fifo_level1"
line.long 0x08 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_fifo_level0,MIIRXFIFOLEVEL0Register"
hexmask.long.byte 0x08 0.--7. 1. "TX_FIFO_LEVEL0,tx_fifo_level0"
line.long 0x0C "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_fifo_level1,MIIRXFIFOLEVEL1Register"
hexmask.long.byte 0x0C 0.--7. 1. "TX_FIFO_LEVEL1,tx_fifo_level1"
tree.end
tree "ICSSM0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G"
base ad:0x30073000
group.long 0x00++0x13
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_icss_g_cfg,ICSS_G Ethernet Cfg"
bitfld.long 0x00 10. "RX_SFD_TX_SOF_EN,Enable the remaping of tx_sof to rx_sfd if auto fwd is enable" "0,1"
bitfld.long 0x00 5.--6. "MII1_MODE,MII1 MODE" "MII,RGMII,SGMII,?..."
bitfld.long 0x00 3.--4. "MII0_MODE,MII0 MODE" "MII,RGMII,SGMII,?..."
newline
bitfld.long 0x00 2. "RX_L2_G_EN,Enable the RX L2 G features of filter frags of size TBD and backpressure RX L2" "Disabled,Enabled"
bitfld.long 0x00 1. "TX_L2_EN,Enable the TX L2 Fifo" "Disabled,Enabled"
bitfld.long 0x00 0. "TX_L1_EN,Enable the TX L1 Fifo" "Disabled,Enabled"
line.long 0x04 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_preempt_cfg,"
hexmask.long.byte 0x04 24.--31. 1. "SMD_R,Response frame TAG"
hexmask.long.byte 0x04 16.--23. 1. "SMD_V,Verification frame TAG"
hexmask.long.byte 0x04 8.--15. 1. "EXP_SMD,None preemptable frame start or express frame"
line.long 0x08 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_smdt1s_cfg,"
hexmask.long.byte 0x08 24.--31. 1. "SMDT1S_3,SMDT1S3 pattern"
hexmask.long.byte 0x08 16.--23. 1. "SMDT1S_2,SMDT1S2 pattern"
hexmask.long.byte 0x08 8.--15. 1. "SMDT1S_1,SMDT1S1 pattern"
newline
hexmask.long.byte 0x08 0.--7. 1. "SMDT1S_0,SMDT1S0 pattern"
line.long 0x0C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_smdt1c_cfg,"
hexmask.long.byte 0x0C 24.--31. 1. "SMDT1C_3,SMDT1C3 pattern"
hexmask.long.byte 0x0C 16.--23. 1. "SMDT1C_2,SMDT1C2 pattern"
hexmask.long.byte 0x0C 8.--15. 1. "SMDT1C_1,SMDT1C1 pattern"
newline
hexmask.long.byte 0x0C 0.--7. 1. "SMDT1C_0,SMDT1C0 pattern"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_pool_ptr_cfg,"
hexmask.long.word 0x10 0.--15. 1. "MAX_PKT_SIZE,Max Pkt Size used in pool ptr logic for wrap around"
hgroup.long 0x14++0x03
hide.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_early_eof,"
group.long 0x18++0x03
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_frag_cnt_cfg,"
hexmask.long.byte 0x00 24.--31. 1. "FRAG_CNT_3,FRAG Cnt3 pattern"
hexmask.long.byte 0x00 16.--23. 1. "FRAG_CNT_2,FRAG Cnt2 pattern"
hexmask.long.byte 0x00 8.--15. 1. "FRAG_CNT_1,FRAG Cnt1 pattern"
newline
hexmask.long.byte 0x00 0.--7. 1. "FRAG_CNT_0,FRAG Cnt0 pattern"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xD00)++0x03
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue$1,"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_H_PTR0,Queue 0"
repeat.end
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xD40)++0x03
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue$1,"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_H_PTR16,Queue 16"
repeat.end
rgroup.long 0xE00++0x3F
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek0,"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_H_PEEK_PTR0,Queue 0 Peek portal"
line.long 0x04 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek1,"
hexmask.long.word 0x04 0.--15. 1. "QUEUE_H_PEEK_PTR1,Queue 1 Peek portal"
line.long 0x08 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek2,"
hexmask.long.word 0x08 0.--15. 1. "QUEUE_H_PEEK_PTR2,Queue 2 Peek portal"
line.long 0x0C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek3,"
hexmask.long.word 0x0C 0.--15. 1. "QUEUE_H_PEEK_PTR3,Queue 3 Peek portal"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek4,"
hexmask.long.word 0x10 0.--15. 1. "QUEUE_H_PEEK_PTR4,Queue 4 Peek portal"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek5,"
hexmask.long.word 0x14 0.--15. 1. "QUEUE_H_PEEK_PTR5,Queue 5 Peek portal"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek6,"
hexmask.long.word 0x18 0.--15. 1. "QUEUE_H_PEEK_PTR6,Queue 6 Peek portal"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek7,"
hexmask.long.word 0x1C 0.--15. 1. "QUEUE_H_PEEK_PTR7,Queue 7 Peek portal"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek8,"
hexmask.long.word 0x20 0.--15. 1. "QUEUE_H_PEEK_PTR8,Queue 8 Peek portal"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek9,"
hexmask.long.word 0x24 0.--15. 1. "QUEUE_H_PEEK_PTR9,Queue 9 Peek portal"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek10,"
hexmask.long.word 0x28 0.--15. 1. "QUEUE_H_PEEK_PTR10,Queue 10 Peek portal"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek11,"
hexmask.long.word 0x2C 0.--15. 1. "QUEUE_H_PEEK_PTR11,Queue 11 Peek portal"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek12,"
hexmask.long.word 0x30 0.--15. 1. "QUEUE_H_PEEK_PTR12,Queue 12 Peek portal"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek13,"
hexmask.long.word 0x34 0.--15. 1. "QUEUE_H_PEEK_PTR13,Queue 13 Peek portal"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek14,"
hexmask.long.word 0x38 0.--15. 1. "QUEUE_H_PEEK_PTR14,Queue 14 Peek portal"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek15,"
hexmask.long.word 0x3C 0.--15. 1. "QUEUE_H_PEEK_PTR15,Queue 15 Peek portal"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0xE40)++0x03
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt$1,"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_CNT_ENTRIES_0,Queue Entry Count0"
repeat.end
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0xE80)++0x03
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt$1,"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_CNT_ENTRIES_16,Queue Entry Count16"
repeat.end
group.long 0xF40++0x03
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_reset,"
bitfld.long 0x00 0.--5. "RESET_QUEUE_ID,Reset Queue ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "ICSSM0_PR1_PDSP0_IRAM"
base ad:0x30062000
group.long 0x00++0x13
line.long 0x00 "PR1_PDSP0__IRAM__REGS_CONTROL,"
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program counter reset value"
newline
bitfld.long 0x00 15. "PDSP_STATE,PDSP run state" "PDSP is halted,PDSP is running"
newline
rbitfld.long 0x00 14. "BIG_ENDIAN,Big-endian input state" "0,1"
newline
bitfld.long 0x00 8. "SINGLE_STEP,Single step enable" "PDSP will free run when enabled,PDSP will execute a single instruction and then.."
newline
bitfld.long 0x00 4. "RESTART,Causes PDSP to stop current operation gracefully and return to the PC reset value" "0,1"
newline
bitfld.long 0x00 3. "COUNTER_ENABLE,PDSP cycle counter enable" "Counters not enabled,Counters enabled"
newline
bitfld.long 0x00 2. "PDSP_SLEEPING,PDSP sleep indicator" "PDSP is not asleep,PDSP us asleep"
newline
bitfld.long 0x00 1. "PDSP_ENABLE,PDSP enable" "PDSP is disabled,PDSP is enabled"
newline
rbitfld.long 0x00 0. "SOFT_RST_N,Soft reset" "0,1"
line.long 0x04 "PR1_PDSP0__IRAM__REGS_STATUS,"
hexmask.long.word 0x04 0.--15. 1. "PCOUNTER,Current PDSP program counter"
line.long 0x08 "PR1_PDSP0__IRAM__REGS_WAKEUP_ENABLE,"
line.long 0x0C "PR1_PDSP0__IRAM__REGS_CYCLE_COUNT,"
line.long 0x10 "PR1_PDSP0__IRAM__REGS_STALL_COUNT,"
group.long 0x20++0x0F
line.long 0x00 "PR1_PDSP0__IRAM__REGS_CONSTANT_TABLE_BLOCK_INDEX_0,"
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PDSP constant entry 25 block index"
newline
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PDSP constant entry 24 block index"
line.long 0x04 "PR1_PDSP0__IRAM__REGS_CONSTANT_TABLE_BLOCK_INDEX_1,"
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PDSP constant entry 27 block index"
newline
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PDSP constant entry 26 block index"
line.long 0x08 "PR1_PDSP0__IRAM__REGS_CONSTANT_TABLE_PROG_PTR_0,"
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PDSP constant entry 29 pointer"
newline
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PDSP constant entry 28 pointer"
line.long 0x0C "PR1_PDSP0__IRAM__REGS_CONSTANT_TABLE_PROG_PTR_1,"
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PDSP constant entry 31 pointer"
newline
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PDSP constant entry 30 pointer"
tree.end
tree "ICSSM0_PR1_PDSP0_IRAM_DEBUG"
base ad:0x30062400
group.long 0x00++0x03
line.long 0x00 "PR1_PDSP0__IRAM__DEBUG_IGP,PDSP Internal General Purpose Register"
rgroup.long 0x80++0x03
line.long 0x00 "PR1_PDSP0__IRAM__DEBUG_ICTE,PDSP Internal Contants Table Entry Register"
tree.end
tree "ICSSM0_PR1_PDSP0_IRAM_RAM"
base ad:0x30074000
group.long 0x00++0x03
line.long 0x00 "PR1_PDSP0__IRAM__RAM_IRAM,PDSP instruction RAM"
tree.end
tree "ICSSM0_PR1_PDSP1_IRAM"
base ad:0x30064000
group.long 0x00++0x13
line.long 0x00 "PR1_PDSP1__IRAM__REGS_CONTROL,"
hexmask.long.word 0x00 16.--31. 1. "PCOUNTER_RST_VAL,Program counter reset value"
newline
bitfld.long 0x00 15. "PDSP_STATE,PDSP run state" "PDSP is halted,PDSP is running"
newline
rbitfld.long 0x00 14. "BIG_ENDIAN,Big-endian input state" "0,1"
newline
bitfld.long 0x00 8. "SINGLE_STEP,Single step enable" "PDSP will free run when enabled,PDSP will execute a single instruction and then.."
newline
bitfld.long 0x00 4. "RESTART,Causes PDSP to stop current operation gracefully and return to the PC reset value" "0,1"
newline
bitfld.long 0x00 3. "COUNTER_ENABLE,PDSP cycle counter enable" "Counters not enabled,Counters enabled"
newline
bitfld.long 0x00 2. "PDSP_SLEEPING,PDSP sleep indicator" "PDSP is not asleep,PDSP us asleep"
newline
bitfld.long 0x00 1. "PDSP_ENABLE,PDSP enable" "PDSP is disabled,PDSP is enabled"
newline
rbitfld.long 0x00 0. "SOFT_RST_N,Soft reset" "0,1"
line.long 0x04 "PR1_PDSP1__IRAM__REGS_STATUS,"
hexmask.long.word 0x04 0.--15. 1. "PCOUNTER,Current PDSP program counter"
line.long 0x08 "PR1_PDSP1__IRAM__REGS_WAKEUP_ENABLE,"
line.long 0x0C "PR1_PDSP1__IRAM__REGS_CYCLE_COUNT,"
line.long 0x10 "PR1_PDSP1__IRAM__REGS_STALL_COUNT,"
group.long 0x20++0x0F
line.long 0x00 "PR1_PDSP1__IRAM__REGS_CONSTANT_TABLE_BLOCK_INDEX_0,"
hexmask.long.byte 0x00 16.--23. 1. "C25_BLK_INDEX,PDSP constant entry 25 block index"
newline
hexmask.long.byte 0x00 0.--7. 1. "C24_BLK_INDEX,PDSP constant entry 24 block index"
line.long 0x04 "PR1_PDSP1__IRAM__REGS_CONSTANT_TABLE_BLOCK_INDEX_1,"
hexmask.long.byte 0x04 16.--23. 1. "C27_BLK_INDEX,PDSP constant entry 27 block index"
newline
hexmask.long.byte 0x04 0.--7. 1. "C26_BLK_INDEX,PDSP constant entry 26 block index"
line.long 0x08 "PR1_PDSP1__IRAM__REGS_CONSTANT_TABLE_PROG_PTR_0,"
hexmask.long.word 0x08 16.--31. 1. "C29_POINTER,PDSP constant entry 29 pointer"
newline
hexmask.long.word 0x08 0.--15. 1. "C28_POINTER,PDSP constant entry 28 pointer"
line.long 0x0C "PR1_PDSP1__IRAM__REGS_CONSTANT_TABLE_PROG_PTR_1,"
hexmask.long.word 0x0C 16.--31. 1. "C31_POINTER,PDSP constant entry 31 pointer"
newline
hexmask.long.word 0x0C 0.--15. 1. "C30_POINTER,PDSP constant entry 30 pointer"
tree.end
tree "ICSSM0_PR1_PDSP1_IRAM_DEBUG"
base ad:0x30064400
group.long 0x00++0x03
line.long 0x00 "PR1_PDSP1__IRAM__DEBUG_IGP,PDSP Internal General Purpose Register"
rgroup.long 0x80++0x03
line.long 0x00 "PR1_PDSP1__IRAM__DEBUG_ICTE,PDSP Internal Contants Table Entry Register"
tree.end
tree "ICSSM0_PR1_PDSP1_IRAM_RAM"
base ad:0x30078000
group.long 0x00++0x03
line.long 0x00 "PR1_PDSP1__IRAM__RAM_IRAM,PDSP instruction RAM"
tree.end
tree "ICSSM0_PR1_PROT_SLV"
base ad:0x30064C00
group.long 0x00++0x07
line.long 0x00 "PR1_PROTECT__SLV__REGS_unlock_key,"
line.long 0x04 "PR1_PROTECT__SLV__REGS_cfg,Config"
bitfld.long 0x04 6. "PRU1_DMEM1_LOCK_EN,Write Protect DMEM1" "disable,enable When enabled.."
bitfld.long 0x04 5. "PRU0_DMEM0_LOCK_EN,Write Protect DMEM0" "disable,enable When enabled.."
bitfld.long 0x04 4. "ICSS_CFG_WP_EN,Write Protect ICSS_CFG" "disable,enable"
newline
bitfld.long 0x04 3. "RTU1_PRU_WP_EN,Write Protect RTU1_PRU access Debug IMEM" "disable,enable"
bitfld.long 0x04 2. "RTU0_PRU_WP_EN,Write Protect RTU0_PRU access Debug IMEM" "disable,enable"
bitfld.long 0x04 1. "PRU1_WP_EN,Write Protect PRU1 access Debug IMEM" "disable,enable"
newline
bitfld.long 0x04 0. "PRU0_WP_EN,Write Protect PRU0 access Debug IMEM" "disable,enable"
tree.end
tree "ICSSM0_RAM_SLV_RAM"
base ad:0x30050000
group.long 0x00++0x03
line.long 0x00 "RAM__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "ICSSM0_RAT_SLICE0_CFG"
base ad:0x30048000
rgroup.long 0x00++0x07
line.long 0x00 "PR1_RAT_SLICE0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PR1_RAT_SLICE0__CFG__MMRS_config,The Config Register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x04 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x04 0.--7. 1. "REGIONS,Number of regions"
group.long 0x804++0x03
line.long 0x00 "PR1_RAT_SLICE0__CFG__MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x820++0x1B
line.long 0x00 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 12 bits"
line.long 0x14 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x840++0x13
line.long 0x00 "PR1_RAT_SLICE0__CFG__MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "PR1_RAT_SLICE0__CFG__MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "PR1_RAT_SLICE0__CFG__MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "PR1_RAT_SLICE0__CFG__MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "PR1_RAT_SLICE0__CFG__MMRS_eoi_reg,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
group.long 0x20++0x0F
line.long 0x00 "PR1_RAT_SLICE0__CFG__MMRS_ctrl,The Control for Region a"
bitfld.long 0x00 31. "EN,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "SIZE,Size of the Region in Address Bits" "1 byte,2B,4B,8B etc,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,4GB,?..."
line.long 0x04 "PR1_RAT_SLICE0__CFG__MMRS_base,The Base Address for Region a"
line.long 0x08 "PR1_RAT_SLICE0__CFG__MMRS_trans_l,The Translated Lower Address Bits for Region a"
line.long 0x0C "PR1_RAT_SLICE0__CFG__MMRS_trans_u,The Translated Upper Address Bits for Region a"
bitfld.long 0x0C 0.--3. "UPPER,Translated Upper Address Bits for the Region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "ICSSM0_RAT_SLICE1_CFG"
base ad:0x30049000
rgroup.long 0x00++0x07
line.long 0x00 "PR1_RAT_SLICE1__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PR1_RAT_SLICE1__CFG__MMRS_config,The Config Register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x04 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x04 0.--7. 1. "REGIONS,Number of regions"
group.long 0x804++0x03
line.long 0x00 "PR1_RAT_SLICE1__CFG__MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x820++0x1B
line.long 0x00 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 12 bits"
line.long 0x14 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x840++0x13
line.long 0x00 "PR1_RAT_SLICE1__CFG__MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "PR1_RAT_SLICE1__CFG__MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "PR1_RAT_SLICE1__CFG__MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "PR1_RAT_SLICE1__CFG__MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "PR1_RAT_SLICE1__CFG__MMRS_eoi_reg,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
group.long 0x20++0x0F
line.long 0x00 "PR1_RAT_SLICE1__CFG__MMRS_ctrl,The Control for Region a"
bitfld.long 0x00 31. "EN,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "SIZE,Size of the Region in Address Bits" "1 byte,2B,4B,8B etc,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,4GB,?..."
line.long 0x04 "PR1_RAT_SLICE1__CFG__MMRS_base,The Base Address for Region a"
line.long 0x08 "PR1_RAT_SLICE1__CFG__MMRS_trans_l,The Translated Lower Address Bits for Region a"
line.long 0x0C "PR1_RAT_SLICE1__CFG__MMRS_trans_u,The Translated Upper Address Bits for Region a"
bitfld.long 0x0C 0.--3. "UPPER,Translated Upper Address Bits for the Region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "MAILBOX0_CLUSTER_0_REGS0"
base ad:0x29000000
rgroup.long 0x00++0x03
line.long 0x00 "REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU identifier" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module family"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_REV,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Special version number" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR_REV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system"
bitfld.long 0x00 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware" "0,1"
group.long 0x40++0x03
line.long 0x00 "REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox"
rgroup.long 0x80++0x03
line.long 0x00 "REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO"
bitfld.long 0x00 0. "FIFO_FULL,Full flag for Mailbox m" "0,1"
rgroup.long 0xC0++0x03
line.long 0x00 "REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]"
bitfld.long 0x00 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7"
group.long 0x140++0x03
line.long 0x00 "REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance"
bitfld.long 0x00 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1"
bitfld.long 0x00 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1"
bitfld.long 0x00 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1"
bitfld.long 0x00 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1"
group.long 0x100++0x0F
line.long 0x00 "REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user .Software may also write 1 to a given bit to set this bit to test interrupt.."
bitfld.long 0x00 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1"
bitfld.long 0x00 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1"
bitfld.long 0x00 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1"
bitfld.long 0x00 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1"
bitfld.long 0x00 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1"
newline
bitfld.long 0x00 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1"
bitfld.long 0x00 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1"
bitfld.long 0x00 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1"
bitfld.long 0x00 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1"
bitfld.long 0x00 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1"
newline
bitfld.long 0x00 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1"
bitfld.long 0x00 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1"
bitfld.long 0x00 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1"
bitfld.long 0x00 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1"
bitfld.long 0x00 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1"
newline
bitfld.long 0x00 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1"
bitfld.long 0x00 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1"
bitfld.long 0x00 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1"
bitfld.long 0x00 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1"
bitfld.long 0x00 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1"
newline
bitfld.long 0x00 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1"
bitfld.long 0x00 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1"
bitfld.long 0x00 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1"
bitfld.long 0x00 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1"
bitfld.long 0x00 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1"
newline
bitfld.long 0x00 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1"
bitfld.long 0x00 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1"
bitfld.long 0x00 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1"
bitfld.long 0x00 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1"
bitfld.long 0x00 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1"
newline
bitfld.long 0x00 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1"
bitfld.long 0x00 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1"
line.long 0x04 "REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information.Software may also write 1 to a.."
bitfld.long 0x04 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1"
line.long 0x08 "REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a].Read value is the current enable bits for each interrupt source.Write 1 to a bit enables an interrupt source"
bitfld.long 0x08 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt" "0,1"
line.long 0x0C "REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a].Read value is the current enable bits for each interrupt sourc.Write 1 to a bit disables an interrupt source"
bitfld.long 0x0C 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt" "0,1"
tree.end
tree "MAIN_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG"
base ad:0xA00000
rgroup.long 0x00++0x07
line.long 0x00 "INTR_ROUTER_CFG_PID,Identification register"
bitfld.long 0x00 30.--31. "SCHEME,scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,function"
bitfld.long 0x00 11.--15. "RTLVER,rtl version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom id" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINREV,minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register"
bitfld.long 0x04 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1"
hexmask.long.byte 0x04 0.--7. 1. "MUX_CNTL,Mux control for interrupt N"
tree.end
tree "MCAN0_CFG"
base ad:0x20701000
rgroup.long 0x00++0x07
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)"
bitfld.long 0x00 28.--31. "REL,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "STEP,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month"
hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321"
hgroup.long 0x08++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register"
group.long 0x0C++0x23
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable"
bitfld.long 0x00 23. "TDC,Transmitter Delay Compensation" "0,1"
bitfld.long 0x00 16.--20. "DBRP,Data Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "DTSEG1,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "DSJW,Data resynchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection"
rbitfld.long 0x04 7. "RX,Receive Pin" "0,1"
bitfld.long 0x04 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
bitfld.long 0x04 4. "LBCK,Loop Back Mode" "0,1"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM"
hexmask.long.byte 0x08 8.--15. 1. "WDV,Watchdog Value"
hexmask.long.byte 0x08 0.--7. 1. "WDC,Watchdog Counter Value"
line.long 0x0C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration"
bitfld.long 0x0C 15. "NISO,Non ISO Operation" "CAN FD frame format according to ISO 11898-1:2015,CAN FD frame format according to Bosch CAN FD.."
bitfld.long 0x0C 14. "TXP,Transmit Pause" "0,1"
bitfld.long 0x0C 13. "EFBI,Edge Filtering during Bus Integration" "0,1"
bitfld.long 0x0C 12. "PXHD,Protocol Exception Handling Disable" "0,1"
newline
bitfld.long 0x0C 9. "BRSE,Bit Rate Switch Enable" "0,1"
bitfld.long 0x0C 8. "FDOE,FD Operation Enable" "0,1"
bitfld.long 0x0C 7. "TEST,Test Mode enable" "0,1"
bitfld.long 0x0C 6. "DAR,Disable Automatic Retransmission" "0,1"
newline
bitfld.long 0x0C 5. "MON,Bus Monitoring Mode" "0,1"
bitfld.long 0x0C 4. "CSR,Clock Stop Request" "0,1"
rbitfld.long 0x0C 3. "CSA,Clock Stop Acknowledge" "0,1"
bitfld.long 0x0C 2. "ASM,Restricted Operation Mode" "0,1"
newline
bitfld.long 0x0C 1. "CCE,Configuration Change Enable" "0,1"
bitfld.long 0x0C 0. "INIT,Initialization" "0,1"
line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing"
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width"
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector"
bitfld.long 0x14 16.--19. "TCP,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3"
line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter"
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter"
line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode"
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period"
bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3"
bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1"
line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter"
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter"
repeat 14. (list 00. 11. 22. 33. 44. 55. 66. 77. 88. 99. 1010. 1111. 1212. 1313. )(list 0x00 0x04 0x08 0x0C 0x1C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x5C )
hgroup.long ($2+0x30)++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved$1,Reserved field"
repeat.end
rgroup.long 0x40++0x0B
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging"
hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging"
bitfld.long 0x00 15. "RP,Receive Error Passive" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter"
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value"
hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
bitfld.long 0x04 14. "PXE,Protocol Exception Event" "0,1"
bitfld.long 0x04 13. "RFDF,Received a CAN FD Message" "0,1"
bitfld.long 0x04 12. "RBRS,BRS flag of last received CAN FD Message" "0,1"
newline
bitfld.long 0x04 11. "RESI,ESI flag of last received CAN FD Message" "0,1"
bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "BO,Bus_Off status" "0,1"
bitfld.long 0x04 6. "EW,Warning Status" "0,1"
newline
bitfld.long 0x04 5. "EP,Error Passive" "0,1"
bitfld.long 0x04 3.--4. "ACT,Activity" "0,1,2,3"
bitfld.long 0x04 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length"
hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
group.long 0x50++0x0F
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags"
bitfld.long 0x00 29. "ARA,Access to Reserved Address" "0,1"
bitfld.long 0x00 28. "PED,Protocol Error in data Phase" "0,1"
bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "0,1"
newline
bitfld.long 0x00 25. "BO,Bus_Off Status" "0,1"
bitfld.long 0x00 24. "EW,Warning Status" "0,1"
bitfld.long 0x00 23. "EP,Error Passive" "0,1"
bitfld.long 0x00 22. "ELO,Error Logging Overflow" "0,1"
newline
bitfld.long 0x00 21. "BEU,Bit Error Uncorrected" "0,1"
bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
bitfld.long 0x00 18. "TOO,Timeout Occurred" "0,1"
bitfld.long 0x00 17. "MRAF,Message RAM Access Failure" "0,1"
newline
bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "0,1"
bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "0,1"
bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
newline
bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "0,1"
bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "0,1"
bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "0,1"
bitfld.long 0x00 9. "TC,Transmission Complete" "0,1"
newline
bitfld.long 0x00 8. "HPM,High Priority Message" "0,1"
bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "0,1"
bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
newline
bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "0,1"
bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
newline
bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "0,1"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable"
bitfld.long 0x04 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1"
bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1"
bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1"
bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "0,1"
newline
bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "0,1"
bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "0,1"
bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
newline
bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
newline
bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1"
bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
bitfld.long 0x04 8. "HPME,High Priority message Interrupt Enable" "0,1"
bitfld.long 0x04 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)"
bitfld.long 0x08 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1"
bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1"
bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1"
bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "0,1"
newline
bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "0,1"
bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
newline
bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
newline
bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1"
newline
bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x08 8. "HPML,High Priority message Interrupt Line" "0,1"
bitfld.long 0x08 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
line.long 0x0C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1"
bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "0,1"
bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "0,1"
group.long 0x80++0x0B
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames"
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
bitfld.long 0x00 1. "RRFS,reject Remote Frames Standard" "0,1"
bitfld.long 0x00 0. "RRFE,reject Remote Frames Extended" "0,1"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x04 16.--23. 1. "LSS,List Size Standard"
hexmask.long.word 0x04 2.--15. 1. "FLSSA,Filter List Standard Start Address"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x08 16.--22. 1. "LSE,List Size Extended"
hexmask.long.word 0x08 2.--15. 1. "FLESA,Filter List Extended Start Address"
group.long 0x90++0x07
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939"
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages"
bitfld.long 0x04 15. "FLST,Filter List" "0,1"
hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index"
bitfld.long 0x04 6.--7. "MSI,Message Storage Indicator" "0,1,2,3"
bitfld.long 0x04 0.--5. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
group.long ($2+0x98)++0x03
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT$1,NewDat flags of dedicated Rx buffers 0-31"
bitfld.long 0x00 31. "ND31,New Data" "0,1"
bitfld.long 0x00 30. "ND30,New Data" "0,1"
bitfld.long 0x00 29. "ND29,New Data" "0,1"
bitfld.long 0x00 28. "ND28,New Data" "0,1"
newline
bitfld.long 0x00 27. "ND27,New Data" "0,1"
bitfld.long 0x00 26. "ND26,New Data" "0,1"
bitfld.long 0x00 25. "ND25,New Data" "0,1"
bitfld.long 0x00 24. "ND24,New Data" "0,1"
newline
bitfld.long 0x00 23. "ND23,New Data" "0,1"
bitfld.long 0x00 22. "ND22,New Data" "0,1"
bitfld.long 0x00 21. "ND21,New Data" "0,1"
bitfld.long 0x00 20. "ND20,New Data" "0,1"
newline
bitfld.long 0x00 19. "ND19,New Data" "0,1"
bitfld.long 0x00 18. "ND18,New Data" "0,1"
bitfld.long 0x00 17. "ND17,New Data" "0,1"
bitfld.long 0x00 16. "ND16,New Data" "0,1"
newline
bitfld.long 0x00 15. "ND15,New Data" "0,1"
bitfld.long 0x00 14. "ND14,New Data" "0,1"
bitfld.long 0x00 13. "ND13,New Data" "0,1"
bitfld.long 0x00 12. "ND12,New Data" "0,1"
newline
bitfld.long 0x00 11. "ND11,New Data" "0,1"
bitfld.long 0x00 10. "ND10,New Data" "0,1"
bitfld.long 0x00 9. "ND9,New Data" "0,1"
bitfld.long 0x00 8. "ND8,New Data" "0,1"
newline
bitfld.long 0x00 7. "ND7,New Data" "0,1"
bitfld.long 0x00 6. "ND6,New Data" "0,1"
bitfld.long 0x00 5. "ND5,New Data" "0,1"
bitfld.long 0x00 4. "ND4,New Data" "0,1"
newline
bitfld.long 0x00 3. "ND3,New Data" "0,1"
bitfld.long 0x00 2. "ND2,New Data" "0,1"
bitfld.long 0x00 1. "ND1,New Data" "0,1"
bitfld.long 0x00 0. "ND0,New Data" "0,1"
repeat.end
group.long 0xA0++0x47
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address"
bitfld.long 0x00 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
hexmask.long.byte 0x00 16.--22. 1. "F0S,Rx FIFO 0 Size"
hexmask.long.word 0x00 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level"
bitfld.long 0x04 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x04 24. "F0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x04 16.--21. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 8.--13. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x04 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level"
bitfld.long 0x08 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section"
hexmask.long.word 0x0C 2.--15. 1. "RBSA,Rx Buffer Start Address"
line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address"
bitfld.long 0x10 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1"
hexmask.long.byte 0x10 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
hexmask.long.byte 0x10 16.--22. 1. "F1S,Rx FIFO 1 Size"
hexmask.long.word 0x10 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level"
bitfld.long 0x14 30.--31. "DMS,Debug Message Status" "0,1,2,3"
bitfld.long 0x14 25. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x14 24. "F1F,Rx FIFO 1 Full" "0,1"
bitfld.long 0x14 16.--21. "F1PI,Rx FIFO 1 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 8.--13. "F1GI,Rx FIFO 1 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x14 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level"
bitfld.long 0x18 0.--5. "F1AI,Rx FIFO 1 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames"
bitfld.long 0x1C 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address"
bitfld.long 0x20 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
bitfld.long 0x20 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x20 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 2.--15. 1. "TBSA,Tx Buffers Start Address"
line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level"
bitfld.long 0x24 21. "TFQF,Tx FIFO/Queue Full" "0,1"
bitfld.long 0x24 16.--20. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 8.--12. "TFGI,Tx Queue Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 0.--5. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission"
bitfld.long 0x28 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request"
bitfld.long 0x2C 31. "TRP31,Transmission Request Pending" "0,1"
bitfld.long 0x2C 30. "TRP30,Transmission Request Pending" "0,1"
bitfld.long 0x2C 29. "TRP29,Transmission Request Pending" "0,1"
bitfld.long 0x2C 28. "TRP28,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 27. "TRP27,Transmission Request Pending" "0,1"
bitfld.long 0x2C 26. "TRP26,Transmission Request Pending" "0,1"
bitfld.long 0x2C 25. "TRP25,Transmission Request Pending" "0,1"
bitfld.long 0x2C 24. "TRP24,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 23. "TRP23,Transmission Request Pending" "0,1"
bitfld.long 0x2C 22. "TRP22,Transmission Request Pending" "0,1"
bitfld.long 0x2C 21. "TRP21,Transmission Request Pending" "0,1"
bitfld.long 0x2C 20. "TRP20,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 19. "TRP19,Transmission Request Pending" "0,1"
bitfld.long 0x2C 18. "TRP18,Transmission Request Pending" "0,1"
bitfld.long 0x2C 17. "TRP17,Transmission Request Pending" "0,1"
bitfld.long 0x2C 16. "TRP16,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 15. "TRP15,Transmission Request Pending" "0,1"
bitfld.long 0x2C 14. "TRP14,Transmission Request Pending" "0,1"
bitfld.long 0x2C 13. "TRP13,Transmission Request Pending" "0,1"
bitfld.long 0x2C 12. "TRP12,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 11. "TRP11,Transmission Request Pending" "0,1"
bitfld.long 0x2C 10. "TRP10,Transmission Request Pending" "0,1"
bitfld.long 0x2C 9. "TRP9,Transmission Request Pending" "0,1"
bitfld.long 0x2C 8. "TRP8,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 7. "TRP7,Transmission Request Pending" "0,1"
bitfld.long 0x2C 6. "TRP6,Transmission Request Pending" "0,1"
bitfld.long 0x2C 5. "TRP5,Transmission Request Pending" "0,1"
bitfld.long 0x2C 4. "TRP4,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 3. "TRP3,Transmission Request Pending" "0,1"
bitfld.long 0x2C 2. "TRP2,Transmission Request Pending" "0,1"
bitfld.long 0x2C 1. "TRP1,Transmission Request Pending" "0,1"
bitfld.long 0x2C 0. "TRP0,Transmission Request Pending" "0,1"
line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests"
bitfld.long 0x30 31. "AR31,Add request" "0,1"
bitfld.long 0x30 30. "AR30,Add request" "0,1"
bitfld.long 0x30 29. "AR29,Add request" "0,1"
bitfld.long 0x30 28. "AR28,Add request" "0,1"
newline
bitfld.long 0x30 27. "AR27,Add request" "0,1"
bitfld.long 0x30 26. "AR26,Add request" "0,1"
bitfld.long 0x30 25. "AR25,Add request" "0,1"
bitfld.long 0x30 24. "AR24,Add request" "0,1"
newline
bitfld.long 0x30 23. "AR23,Add request" "0,1"
bitfld.long 0x30 22. "AR22,Add request" "0,1"
bitfld.long 0x30 21. "AR21,Add request" "0,1"
bitfld.long 0x30 20. "AR20,Add request" "0,1"
newline
bitfld.long 0x30 19. "AR19,Add request" "0,1"
bitfld.long 0x30 18. "AR18,Add request" "0,1"
bitfld.long 0x30 17. "AR17,Add request" "0,1"
bitfld.long 0x30 16. "AR16,Add request" "0,1"
newline
bitfld.long 0x30 15. "AR15,Add request" "0,1"
bitfld.long 0x30 14. "AR14,Add request" "0,1"
bitfld.long 0x30 13. "AR13,Add request" "0,1"
bitfld.long 0x30 12. "AR12,Add request" "0,1"
newline
bitfld.long 0x30 11. "AR11,Add request" "0,1"
bitfld.long 0x30 10. "AR10,Add request" "0,1"
bitfld.long 0x30 9. "AR9,Add request" "0,1"
bitfld.long 0x30 8. "AR8,Add request" "0,1"
newline
bitfld.long 0x30 7. "AR7,Add request" "0,1"
bitfld.long 0x30 6. "AR6,Add request" "0,1"
bitfld.long 0x30 5. "AR5,Add request" "0,1"
bitfld.long 0x30 4. "AR4,Add request" "0,1"
newline
bitfld.long 0x30 3. "AR3,Add request" "0,1"
bitfld.long 0x30 2. "AR2,Add request" "0,1"
bitfld.long 0x30 1. "AR1,Add request" "0,1"
bitfld.long 0x30 0. "AR0,Add request" "0,1"
line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions"
bitfld.long 0x34 31. "CR31,Cancellation Request" "0,1"
bitfld.long 0x34 30. "CR30,Cancellation Request" "0,1"
bitfld.long 0x34 29. "CR29,Cancellation Request" "0,1"
bitfld.long 0x34 28. "CR28,Cancellation Request" "0,1"
newline
bitfld.long 0x34 27. "CR27,Cancellation Request" "0,1"
bitfld.long 0x34 26. "CR26,Cancellation Request" "0,1"
bitfld.long 0x34 25. "CR25,Cancellation Request" "0,1"
bitfld.long 0x34 24. "CR24,Cancellation Request" "0,1"
newline
bitfld.long 0x34 23. "CR23,Cancellation Request" "0,1"
bitfld.long 0x34 22. "CR22,Cancellation Request" "0,1"
bitfld.long 0x34 21. "CR21,Cancellation Request" "0,1"
bitfld.long 0x34 20. "CR20,Cancellation Request" "0,1"
newline
bitfld.long 0x34 19. "CR19,Cancellation Request" "0,1"
bitfld.long 0x34 18. "CR18,Cancellation Request" "0,1"
bitfld.long 0x34 17. "CR17,Cancellation Request" "0,1"
bitfld.long 0x34 16. "CR16,Cancellation Request" "0,1"
newline
bitfld.long 0x34 15. "CR15,Cancellation Request" "0,1"
bitfld.long 0x34 14. "CR14,Cancellation Request" "0,1"
bitfld.long 0x34 13. "CR13,Cancellation Request" "0,1"
bitfld.long 0x34 12. "CR12,Cancellation Request" "0,1"
newline
bitfld.long 0x34 11. "CR11,Cancellation Request" "0,1"
bitfld.long 0x34 10. "CR10,Cancellation Request" "0,1"
bitfld.long 0x34 9. "CR9,Cancellation Request" "0,1"
bitfld.long 0x34 8. "CR8,Cancellation Request" "0,1"
newline
bitfld.long 0x34 7. "CR7,Cancellation Request" "0,1"
bitfld.long 0x34 6. "CR6,Cancellation Request" "0,1"
bitfld.long 0x34 5. "CR5,Cancellation Request" "0,1"
bitfld.long 0x34 4. "CR4,Cancellation Request" "0,1"
newline
bitfld.long 0x34 3. "CR3,Cancellation Request" "0,1"
bitfld.long 0x34 2. "CR2,Cancellation Request" "0,1"
bitfld.long 0x34 1. "CR1,Cancellation Request" "0,1"
bitfld.long 0x34 0. "CR0,Cancellation Request" "0,1"
line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared"
bitfld.long 0x38 31. "TO31,Transmission Occurred" "0,1"
bitfld.long 0x38 30. "TO30,Transmission Occurred" "0,1"
bitfld.long 0x38 29. "TO29,Transmission Occurred" "0,1"
bitfld.long 0x38 28. "TO28,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 27. "TO27,Transmission Occurred" "0,1"
bitfld.long 0x38 26. "TO26,Transmission Occurred" "0,1"
bitfld.long 0x38 25. "TO25,Transmission Occurred" "0,1"
bitfld.long 0x38 24. "TO24,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 23. "TO23,Transmission Occurred" "0,1"
bitfld.long 0x38 22. "TO22,Transmission Occurred" "0,1"
bitfld.long 0x38 21. "TO21,Transmission Occurred" "0,1"
bitfld.long 0x38 20. "TO20,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 19. "TO19,Transmission Occurred" "0,1"
bitfld.long 0x38 18. "TO18,Transmission Occurred" "0,1"
bitfld.long 0x38 17. "TO17,Transmission Occurred" "0,1"
bitfld.long 0x38 16. "TO16,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 15. "TO15,Transmission Occurred" "0,1"
bitfld.long 0x38 14. "TO14,Transmission Occurred" "0,1"
bitfld.long 0x38 13. "TO13,Transmission Occurred" "0,1"
bitfld.long 0x38 12. "TO12,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 11. "TO11,Transmission Occurred" "0,1"
bitfld.long 0x38 10. "TO10,Transmission Occurred" "0,1"
bitfld.long 0x38 9. "TO9,Transmission Occurred" "0,1"
bitfld.long 0x38 8. "TO8,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 7. "TO7,Transmission Occurred" "0,1"
bitfld.long 0x38 6. "TO6,Transmission Occurred" "0,1"
bitfld.long 0x38 5. "TO5,Transmission Occurred" "0,1"
bitfld.long 0x38 4. "TO4,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 3. "TO3,Transmission Occurred" "0,1"
bitfld.long 0x38 2. "TO2,Transmission Occurred" "0,1"
bitfld.long 0x38 1. "TO1,Transmission Occurred" "0,1"
bitfld.long 0x38 0. "TO0,Transmission Occurred" "0,1"
line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request"
bitfld.long 0x3C 31. "CF31,Cancellation Finished" "0,1"
bitfld.long 0x3C 30. "CF30,Cancellation Finished" "0,1"
bitfld.long 0x3C 29. "CF29,Cancellation Finished" "0,1"
bitfld.long 0x3C 28. "CF28,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 27. "CF27,Cancellation Finished" "0,1"
bitfld.long 0x3C 26. "CF26,Cancellation Finished" "0,1"
bitfld.long 0x3C 25. "CF25,Cancellation Finished" "0,1"
bitfld.long 0x3C 24. "CF24,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 23. "CF23,Cancellation Finished" "0,1"
bitfld.long 0x3C 22. "CF22,Cancellation Finished" "0,1"
bitfld.long 0x3C 21. "CF21,Cancellation Finished" "0,1"
bitfld.long 0x3C 20. "CF20,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 19. "CF19,Cancellation Finished" "0,1"
bitfld.long 0x3C 18. "CF18,Cancellation Finished" "0,1"
bitfld.long 0x3C 17. "CF17,Cancellation Finished" "0,1"
bitfld.long 0x3C 16. "CF16,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 15. "CF15,Cancellation Finished" "0,1"
bitfld.long 0x3C 14. "CF14,Cancellation Finished" "0,1"
bitfld.long 0x3C 13. "CF13,Cancellation Finished" "0,1"
bitfld.long 0x3C 12. "CF12,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 11. "CF11,Cancellation Finished" "0,1"
bitfld.long 0x3C 10. "CF10,Cancellation Finished" "0,1"
bitfld.long 0x3C 9. "CF9,Cancellation Finished" "0,1"
bitfld.long 0x3C 8. "CF8,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 7. "CF7,Cancellation Finished" "0,1"
bitfld.long 0x3C 6. "CF6,Cancellation Finished" "0,1"
bitfld.long 0x3C 5. "CF5,Cancellation Finished" "0,1"
bitfld.long 0x3C 4. "CF4,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 3. "CF3,Cancellation Finished" "0,1"
bitfld.long 0x3C 2. "CF2,Cancellation Finished" "0,1"
bitfld.long 0x3C 1. "CF1,Cancellation Finished" "0,1"
bitfld.long 0x3C 0. "CF0,Cancellation Finished" "0,1"
line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers"
bitfld.long 0x40 31. "TIE31,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 30. "TIE30,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 29. "TIE29,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 28. "TIE28,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 27. "TIE27,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 26. "TIE26,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 25. "TIE25,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 24. "TIE24,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 23. "TIE23,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 22. "TIE22,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 21. "TIE21,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 20. "TIE20,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 19. "TIE19,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 18. "TIE18,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 17. "TIE17,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 16. "TIE16,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 15. "TIE15,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 14. "TIE14,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 13. "TIE13,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 12. "TIE12,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 11. "TIE11,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 10. "TIE10,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 9. "TIE9,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 8. "TIE8,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 7. "TIE7,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 6. "TIE6,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 5. "TIE5,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 4. "TIE4,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 3. "TIE3,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 2. "TIE2,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 1. "TIE1,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 0. "TIE0,Transmission Interrupt Enable" "0,1"
line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers"
bitfld.long 0x44 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1"
repeat 3. (list 1414. 1515. 1616. )(list 0x00 0x04 0x14 )
hgroup.long ($2+0xE8)++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved$1,Reserved Field"
repeat.end
group.long 0xF0++0x0B
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address"
bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level"
bitfld.long 0x04 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x04 24. "EFF,Event FIFO Full" "0,1"
bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 0.--5. "EFFL,Event FIFO Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level"
bitfld.long 0x08 0.--4. "EFAI,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hgroup.long 0x100++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field"
tree.end
tree "MCAN0_ECC_AGGR"
base ad:0x24018000
rgroup.long 0x00++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCAN0_MSGMEM_RAM"
base ad:0x20708000
group.long 0x00++0x03
line.long 0x00 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "MCAN0_SS"
base ad:0x20700000
rgroup.long 0x00++0x2B
line.long 0x00 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS"
bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1"
bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
bitfld.long 0x04 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1"
bitfld.long 0x04 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1"
line.long 0x08 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS"
bitfld.long 0x08 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1"
bitfld.long 0x08 1. "MEM_INIT_DONE," "0,1"
line.long 0x0C "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits"
bitfld.long 0x0C 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x10 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status"
bitfld.long 0x10 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x14 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits"
bitfld.long 0x14 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x18 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable"
bitfld.long 0x18 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x1C "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts"
bitfld.long 0x1C 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x20 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register"
hexmask.long.byte 0x20 0.--7. 1. "EOI,Write with bit position of targeted interrupt"
line.long 0x24 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler"
hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value"
line.long 0x28 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter"
bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "MCASP0_CFG"
base ad:0x2B00000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_PID,The revision identification register (PID) contains identification data for the peripheral"
line.long 0x04 "CFG_PWRIDLESYSCONFIG,"
hexmask.long 0x04 6.--31. 1. "RESERVED66,"
bitfld.long 0x04 2.--5. "OTHER,Reserved for future programming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--1. "IDLEMODE,Power management Configuration of the local target state management mode" "0,1,2,3"
group.long 0x10++0x13
line.long 0x00 "CFG_PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin"
bitfld.long 0x00 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO" "0,1"
bitfld.long 0x00 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO" "0,1"
newline
bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO" "0,1"
bitfld.long 0x00 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO" "0,1"
newline
bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO" "0,1"
bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO" "0,1"
newline
bitfld.long 0x00 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO" "0,1"
hexmask.long.tbyte 0x00 4.--24. 1. "RESERVED67,"
newline
bitfld.long 0x00 0.--3. "AXR,Determines if AXRn pin functions as McASP or GPIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CFG_PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin"
bitfld.long 0x04 31. "AFSR,Determines if AFSR pin functions as an input or output" "0,1"
bitfld.long 0x04 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output" "0,1"
newline
bitfld.long 0x04 29. "ACLKR,Determines if ACLKR pin functions as an input or output" "0,1"
bitfld.long 0x04 28. "AFSX,Determines if AFSX pin functions as an input or output" "0,1"
newline
bitfld.long 0x04 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output" "0,1"
bitfld.long 0x04 26. "ACLKX,Determines if ACLKX pin functions as an input or output" "0,1"
newline
bitfld.long 0x04 25. "AMUTE,Determines if AMUTE pin functions as an input or output" "0,1"
hexmask.long.tbyte 0x04 4.--24. 1. "RESERVED68,"
newline
bitfld.long 0x04 0.--3. "AXR,Determines if AXRn pin functions as an input or output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CFG_PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times"
bitfld.long 0x08 31. "AFSR,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1" "0,1"
bitfld.long 0x08 30. "AHCLKR,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1" "0,1"
newline
bitfld.long 0x08 29. "ACLKR,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1" "0,1"
bitfld.long 0x08 28. "AFSX,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1" "0,1"
newline
bitfld.long 0x08 27. "AHCLKX,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1" "0,1"
bitfld.long 0x08 26. "ACLKX,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1" "0,1"
newline
bitfld.long 0x08 25. "AMUTE,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1" "0,1"
hexmask.long.tbyte 0x08 4.--24. 1. "RESERVED69,"
newline
bitfld.long 0x08 0.--3. "AXR,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CFG_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins"
bitfld.long 0x0C 31. "AFSR,Logic level on AFSR pin" "0,1"
bitfld.long 0x0C 30. "AHCLKR,Logic level on AHCLKR pin" "0,1"
newline
bitfld.long 0x0C 29. "ACLKR,Logic level on ACLKR pin" "0,1"
bitfld.long 0x0C 28. "AFSX,Logic level on AFSX pin" "0,1"
newline
bitfld.long 0x0C 27. "AHCLKX,Logic level on AHCLKX pin" "0,1"
bitfld.long 0x0C 26. "ACLKX,Logic level on ACLKX pin" "0,1"
newline
bitfld.long 0x0C 25. "AMUTE,Logic level on AMUTE pin" "0,1"
hexmask.long.tbyte 0x0C 4.--24. 1. "RESERVED70,"
newline
bitfld.long 0x0C 0.--3. "AXR,Logic level on AXR[n] pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CFG_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only"
bitfld.long 0x10 31. "AFSR,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
bitfld.long 0x10 30. "AHCLKR,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
newline
bitfld.long 0x10 29. "ACLKR,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
bitfld.long 0x10 28. "AFSX,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
newline
bitfld.long 0x10 27. "AHCLKX,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
bitfld.long 0x10 26. "ACLKX,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
newline
bitfld.long 0x10 25. "AMUTE,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
hexmask.long.tbyte 0x10 4.--24. 1. "RESERVED71,"
newline
bitfld.long 0x10 0.--3. "AXR,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x44++0x0F
line.long 0x00 "CFG_GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections"
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED73,"
bitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "0,1"
newline
bitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "0,1"
bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "0,1"
newline
bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "0,1"
bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "0,1"
newline
rbitfld.long 0x00 5.--7. "RESERVED72," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "0,1"
newline
bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "0,1"
bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "0,1"
newline
bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
bitfld.long 0x00 0. "RCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
line.long 0x04 "CFG_AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin"
hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED74,"
bitfld.long 0x04 12. "XDMAERR,If transmit DMA error [XDMAERR] drive AMUTE active enable bit" "0,1"
newline
bitfld.long 0x04 11. "RDMAERR,If receive DMA error [RDMAERR] drive AMUTE active enable bit" "0,1"
bitfld.long 0x04 10. "XCKFAIL,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit" "0,1"
newline
bitfld.long 0x04 9. "RCKFAIL,If receive clock failure [RCKFAIL] drive AMUTE active enable bit" "0,1"
bitfld.long 0x04 8. "XSYNCERR,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit" "0,1"
newline
bitfld.long 0x04 7. "RSYNCERR,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit" "0,1"
bitfld.long 0x04 6. "XUNDRN,If transmit underrun error [XUNDRN] drive AMUTE active enable bit" "0,1"
newline
bitfld.long 0x04 5. "ROVRN,If receiver overrun error [ROVRN] drive AMUTE active enable bit" "0,1"
rbitfld.long 0x04 4. "INSTAT,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1" "0,1"
newline
bitfld.long 0x04 3. "INEN,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]" "0,1"
bitfld.long 0x04 2. "INPOL,Audio mute in [AMUTEIN] polarity select bit" "0,1"
newline
bitfld.long 0x04 0.--1. "MUTEN,AMUTE pin enable bit [unless overridden by GPIO registers]" "0,1,2,3"
line.long 0x08 "CFG_DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode"
hexmask.long 0x08 4.--31. 1. "RESERVED75,"
bitfld.long 0x08 2.--3. "MODE,Loopback generator mode bits" "0,1,2,3"
newline
bitfld.long 0x08 1. "ORD,Loopback order bit when loopback mode is enabled [DLBEN = 1]" "0,1"
bitfld.long 0x08 0. "DLBEN,Loopback mode enable bit" "0,1"
line.long 0x0C "CFG_DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP"
hexmask.long 0x0C 4.--31. 1. "RESERVED77,"
bitfld.long 0x0C 3. "VB,Valid bit for odd time slots [DIT right subframe]" "0,1"
newline
bitfld.long 0x0C 2. "VA,Valid bit for even time slots [DIT left subframe]" "0,1"
rbitfld.long 0x0C 1. "RESERVED76," "0,1"
newline
bitfld.long 0x0C 0. "DITEN,DIT mode enable bit" "0,1"
group.long 0x60++0x2F
line.long 0x00 "CFG_RGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED79,"
rbitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "0,1"
newline
rbitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "0,1"
rbitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "0,1"
newline
rbitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "0,1"
newline
rbitfld.long 0x00 5.--7. "RESERVED78," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "0,1"
newline
bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "0,1"
bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "0,1"
newline
bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "0,1"
line.long 0x04 "CFG_RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA"
line.long 0x08 "CFG_RFMT,The receive bit stream format register (RFMT) configures the receive data format"
hexmask.long.word 0x08 18.--31. 1. "RESERVED80,"
bitfld.long 0x08 16.--17. "RDATDLY,Receive bit delay" "0,1,2,3"
newline
bitfld.long 0x08 15. "RRVRS,Receive serial bitstream order" "0,1"
bitfld.long 0x08 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "0,1,2,3"
newline
bitfld.long 0x08 8.--12. "RPBIT,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 4.--7. "RSSZ,Receive slot size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "0,1"
bitfld.long 0x08 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "0,1,2,3,4,5,6,7"
line.long 0x0C "CFG_AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED83,"
hexmask.long.word 0x0C 7.--15. 1. "RMOD,Receive frame sync mode select bits"
newline
rbitfld.long 0x0C 5.--6. "RESERVED82," "0,1,2,3"
bitfld.long 0x0C 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period" "0,1"
newline
rbitfld.long 0x0C 2.--3. "RESERVED81," "0,1,2,3"
bitfld.long 0x0C 1. "FSRM,Receive frame sync generation select bit" "0,1"
newline
bitfld.long 0x0C 0. "FSRP,Receive frame sync polarity select bit" "0,1"
line.long 0x10 "CFG_ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator"
hexmask.long.word 0x10 21.--31. 1. "RESERVED86,"
bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1"
newline
bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1"
bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1"
newline
bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "0,1,2,3"
hexmask.long.byte 0x10 8.--15. 1. "RESERVED85,"
newline
bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit" "0,1"
rbitfld.long 0x10 6. "RESERVED84," "0,1"
newline
bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit" "0,1"
bitfld.long 0x10 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "CFG_AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator"
hexmask.long.word 0x14 21.--31. 1. "RESERVED88,"
bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1"
newline
bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1"
bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1"
newline
bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "0,1,2,3"
bitfld.long 0x14 15. "HCLKRM,Receive high-frequency clock source bit" "0,1"
newline
bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "0,1"
rbitfld.long 0x14 12.--13. "RESERVED87," "0,1,2,3"
newline
hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR"
line.long 0x18 "CFG_RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active"
line.long 0x1C "CFG_RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED90,"
bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit" "0,1"
newline
rbitfld.long 0x1C 6. "RESERVED89," "0,1"
bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit" "0,1"
bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit" "0,1"
bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit" "0,1"
line.long 0x20 "CFG_RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED91,"
bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "0,1"
newline
bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag" "0,1"
bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag" "0,1"
newline
bitfld.long 0x20 5. "RDATA,Receive data ready flag" "0,1"
bitfld.long 0x20 4. "RLAST,Receive last slot flag" "0,1"
newline
rbitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT" "0,1"
bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag" "0,1"
newline
bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag" "0,1"
bitfld.long 0x20 0. "ROVRN,Receiver overrun flag" "0,1"
line.long 0x24 "CFG_RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame"
hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED92,"
hexmask.long.word 0x24 0.--8. 1. "RSLOTCNT,"
line.long 0x28 "CFG_RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "RCNT,Receive clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "RMAX,Receive clock maximum boundary"
newline
hexmask.long.byte 0x28 8.--15. 1. "RMIN,Receive clock minimum boundary"
rbitfld.long 0x28 4.--7. "RESERVED93," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 0.--3. "RPS,Receive clock check prescaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "CFG_PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event"
hexmask.long 0x2C 1.--31. 1. "RESERVED94,"
bitfld.long 0x2C 0. "RDATDMA,Receive data DMA request enable bit" "0,1"
group.long 0xA0++0x2F
line.long 0x00 "CFG_XGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED96,"
bitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "0,1"
newline
bitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "0,1"
bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "0,1"
newline
bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "0,1"
bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "0,1"
newline
rbitfld.long 0x00 5.--7. "RESERVED95," "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "0,1"
newline
rbitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "0,1"
rbitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "0,1"
newline
rbitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "0,1"
line.long 0x04 "CFG_XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP"
line.long 0x08 "CFG_XFMT,The transmit bit stream format register (XFMT) configures the transmit data format"
hexmask.long.word 0x08 18.--31. 1. "RESERVED97,"
bitfld.long 0x08 16.--17. "XDATDLY,Transmit sync bit delay" "0,1,2,3"
newline
bitfld.long 0x08 15. "XRVRS,Transmit serial bitstream order" "0,1"
bitfld.long 0x08 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "0,1,2,3"
newline
bitfld.long 0x08 8.--12. "XPBIT,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 4.--7. "XSSZ,Transmit slot size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "0,1"
bitfld.long 0x08 0.--2. "XROT,Right-rotation value for transmit rotate right format unit" "0,1,2,3,4,5,6,7"
line.long 0x0C "CFG_AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED100,"
hexmask.long.word 0x0C 7.--15. 1. "XMOD,Transmit frame sync mode select bits"
newline
rbitfld.long 0x0C 5.--6. "RESERVED99," "0,1,2,3"
bitfld.long 0x0C 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period" "0,1"
newline
rbitfld.long 0x0C 2.--3. "RESERVED98," "0,1,2,3"
bitfld.long 0x0C 1. "FSXM,Transmit frame sync generation select bit" "0,1"
newline
bitfld.long 0x0C 0. "FSXP,Transmit frame sync polarity select bit" "0,1"
line.long 0x10 "CFG_ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator"
hexmask.long.word 0x10 21.--31. 1. "RESERVED102,"
bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1"
newline
bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1"
bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1"
newline
bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "0,1,2,3"
hexmask.long.byte 0x10 8.--15. 1. "RESERVED101,"
newline
bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit" "0,1"
bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit" "0,1"
newline
bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit" "0,1"
bitfld.long 0x10 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "CFG_AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator"
hexmask.long.word 0x14 21.--31. 1. "RESERVED104,"
bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1"
newline
bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1"
bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1"
newline
bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "0,1,2,3"
bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit" "0,1"
newline
bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "0,1"
rbitfld.long 0x14 12.--13. "RESERVED103," "0,1,2,3"
newline
hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX"
line.long 0x18 "CFG_XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active"
line.long 0x1C "CFG_XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED106,"
bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit" "0,1"
newline
rbitfld.long 0x1C 6. "RESERVED105," "0,1"
bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit" "0,1"
bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit" "0,1"
bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit" "0,1"
line.long 0x20 "CFG_XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED107,"
bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "0,1"
newline
bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag" "0,1"
bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag" "0,1"
newline
bitfld.long 0x20 5. "XDATA,Transmit data ready flag" "0,1"
bitfld.long 0x20 4. "XLAST,Transmit last slot flag" "0,1"
newline
rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT" "0,1"
bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag" "0,1"
newline
bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag" "0,1"
bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag" "0,1"
line.long 0x24 "CFG_XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame"
hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED108,"
hexmask.long.word 0x24 0.--9. 1. "XSLOTCNT,Current transmit time slot count"
line.long 0x28 "CFG_XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "XCNT,Transmit clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "XMAX,Transmit clock maximum boundary"
newline
hexmask.long.byte 0x28 8.--15. 1. "XMIN,Transmit clock minimum boundary"
rbitfld.long 0x28 4.--7. "RESERVED109," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 0.--3. "XPS,Transmit clock check prescaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "CFG_XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event"
hexmask.long 0x2C 1.--31. 1. "RESERVED110,"
bitfld.long 0x2C 0. "XDATDMA,Transmit data DMA request enable bit" "0,1"
group.long 0x100++0x03
line.long 0x00 "CFG_DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot)"
repeat 5. (list 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x104)++0x03
line.long 0x00 "CFG_DITCSRA$1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x118)++0x03
line.long 0x00 "CFG_DITCSRB$1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x130)++0x03
line.long 0x00 "CFG_DITUDRA$1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x148)++0x03
line.long 0x00 "CFG_DITUDRB$1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot)"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x180)++0x03
line.long 0x00 "CFG_SRCTL$1,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x00 6.--31. 1. "RESERVED111,"
rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "0,1"
newline
rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "0,1"
bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit" "0,1,2,3"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "CFG_XBUF$1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "CFG_RBUF$1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit"
repeat.end
group.long 0x1000++0x0F
line.long 0x00 "CFG_WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO"
hexmask.long.word 0x00 17.--31. 1. "RESERVED127,"
bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "WNUMEVT,Write word count per DMA event [32 bit]"
hexmask.long.byte 0x00 0.--7. 1. "WNUMDMA,Write word count per transfer [32 bit words]"
line.long 0x04 "CFG_WFIFOSTS,"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED128,"
abitfld.long 0x04 0.--7. "WLVL,Write level [read-only]" "0x40=3 to 64 words currently in Write FIFO from..,0xFF=Reserved from 41h to FFh"
line.long 0x08 "CFG_RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO"
hexmask.long.word 0x08 17.--31. 1. "RESERVED129,"
bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "0,1"
newline
abitfld.long 0x08 8.--15. "RNUMEVT,Read word count per DMA event [32 bit]" "0x41=FFh,0xFF=.."
abitfld.long 0x08 0.--7. "RNUMDMA,Read word count per transfer [32 bit words]" "0x10=3 to 16 words from 3h to 10h,0xFF=Reserved from 11h to FFh"
line.long 0x0C "CFG_RFIFOSTS,"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED130,"
abitfld.long 0x0C 0.--7. "RLVL,Read level [read-only]" "0x40=3 to 64 words currently in Read FIFO from..,0xFF=Reserved from 41h to FFh"
tree.end
tree "MCASP0_DMA"
base ad:0x2B08000
tree.end
tree "MCASP1_CFG"
base ad:0x2B10000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_PID,The revision identification register (PID) contains identification data for the peripheral"
line.long 0x04 "CFG_PWRIDLESYSCONFIG,"
hexmask.long 0x04 6.--31. 1. "RESERVED66,"
bitfld.long 0x04 2.--5. "OTHER,Reserved for future programming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--1. "IDLEMODE,Power management Configuration of the local target state management mode" "0,1,2,3"
group.long 0x10++0x13
line.long 0x00 "CFG_PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin"
bitfld.long 0x00 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO" "0,1"
bitfld.long 0x00 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO" "0,1"
newline
bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO" "0,1"
bitfld.long 0x00 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO" "0,1"
newline
bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO" "0,1"
bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO" "0,1"
newline
bitfld.long 0x00 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO" "0,1"
hexmask.long.tbyte 0x00 4.--24. 1. "RESERVED67,"
newline
bitfld.long 0x00 0.--3. "AXR,Determines if AXRn pin functions as McASP or GPIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CFG_PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin"
bitfld.long 0x04 31. "AFSR,Determines if AFSR pin functions as an input or output" "0,1"
bitfld.long 0x04 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output" "0,1"
newline
bitfld.long 0x04 29. "ACLKR,Determines if ACLKR pin functions as an input or output" "0,1"
bitfld.long 0x04 28. "AFSX,Determines if AFSX pin functions as an input or output" "0,1"
newline
bitfld.long 0x04 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output" "0,1"
bitfld.long 0x04 26. "ACLKX,Determines if ACLKX pin functions as an input or output" "0,1"
newline
bitfld.long 0x04 25. "AMUTE,Determines if AMUTE pin functions as an input or output" "0,1"
hexmask.long.tbyte 0x04 4.--24. 1. "RESERVED68,"
newline
bitfld.long 0x04 0.--3. "AXR,Determines if AXRn pin functions as an input or output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CFG_PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times"
bitfld.long 0x08 31. "AFSR,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1" "0,1"
bitfld.long 0x08 30. "AHCLKR,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1" "0,1"
newline
bitfld.long 0x08 29. "ACLKR,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1" "0,1"
bitfld.long 0x08 28. "AFSX,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1" "0,1"
newline
bitfld.long 0x08 27. "AHCLKX,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1" "0,1"
bitfld.long 0x08 26. "ACLKX,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1" "0,1"
newline
bitfld.long 0x08 25. "AMUTE,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1" "0,1"
hexmask.long.tbyte 0x08 4.--24. 1. "RESERVED69,"
newline
bitfld.long 0x08 0.--3. "AXR,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CFG_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins"
bitfld.long 0x0C 31. "AFSR,Logic level on AFSR pin" "0,1"
bitfld.long 0x0C 30. "AHCLKR,Logic level on AHCLKR pin" "0,1"
newline
bitfld.long 0x0C 29. "ACLKR,Logic level on ACLKR pin" "0,1"
bitfld.long 0x0C 28. "AFSX,Logic level on AFSX pin" "0,1"
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bitfld.long 0x0C 27. "AHCLKX,Logic level on AHCLKX pin" "0,1"
bitfld.long 0x0C 26. "ACLKX,Logic level on ACLKX pin" "0,1"
newline
bitfld.long 0x0C 25. "AMUTE,Logic level on AMUTE pin" "0,1"
hexmask.long.tbyte 0x0C 4.--24. 1. "RESERVED70,"
newline
bitfld.long 0x0C 0.--3. "AXR,Logic level on AXR[n] pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CFG_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only"
bitfld.long 0x10 31. "AFSR,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
bitfld.long 0x10 30. "AHCLKR,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
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bitfld.long 0x10 29. "ACLKR,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
bitfld.long 0x10 28. "AFSX,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
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bitfld.long 0x10 27. "AHCLKX,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
bitfld.long 0x10 26. "ACLKX,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
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bitfld.long 0x10 25. "AMUTE,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
hexmask.long.tbyte 0x10 4.--24. 1. "RESERVED71,"
newline
bitfld.long 0x10 0.--3. "AXR,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x44++0x0F
line.long 0x00 "CFG_GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections"
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED73,"
bitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "0,1"
newline
bitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "0,1"
bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "0,1"
newline
bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "0,1"
bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "0,1"
newline
rbitfld.long 0x00 5.--7. "RESERVED72," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "0,1"
newline
bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "0,1"
bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "0,1"
newline
bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
bitfld.long 0x00 0. "RCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
line.long 0x04 "CFG_AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin"
hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED74,"
bitfld.long 0x04 12. "XDMAERR,If transmit DMA error [XDMAERR] drive AMUTE active enable bit" "0,1"
newline
bitfld.long 0x04 11. "RDMAERR,If receive DMA error [RDMAERR] drive AMUTE active enable bit" "0,1"
bitfld.long 0x04 10. "XCKFAIL,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit" "0,1"
newline
bitfld.long 0x04 9. "RCKFAIL,If receive clock failure [RCKFAIL] drive AMUTE active enable bit" "0,1"
bitfld.long 0x04 8. "XSYNCERR,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit" "0,1"
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bitfld.long 0x04 7. "RSYNCERR,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit" "0,1"
bitfld.long 0x04 6. "XUNDRN,If transmit underrun error [XUNDRN] drive AMUTE active enable bit" "0,1"
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bitfld.long 0x04 5. "ROVRN,If receiver overrun error [ROVRN] drive AMUTE active enable bit" "0,1"
rbitfld.long 0x04 4. "INSTAT,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1" "0,1"
newline
bitfld.long 0x04 3. "INEN,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]" "0,1"
bitfld.long 0x04 2. "INPOL,Audio mute in [AMUTEIN] polarity select bit" "0,1"
newline
bitfld.long 0x04 0.--1. "MUTEN,AMUTE pin enable bit [unless overridden by GPIO registers]" "0,1,2,3"
line.long 0x08 "CFG_DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode"
hexmask.long 0x08 4.--31. 1. "RESERVED75,"
bitfld.long 0x08 2.--3. "MODE,Loopback generator mode bits" "0,1,2,3"
newline
bitfld.long 0x08 1. "ORD,Loopback order bit when loopback mode is enabled [DLBEN = 1]" "0,1"
bitfld.long 0x08 0. "DLBEN,Loopback mode enable bit" "0,1"
line.long 0x0C "CFG_DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP"
hexmask.long 0x0C 4.--31. 1. "RESERVED77,"
bitfld.long 0x0C 3. "VB,Valid bit for odd time slots [DIT right subframe]" "0,1"
newline
bitfld.long 0x0C 2. "VA,Valid bit for even time slots [DIT left subframe]" "0,1"
rbitfld.long 0x0C 1. "RESERVED76," "0,1"
newline
bitfld.long 0x0C 0. "DITEN,DIT mode enable bit" "0,1"
group.long 0x60++0x2F
line.long 0x00 "CFG_RGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED79,"
rbitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "0,1"
newline
rbitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "0,1"
rbitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "0,1"
newline
rbitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "0,1"
newline
rbitfld.long 0x00 5.--7. "RESERVED78," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "0,1"
newline
bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "0,1"
bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "0,1"
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bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "0,1"
line.long 0x04 "CFG_RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA"
line.long 0x08 "CFG_RFMT,The receive bit stream format register (RFMT) configures the receive data format"
hexmask.long.word 0x08 18.--31. 1. "RESERVED80,"
bitfld.long 0x08 16.--17. "RDATDLY,Receive bit delay" "0,1,2,3"
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bitfld.long 0x08 15. "RRVRS,Receive serial bitstream order" "0,1"
bitfld.long 0x08 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "0,1,2,3"
newline
bitfld.long 0x08 8.--12. "RPBIT,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 4.--7. "RSSZ,Receive slot size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "0,1"
bitfld.long 0x08 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "0,1,2,3,4,5,6,7"
line.long 0x0C "CFG_AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED83,"
hexmask.long.word 0x0C 7.--15. 1. "RMOD,Receive frame sync mode select bits"
newline
rbitfld.long 0x0C 5.--6. "RESERVED82," "0,1,2,3"
bitfld.long 0x0C 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period" "0,1"
newline
rbitfld.long 0x0C 2.--3. "RESERVED81," "0,1,2,3"
bitfld.long 0x0C 1. "FSRM,Receive frame sync generation select bit" "0,1"
newline
bitfld.long 0x0C 0. "FSRP,Receive frame sync polarity select bit" "0,1"
line.long 0x10 "CFG_ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator"
hexmask.long.word 0x10 21.--31. 1. "RESERVED86,"
bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1"
newline
bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1"
bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1"
newline
bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "0,1,2,3"
hexmask.long.byte 0x10 8.--15. 1. "RESERVED85,"
newline
bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit" "0,1"
rbitfld.long 0x10 6. "RESERVED84," "0,1"
newline
bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit" "0,1"
bitfld.long 0x10 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "CFG_AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator"
hexmask.long.word 0x14 21.--31. 1. "RESERVED88,"
bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1"
newline
bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1"
bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1"
newline
bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "0,1,2,3"
bitfld.long 0x14 15. "HCLKRM,Receive high-frequency clock source bit" "0,1"
newline
bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "0,1"
rbitfld.long 0x14 12.--13. "RESERVED87," "0,1,2,3"
newline
hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR"
line.long 0x18 "CFG_RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active"
line.long 0x1C "CFG_RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED90,"
bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit" "0,1"
newline
rbitfld.long 0x1C 6. "RESERVED89," "0,1"
bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit" "0,1"
bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit" "0,1"
bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit" "0,1"
line.long 0x20 "CFG_RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED91,"
bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "0,1"
newline
bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag" "0,1"
bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag" "0,1"
newline
bitfld.long 0x20 5. "RDATA,Receive data ready flag" "0,1"
bitfld.long 0x20 4. "RLAST,Receive last slot flag" "0,1"
newline
rbitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT" "0,1"
bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag" "0,1"
newline
bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag" "0,1"
bitfld.long 0x20 0. "ROVRN,Receiver overrun flag" "0,1"
line.long 0x24 "CFG_RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame"
hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED92,"
hexmask.long.word 0x24 0.--8. 1. "RSLOTCNT,"
line.long 0x28 "CFG_RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "RCNT,Receive clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "RMAX,Receive clock maximum boundary"
newline
hexmask.long.byte 0x28 8.--15. 1. "RMIN,Receive clock minimum boundary"
rbitfld.long 0x28 4.--7. "RESERVED93," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 0.--3. "RPS,Receive clock check prescaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "CFG_PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event"
hexmask.long 0x2C 1.--31. 1. "RESERVED94,"
bitfld.long 0x2C 0. "RDATDMA,Receive data DMA request enable bit" "0,1"
group.long 0xA0++0x2F
line.long 0x00 "CFG_XGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED96,"
bitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "0,1"
newline
bitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "0,1"
bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "0,1"
newline
bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "0,1"
bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "0,1"
newline
rbitfld.long 0x00 5.--7. "RESERVED95," "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "0,1"
newline
rbitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "0,1"
rbitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "0,1"
newline
rbitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "0,1"
line.long 0x04 "CFG_XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP"
line.long 0x08 "CFG_XFMT,The transmit bit stream format register (XFMT) configures the transmit data format"
hexmask.long.word 0x08 18.--31. 1. "RESERVED97,"
bitfld.long 0x08 16.--17. "XDATDLY,Transmit sync bit delay" "0,1,2,3"
newline
bitfld.long 0x08 15. "XRVRS,Transmit serial bitstream order" "0,1"
bitfld.long 0x08 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "0,1,2,3"
newline
bitfld.long 0x08 8.--12. "XPBIT,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 4.--7. "XSSZ,Transmit slot size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "0,1"
bitfld.long 0x08 0.--2. "XROT,Right-rotation value for transmit rotate right format unit" "0,1,2,3,4,5,6,7"
line.long 0x0C "CFG_AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED100,"
hexmask.long.word 0x0C 7.--15. 1. "XMOD,Transmit frame sync mode select bits"
newline
rbitfld.long 0x0C 5.--6. "RESERVED99," "0,1,2,3"
bitfld.long 0x0C 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period" "0,1"
newline
rbitfld.long 0x0C 2.--3. "RESERVED98," "0,1,2,3"
bitfld.long 0x0C 1. "FSXM,Transmit frame sync generation select bit" "0,1"
newline
bitfld.long 0x0C 0. "FSXP,Transmit frame sync polarity select bit" "0,1"
line.long 0x10 "CFG_ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator"
hexmask.long.word 0x10 21.--31. 1. "RESERVED102,"
bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1"
newline
bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1"
bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1"
newline
bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "0,1,2,3"
hexmask.long.byte 0x10 8.--15. 1. "RESERVED101,"
newline
bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit" "0,1"
bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit" "0,1"
newline
bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit" "0,1"
bitfld.long 0x10 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "CFG_AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator"
hexmask.long.word 0x14 21.--31. 1. "RESERVED104,"
bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1"
newline
bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1"
bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1"
newline
bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "0,1,2,3"
bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit" "0,1"
newline
bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "0,1"
rbitfld.long 0x14 12.--13. "RESERVED103," "0,1,2,3"
newline
hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX"
line.long 0x18 "CFG_XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active"
line.long 0x1C "CFG_XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED106,"
bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit" "0,1"
newline
rbitfld.long 0x1C 6. "RESERVED105," "0,1"
bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit" "0,1"
bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit" "0,1"
bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit" "0,1"
line.long 0x20 "CFG_XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED107,"
bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "0,1"
newline
bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag" "0,1"
bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag" "0,1"
newline
bitfld.long 0x20 5. "XDATA,Transmit data ready flag" "0,1"
bitfld.long 0x20 4. "XLAST,Transmit last slot flag" "0,1"
newline
rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT" "0,1"
bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag" "0,1"
newline
bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag" "0,1"
bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag" "0,1"
line.long 0x24 "CFG_XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame"
hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED108,"
hexmask.long.word 0x24 0.--9. 1. "XSLOTCNT,Current transmit time slot count"
line.long 0x28 "CFG_XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "XCNT,Transmit clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "XMAX,Transmit clock maximum boundary"
newline
hexmask.long.byte 0x28 8.--15. 1. "XMIN,Transmit clock minimum boundary"
rbitfld.long 0x28 4.--7. "RESERVED109," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 0.--3. "XPS,Transmit clock check prescaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "CFG_XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event"
hexmask.long 0x2C 1.--31. 1. "RESERVED110,"
bitfld.long 0x2C 0. "XDATDMA,Transmit data DMA request enable bit" "0,1"
group.long 0x100++0x03
line.long 0x00 "CFG_DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot)"
repeat 5. (list 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x104)++0x03
line.long 0x00 "CFG_DITCSRA$1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x118)++0x03
line.long 0x00 "CFG_DITCSRB$1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x130)++0x03
line.long 0x00 "CFG_DITUDRA$1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x148)++0x03
line.long 0x00 "CFG_DITUDRB$1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot)"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x180)++0x03
line.long 0x00 "CFG_SRCTL$1,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x00 6.--31. 1. "RESERVED111,"
rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "0,1"
newline
rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "0,1"
bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit" "0,1,2,3"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "CFG_XBUF$1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "CFG_RBUF$1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit"
repeat.end
group.long 0x1000++0x0F
line.long 0x00 "CFG_WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO"
hexmask.long.word 0x00 17.--31. 1. "RESERVED127,"
bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "WNUMEVT,Write word count per DMA event [32 bit]"
hexmask.long.byte 0x00 0.--7. 1. "WNUMDMA,Write word count per transfer [32 bit words]"
line.long 0x04 "CFG_WFIFOSTS,"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED128,"
abitfld.long 0x04 0.--7. "WLVL,Write level [read-only]" "0x40=3 to 64 words currently in Write FIFO from..,0xFF=Reserved from 41h to FFh"
line.long 0x08 "CFG_RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO"
hexmask.long.word 0x08 17.--31. 1. "RESERVED129,"
bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "0,1"
newline
abitfld.long 0x08 8.--15. "RNUMEVT,Read word count per DMA event [32 bit]" "0x41=FFh,0xFF=.."
abitfld.long 0x08 0.--7. "RNUMDMA,Read word count per transfer [32 bit words]" "0x10=3 to 16 words from 3h to 10h,0xFF=Reserved from 11h to FFh"
line.long 0x0C "CFG_RFIFOSTS,"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED130,"
abitfld.long 0x0C 0.--7. "RLVL,Read level [read-only]" "0x40=3 to 64 words currently in Read FIFO from..,0xFF=Reserved from 41h to FFh"
tree.end
tree "MCASP1_DMA"
base ad:0x2B18000
tree.end
tree "MCASP2_CFG"
base ad:0x2B20000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_PID,The revision identification register (PID) contains identification data for the peripheral"
line.long 0x04 "CFG_PWRIDLESYSCONFIG,"
hexmask.long 0x04 6.--31. 1. "RESERVED66,"
bitfld.long 0x04 2.--5. "OTHER,Reserved for future programming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--1. "IDLEMODE,Power management Configuration of the local target state management mode" "0,1,2,3"
group.long 0x10++0x13
line.long 0x00 "CFG_PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin"
bitfld.long 0x00 31. "AFSR,Determines if AFSR pin functions as McASP or GPIO" "0,1"
bitfld.long 0x00 30. "AHCLKR,Determines if AHCLKR pin functions as McASP or GPIO" "0,1"
newline
bitfld.long 0x00 29. "ACLKR,Determines if ACLKR pin functions as McASP or GPIO" "0,1"
bitfld.long 0x00 28. "AFSX,Determines if AFSX pin functions as McASP or GPIO" "0,1"
newline
bitfld.long 0x00 27. "AHCLKX,Determines if AHCLKX pin functions as McASP or GPIO" "0,1"
bitfld.long 0x00 26. "ACLKX,Determines if ACLKX pin functions as McASP or GPIO" "0,1"
newline
bitfld.long 0x00 25. "AMUTE,Determines if AMUTE pin functions as McASP or GPIO" "0,1"
hexmask.long.tbyte 0x00 4.--24. 1. "RESERVED67,"
newline
bitfld.long 0x00 0.--3. "AXR,Determines if AXRn pin functions as McASP or GPIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CFG_PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin"
bitfld.long 0x04 31. "AFSR,Determines if AFSR pin functions as an input or output" "0,1"
bitfld.long 0x04 30. "AHCLKR,Determines if AHCLKR pin functions as an input or output" "0,1"
newline
bitfld.long 0x04 29. "ACLKR,Determines if ACLKR pin functions as an input or output" "0,1"
bitfld.long 0x04 28. "AFSX,Determines if AFSX pin functions as an input or output" "0,1"
newline
bitfld.long 0x04 27. "AHCLKX,Determines if AHCLKX pin functions as an input or output" "0,1"
bitfld.long 0x04 26. "ACLKX,Determines if ACLKX pin functions as an input or output" "0,1"
newline
bitfld.long 0x04 25. "AMUTE,Determines if AMUTE pin functions as an input or output" "0,1"
hexmask.long.tbyte 0x04 4.--24. 1. "RESERVED68,"
newline
bitfld.long 0x04 0.--3. "AXR,Determines if AXRn pin functions as an input or output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CFG_PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times"
bitfld.long 0x08 31. "AFSR,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1" "0,1"
bitfld.long 0x08 30. "AHCLKR,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1" "0,1"
newline
bitfld.long 0x08 29. "ACLKR,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1" "0,1"
bitfld.long 0x08 28. "AFSX,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1" "0,1"
newline
bitfld.long 0x08 27. "AHCLKX,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1" "0,1"
bitfld.long 0x08 26. "ACLKX,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1" "0,1"
newline
bitfld.long 0x08 25. "AMUTE,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1" "0,1"
hexmask.long.tbyte 0x08 4.--24. 1. "RESERVED69,"
newline
bitfld.long 0x08 0.--3. "AXR,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CFG_PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins"
bitfld.long 0x0C 31. "AFSR,Logic level on AFSR pin" "0,1"
bitfld.long 0x0C 30. "AHCLKR,Logic level on AHCLKR pin" "0,1"
newline
bitfld.long 0x0C 29. "ACLKR,Logic level on ACLKR pin" "0,1"
bitfld.long 0x0C 28. "AFSX,Logic level on AFSX pin" "0,1"
newline
bitfld.long 0x0C 27. "AHCLKX,Logic level on AHCLKX pin" "0,1"
bitfld.long 0x0C 26. "ACLKX,Logic level on ACLKX pin" "0,1"
newline
bitfld.long 0x0C 25. "AMUTE,Logic level on AMUTE pin" "0,1"
hexmask.long.tbyte 0x0C 4.--24. 1. "RESERVED70,"
newline
bitfld.long 0x0C 0.--3. "AXR,Logic level on AXR[n] pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CFG_PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only"
bitfld.long 0x10 31. "AFSR,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
bitfld.long 0x10 30. "AHCLKR,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
newline
bitfld.long 0x10 29. "ACLKR,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
bitfld.long 0x10 28. "AFSX,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
newline
bitfld.long 0x10 27. "AHCLKX,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
bitfld.long 0x10 26. "ACLKX,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
newline
bitfld.long 0x10 25. "AMUTE,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1"
hexmask.long.tbyte 0x10 4.--24. 1. "RESERVED71,"
newline
bitfld.long 0x10 0.--3. "AXR,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x44++0x0F
line.long 0x00 "CFG_GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections"
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED73,"
bitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "0,1"
newline
bitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "0,1"
bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "0,1"
newline
bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "0,1"
bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "0,1"
newline
rbitfld.long 0x00 5.--7. "RESERVED72," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "0,1"
newline
bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "0,1"
bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "0,1"
newline
bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
bitfld.long 0x00 0. "RCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
line.long 0x04 "CFG_AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin"
hexmask.long.tbyte 0x04 13.--31. 1. "RESERVED74,"
bitfld.long 0x04 12. "XDMAERR,If transmit DMA error [XDMAERR] drive AMUTE active enable bit" "0,1"
newline
bitfld.long 0x04 11. "RDMAERR,If receive DMA error [RDMAERR] drive AMUTE active enable bit" "0,1"
bitfld.long 0x04 10. "XCKFAIL,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit" "0,1"
newline
bitfld.long 0x04 9. "RCKFAIL,If receive clock failure [RCKFAIL] drive AMUTE active enable bit" "0,1"
bitfld.long 0x04 8. "XSYNCERR,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit" "0,1"
newline
bitfld.long 0x04 7. "RSYNCERR,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit" "0,1"
bitfld.long 0x04 6. "XUNDRN,If transmit underrun error [XUNDRN] drive AMUTE active enable bit" "0,1"
newline
bitfld.long 0x04 5. "ROVRN,If receiver overrun error [ROVRN] drive AMUTE active enable bit" "0,1"
rbitfld.long 0x04 4. "INSTAT,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1" "0,1"
newline
bitfld.long 0x04 3. "INEN,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]" "0,1"
bitfld.long 0x04 2. "INPOL,Audio mute in [AMUTEIN] polarity select bit" "0,1"
newline
bitfld.long 0x04 0.--1. "MUTEN,AMUTE pin enable bit [unless overridden by GPIO registers]" "0,1,2,3"
line.long 0x08 "CFG_DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode"
hexmask.long 0x08 4.--31. 1. "RESERVED75,"
bitfld.long 0x08 2.--3. "MODE,Loopback generator mode bits" "0,1,2,3"
newline
bitfld.long 0x08 1. "ORD,Loopback order bit when loopback mode is enabled [DLBEN = 1]" "0,1"
bitfld.long 0x08 0. "DLBEN,Loopback mode enable bit" "0,1"
line.long 0x0C "CFG_DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP"
hexmask.long 0x0C 4.--31. 1. "RESERVED77,"
bitfld.long 0x0C 3. "VB,Valid bit for odd time slots [DIT right subframe]" "0,1"
newline
bitfld.long 0x0C 2. "VA,Valid bit for even time slots [DIT left subframe]" "0,1"
rbitfld.long 0x0C 1. "RESERVED76," "0,1"
newline
bitfld.long 0x0C 0. "DITEN,DIT mode enable bit" "0,1"
group.long 0x60++0x2F
line.long 0x00 "CFG_RGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED79,"
rbitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "0,1"
newline
rbitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "0,1"
rbitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "0,1"
newline
rbitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "0,1"
newline
rbitfld.long 0x00 5.--7. "RESERVED78," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "0,1"
newline
bitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "0,1"
bitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "0,1"
newline
bitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
bitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "0,1"
line.long 0x04 "CFG_RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA"
line.long 0x08 "CFG_RFMT,The receive bit stream format register (RFMT) configures the receive data format"
hexmask.long.word 0x08 18.--31. 1. "RESERVED80,"
bitfld.long 0x08 16.--17. "RDATDLY,Receive bit delay" "0,1,2,3"
newline
bitfld.long 0x08 15. "RRVRS,Receive serial bitstream order" "0,1"
bitfld.long 0x08 13.--14. "RPAD,Pad value for extra bits in slot not belonging to the word" "0,1,2,3"
newline
bitfld.long 0x08 8.--12. "RPBIT,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 4.--7. "RSSZ,Receive slot size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 3. "RBUSEL,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "0,1"
bitfld.long 0x08 0.--2. "RROT,Right-rotation value for receive rotate right format unit" "0,1,2,3,4,5,6,7"
line.long 0x0C "CFG_AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED83,"
hexmask.long.word 0x0C 7.--15. 1. "RMOD,Receive frame sync mode select bits"
newline
rbitfld.long 0x0C 5.--6. "RESERVED82," "0,1,2,3"
bitfld.long 0x0C 4. "FRWID,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period" "0,1"
newline
rbitfld.long 0x0C 2.--3. "RESERVED81," "0,1,2,3"
bitfld.long 0x0C 1. "FSRM,Receive frame sync generation select bit" "0,1"
newline
bitfld.long 0x0C 0. "FSRP,Receive frame sync polarity select bit" "0,1"
line.long 0x10 "CFG_ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator"
hexmask.long.word 0x10 21.--31. 1. "RESERVED86,"
bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1"
newline
bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1"
bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1"
newline
bitfld.long 0x10 16.--17. "CLKRADJ,CLKRDIV one-shot adjustment" "0,1,2,3"
hexmask.long.byte 0x10 8.--15. 1. "RESERVED85,"
newline
bitfld.long 0x10 7. "CLKRP,Receive bitstream clock polarity select bit" "0,1"
rbitfld.long 0x10 6. "RESERVED84," "0,1"
newline
bitfld.long 0x10 5. "CLKRM,Receive bit clock source bit" "0,1"
bitfld.long 0x10 0.--4. "CLKRDIV,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "CFG_AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator"
hexmask.long.word 0x14 21.--31. 1. "RESERVED88,"
bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1"
newline
bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1"
bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1"
newline
bitfld.long 0x14 16.--17. "HCLKRADJ,HCLKRDIV one-shot adjustment" "0,1,2,3"
bitfld.long 0x14 15. "HCLKRM,Receive high-frequency clock source bit" "0,1"
newline
bitfld.long 0x14 14. "HCLKRP,Receive bitstream high-frequency clock polarity select bit" "0,1"
rbitfld.long 0x14 12.--13. "RESERVED87," "0,1,2,3"
newline
hexmask.long.word 0x14 0.--11. 1. "HCLKRDIV,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR"
line.long 0x18 "CFG_RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active"
line.long 0x1C "CFG_RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED90,"
bitfld.long 0x1C 7. "RSTAFRM,Receive start of frame interrupt enable bit" "0,1"
newline
rbitfld.long 0x1C 6. "RESERVED89," "0,1"
bitfld.long 0x1C 5. "RDATA,Receive data ready interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 4. "RLAST,Receive last slot interrupt enable bit" "0,1"
bitfld.long 0x1C 3. "RDMAERR,Receive DMA error interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 2. "RCKFAIL,Receive clock failure interrupt enable bit" "0,1"
bitfld.long 0x1C 1. "RSYNCERR,Unexpected receive frame sync interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 0. "ROVRN,Receiver overrun interrupt enable bit" "0,1"
line.long 0x20 "CFG_RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED91,"
bitfld.long 0x20 8. "RERR,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "0,1"
newline
bitfld.long 0x20 7. "RDMAERR,Receive DMA error flag" "0,1"
bitfld.long 0x20 6. "RSTAFRM,Receive start of frame flag" "0,1"
newline
bitfld.long 0x20 5. "RDATA,Receive data ready flag" "0,1"
bitfld.long 0x20 4. "RLAST,Receive last slot flag" "0,1"
newline
rbitfld.long 0x20 3. "RTDMSLOT,Returns the LSB of RSLOT" "0,1"
bitfld.long 0x20 2. "RCKFAIL,Receive clock failure flag" "0,1"
newline
bitfld.long 0x20 1. "RSYNCERR,Unexpected receive frame sync flag" "0,1"
bitfld.long 0x20 0. "ROVRN,Receiver overrun flag" "0,1"
line.long 0x24 "CFG_RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame"
hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED92,"
hexmask.long.word 0x24 0.--8. 1. "RSLOTCNT,"
line.long 0x28 "CFG_RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "RCNT,Receive clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "RMAX,Receive clock maximum boundary"
newline
hexmask.long.byte 0x28 8.--15. 1. "RMIN,Receive clock minimum boundary"
rbitfld.long 0x28 4.--7. "RESERVED93," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 0.--3. "RPS,Receive clock check prescaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "CFG_PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event"
hexmask.long 0x2C 1.--31. 1. "RESERVED94,"
bitfld.long 0x2C 0. "RDATDMA,Receive data DMA request enable bit" "0,1"
group.long 0xA0++0x2F
line.long 0x00 "CFG_XGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "RESERVED96,"
bitfld.long 0x00 12. "XFRST,Transmit frame sync generator reset enable bit" "0,1"
newline
bitfld.long 0x00 11. "XSMRST,Transmit state machine reset enable bit" "0,1"
bitfld.long 0x00 10. "XSRCLR,Transmit serializer clear enable bit" "0,1"
newline
bitfld.long 0x00 9. "XHCLKRST,Transmit high-frequency clock divider reset enable bit" "0,1"
bitfld.long 0x00 8. "XCLKRST,Transmit clock divider reset enable bit" "0,1"
newline
rbitfld.long 0x00 5.--7. "RESERVED95," "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "RFRST,Receive frame sync generator reset enable bit" "0,1"
newline
rbitfld.long 0x00 3. "RSMRST,Receive state machine reset enable bit" "0,1"
rbitfld.long 0x00 2. "RSRCLR,Receive serializer clear enable bit" "0,1"
newline
rbitfld.long 0x00 1. "RHCLKRST,Receive high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 0. "RCLKRST,Receive clock divider reset enable bit" "0,1"
line.long 0x04 "CFG_XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP"
line.long 0x08 "CFG_XFMT,The transmit bit stream format register (XFMT) configures the transmit data format"
hexmask.long.word 0x08 18.--31. 1. "RESERVED97,"
bitfld.long 0x08 16.--17. "XDATDLY,Transmit sync bit delay" "0,1,2,3"
newline
bitfld.long 0x08 15. "XRVRS,Transmit serial bitstream order" "0,1"
bitfld.long 0x08 13.--14. "XPAD,Pad value for extra bits in slot not belonging to word defined by XMASK" "0,1,2,3"
newline
bitfld.long 0x08 8.--12. "XPBIT,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 4.--7. "XSSZ,Transmit slot size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 3. "XBUSEL,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "0,1"
bitfld.long 0x08 0.--2. "XROT,Right-rotation value for transmit rotate right format unit" "0,1,2,3,4,5,6,7"
line.long 0x0C "CFG_AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED100,"
hexmask.long.word 0x0C 7.--15. 1. "XMOD,Transmit frame sync mode select bits"
newline
rbitfld.long 0x0C 5.--6. "RESERVED99," "0,1,2,3"
bitfld.long 0x0C 4. "FXWID,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period" "0,1"
newline
rbitfld.long 0x0C 2.--3. "RESERVED98," "0,1,2,3"
bitfld.long 0x0C 1. "FSXM,Transmit frame sync generation select bit" "0,1"
newline
bitfld.long 0x0C 0. "FSXP,Transmit frame sync polarity select bit" "0,1"
line.long 0x10 "CFG_ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator"
hexmask.long.word 0x10 21.--31. 1. "RESERVED102,"
bitfld.long 0x10 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1"
newline
bitfld.long 0x10 19. "DIVBUSY,Status: divide ratio change in progress" "0,1"
bitfld.long 0x10 18. "ADJBUSY,Status: one-shot adjustment in progress" "0,1"
newline
bitfld.long 0x10 16.--17. "CLKXADJ,CLKXDIV one-shot adjustment" "0,1,2,3"
hexmask.long.byte 0x10 8.--15. 1. "RESERVED101,"
newline
bitfld.long 0x10 7. "CLKXP,Transmit bitstream clock polarity select bit" "0,1"
bitfld.long 0x10 6. "ASYNC,Transmit/receive operation asynchronous enable bit" "0,1"
newline
bitfld.long 0x10 5. "CLKXM,Transmit bit clock source bit" "0,1"
bitfld.long 0x10 0.--4. "CLKXDIV,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "CFG_AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator"
hexmask.long.word 0x14 21.--31. 1. "RESERVED104,"
bitfld.long 0x14 20. "BUSY,Status: logical OR of DIVBUSY ADJBUSY" "0,1"
newline
bitfld.long 0x14 19. "DIVBUSY,Status: divide ratio change in progress?" "0,1"
bitfld.long 0x14 18. "ADJBUSY,Status: one-shot adjustment in progress?" "0,1"
newline
bitfld.long 0x14 16.--17. "HCLKXADJ,HCLKXDIV one-shot adjustment" "0,1,2,3"
bitfld.long 0x14 15. "HCLKXM,Transmit high-frequency clock source bit" "0,1"
newline
bitfld.long 0x14 14. "HCLKXP,Transmit bitstream high-frequency clock polarity select bit" "0,1"
rbitfld.long 0x14 12.--13. "RESERVED103," "0,1,2,3"
newline
hexmask.long.word 0x14 0.--11. 1. "HCLKXDIV,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX"
line.long 0x18 "CFG_XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active"
line.long 0x1C "CFG_XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED106,"
bitfld.long 0x1C 7. "XSTAFRM,Transmit start of frame interrupt enable bit" "0,1"
newline
rbitfld.long 0x1C 6. "RESERVED105," "0,1"
bitfld.long 0x1C 5. "XDATA,Transmit data ready interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 4. "XLAST,Transmit last slot interrupt enable bit" "0,1"
bitfld.long 0x1C 3. "XDMAERR,Transmit DMA error interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 2. "XCKFAIL,Transmit clock failure interrupt enable bit" "0,1"
bitfld.long 0x1C 1. "XSYNCERR,Unexpected transmit frame sync interrupt enable bit" "0,1"
newline
bitfld.long 0x1C 0. "XUNDRN,Transmitter underrun interrupt enable bit" "0,1"
line.long 0x20 "CFG_XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "RESERVED107,"
bitfld.long 0x20 8. "XERR,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "0,1"
newline
bitfld.long 0x20 7. "XDMAERR,Transmit DMA error flag" "0,1"
bitfld.long 0x20 6. "XSTAFRM,Transmit start of frame flag" "0,1"
newline
bitfld.long 0x20 5. "XDATA,Transmit data ready flag" "0,1"
bitfld.long 0x20 4. "XLAST,Transmit last slot flag" "0,1"
newline
rbitfld.long 0x20 3. "XTDMSLOT,Returns the LSB of XSLOT" "0,1"
bitfld.long 0x20 2. "XCKFAIL,Transmit clock failure flag" "0,1"
newline
bitfld.long 0x20 1. "XSYNCERR,Unexpected transmit frame sync flag" "0,1"
bitfld.long 0x20 0. "XUNDRN,Transmitter underrun flag" "0,1"
line.long 0x24 "CFG_XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame"
hexmask.long.tbyte 0x24 10.--31. 1. "RESERVED108,"
hexmask.long.word 0x24 0.--9. 1. "XSLOTCNT,Current transmit time slot count"
line.long 0x28 "CFG_XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "XCNT,Transmit clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "XMAX,Transmit clock maximum boundary"
newline
hexmask.long.byte 0x28 8.--15. 1. "XMIN,Transmit clock minimum boundary"
rbitfld.long 0x28 4.--7. "RESERVED109," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 0.--3. "XPS,Transmit clock check prescaler value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "CFG_XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event"
hexmask.long 0x2C 1.--31. 1. "RESERVED110,"
bitfld.long 0x2C 0. "XDATDMA,Transmit data DMA request enable bit" "0,1"
group.long 0x100++0x03
line.long 0x00 "CFG_DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot)"
repeat 5. (list 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x104)++0x03
line.long 0x00 "CFG_DITCSRA$1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x118)++0x03
line.long 0x00 "CFG_DITCSRB$1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x130)++0x03
line.long 0x00 "CFG_DITUDRA$1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x148)++0x03
line.long 0x00 "CFG_DITUDRB$1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot)"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x180)++0x03
line.long 0x00 "CFG_SRCTL$1,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x00 6.--31. 1. "RESERVED111,"
rbitfld.long 0x00 5. "RRDY,Receive buffer ready bit" "0,1"
newline
rbitfld.long 0x00 4. "XRDY,Transmit buffer ready bit" "0,1"
bitfld.long 0x00 2.--3. "DISMOD,Serializer pin drive mode bit" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "SRMOD,Serializer mode bit" "0,1,2,3"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "CFG_XBUF$1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "CFG_RBUF$1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit"
repeat.end
group.long 0x1000++0x0F
line.long 0x00 "CFG_WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO"
hexmask.long.word 0x00 17.--31. 1. "RESERVED127,"
bitfld.long 0x00 16. "WENA,Write FIFO enable bit" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "WNUMEVT,Write word count per DMA event [32 bit]"
hexmask.long.byte 0x00 0.--7. 1. "WNUMDMA,Write word count per transfer [32 bit words]"
line.long 0x04 "CFG_WFIFOSTS,"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED128,"
abitfld.long 0x04 0.--7. "WLVL,Write level [read-only]" "0x40=3 to 64 words currently in Write FIFO from..,0xFF=Reserved from 41h to FFh"
line.long 0x08 "CFG_RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO"
hexmask.long.word 0x08 17.--31. 1. "RESERVED129,"
bitfld.long 0x08 16. "RENA,Read FIFO enable bit" "0,1"
newline
abitfld.long 0x08 8.--15. "RNUMEVT,Read word count per DMA event [32 bit]" "0x41=FFh,0xFF=.."
abitfld.long 0x08 0.--7. "RNUMDMA,Read word count per transfer [32 bit words]" "0x10=3 to 16 words from 3h to 10h,0xFF=Reserved from 11h to FFh"
line.long 0x0C "CFG_RFIFOSTS,"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED130,"
abitfld.long 0x0C 0.--7. "RLVL,Read level [read-only]" "0x40=3 to 64 words currently in Read FIFO from..,0xFF=Reserved from 41h to FFh"
tree.end
tree "MCASP2_DMA"
base ad:0x2B28000
tree.end
tree "MCRC64_0_REGS"
base ad:0x30300000
group.long 0x00++0x03
line.long 0x00 "MCRC64_REGS_CRC_CTRL0,CRC Global Control Register 0"
bitfld.long 0x00 24. "CH4_PSA_SWRE,Channel 4 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
newline
bitfld.long 0x00 16. "CH3_PSA_SWRE,Channel 3 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
newline
bitfld.long 0x00 8. "CH2_PSA_SWRE,Channel 2 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
newline
bitfld.long 0x00 0. "CH1_PSA_SWRE,Channel 1 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
group.long 0x08++0x03
line.long 0x00 "MCRC64_REGS_CRC_CTRL1,CRC Global Control Register 1"
bitfld.long 0x00 0. "PWDN,Power Down" "MCRC is not in power down mode,MCRC is in power down mode"
group.long 0x10++0x03
line.long 0x00 "MCRC64_REGS_CRC_CTRL2,Data capture mode is especially useful when it is used in conjunction when data trace (CH1_TRACEEN) for channel 1"
bitfld.long 0x00 24.--25. "CH4_MODE,Channel 4 Mode" "Data Capture mode,AUTO mode,Semi-CPU mode,Full-CPU mode For all four channels the seed.."
newline
bitfld.long 0x00 16.--17. "CH3_MODE,Channel 3 Mode" "Data Capture mode,AUTO mode,Semi-CPU mode,Full-CPU mode"
newline
bitfld.long 0x00 8.--9. "CH2_MODE,Channel 2 Mode" "Data Capture mode,AUTO mode,Semi-CPU mode,Full-CPU mode"
newline
bitfld.long 0x00 4. "CH1_TRACEEN,Channel 1 Data Trace Enable When set the channel is put into data trace mode" "Data Trace disable,Data Trace enable"
newline
bitfld.long 0x00 0.--1. "CH1_MODE,Channel 1 Mode" "Data Capture mode,AUTO mode,Semi-CPU mode,Full-CPU mode"
group.long 0x18++0x03
line.long 0x00 "MCRC64_REGS_CRC_INTS,CRC Interrupt Enable Set Register"
bitfld.long 0x00 28. "CH4_TIME_OUT_ENS_,Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 27. "CH4_UNDERENS,Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 26. "CH4_OVERENS,Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 25. "CH4_CRC_FAILENS,Channel 4 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 24. "CH4_CCITENS,Channel 4 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable"
newline
bitfld.long 0x00 20. "CH3_TIME_OUT_ENS,Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 19. "CH3_UNDERENS,Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 18. "CH3_OVERENS,Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 17. "CH3_CRC_FAILENS,Channel 3 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 16. "CH3_CCITENS,Channel 3 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable"
newline
bitfld.long 0x00 12. "CH2_TIME_OUT_ENS_,Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 9. "CH2_CRC_FAILENS,Channel 2 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 8. "CH2_CCITENS,Channel 2 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable"
newline
bitfld.long 0x00 4. "CH1_TIME_OUT_ENS_,Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 1. "CH1_CRC_FAILENS,Channel 1 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 0. "CH1_CCITENS,Channel 1 Compression Complete Interrupt Enable Bit" "Has no effect,Compression Complete Interrupt enable"
group.long 0x20++0x03
line.long 0x00 "MCRC64_REGS_CRC_INTR,CRC Interrupt Enable Reset Register"
bitfld.long 0x00 28. "CH4_TIME_OUT_ENR,Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 27. "CH4_UNDERENR,Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 26. "CH4_OVERENR,Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 25. "CH4_CRC_FAILENR,Channel 4 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 24. "CH4_CCITENR,Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable"
newline
bitfld.long 0x00 20. "CH3_TIME_OUT_ENR_,Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 19. "CH3_UNDERENR,Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 18. "CH3_OVERENR,Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 17. "CH3_CRC_FAILENR,Channel 3 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 16. "CH3_CCITENR,Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable"
newline
bitfld.long 0x00 12. "CH2_TIME_OUT_ENR_,Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 9. "CH2_CRC_FAILENR,Channel 2 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 8. "CH2_CCITENR,Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable"
newline
bitfld.long 0x00 4. "CH1_TIME_OUT_ENR_,Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 1. "CH1_CRC_FAILENR,Channel 1 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
bitfld.long 0x00 0. "CH1_CCITENR,Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt" "Has no effect,Compression Complete Interrupt disable"
group.long 0x28++0x03
line.long 0x00 "MCRC64_REGS_CRC_STATUS,CRC Interrupt Status Register"
bitfld.long 0x00 28. "CH4_TIME_OUT,Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active"
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bitfld.long 0x00 27. "CH4_UNDER,Channel 4 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 26. "CH4_OVER,Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 25. "CH4_CRC_FAIL,Channel 4 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
bitfld.long 0x00 24. "CH4_CCIT,Channel 4 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.."
newline
bitfld.long 0x00 20. "CH3_TIME_OUT,Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 19. "CH3_UNDER,Channel 3 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 18. "CH3_OVER,Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 17. "CH3_CRC_FAIL,Channel 3 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
bitfld.long 0x00 16. "CH3_CCIT,Channel 3 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.."
newline
bitfld.long 0x00 12. "CH2_TIME_OUT,Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 9. "CH2_CRC_FAIL,Channel 2 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
bitfld.long 0x00 8. "CH2_CCIT,Channel 2 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.."
newline
bitfld.long 0x00 4. "CH1_TIME_OUT,Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 1. "CH1_CRC_FAIL,Channel 1 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
bitfld.long 0x00 0. "CH1_CCIT,Channel 1 CRC Pattern Compression Complete Status Flag" "No CRC pattern compression complete interrupt is..,CRC pattern compression complete interrupt is.."
rgroup.long 0x30++0x03
line.long 0x00 "MCRC64_REGS_CRC_INT_OFFSET_REG,CRC Interrupt Offset"
hexmask.long.byte 0x00 0.--7. 1. "CRC,Interrupt Offset"
rgroup.long 0x38++0x03
line.long 0x00 "MCRC64_REGS_CRC_BUSY,CRC Busy Register"
bitfld.long 0x00 24. "CH4_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed" "0,1"
newline
bitfld.long 0x00 16. "CH3_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed" "0,1"
newline
bitfld.long 0x00 8. "CH2_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed" "0,1"
newline
bitfld.long 0x00 0. "CH1_BUSY,During AUTO or Semi-CPU mode the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed" "0,1"
group.long 0x40++0x13
line.long 0x00 "MCRC64_REGS_CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register1"
hexmask.long.tbyte 0x00 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register"
line.long 0x04 "MCRC64_REGS_CRC_SCOUNT_REG1,CRC Sector Counter Preload Register1"
hexmask.long.word 0x04 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register"
line.long 0x08 "MCRC64_REGS_CRC_CURSEC_REG1,CRC Current Sector Register 1"
hexmask.long.word 0x08 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register"
line.long 0x0C "MCRC64_REGS_CRC_WDTOPLD1,CRC channel 1 Watchdog Timeout Preload Register A"
hexmask.long.tbyte 0x0C 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register"
line.long 0x10 "MCRC64_REGS_CRC_BCTOPLD1,CRC channel 1 Block Complete Timeout Preload Register B"
hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Register"
group.long 0x60++0x33
line.long 0x00 "MCRC64_REGS_PSA_SIGREGL1,Channel 1 PSA signature low register"
line.long 0x04 "MCRC64_REGS_PSA_SIGREGH1,Channel 1 PSA signature high register"
line.long 0x08 "MCRC64_REGS_CRC_REGL1,Channel 1 CRC value low register"
line.long 0x0C "MCRC64_REGS_CRC_REGH1,Channel 1 CRC value high register"
line.long 0x10 "MCRC64_REGS_PSA_SECSIGREGL1,Channel 1 PSA sector signature low register"
line.long 0x14 "MCRC64_REGS_PSA_SECSIGREGH1,Channel 1 PSA sector signature high register"
line.long 0x18 "MCRC64_REGS_RAW_DATAREGL1,Channel 1 Raw Data Low Register"
line.long 0x1C "MCRC64_REGS_RAW_DATAREGH1,Channel 1 Raw Data High Register"
line.long 0x20 "MCRC64_REGS_CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register2"
hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT2,CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed"
line.long 0x24 "MCRC64_REGS_CRC_SCOUNT_REG2,CRC Sector Counter Preload Register2"
hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register"
line.long 0x28 "MCRC64_REGS_CRC_CURSEC_REG2,CRC Current Sector Register 2"
hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register"
line.long 0x2C "MCRC64_REGS_CRC_WDTOPLD2,CRC channel 2 Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register"
line.long 0x30 "MCRC64_REGS_CRC_BCTOPLD2,CRC channel 2 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Register"
group.long 0xA0++0x33
line.long 0x00 "MCRC64_REGS_PSA_SIGREGL2,Channel 2 PSA signature low register"
line.long 0x04 "MCRC64_REGS_PSA_SIGREGH2,Channel 2 PSA signature high register"
line.long 0x08 "MCRC64_REGS_CRC_REGL2,Channel 2 CRC value low register"
line.long 0x0C "MCRC64_REGS_CRC_REGH2,Channel 2 CRC value high register"
line.long 0x10 "MCRC64_REGS_PSA_SECSIGREGL2,Channel 2 PSA sector signature low register"
line.long 0x14 "MCRC64_REGS_PSA_SECSIGREGH2,Channel 2 PSA sector signature high register"
line.long 0x18 "MCRC64_REGS_RAW_DATAREGL2,Channel 2 Raw Data Low Register"
line.long 0x1C "MCRC64_REGS_RAW_DATAREGH2,Channel 2 Raw Data High Register"
line.long 0x20 "MCRC64_REGS_CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register3"
hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT3,Channel 3 Pattern Counter Preload Register"
line.long 0x24 "MCRC64_REGS_CRC_SCOUNT_REG3,CRC Sector Counter Preload Register3"
hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT3,Channel 3 Sector Counter Preload Register"
line.long 0x28 "MCRC64_REGS_CRC_CURSEC_REG3,CRC Current Sector Register 3"
hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC3,Channel 3 Current Sector ID Register"
line.long 0x2C "MCRC64_REGS_CRC_WDTOPLD3,CRC channel 3 Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD3,Channel 3 Watchdog Timeout Counter Preload Register"
line.long 0x30 "MCRC64_REGS_CRC_BCTOPLD3,CRC channel 3 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD3,Channel 3 Block Complete Timeout Counter Preload Register"
group.long 0xE0++0x33
line.long 0x00 "MCRC64_REGS_PSA_SIGREGL3,Channel 3 PSA signature low register"
line.long 0x04 "MCRC64_REGS_PSA_SIGREGH3,Channel 3 PSA signature high register"
line.long 0x08 "MCRC64_REGS_CRC_REGL3,Channel 3 CRC value low register"
line.long 0x0C "MCRC64_REGS_CRC_REGH3,Channel 3 CRC value high register"
line.long 0x10 "MCRC64_REGS_PSA_SECSIGREGL3,Channel 3 PSA sector signature low register"
line.long 0x14 "MCRC64_REGS_PSA_SECSIGREGH3,Channel 3 PSA sector signature high register"
line.long 0x18 "MCRC64_REGS_RAW_DATAREGL3,Channel 3 Raw Data Low Register"
line.long 0x1C "MCRC64_REGS_RAW_DATAREGH3,Channel 3 Raw Data High Register"
line.long 0x20 "MCRC64_REGS_CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register4"
hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT4,Channel 4 Pattern Counter Preload Register"
line.long 0x24 "MCRC64_REGS_CRC_SCOUNT_REG4,CRC Sector Counter Preload Register4"
hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT4,Channel 4 Sector Counter Preload Register"
line.long 0x28 "MCRC64_REGS_CRC_CURSEC_REG4,CRC Current Sector Register 4"
hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC4,In AUTO mode this register contains the current sector number of which the signature verification fails"
line.long 0x2C "MCRC64_REGS_CRC_WDTOPLD4,CRC channel 4 Watchdog Timeout Preload Register"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD4,This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns"
line.long 0x30 "MCRC64_REGS_CRC_BCTOPLD4,CRC channel 4 Block Complete Timeout Preload Register"
hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD4,This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated"
group.long 0x120++0x23
line.long 0x00 "MCRC64_REGS_PSA_SIGREGL4,Channel 4 PSA signature low register"
line.long 0x04 "MCRC64_REGS_PSA_SIGREGH4,Channel 4 PSA signature high register"
line.long 0x08 "MCRC64_REGS_CRC_REGL4,Channel 4 CRC value low register"
line.long 0x0C "MCRC64_REGS_CRC_REGH4,Channel 4 CRC value high register"
line.long 0x10 "MCRC64_REGS_PSA_SECSIGREGL4,Channel 4 PSA sector signature low register"
line.long 0x14 "MCRC64_REGS_PSA_SECSIGREGH4,Channel 4 PSA sector signature high register"
line.long 0x18 "MCRC64_REGS_RAW_DATAREGL4,Channel 4 Raw Data Low Register"
line.long 0x1C "MCRC64_REGS_RAW_DATAREGH4,Channel 4 Raw Data High Register"
line.long 0x20 "MCRC64_REGS_MCRC_BUS_SEL,Data bus tracing selection"
bitfld.long 0x20 2. "MEN,Enable/disables the tracing of VBUSM" "Tracing of VBUSM master bus has been disabled,Tracing of VBUSM master bus has been enabled"
newline
bitfld.long 0x20 1. "DTC_MEN,Enable/disables the tracing of data TCM" "Tracing of DTCM_ODD and DTCM_EVEN buses have..,Tracing of DTCM_ODD and DTCM_EVEN buses have.."
newline
bitfld.long 0x20 0. "ITC_MEN,Enable/disables the tracing of instruction TCM" "Tracing of ITCM bus has been disabled,Tracing of ITCM bus has been enabled Please.."
group.long 0x200++0x03
line.long 0x00 "MCRC64_REGS_I0_PSA_SIGREG1_CPY,Region for Channel 1 PSA signature block used by DMA based systems"
group.long 0x280++0x03
line.long 0x00 "MCRC64_REGS_I0_PSA_SIGREG2_CPY,Region for Channel 2 PSA signature block used by DMA based systems"
group.long 0x300++0x03
line.long 0x00 "MCRC64_REGS_I0_PSA_SIGREG3_CPY,Region for Channel 3 PSA signature block used by DMA based systems"
group.long 0x380++0x03
line.long 0x00 "MCRC64_REGS_I0_PSA_SIGREG4_CPY,Region for Channel 4 PSA signature block used by DMA based systems"
tree.end
tree "MCSPI0_CFG"
base ad:0x20100000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned"
bitfld.long 0x00 11.--15. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e"
hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored"
bitfld.long 0x04 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1"
group.long 0x10++0x03
line.long 0x00 "CFG_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3"
bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset [Optional]" "0,1"
rgroup.long 0x100++0x03
line.long 0x00 "CFG_REVISION,This register contains the hard coded RTL revision number"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_13,Reads returns 0"
hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21"
group.long 0x110++0x73
line.long 0x00 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface"
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED_14,Reads returns 0"
bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3"
rbitfld.long 0x00 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,WakeUp feature control" "0,1"
newline
bitfld.long 0x00 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1"
line.long 0x04 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0"
rbitfld.long 0x04 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x08 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1"
bitfld.long 0x08 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x08 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1"
newline
bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1"
bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1"
bitfld.long 0x08 11. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1"
bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1"
newline
bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1"
bitfld.long 0x08 7. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1"
bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1"
bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1"
newline
bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1"
bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1"
bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1"
bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1"
line.long 0x0C "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis"
hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reads return 0"
bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1"
bitfld.long 0x0C 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x0C 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1"
newline
bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1"
bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1"
bitfld.long 0x0C 11. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1"
newline
bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 7. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1"
newline
bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1"
line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis"
hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0"
bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode"
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x14 11. "SSB,Set status bit" "0,1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1"
bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1"
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bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1"
bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the CLKSPI.." "0,1"
bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface"
hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1"
bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1"
bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1"
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bitfld.long 0x18 2. "MS,Master/ Slave" "0,1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1"
bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1"
line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0"
bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x1C 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1"
line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0"
hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0"
hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EN,Channel Enable" "0,1"
line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x2C "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x30 "CFG_CH1CONF,This register is dedicated to the configuration of the channel"
bitfld.long 0x30 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x30 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x30 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x30 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x30 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x30 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x30 18. "IS,Input Select" "0,1"
bitfld.long 0x30 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x30 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x30 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x30 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x30 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x30 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x30 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x30 0. "PHA,SPICLK phase" "0,1"
line.long 0x34 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1"
hexmask.long 0x34 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x34 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x34 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x34 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x34 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x34 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x34 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x34 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x38 "CFG_CH1CTRL,This register is dedicated to enable the channel 1"
hexmask.long.word 0x38 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x38 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x38 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x38 0. "EN,Channel Enable" "0,1"
line.long 0x3C "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x40 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x44 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2"
bitfld.long 0x44 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x44 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x44 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x44 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x44 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x44 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x44 18. "IS,Input Select" "0,1"
bitfld.long 0x44 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x44 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x44 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x44 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x44 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x44 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x44 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x44 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x44 0. "PHA,SPICLK phase" "0,1"
line.long 0x48 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2"
hexmask.long 0x48 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x48 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x48 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x48 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x48 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x48 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x48 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x48 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x4C "CFG_CH2CTRL,This register is dedicated to enable the channel 2"
hexmask.long.word 0x4C 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x4C 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x4C 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x4C 0. "EN,Channel Enable" "0,1"
line.long 0x50 "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x54 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x58 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3"
bitfld.long 0x58 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x58 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x58 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x58 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x58 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x58 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x58 18. "IS,Input Select" "0,1"
bitfld.long 0x58 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x58 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x58 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x58 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x58 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x58 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x58 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x58 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x58 0. "PHA,SPICLK phase" "0,1"
line.long 0x5C "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3"
hexmask.long 0x5C 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x5C 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x5C 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x5C 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x5C 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x5C 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x5C 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x5C 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x60 "CFG_CH3CTRL,This register is dedicated to enable the channel 3"
hexmask.long.word 0x60 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x60 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x60 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x60 0. "EN,Channel Enable" "0,1"
line.long 0x64 "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x68 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x6C "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer"
hexmask.long.word 0x6C 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index"
hexmask.long.byte 0x6C 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.."
hexmask.long.byte 0x6C 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.."
line.long 0x70 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled"
rgroup.long 0x1A0++0x03
line.long 0x00 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled"
tree.end
tree "MCSPI1_CFG"
base ad:0x20110000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned"
bitfld.long 0x00 11.--15. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e"
hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored"
bitfld.long 0x04 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1"
group.long 0x10++0x03
line.long 0x00 "CFG_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3"
bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset [Optional]" "0,1"
rgroup.long 0x100++0x03
line.long 0x00 "CFG_REVISION,This register contains the hard coded RTL revision number"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_13,Reads returns 0"
hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21"
group.long 0x110++0x73
line.long 0x00 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface"
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED_14,Reads returns 0"
bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3"
rbitfld.long 0x00 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,WakeUp feature control" "0,1"
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bitfld.long 0x00 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1"
line.long 0x04 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0"
rbitfld.long 0x04 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x08 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1"
bitfld.long 0x08 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x08 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1"
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bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1"
bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1"
bitfld.long 0x08 11. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1"
bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1"
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bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1"
bitfld.long 0x08 7. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1"
bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1"
bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1"
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bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1"
bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1"
bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1"
bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1"
line.long 0x0C "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis"
hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reads return 0"
bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1"
bitfld.long 0x0C 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x0C 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1"
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bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1"
bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1"
bitfld.long 0x0C 11. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1"
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bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 7. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1"
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bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1"
line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis"
hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0"
bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode"
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x14 11. "SSB,Set status bit" "0,1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1"
bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1"
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bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1"
bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the CLKSPI.." "0,1"
bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface"
hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1"
bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1"
bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1"
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bitfld.long 0x18 2. "MS,Master/ Slave" "0,1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1"
bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1"
line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0"
bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x1C 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1"
line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0"
hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0"
hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EN,Channel Enable" "0,1"
line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x2C "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x30 "CFG_CH1CONF,This register is dedicated to the configuration of the channel"
bitfld.long 0x30 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x30 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x30 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x30 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x30 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x30 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x30 18. "IS,Input Select" "0,1"
bitfld.long 0x30 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x30 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x30 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x30 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x30 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x30 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x30 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x30 0. "PHA,SPICLK phase" "0,1"
line.long 0x34 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1"
hexmask.long 0x34 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x34 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x34 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x34 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x34 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x34 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x34 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x34 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x38 "CFG_CH1CTRL,This register is dedicated to enable the channel 1"
hexmask.long.word 0x38 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x38 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x38 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x38 0. "EN,Channel Enable" "0,1"
line.long 0x3C "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x40 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x44 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2"
bitfld.long 0x44 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x44 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x44 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x44 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x44 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x44 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x44 18. "IS,Input Select" "0,1"
bitfld.long 0x44 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x44 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x44 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x44 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x44 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x44 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x44 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x44 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x44 0. "PHA,SPICLK phase" "0,1"
line.long 0x48 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2"
hexmask.long 0x48 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x48 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x48 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x48 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x48 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x48 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x48 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x48 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x4C "CFG_CH2CTRL,This register is dedicated to enable the channel 2"
hexmask.long.word 0x4C 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x4C 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x4C 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x4C 0. "EN,Channel Enable" "0,1"
line.long 0x50 "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x54 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x58 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3"
bitfld.long 0x58 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x58 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x58 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x58 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x58 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x58 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x58 18. "IS,Input Select" "0,1"
bitfld.long 0x58 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x58 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x58 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x58 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x58 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x58 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x58 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x58 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x58 0. "PHA,SPICLK phase" "0,1"
line.long 0x5C "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3"
hexmask.long 0x5C 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x5C 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x5C 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x5C 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x5C 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x5C 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x5C 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x5C 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x60 "CFG_CH3CTRL,This register is dedicated to enable the channel 3"
hexmask.long.word 0x60 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x60 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x60 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x60 0. "EN,Channel Enable" "0,1"
line.long 0x64 "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x68 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x6C "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer"
hexmask.long.word 0x6C 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index"
hexmask.long.byte 0x6C 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.."
hexmask.long.byte 0x6C 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.."
line.long 0x70 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled"
rgroup.long 0x1A0++0x03
line.long 0x00 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled"
tree.end
tree "MCSPI2_CFG"
base ad:0x20120000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned"
bitfld.long 0x00 11.--15. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e"
hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored"
bitfld.long 0x04 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1"
group.long 0x10++0x03
line.long 0x00 "CFG_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3"
bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset [Optional]" "0,1"
rgroup.long 0x100++0x03
line.long 0x00 "CFG_REVISION,This register contains the hard coded RTL revision number"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_13,Reads returns 0"
hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21"
group.long 0x110++0x73
line.long 0x00 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface"
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED_14,Reads returns 0"
bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3"
rbitfld.long 0x00 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,WakeUp feature control" "0,1"
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bitfld.long 0x00 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1"
line.long 0x04 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0"
rbitfld.long 0x04 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x08 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1"
bitfld.long 0x08 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x08 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1"
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bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1"
bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1"
bitfld.long 0x08 11. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1"
bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1"
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bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1"
bitfld.long 0x08 7. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1"
bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1"
bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1"
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bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1"
bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1"
bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1"
bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1"
line.long 0x0C "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis"
hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reads return 0"
bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1"
bitfld.long 0x0C 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x0C 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1"
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bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1"
bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1"
bitfld.long 0x0C 11. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1"
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bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 7. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1"
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bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1"
line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis"
hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0"
bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode"
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x14 11. "SSB,Set status bit" "0,1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1"
bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1"
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bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1"
bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the CLKSPI.." "0,1"
bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface"
hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1"
bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1"
bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1"
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bitfld.long 0x18 2. "MS,Master/ Slave" "0,1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1"
bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1"
line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0"
bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
newline
bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x1C 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1"
newline
bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1"
line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0"
hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
newline
rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0"
hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EN,Channel Enable" "0,1"
line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x2C "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x30 "CFG_CH1CONF,This register is dedicated to the configuration of the channel"
bitfld.long 0x30 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x30 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
newline
bitfld.long 0x30 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x30 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x30 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x30 19. "TURBO,Turbo mode" "0,1"
newline
bitfld.long 0x30 18. "IS,Input Select" "0,1"
bitfld.long 0x30 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x30 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x30 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x30 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
newline
bitfld.long 0x30 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x30 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x30 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 1. "POL,SPICLK polarity" "0,1"
newline
bitfld.long 0x30 0. "PHA,SPICLK phase" "0,1"
line.long 0x34 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1"
hexmask.long 0x34 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x34 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x34 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x34 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x34 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
newline
rbitfld.long 0x34 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x34 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x34 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x38 "CFG_CH1CTRL,This register is dedicated to enable the channel 1"
hexmask.long.word 0x38 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x38 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x38 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x38 0. "EN,Channel Enable" "0,1"
line.long 0x3C "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x40 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x44 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2"
bitfld.long 0x44 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x44 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
newline
bitfld.long 0x44 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x44 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x44 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x44 19. "TURBO,Turbo mode" "0,1"
newline
bitfld.long 0x44 18. "IS,Input Select" "0,1"
bitfld.long 0x44 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x44 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x44 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x44 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
newline
bitfld.long 0x44 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x44 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x44 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x44 1. "POL,SPICLK polarity" "0,1"
newline
bitfld.long 0x44 0. "PHA,SPICLK phase" "0,1"
line.long 0x48 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2"
hexmask.long 0x48 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x48 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x48 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x48 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x48 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
newline
rbitfld.long 0x48 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x48 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x48 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x4C "CFG_CH2CTRL,This register is dedicated to enable the channel 2"
hexmask.long.word 0x4C 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x4C 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x4C 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x4C 0. "EN,Channel Enable" "0,1"
line.long 0x50 "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x54 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x58 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3"
bitfld.long 0x58 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x58 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
newline
bitfld.long 0x58 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x58 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x58 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x58 19. "TURBO,Turbo mode" "0,1"
newline
bitfld.long 0x58 18. "IS,Input Select" "0,1"
bitfld.long 0x58 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x58 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x58 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x58 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
newline
bitfld.long 0x58 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x58 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x58 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x58 1. "POL,SPICLK polarity" "0,1"
newline
bitfld.long 0x58 0. "PHA,SPICLK phase" "0,1"
line.long 0x5C "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3"
hexmask.long 0x5C 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x5C 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x5C 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x5C 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x5C 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
newline
rbitfld.long 0x5C 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x5C 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x5C 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x60 "CFG_CH3CTRL,This register is dedicated to enable the channel 3"
hexmask.long.word 0x60 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x60 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x60 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x60 0. "EN,Channel Enable" "0,1"
line.long 0x64 "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x68 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x6C "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer"
hexmask.long.word 0x6C 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index"
hexmask.long.byte 0x6C 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.."
hexmask.long.byte 0x6C 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.."
line.long 0x70 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled"
rgroup.long 0x1A0++0x03
line.long 0x00 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled"
tree.end
tree "MCU_CBASS0_ERR"
base ad:0x4720000
rgroup.long 0x00++0x07
line.long 0x00 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "MCU_CBASS0_GLB"
base ad:0x45B02000
rgroup.long 0x00++0x03
line.long 0x00 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "MCU_CBASS0_ISC"
base ad:0x45818000
group.long 0x00++0x03
line.long 0x00 "ISC_REGS_Iblazar_mcu_0_vbusp_m_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Iblazar_mcu_0.vbusp_m region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x13
line.long 0x00 "ISC_REGS_Iblazar_mcu_0_vbusp_m_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Iblazar_mcu_0.vbusp_m region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Iblazar_mcu_0_vbusp_m_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Iblazar_mcu_0.vbusp_m region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Iblazar_mcu_0_vbusp_m_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Iblazar_mcu_0.vbusp_m region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Iblazar_mcu_0_vbusp_m_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Iblazar_mcu_0.vbusp_m region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Iblazar_mcu_0_vbusp_m_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Iblazar_mcu_0.vbusp_m region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
newline
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
newline
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "MCU_CBASS0_QOS"
base ad:0x45D18000
group.long 0x100++0x03
line.long 0x00 "QOS_REGS_Iblazar_mcu_0_vbusp_m_map0,The Map Register defines the fields for the master Iblazar_mcu_0.vbusp_m per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
tree.end
tree "MCU_DCC0"
base ad:0x4C00000
group.long 0x00++0x37
line.long 0x00 "CFG_DCCGCTRL,Starts / stops the counters"
bitfld.long 0x00 12.--15. "DONEENA,The DONEENA bit enables/disables the done interrupt signal but has no effect on the done status flag in DCCSTAT register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "SINGLESHOT,The SINGLESHOT bit enables/disables repetitive operation of the DCC" "?,?,?,?,?,?,?,?,?,?,stop counting when counter0 and valid0 both..,stop counting when counter1 reaches zero others..,?..."
newline
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CFG_DCCREV,Specifies the module version"
bitfld.long 0x04 30.--31. "SCHEME,User privilege and debug mode (read): Returns 01" "0,1,2,3"
hexmask.long.word 0x04 16.--27. 1. "FUNC,Reflects software-compatability"
newline
bitfld.long 0x04 11.--15. "RTL,Incremented for releases due to spec changes or post-release design changes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--10. "MAJOR,Represents major changes to the module (e.g. entirely new features are added/changed)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 6.--7. "CUSTOM,Indicates a special version of the module" "0,1,2,3"
bitfld.long 0x04 0.--5. "MINOR,Represents minor changes to the module (e.g. enhancements to existing features)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CFG_DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,This field contains the seed value that gets loaded into counter 0 (clock source 0)"
line.long 0x0C "CFG_DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,This field contains the seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "CFG_DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,This field contains the seed value that gets loaded into counter 1 (clock source 1)"
line.long 0x14 "CFG_DCCSTAT,Specifies the status of the DCC Module"
bitfld.long 0x14 1. "DONEFLG,Indicates when single-shot mode is complete without error" "no effect,clear the done flag"
bitfld.long 0x14 0. "ERRFLG,Indicates whether or not an error has occured" "no effect,clear the error flag"
line.long 0x18 "CFG_DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "CFG_DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "CFG_DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "CFG_DCCCLKSRC1,Selects the clock source for counter 1"
bitfld.long 0x24 12.--15. "KEY,This field enables or disables clock source selection for counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 0.--4. "CLKSRC1,This field specifies the clock source for counter 1 when the KEY field enables this feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x28 "CFG_DCCCLKSRC0,Selects the clock source for counter 0"
bitfld.long 0x28 12.--15. "KEY,This field enables or disables clock source selection for counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 0.--3. "CLKSRC0,This field specifies the clock source for counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "CFG_DCCGCTRL2,Allows configuring different modes of operation for DCC"
bitfld.long 0x2C 8.--11. "FIFO_NONERR,Enables/disables FIFO writes without the error event on completion of comparison window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x2C 4.--7. "FIFO_READ,Enables the counter read registers reflect FIFO output instead of the live counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x2C 0.--3. "CONT_ON_ERR,Continues to next window of comparison despite the error condition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "CFG_DCCSTATUS2,Specifies the status of the DCC FIFOs"
bitfld.long 0x30 5. "COUNT1_FIFO_FULL,Count1 FIFO Full" "Count1 FIFO is not full,Count1 FIFO is full"
bitfld.long 0x30 4. "VALID0_FIFO_FULL,Valid0 FIFO Full" "Valid0 FIFO is not full,Valid0 FIFO is full"
newline
bitfld.long 0x30 3. "COUNT0_FIFO_FULL,Count0 FIFO Full" "Count0 FIFO is not full,Count0 FIFO is full"
bitfld.long 0x30 2. "COUNT1_FIFO_EMPTY,Count1 FIFO Empty" "Count1 FIFO is not empty,Count1 FIFO is empty"
newline
bitfld.long 0x30 1. "VALID0_FIFO_EMPTY,Valid0 FIFO Empty" "Valid0 FIFO is not empty,Valid0 FIFO is empty"
bitfld.long 0x30 0. "COUNT0_FIFO_EMPTY,Count0 FIFO Empty" "Count0 FIFO is not empty,Count0 FIFO is empty"
line.long 0x34 "CFG_DCCERRCNT,Counts number of errors since last clear"
hexmask.long.word 0x34 0.--9. 1. "ERRCNT,Counts the number of errors after the last write to this register or reset"
tree.end
tree "MCU_GPIO0"
base ad:0x4201000
rgroup.long 0x00++0x0B
line.long 0x00 "MEM_pid,GPIO Periperal ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Current scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function code assigned to TCP3"
bitfld.long 0x00 11.--15. "RTL,RTL Version R code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version code" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision Y code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MEM_PCR,Peripheral Control Register"
bitfld.long 0x04 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1"
bitfld.long 0x04 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend" "0,1"
line.long 0x08 "MEM_BINTEN,Bit Interrupt Enable Register"
abitfld.long 0x08 0.--15. "EN,Per bank interrupt enable" "0x0000=disable,0x0001=enable"
group.long 0x10++0x0B
line.long 0x00 "MEM_DIR01,Direction Register"
abitfld.long 0x00 16.--31. "DIR1,Direction of GPIO bank 1 bits " "0x0000=output,0x0001=input"
abitfld.long 0x00 0.--15. "DIR0,Direction of GPIO bank 0 bits " "0x0000=output,0x0001=input"
line.long 0x04 "MEM_OUT_DATA01,Output Drive State Register"
hexmask.long.word 0x04 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x04 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x08 "MEM_SET_DATA01,Set Output Drive State Register"
hexmask.long.word 0x08 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state"
hexmask.long.word 0x08 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state"
repeat 4. (list 01. 23. 45. 67. )(list 0x00 0x28 0x50 0x78 )
group.long ($2+0x1C)++0x03
line.long 0x00 "MEM_CLR_DATA$1,Clear Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
repeat.end
rgroup.long 0x20++0x23
line.long 0x00 "MEM_IN_DATA01,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN1,Status of GPIO bank 1 bits"
hexmask.long.word 0x00 0.--15. 1. "IN0,Status of GPIO bank 0 bits"
line.long 0x04 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits"
line.long 0x0C "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits"
line.long 0x14 "MEM_INTSTAT01,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT1,Status of GPIO bank 0 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT0,Status of GPIO bank 0 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR23,Direction Register"
abitfld.long 0x18 16.--31. "DIR3,Direction of GPIO bank 3 bits " "0x0000=output,0x0001=input"
abitfld.long 0x18 0.--15. "DIR2,Direction of GPIO bank 2 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA23,Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA23,Set Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state"
rgroup.long 0x48++0x23
line.long 0x00 "MEM_IN_DATA23,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN3,Status of GPIO bank 3 bits"
hexmask.long.word 0x00 0.--15. 1. "IN2,Status of GPIO bank 2 bits"
line.long 0x04 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits"
line.long 0x0C "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits"
line.long 0x14 "MEM_INTSTAT23,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT3,Status of GPIO bank 2 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT2,Status of GPIO bank 2 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR45,Direction Register"
abitfld.long 0x18 16.--31. "DIR5,Direction of GPIO bank 5 bits " "0x0000=output,0x0001=input"
abitfld.long 0x18 0.--15. "DIR4,Direction of GPIO bank 4 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA45,Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA45,Set Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state"
rgroup.long 0x70++0x23
line.long 0x00 "MEM_IN_DATA45,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN5,Status of GPIO bank 5 bits"
hexmask.long.word 0x00 0.--15. 1. "IN4,Status of GPIO bank 4 bits"
line.long 0x04 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits"
line.long 0x0C "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits"
line.long 0x14 "MEM_INTSTAT45,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT5,Status of GPIO bank 4 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT4,Status of GPIO bank 4 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR67,Direction Register"
abitfld.long 0x18 16.--31. "DIR7,Direction of GPIO bank 7 bits " "0x0000=output,0x0001=input"
abitfld.long 0x18 0.--15. "DIR6,Direction of GPIO bank 6 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA67,Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA67,Set Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state"
rgroup.long 0x98++0x3F
line.long 0x00 "MEM_IN_DATA67,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN7,Status of GPIO bank 7 bits"
hexmask.long.word 0x00 0.--15. 1. "IN6,Status of GPIO bank 6 bits"
line.long 0x04 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits"
line.long 0x0C "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits"
line.long 0x14 "MEM_INTSTAT67,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT7,Status of GPIO bank 6 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT6,Status of GPIO bank 6 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR8,Direction Register"
abitfld.long 0x18 0.--15. "DIR8,Direction of GPIO bank 8 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA8,Output Drive State Register"
hexmask.long.word 0x1C 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA8,Set Output Drive State Register"
hexmask.long.word 0x20 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state"
line.long 0x24 "MEM_CLR_DATA8,Clear Output Drive State Register"
hexmask.long.word 0x24 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
line.long 0x28 "MEM_IN_DATA8,Bank Status Register"
hexmask.long.word 0x28 0.--15. 1. "IN8,Status of GPIO bank 8 bits"
line.long 0x2C "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register"
hexmask.long.word 0x2C 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits"
line.long 0x30 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register"
hexmask.long.word 0x30 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits"
line.long 0x34 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register"
hexmask.long.word 0x34 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits"
line.long 0x38 "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register"
hexmask.long.word 0x38 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits"
line.long 0x3C "MEM_INTSTAT8,Bank Interrupt Status Register"
abitfld.long 0x3C 0.--15. "STAT8,Status of GPIO bank 8 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
tree.end
tree "MCU_I2C0_CFG"
base ad:0x4900000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x04 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x04 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x00 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
newline
bitfld.long 0x00 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Autoidle bit" "0,1"
group.long 0x20++0x2F
line.long 0x00 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
line.long 0x04 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x08 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x08 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x08 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x08 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x08 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x08 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x08 8. "BF,Bus Free IRQ enabled status" "0,1"
newline
bitfld.long 0x08 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x08 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x08 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x08 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x08 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x0C "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector"
bitfld.long 0x0C 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0C 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0C 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0C 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x0C 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0C 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0C 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0C 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x0C 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0C 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0C 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0C 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x0C 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0C 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0C 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector"
bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1"
newline
bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x14 "CFG_I2C_WE,I2C wakeup enable vector (legacy)"
bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x18 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set"
bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set"
bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x20 "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear"
bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear"
bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x28 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable"
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x2C "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable"
bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x07
line.long 0x00 "CFG_I2C_IE,I2C interrupt enable vector (legacy)"
bitfld.long 0x00 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x00 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x00 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x00 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x00 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x00 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x00 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x00 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x00 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x00 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x00 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x00 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x00 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x00 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x00 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x04 "CFG_I2C_STAT,I2C interrupt status vector (legacy)"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
rgroup.long 0x90++0x0F
line.long 0x00 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x00 0. "RDONE,Reset done bit" "0,1"
line.long 0x04 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x04 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x04 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
bitfld.long 0x04 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
newline
bitfld.long 0x04 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
bitfld.long 0x04 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x08 0.--15. 1. "DCOUNT,Data count"
line.long 0x0C "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x0C 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x33
line.long 0x00 "CFG_I2C_CON,I2C configuration register"
bitfld.long 0x00 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x00 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x00 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x00 10. "MST,Master/slave mode" "0,1"
newline
bitfld.long 0x00 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x00 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x00 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x00 6. "XOA1,Expand Own address 1" "0,1"
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bitfld.long 0x00 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x00 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x00 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x00 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x04 "CFG_I2C_OA,Own address register"
bitfld.long 0x04 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "OA,Own address"
line.long 0x08 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x08 0.--9. 1. "SA,Slave address"
line.long 0x0C "CFG_I2C_PSC,I2C Clock Prescaler Register"
abitfld.long 0x0C 0.--7. "PSC,Fast/Standard mode prescale sampling clock divider value" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
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rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
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bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
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bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
line.long 0x1C "CFG_I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x1C 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
bitfld.long 0x1C 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1C 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x20 0.--9. 1. "OA1,Own address 1"
line.long 0x24 "CFG_I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x24 0.--9. 1. "OA2,Own address 2"
line.long 0x28 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x28 0.--9. 1. "OA3,Own address 3"
line.long 0x2C "CFG_I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x2C 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x2C 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x2C 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x2C 0. "OA0_ACT,Own Address 0 active" "0,1"
line.long 0x30 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x30 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x30 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x30 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x30 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree "MCU_M4FSS0_DRAM_0_DRAM"
base ad:0x5040000
group.long 0x00++0x03
line.long 0x00 "IDRAM__SLV__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "MCU_M4FSS0_ECC_AGGR_0_ECC_AGGR"
base ad:0x5FF1000
rgroup.long 0x00++0x03
line.long 0x00 "ECC__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
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bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
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bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "ECC__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
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hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
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bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
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hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ECC__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ECC__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "ECC__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 13. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1"
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bitfld.long 0x04 12. "BLAZAR_IA2V_S_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_Ia2v_s_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x04 11. "BLAZAR_IA2V_D_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_Ia2v_d_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x04 10. "BLAZAR_IA2V_I_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_Ia2v_i_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 9. "BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_PEND,Interrupt Pending Status for blazar_sys_scr_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x04 8. "BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x04 7. "BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_blazar_scr_scr_blazar_cbass_blazar_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 6. "BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_Iecc_s_p2p_bridge_Iecc_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x04 5. "BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_vbusp_s_p2p_bridge_vbusp_s_bridge_busecc_pend" "0,1"
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bitfld.long 0x04 4. "BLAZAR_RAT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_rat_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 3. "DRAM_BUSECC_PEND,Interrupt Pending Status for dram_busecc_pend" "0,1"
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bitfld.long 0x04 2. "IRAM_BUSECC_PEND,Interrupt Pending Status for iram_busecc_pend" "0,1"
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bitfld.long 0x04 1. "DRAM_RAMECC_PEND,Interrupt Pending Status for dram_ramecc_pend" "0,1"
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bitfld.long 0x04 0. "IRAM_RAMECC_PEND,Interrupt Pending Status for iram_ramecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ECC__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 13. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1"
newline
bitfld.long 0x00 12. "BLAZAR_IA2V_S_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_Ia2v_s_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 11. "BLAZAR_IA2V_D_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_Ia2v_d_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x00 10. "BLAZAR_IA2V_I_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_Ia2v_i_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x00 9. "BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_sys_scr_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
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bitfld.long 0x00 8. "BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
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bitfld.long 0x00 7. "BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_blazar_scr_scr_blazar_cbass_blazar_scr_scr_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x00 6. "BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_Iecc_s_p2p_bridge_Iecc_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x00 5. "BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_vbusp_s_p2p_bridge_vbusp_s_bridge_busecc_pend" "0,1"
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bitfld.long 0x00 4. "BLAZAR_RAT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_rat_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x00 3. "DRAM_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dram_busecc_pend" "0,1"
newline
bitfld.long 0x00 2. "IRAM_BUSECC_ENABLE_SET,Interrupt Enable Set Register for iram_busecc_pend" "0,1"
newline
bitfld.long 0x00 1. "DRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dram_ramecc_pend" "0,1"
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bitfld.long 0x00 0. "IRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for iram_ramecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ECC__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 13. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1"
newline
bitfld.long 0x00 12. "BLAZAR_IA2V_S_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_Ia2v_s_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x00 11. "BLAZAR_IA2V_D_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_Ia2v_d_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x00 10. "BLAZAR_IA2V_I_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_Ia2v_i_edc_ctrl_busecc_pend" "0,1"
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bitfld.long 0x00 9. "BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_sys_scr_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x00 8. "BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x00 7. "BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_blazar_scr_scr_blazar_cbass_blazar_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 6. "BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_Iecc_s_p2p_bridge_Iecc_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x00 5. "BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_vbusp_s_p2p_bridge_vbusp_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x00 4. "BLAZAR_RAT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_rat_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 3. "DRAM_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dram_busecc_pend" "0,1"
newline
bitfld.long 0x00 2. "IRAM_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for iram_busecc_pend" "0,1"
newline
bitfld.long 0x00 1. "DRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "IRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for iram_ramecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ECC__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 13. "ECCAGG_PEND,Interrupt Pending Status for eccagg_pend" "0,1"
newline
bitfld.long 0x04 12. "BLAZAR_IA2V_S_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_Ia2v_s_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 11. "BLAZAR_IA2V_D_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_Ia2v_d_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 10. "BLAZAR_IA2V_I_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_Ia2v_i_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 9. "BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_PEND,Interrupt Pending Status for blazar_sys_scr_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x04 8. "BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x04 7. "BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_blazar_scr_scr_blazar_cbass_blazar_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 6. "BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_Iecc_s_p2p_bridge_Iecc_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x04 5. "BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_PEND,Interrupt Pending Status for blazar_cbass_vbusp_s_p2p_bridge_vbusp_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x04 4. "BLAZAR_RAT_EDC_CTRL_BUSECC_PEND,Interrupt Pending Status for blazar_rat_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x04 3. "DRAM_BUSECC_PEND,Interrupt Pending Status for dram_busecc_pend" "0,1"
newline
bitfld.long 0x04 2. "IRAM_BUSECC_PEND,Interrupt Pending Status for iram_busecc_pend" "0,1"
newline
bitfld.long 0x04 1. "DRAM_RAMECC_PEND,Interrupt Pending Status for dram_ramecc_pend" "0,1"
newline
bitfld.long 0x04 0. "IRAM_RAMECC_PEND,Interrupt Pending Status for iram_ramecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ECC__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 13. "ECCAGG_ENABLE_SET,Interrupt Enable Set Register for eccagg_pend" "0,1"
newline
bitfld.long 0x00 12. "BLAZAR_IA2V_S_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_Ia2v_s_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 11. "BLAZAR_IA2V_D_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_Ia2v_d_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 10. "BLAZAR_IA2V_I_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_Ia2v_i_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 9. "BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_sys_scr_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x00 8. "BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x00 7. "BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_blazar_scr_scr_blazar_cbass_blazar_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 6. "BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_Iecc_s_p2p_bridge_Iecc_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x00 5. "BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_cbass_vbusp_s_p2p_bridge_vbusp_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x00 4. "BLAZAR_RAT_EDC_CTRL_BUSECC_ENABLE_SET,Interrupt Enable Set Register for blazar_rat_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 3. "DRAM_BUSECC_ENABLE_SET,Interrupt Enable Set Register for dram_busecc_pend" "0,1"
newline
bitfld.long 0x00 2. "IRAM_BUSECC_ENABLE_SET,Interrupt Enable Set Register for iram_busecc_pend" "0,1"
newline
bitfld.long 0x00 1. "DRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for dram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "IRAM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for iram_ramecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ECC__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 13. "ECCAGG_ENABLE_CLR,Interrupt Enable Clear Register for eccagg_pend" "0,1"
newline
bitfld.long 0x00 12. "BLAZAR_IA2V_S_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_Ia2v_s_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 11. "BLAZAR_IA2V_D_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_Ia2v_d_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 10. "BLAZAR_IA2V_I_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_Ia2v_i_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 9. "BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_sys_scr_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x00 8. "BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_vbus_clk_edc_ctrl_cbass_int_vbus_busecc_pend" "0,1"
newline
bitfld.long 0x00 7. "BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_blazar_scr_scr_blazar_cbass_blazar_scr_scr_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 6. "BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_Iecc_s_p2p_bridge_Iecc_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x00 5. "BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_cbass_vbusp_s_p2p_bridge_vbusp_s_bridge_busecc_pend" "0,1"
newline
bitfld.long 0x00 4. "BLAZAR_RAT_EDC_CTRL_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for blazar_rat_edc_ctrl_busecc_pend" "0,1"
newline
bitfld.long 0x00 3. "DRAM_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for dram_busecc_pend" "0,1"
newline
bitfld.long 0x00 2. "IRAM_BUSECC_ENABLE_CLR,Interrupt Enable Clear Register for iram_busecc_pend" "0,1"
newline
bitfld.long 0x00 1. "DRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for dram_ramecc_pend" "0,1"
newline
bitfld.long 0x00 0. "IRAM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for iram_ramecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ECC__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ECC__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ECC__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ECC__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCU_M4FSS0_IRAM_0_IRAM"
base ad:0x5000000
group.long 0x00++0x03
line.long 0x00 "BLAZAR_IRAM_RAM_REG,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "MCU_M4FSS0_RAT_0_RAT"
base ad:0x5FF0000
rgroup.long 0x00++0x07
line.long 0x00 "RAT__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "RAT__CFG__MMRS_config,The Config Register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x04 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x04 0.--7. 1. "REGIONS,Number of regions"
group.long 0x804++0x03
line.long 0x00 "RAT__CFG__MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x820++0x1B
line.long 0x00 "RAT__CFG__MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "RAT__CFG__MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "RAT__CFG__MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "RAT__CFG__MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "RAT__CFG__MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 12 bits"
line.long 0x14 "RAT__CFG__MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "RAT__CFG__MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x840++0x13
line.long 0x00 "RAT__CFG__MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "RAT__CFG__MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "RAT__CFG__MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "RAT__CFG__MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "RAT__CFG__MMRS_eoi_reg,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
group.long 0x20++0x0F
line.long 0x00 "RAT__CFG__MMRS_ctrl,The Control for Region a"
bitfld.long 0x00 31. "EN,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "SIZE,Size of the Region in Address Bits" "1 byte,2B,4B,8B etc,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,4GB,?..."
line.long 0x04 "RAT__CFG__MMRS_base,The Base Address for Region a"
line.long 0x08 "RAT__CFG__MMRS_trans_l,The Translated Lower Address Bits for Region a"
line.long 0x0C "RAT__CFG__MMRS_trans_u,The Translated Upper Address Bits for Region a"
bitfld.long 0x0C 0.--3. "UPPER,Translated Upper Address Bits for the Region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "MCU_MCAN0_CFG"
base ad:0x4E08000
rgroup.long 0x00++0x07
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)"
bitfld.long 0x00 28.--31. "REL,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "STEP,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month"
hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321"
hgroup.long 0x08++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register"
group.long 0x0C++0x23
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable"
bitfld.long 0x00 23. "TDC,Transmitter Delay Compensation" "0,1"
bitfld.long 0x00 16.--20. "DBRP,Data Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "DTSEG1,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "DSJW,Data resynchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection"
rbitfld.long 0x04 7. "RX,Receive Pin" "0,1"
bitfld.long 0x04 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
bitfld.long 0x04 4. "LBCK,Loop Back Mode" "0,1"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM"
hexmask.long.byte 0x08 8.--15. 1. "WDV,Watchdog Value"
hexmask.long.byte 0x08 0.--7. 1. "WDC,Watchdog Counter Value"
line.long 0x0C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration"
bitfld.long 0x0C 15. "NISO,Non ISO Operation" "CAN FD frame format according to ISO 11898-1:2015,CAN FD frame format according to Bosch CAN FD.."
bitfld.long 0x0C 14. "TXP,Transmit Pause" "0,1"
bitfld.long 0x0C 13. "EFBI,Edge Filtering during Bus Integration" "0,1"
bitfld.long 0x0C 12. "PXHD,Protocol Exception Handling Disable" "0,1"
newline
bitfld.long 0x0C 9. "BRSE,Bit Rate Switch Enable" "0,1"
bitfld.long 0x0C 8. "FDOE,FD Operation Enable" "0,1"
bitfld.long 0x0C 7. "TEST,Test Mode enable" "0,1"
bitfld.long 0x0C 6. "DAR,Disable Automatic Retransmission" "0,1"
newline
bitfld.long 0x0C 5. "MON,Bus Monitoring Mode" "0,1"
bitfld.long 0x0C 4. "CSR,Clock Stop Request" "0,1"
rbitfld.long 0x0C 3. "CSA,Clock Stop Acknowledge" "0,1"
bitfld.long 0x0C 2. "ASM,Restricted Operation Mode" "0,1"
newline
bitfld.long 0x0C 1. "CCE,Configuration Change Enable" "0,1"
bitfld.long 0x0C 0. "INIT,Initialization" "0,1"
line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing"
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width"
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector"
bitfld.long 0x14 16.--19. "TCP,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3"
line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter"
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter"
line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode"
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period"
bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3"
bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1"
line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter"
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter"
repeat 14. (list 00. 11. 22. 33. 44. 55. 66. 77. 88. 99. 1010. 1111. 1212. 1313. )(list 0x00 0x04 0x08 0x0C 0x1C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x5C )
hgroup.long ($2+0x30)++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved$1,Reserved field"
repeat.end
rgroup.long 0x40++0x0B
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging"
hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging"
bitfld.long 0x00 15. "RP,Receive Error Passive" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter"
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value"
hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
bitfld.long 0x04 14. "PXE,Protocol Exception Event" "0,1"
bitfld.long 0x04 13. "RFDF,Received a CAN FD Message" "0,1"
bitfld.long 0x04 12. "RBRS,BRS flag of last received CAN FD Message" "0,1"
newline
bitfld.long 0x04 11. "RESI,ESI flag of last received CAN FD Message" "0,1"
bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "BO,Bus_Off status" "0,1"
bitfld.long 0x04 6. "EW,Warning Status" "0,1"
newline
bitfld.long 0x04 5. "EP,Error Passive" "0,1"
bitfld.long 0x04 3.--4. "ACT,Activity" "0,1,2,3"
bitfld.long 0x04 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length"
hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
group.long 0x50++0x0F
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags"
bitfld.long 0x00 29. "ARA,Access to Reserved Address" "0,1"
bitfld.long 0x00 28. "PED,Protocol Error in data Phase" "0,1"
bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "0,1"
newline
bitfld.long 0x00 25. "BO,Bus_Off Status" "0,1"
bitfld.long 0x00 24. "EW,Warning Status" "0,1"
bitfld.long 0x00 23. "EP,Error Passive" "0,1"
bitfld.long 0x00 22. "ELO,Error Logging Overflow" "0,1"
newline
bitfld.long 0x00 21. "BEU,Bit Error Uncorrected" "0,1"
bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
bitfld.long 0x00 18. "TOO,Timeout Occurred" "0,1"
bitfld.long 0x00 17. "MRAF,Message RAM Access Failure" "0,1"
newline
bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "0,1"
bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "0,1"
bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
newline
bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "0,1"
bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "0,1"
bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "0,1"
bitfld.long 0x00 9. "TC,Transmission Complete" "0,1"
newline
bitfld.long 0x00 8. "HPM,High Priority Message" "0,1"
bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "0,1"
bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
newline
bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "0,1"
bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
newline
bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "0,1"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable"
bitfld.long 0x04 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1"
bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1"
bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1"
bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "0,1"
newline
bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "0,1"
bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "0,1"
bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
newline
bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
newline
bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1"
bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
bitfld.long 0x04 8. "HPME,High Priority message Interrupt Enable" "0,1"
bitfld.long 0x04 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)"
bitfld.long 0x08 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1"
bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1"
bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1"
bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "0,1"
newline
bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "0,1"
bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
newline
bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
newline
bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1"
newline
bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x08 8. "HPML,High Priority message Interrupt Line" "0,1"
bitfld.long 0x08 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
line.long 0x0C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1"
bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "0,1"
bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "0,1"
group.long 0x80++0x0B
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames"
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
bitfld.long 0x00 1. "RRFS,reject Remote Frames Standard" "0,1"
bitfld.long 0x00 0. "RRFE,reject Remote Frames Extended" "0,1"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x04 16.--23. 1. "LSS,List Size Standard"
hexmask.long.word 0x04 2.--15. 1. "FLSSA,Filter List Standard Start Address"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x08 16.--22. 1. "LSE,List Size Extended"
hexmask.long.word 0x08 2.--15. 1. "FLESA,Filter List Extended Start Address"
group.long 0x90++0x07
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939"
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages"
bitfld.long 0x04 15. "FLST,Filter List" "0,1"
hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index"
bitfld.long 0x04 6.--7. "MSI,Message Storage Indicator" "0,1,2,3"
bitfld.long 0x04 0.--5. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
group.long ($2+0x98)++0x03
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT$1,NewDat flags of dedicated Rx buffers 0-31"
bitfld.long 0x00 31. "ND31,New Data" "0,1"
bitfld.long 0x00 30. "ND30,New Data" "0,1"
bitfld.long 0x00 29. "ND29,New Data" "0,1"
bitfld.long 0x00 28. "ND28,New Data" "0,1"
newline
bitfld.long 0x00 27. "ND27,New Data" "0,1"
bitfld.long 0x00 26. "ND26,New Data" "0,1"
bitfld.long 0x00 25. "ND25,New Data" "0,1"
bitfld.long 0x00 24. "ND24,New Data" "0,1"
newline
bitfld.long 0x00 23. "ND23,New Data" "0,1"
bitfld.long 0x00 22. "ND22,New Data" "0,1"
bitfld.long 0x00 21. "ND21,New Data" "0,1"
bitfld.long 0x00 20. "ND20,New Data" "0,1"
newline
bitfld.long 0x00 19. "ND19,New Data" "0,1"
bitfld.long 0x00 18. "ND18,New Data" "0,1"
bitfld.long 0x00 17. "ND17,New Data" "0,1"
bitfld.long 0x00 16. "ND16,New Data" "0,1"
newline
bitfld.long 0x00 15. "ND15,New Data" "0,1"
bitfld.long 0x00 14. "ND14,New Data" "0,1"
bitfld.long 0x00 13. "ND13,New Data" "0,1"
bitfld.long 0x00 12. "ND12,New Data" "0,1"
newline
bitfld.long 0x00 11. "ND11,New Data" "0,1"
bitfld.long 0x00 10. "ND10,New Data" "0,1"
bitfld.long 0x00 9. "ND9,New Data" "0,1"
bitfld.long 0x00 8. "ND8,New Data" "0,1"
newline
bitfld.long 0x00 7. "ND7,New Data" "0,1"
bitfld.long 0x00 6. "ND6,New Data" "0,1"
bitfld.long 0x00 5. "ND5,New Data" "0,1"
bitfld.long 0x00 4. "ND4,New Data" "0,1"
newline
bitfld.long 0x00 3. "ND3,New Data" "0,1"
bitfld.long 0x00 2. "ND2,New Data" "0,1"
bitfld.long 0x00 1. "ND1,New Data" "0,1"
bitfld.long 0x00 0. "ND0,New Data" "0,1"
repeat.end
group.long 0xA0++0x47
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address"
bitfld.long 0x00 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
hexmask.long.byte 0x00 16.--22. 1. "F0S,Rx FIFO 0 Size"
hexmask.long.word 0x00 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level"
bitfld.long 0x04 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x04 24. "F0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x04 16.--21. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 8.--13. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x04 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level"
bitfld.long 0x08 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section"
hexmask.long.word 0x0C 2.--15. 1. "RBSA,Rx Buffer Start Address"
line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address"
bitfld.long 0x10 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1"
hexmask.long.byte 0x10 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
hexmask.long.byte 0x10 16.--22. 1. "F1S,Rx FIFO 1 Size"
hexmask.long.word 0x10 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level"
bitfld.long 0x14 30.--31. "DMS,Debug Message Status" "0,1,2,3"
bitfld.long 0x14 25. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x14 24. "F1F,Rx FIFO 1 Full" "0,1"
bitfld.long 0x14 16.--21. "F1PI,Rx FIFO 1 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 8.--13. "F1GI,Rx FIFO 1 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x14 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level"
bitfld.long 0x18 0.--5. "F1AI,Rx FIFO 1 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames"
bitfld.long 0x1C 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address"
bitfld.long 0x20 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
bitfld.long 0x20 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x20 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 2.--15. 1. "TBSA,Tx Buffers Start Address"
line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level"
bitfld.long 0x24 21. "TFQF,Tx FIFO/Queue Full" "0,1"
bitfld.long 0x24 16.--20. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 8.--12. "TFGI,Tx Queue Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 0.--5. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission"
bitfld.long 0x28 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request"
bitfld.long 0x2C 31. "TRP31,Transmission Request Pending" "0,1"
bitfld.long 0x2C 30. "TRP30,Transmission Request Pending" "0,1"
bitfld.long 0x2C 29. "TRP29,Transmission Request Pending" "0,1"
bitfld.long 0x2C 28. "TRP28,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 27. "TRP27,Transmission Request Pending" "0,1"
bitfld.long 0x2C 26. "TRP26,Transmission Request Pending" "0,1"
bitfld.long 0x2C 25. "TRP25,Transmission Request Pending" "0,1"
bitfld.long 0x2C 24. "TRP24,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 23. "TRP23,Transmission Request Pending" "0,1"
bitfld.long 0x2C 22. "TRP22,Transmission Request Pending" "0,1"
bitfld.long 0x2C 21. "TRP21,Transmission Request Pending" "0,1"
bitfld.long 0x2C 20. "TRP20,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 19. "TRP19,Transmission Request Pending" "0,1"
bitfld.long 0x2C 18. "TRP18,Transmission Request Pending" "0,1"
bitfld.long 0x2C 17. "TRP17,Transmission Request Pending" "0,1"
bitfld.long 0x2C 16. "TRP16,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 15. "TRP15,Transmission Request Pending" "0,1"
bitfld.long 0x2C 14. "TRP14,Transmission Request Pending" "0,1"
bitfld.long 0x2C 13. "TRP13,Transmission Request Pending" "0,1"
bitfld.long 0x2C 12. "TRP12,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 11. "TRP11,Transmission Request Pending" "0,1"
bitfld.long 0x2C 10. "TRP10,Transmission Request Pending" "0,1"
bitfld.long 0x2C 9. "TRP9,Transmission Request Pending" "0,1"
bitfld.long 0x2C 8. "TRP8,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 7. "TRP7,Transmission Request Pending" "0,1"
bitfld.long 0x2C 6. "TRP6,Transmission Request Pending" "0,1"
bitfld.long 0x2C 5. "TRP5,Transmission Request Pending" "0,1"
bitfld.long 0x2C 4. "TRP4,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 3. "TRP3,Transmission Request Pending" "0,1"
bitfld.long 0x2C 2. "TRP2,Transmission Request Pending" "0,1"
bitfld.long 0x2C 1. "TRP1,Transmission Request Pending" "0,1"
bitfld.long 0x2C 0. "TRP0,Transmission Request Pending" "0,1"
line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests"
bitfld.long 0x30 31. "AR31,Add request" "0,1"
bitfld.long 0x30 30. "AR30,Add request" "0,1"
bitfld.long 0x30 29. "AR29,Add request" "0,1"
bitfld.long 0x30 28. "AR28,Add request" "0,1"
newline
bitfld.long 0x30 27. "AR27,Add request" "0,1"
bitfld.long 0x30 26. "AR26,Add request" "0,1"
bitfld.long 0x30 25. "AR25,Add request" "0,1"
bitfld.long 0x30 24. "AR24,Add request" "0,1"
newline
bitfld.long 0x30 23. "AR23,Add request" "0,1"
bitfld.long 0x30 22. "AR22,Add request" "0,1"
bitfld.long 0x30 21. "AR21,Add request" "0,1"
bitfld.long 0x30 20. "AR20,Add request" "0,1"
newline
bitfld.long 0x30 19. "AR19,Add request" "0,1"
bitfld.long 0x30 18. "AR18,Add request" "0,1"
bitfld.long 0x30 17. "AR17,Add request" "0,1"
bitfld.long 0x30 16. "AR16,Add request" "0,1"
newline
bitfld.long 0x30 15. "AR15,Add request" "0,1"
bitfld.long 0x30 14. "AR14,Add request" "0,1"
bitfld.long 0x30 13. "AR13,Add request" "0,1"
bitfld.long 0x30 12. "AR12,Add request" "0,1"
newline
bitfld.long 0x30 11. "AR11,Add request" "0,1"
bitfld.long 0x30 10. "AR10,Add request" "0,1"
bitfld.long 0x30 9. "AR9,Add request" "0,1"
bitfld.long 0x30 8. "AR8,Add request" "0,1"
newline
bitfld.long 0x30 7. "AR7,Add request" "0,1"
bitfld.long 0x30 6. "AR6,Add request" "0,1"
bitfld.long 0x30 5. "AR5,Add request" "0,1"
bitfld.long 0x30 4. "AR4,Add request" "0,1"
newline
bitfld.long 0x30 3. "AR3,Add request" "0,1"
bitfld.long 0x30 2. "AR2,Add request" "0,1"
bitfld.long 0x30 1. "AR1,Add request" "0,1"
bitfld.long 0x30 0. "AR0,Add request" "0,1"
line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions"
bitfld.long 0x34 31. "CR31,Cancellation Request" "0,1"
bitfld.long 0x34 30. "CR30,Cancellation Request" "0,1"
bitfld.long 0x34 29. "CR29,Cancellation Request" "0,1"
bitfld.long 0x34 28. "CR28,Cancellation Request" "0,1"
newline
bitfld.long 0x34 27. "CR27,Cancellation Request" "0,1"
bitfld.long 0x34 26. "CR26,Cancellation Request" "0,1"
bitfld.long 0x34 25. "CR25,Cancellation Request" "0,1"
bitfld.long 0x34 24. "CR24,Cancellation Request" "0,1"
newline
bitfld.long 0x34 23. "CR23,Cancellation Request" "0,1"
bitfld.long 0x34 22. "CR22,Cancellation Request" "0,1"
bitfld.long 0x34 21. "CR21,Cancellation Request" "0,1"
bitfld.long 0x34 20. "CR20,Cancellation Request" "0,1"
newline
bitfld.long 0x34 19. "CR19,Cancellation Request" "0,1"
bitfld.long 0x34 18. "CR18,Cancellation Request" "0,1"
bitfld.long 0x34 17. "CR17,Cancellation Request" "0,1"
bitfld.long 0x34 16. "CR16,Cancellation Request" "0,1"
newline
bitfld.long 0x34 15. "CR15,Cancellation Request" "0,1"
bitfld.long 0x34 14. "CR14,Cancellation Request" "0,1"
bitfld.long 0x34 13. "CR13,Cancellation Request" "0,1"
bitfld.long 0x34 12. "CR12,Cancellation Request" "0,1"
newline
bitfld.long 0x34 11. "CR11,Cancellation Request" "0,1"
bitfld.long 0x34 10. "CR10,Cancellation Request" "0,1"
bitfld.long 0x34 9. "CR9,Cancellation Request" "0,1"
bitfld.long 0x34 8. "CR8,Cancellation Request" "0,1"
newline
bitfld.long 0x34 7. "CR7,Cancellation Request" "0,1"
bitfld.long 0x34 6. "CR6,Cancellation Request" "0,1"
bitfld.long 0x34 5. "CR5,Cancellation Request" "0,1"
bitfld.long 0x34 4. "CR4,Cancellation Request" "0,1"
newline
bitfld.long 0x34 3. "CR3,Cancellation Request" "0,1"
bitfld.long 0x34 2. "CR2,Cancellation Request" "0,1"
bitfld.long 0x34 1. "CR1,Cancellation Request" "0,1"
bitfld.long 0x34 0. "CR0,Cancellation Request" "0,1"
line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared"
bitfld.long 0x38 31. "TO31,Transmission Occurred" "0,1"
bitfld.long 0x38 30. "TO30,Transmission Occurred" "0,1"
bitfld.long 0x38 29. "TO29,Transmission Occurred" "0,1"
bitfld.long 0x38 28. "TO28,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 27. "TO27,Transmission Occurred" "0,1"
bitfld.long 0x38 26. "TO26,Transmission Occurred" "0,1"
bitfld.long 0x38 25. "TO25,Transmission Occurred" "0,1"
bitfld.long 0x38 24. "TO24,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 23. "TO23,Transmission Occurred" "0,1"
bitfld.long 0x38 22. "TO22,Transmission Occurred" "0,1"
bitfld.long 0x38 21. "TO21,Transmission Occurred" "0,1"
bitfld.long 0x38 20. "TO20,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 19. "TO19,Transmission Occurred" "0,1"
bitfld.long 0x38 18. "TO18,Transmission Occurred" "0,1"
bitfld.long 0x38 17. "TO17,Transmission Occurred" "0,1"
bitfld.long 0x38 16. "TO16,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 15. "TO15,Transmission Occurred" "0,1"
bitfld.long 0x38 14. "TO14,Transmission Occurred" "0,1"
bitfld.long 0x38 13. "TO13,Transmission Occurred" "0,1"
bitfld.long 0x38 12. "TO12,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 11. "TO11,Transmission Occurred" "0,1"
bitfld.long 0x38 10. "TO10,Transmission Occurred" "0,1"
bitfld.long 0x38 9. "TO9,Transmission Occurred" "0,1"
bitfld.long 0x38 8. "TO8,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 7. "TO7,Transmission Occurred" "0,1"
bitfld.long 0x38 6. "TO6,Transmission Occurred" "0,1"
bitfld.long 0x38 5. "TO5,Transmission Occurred" "0,1"
bitfld.long 0x38 4. "TO4,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 3. "TO3,Transmission Occurred" "0,1"
bitfld.long 0x38 2. "TO2,Transmission Occurred" "0,1"
bitfld.long 0x38 1. "TO1,Transmission Occurred" "0,1"
bitfld.long 0x38 0. "TO0,Transmission Occurred" "0,1"
line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request"
bitfld.long 0x3C 31. "CF31,Cancellation Finished" "0,1"
bitfld.long 0x3C 30. "CF30,Cancellation Finished" "0,1"
bitfld.long 0x3C 29. "CF29,Cancellation Finished" "0,1"
bitfld.long 0x3C 28. "CF28,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 27. "CF27,Cancellation Finished" "0,1"
bitfld.long 0x3C 26. "CF26,Cancellation Finished" "0,1"
bitfld.long 0x3C 25. "CF25,Cancellation Finished" "0,1"
bitfld.long 0x3C 24. "CF24,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 23. "CF23,Cancellation Finished" "0,1"
bitfld.long 0x3C 22. "CF22,Cancellation Finished" "0,1"
bitfld.long 0x3C 21. "CF21,Cancellation Finished" "0,1"
bitfld.long 0x3C 20. "CF20,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 19. "CF19,Cancellation Finished" "0,1"
bitfld.long 0x3C 18. "CF18,Cancellation Finished" "0,1"
bitfld.long 0x3C 17. "CF17,Cancellation Finished" "0,1"
bitfld.long 0x3C 16. "CF16,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 15. "CF15,Cancellation Finished" "0,1"
bitfld.long 0x3C 14. "CF14,Cancellation Finished" "0,1"
bitfld.long 0x3C 13. "CF13,Cancellation Finished" "0,1"
bitfld.long 0x3C 12. "CF12,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 11. "CF11,Cancellation Finished" "0,1"
bitfld.long 0x3C 10. "CF10,Cancellation Finished" "0,1"
bitfld.long 0x3C 9. "CF9,Cancellation Finished" "0,1"
bitfld.long 0x3C 8. "CF8,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 7. "CF7,Cancellation Finished" "0,1"
bitfld.long 0x3C 6. "CF6,Cancellation Finished" "0,1"
bitfld.long 0x3C 5. "CF5,Cancellation Finished" "0,1"
bitfld.long 0x3C 4. "CF4,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 3. "CF3,Cancellation Finished" "0,1"
bitfld.long 0x3C 2. "CF2,Cancellation Finished" "0,1"
bitfld.long 0x3C 1. "CF1,Cancellation Finished" "0,1"
bitfld.long 0x3C 0. "CF0,Cancellation Finished" "0,1"
line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers"
bitfld.long 0x40 31. "TIE31,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 30. "TIE30,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 29. "TIE29,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 28. "TIE28,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 27. "TIE27,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 26. "TIE26,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 25. "TIE25,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 24. "TIE24,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 23. "TIE23,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 22. "TIE22,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 21. "TIE21,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 20. "TIE20,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 19. "TIE19,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 18. "TIE18,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 17. "TIE17,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 16. "TIE16,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 15. "TIE15,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 14. "TIE14,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 13. "TIE13,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 12. "TIE12,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 11. "TIE11,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 10. "TIE10,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 9. "TIE9,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 8. "TIE8,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 7. "TIE7,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 6. "TIE6,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 5. "TIE5,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 4. "TIE4,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 3. "TIE3,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 2. "TIE2,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 1. "TIE1,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 0. "TIE0,Transmission Interrupt Enable" "0,1"
line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers"
bitfld.long 0x44 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1"
repeat 3. (list 1414. 1515. 1616. )(list 0x00 0x04 0x14 )
hgroup.long ($2+0xE8)++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved$1,Reserved Field"
repeat.end
group.long 0xF0++0x0B
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address"
bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level"
bitfld.long 0x04 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x04 24. "EFF,Event FIFO Full" "0,1"
bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 0.--5. "EFFL,Event FIFO Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level"
bitfld.long 0x08 0.--4. "EFAI,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hgroup.long 0x100++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field"
tree.end
tree "MCU_MCAN0_ECC_AGGR"
base ad:0x4701000
rgroup.long 0x00++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCU_MCAN0_MSGMEM_RAM"
base ad:0x4E00000
group.long 0x00++0x03
line.long 0x00 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "MCU_MCAN0_SS"
base ad:0x4E09000
rgroup.long 0x00++0x2B
line.long 0x00 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS"
bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1"
bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
bitfld.long 0x04 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1"
bitfld.long 0x04 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1"
line.long 0x08 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS"
bitfld.long 0x08 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1"
bitfld.long 0x08 1. "MEM_INIT_DONE," "0,1"
line.long 0x0C "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits"
bitfld.long 0x0C 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x10 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status"
bitfld.long 0x10 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x14 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits"
bitfld.long 0x14 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x18 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable"
bitfld.long 0x18 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x1C "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts"
bitfld.long 0x1C 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x20 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register"
hexmask.long.byte 0x20 0.--7. 1. "EOI,Write with bit position of targeted interrupt"
line.long 0x24 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler"
hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value"
line.long 0x28 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter"
bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "MCU_MCAN1_CFG"
base ad:0x4E18000
rgroup.long 0x00++0x07
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)"
bitfld.long 0x00 28.--31. "REL,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "STEP,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month"
hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321"
hgroup.long 0x08++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register"
group.long 0x0C++0x23
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable"
bitfld.long 0x00 23. "TDC,Transmitter Delay Compensation" "0,1"
bitfld.long 0x00 16.--20. "DBRP,Data Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "DTSEG1,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "DSJW,Data resynchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection"
rbitfld.long 0x04 7. "RX,Receive Pin" "0,1"
bitfld.long 0x04 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
bitfld.long 0x04 4. "LBCK,Loop Back Mode" "0,1"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM"
hexmask.long.byte 0x08 8.--15. 1. "WDV,Watchdog Value"
hexmask.long.byte 0x08 0.--7. 1. "WDC,Watchdog Counter Value"
line.long 0x0C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration"
bitfld.long 0x0C 15. "NISO,Non ISO Operation" "CAN FD frame format according to ISO 11898-1:2015,CAN FD frame format according to Bosch CAN FD.."
bitfld.long 0x0C 14. "TXP,Transmit Pause" "0,1"
bitfld.long 0x0C 13. "EFBI,Edge Filtering during Bus Integration" "0,1"
bitfld.long 0x0C 12. "PXHD,Protocol Exception Handling Disable" "0,1"
newline
bitfld.long 0x0C 9. "BRSE,Bit Rate Switch Enable" "0,1"
bitfld.long 0x0C 8. "FDOE,FD Operation Enable" "0,1"
bitfld.long 0x0C 7. "TEST,Test Mode enable" "0,1"
bitfld.long 0x0C 6. "DAR,Disable Automatic Retransmission" "0,1"
newline
bitfld.long 0x0C 5. "MON,Bus Monitoring Mode" "0,1"
bitfld.long 0x0C 4. "CSR,Clock Stop Request" "0,1"
rbitfld.long 0x0C 3. "CSA,Clock Stop Acknowledge" "0,1"
bitfld.long 0x0C 2. "ASM,Restricted Operation Mode" "0,1"
newline
bitfld.long 0x0C 1. "CCE,Configuration Change Enable" "0,1"
bitfld.long 0x0C 0. "INIT,Initialization" "0,1"
line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing"
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width"
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector"
bitfld.long 0x14 16.--19. "TCP,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3"
line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter"
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter"
line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode"
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period"
bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3"
bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1"
line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter"
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter"
repeat 14. (list 00. 11. 22. 33. 44. 55. 66. 77. 88. 99. 1010. 1111. 1212. 1313. )(list 0x00 0x04 0x08 0x0C 0x1C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x5C )
hgroup.long ($2+0x30)++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved$1,Reserved field"
repeat.end
rgroup.long 0x40++0x0B
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging"
hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging"
bitfld.long 0x00 15. "RP,Receive Error Passive" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter"
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value"
hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
bitfld.long 0x04 14. "PXE,Protocol Exception Event" "0,1"
bitfld.long 0x04 13. "RFDF,Received a CAN FD Message" "0,1"
bitfld.long 0x04 12. "RBRS,BRS flag of last received CAN FD Message" "0,1"
newline
bitfld.long 0x04 11. "RESI,ESI flag of last received CAN FD Message" "0,1"
bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "BO,Bus_Off status" "0,1"
bitfld.long 0x04 6. "EW,Warning Status" "0,1"
newline
bitfld.long 0x04 5. "EP,Error Passive" "0,1"
bitfld.long 0x04 3.--4. "ACT,Activity" "0,1,2,3"
bitfld.long 0x04 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length"
hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
group.long 0x50++0x0F
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags"
bitfld.long 0x00 29. "ARA,Access to Reserved Address" "0,1"
bitfld.long 0x00 28. "PED,Protocol Error in data Phase" "0,1"
bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "0,1"
newline
bitfld.long 0x00 25. "BO,Bus_Off Status" "0,1"
bitfld.long 0x00 24. "EW,Warning Status" "0,1"
bitfld.long 0x00 23. "EP,Error Passive" "0,1"
bitfld.long 0x00 22. "ELO,Error Logging Overflow" "0,1"
newline
bitfld.long 0x00 21. "BEU,Bit Error Uncorrected" "0,1"
bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
bitfld.long 0x00 18. "TOO,Timeout Occurred" "0,1"
bitfld.long 0x00 17. "MRAF,Message RAM Access Failure" "0,1"
newline
bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "0,1"
bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "0,1"
bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
newline
bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "0,1"
bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "0,1"
bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "0,1"
bitfld.long 0x00 9. "TC,Transmission Complete" "0,1"
newline
bitfld.long 0x00 8. "HPM,High Priority Message" "0,1"
bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "0,1"
bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
newline
bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "0,1"
bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
newline
bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "0,1"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable"
bitfld.long 0x04 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1"
bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1"
bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1"
bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "0,1"
newline
bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "0,1"
bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "0,1"
bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
newline
bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
newline
bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1"
bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
bitfld.long 0x04 8. "HPME,High Priority message Interrupt Enable" "0,1"
bitfld.long 0x04 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)"
bitfld.long 0x08 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1"
bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1"
bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1"
bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "0,1"
newline
bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "0,1"
bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
newline
bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
newline
bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1"
newline
bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x08 8. "HPML,High Priority message Interrupt Line" "0,1"
bitfld.long 0x08 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
line.long 0x0C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1"
bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "0,1"
bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "0,1"
group.long 0x80++0x0B
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames"
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
bitfld.long 0x00 1. "RRFS,reject Remote Frames Standard" "0,1"
bitfld.long 0x00 0. "RRFE,reject Remote Frames Extended" "0,1"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x04 16.--23. 1. "LSS,List Size Standard"
hexmask.long.word 0x04 2.--15. 1. "FLSSA,Filter List Standard Start Address"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x08 16.--22. 1. "LSE,List Size Extended"
hexmask.long.word 0x08 2.--15. 1. "FLESA,Filter List Extended Start Address"
group.long 0x90++0x07
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939"
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages"
bitfld.long 0x04 15. "FLST,Filter List" "0,1"
hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index"
bitfld.long 0x04 6.--7. "MSI,Message Storage Indicator" "0,1,2,3"
bitfld.long 0x04 0.--5. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
group.long ($2+0x98)++0x03
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT$1,NewDat flags of dedicated Rx buffers 0-31"
bitfld.long 0x00 31. "ND31,New Data" "0,1"
bitfld.long 0x00 30. "ND30,New Data" "0,1"
bitfld.long 0x00 29. "ND29,New Data" "0,1"
bitfld.long 0x00 28. "ND28,New Data" "0,1"
newline
bitfld.long 0x00 27. "ND27,New Data" "0,1"
bitfld.long 0x00 26. "ND26,New Data" "0,1"
bitfld.long 0x00 25. "ND25,New Data" "0,1"
bitfld.long 0x00 24. "ND24,New Data" "0,1"
newline
bitfld.long 0x00 23. "ND23,New Data" "0,1"
bitfld.long 0x00 22. "ND22,New Data" "0,1"
bitfld.long 0x00 21. "ND21,New Data" "0,1"
bitfld.long 0x00 20. "ND20,New Data" "0,1"
newline
bitfld.long 0x00 19. "ND19,New Data" "0,1"
bitfld.long 0x00 18. "ND18,New Data" "0,1"
bitfld.long 0x00 17. "ND17,New Data" "0,1"
bitfld.long 0x00 16. "ND16,New Data" "0,1"
newline
bitfld.long 0x00 15. "ND15,New Data" "0,1"
bitfld.long 0x00 14. "ND14,New Data" "0,1"
bitfld.long 0x00 13. "ND13,New Data" "0,1"
bitfld.long 0x00 12. "ND12,New Data" "0,1"
newline
bitfld.long 0x00 11. "ND11,New Data" "0,1"
bitfld.long 0x00 10. "ND10,New Data" "0,1"
bitfld.long 0x00 9. "ND9,New Data" "0,1"
bitfld.long 0x00 8. "ND8,New Data" "0,1"
newline
bitfld.long 0x00 7. "ND7,New Data" "0,1"
bitfld.long 0x00 6. "ND6,New Data" "0,1"
bitfld.long 0x00 5. "ND5,New Data" "0,1"
bitfld.long 0x00 4. "ND4,New Data" "0,1"
newline
bitfld.long 0x00 3. "ND3,New Data" "0,1"
bitfld.long 0x00 2. "ND2,New Data" "0,1"
bitfld.long 0x00 1. "ND1,New Data" "0,1"
bitfld.long 0x00 0. "ND0,New Data" "0,1"
repeat.end
group.long 0xA0++0x47
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address"
bitfld.long 0x00 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
hexmask.long.byte 0x00 16.--22. 1. "F0S,Rx FIFO 0 Size"
hexmask.long.word 0x00 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level"
bitfld.long 0x04 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x04 24. "F0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x04 16.--21. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 8.--13. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x04 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level"
bitfld.long 0x08 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section"
hexmask.long.word 0x0C 2.--15. 1. "RBSA,Rx Buffer Start Address"
line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address"
bitfld.long 0x10 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1"
hexmask.long.byte 0x10 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
hexmask.long.byte 0x10 16.--22. 1. "F1S,Rx FIFO 1 Size"
hexmask.long.word 0x10 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level"
bitfld.long 0x14 30.--31. "DMS,Debug Message Status" "0,1,2,3"
bitfld.long 0x14 25. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x14 24. "F1F,Rx FIFO 1 Full" "0,1"
bitfld.long 0x14 16.--21. "F1PI,Rx FIFO 1 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 8.--13. "F1GI,Rx FIFO 1 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x14 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level"
bitfld.long 0x18 0.--5. "F1AI,Rx FIFO 1 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames"
bitfld.long 0x1C 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address"
bitfld.long 0x20 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
bitfld.long 0x20 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x20 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 2.--15. 1. "TBSA,Tx Buffers Start Address"
line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level"
bitfld.long 0x24 21. "TFQF,Tx FIFO/Queue Full" "0,1"
bitfld.long 0x24 16.--20. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 8.--12. "TFGI,Tx Queue Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 0.--5. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission"
bitfld.long 0x28 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request"
bitfld.long 0x2C 31. "TRP31,Transmission Request Pending" "0,1"
bitfld.long 0x2C 30. "TRP30,Transmission Request Pending" "0,1"
bitfld.long 0x2C 29. "TRP29,Transmission Request Pending" "0,1"
bitfld.long 0x2C 28. "TRP28,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 27. "TRP27,Transmission Request Pending" "0,1"
bitfld.long 0x2C 26. "TRP26,Transmission Request Pending" "0,1"
bitfld.long 0x2C 25. "TRP25,Transmission Request Pending" "0,1"
bitfld.long 0x2C 24. "TRP24,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 23. "TRP23,Transmission Request Pending" "0,1"
bitfld.long 0x2C 22. "TRP22,Transmission Request Pending" "0,1"
bitfld.long 0x2C 21. "TRP21,Transmission Request Pending" "0,1"
bitfld.long 0x2C 20. "TRP20,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 19. "TRP19,Transmission Request Pending" "0,1"
bitfld.long 0x2C 18. "TRP18,Transmission Request Pending" "0,1"
bitfld.long 0x2C 17. "TRP17,Transmission Request Pending" "0,1"
bitfld.long 0x2C 16. "TRP16,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 15. "TRP15,Transmission Request Pending" "0,1"
bitfld.long 0x2C 14. "TRP14,Transmission Request Pending" "0,1"
bitfld.long 0x2C 13. "TRP13,Transmission Request Pending" "0,1"
bitfld.long 0x2C 12. "TRP12,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 11. "TRP11,Transmission Request Pending" "0,1"
bitfld.long 0x2C 10. "TRP10,Transmission Request Pending" "0,1"
bitfld.long 0x2C 9. "TRP9,Transmission Request Pending" "0,1"
bitfld.long 0x2C 8. "TRP8,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 7. "TRP7,Transmission Request Pending" "0,1"
bitfld.long 0x2C 6. "TRP6,Transmission Request Pending" "0,1"
bitfld.long 0x2C 5. "TRP5,Transmission Request Pending" "0,1"
bitfld.long 0x2C 4. "TRP4,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 3. "TRP3,Transmission Request Pending" "0,1"
bitfld.long 0x2C 2. "TRP2,Transmission Request Pending" "0,1"
bitfld.long 0x2C 1. "TRP1,Transmission Request Pending" "0,1"
bitfld.long 0x2C 0. "TRP0,Transmission Request Pending" "0,1"
line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests"
bitfld.long 0x30 31. "AR31,Add request" "0,1"
bitfld.long 0x30 30. "AR30,Add request" "0,1"
bitfld.long 0x30 29. "AR29,Add request" "0,1"
bitfld.long 0x30 28. "AR28,Add request" "0,1"
newline
bitfld.long 0x30 27. "AR27,Add request" "0,1"
bitfld.long 0x30 26. "AR26,Add request" "0,1"
bitfld.long 0x30 25. "AR25,Add request" "0,1"
bitfld.long 0x30 24. "AR24,Add request" "0,1"
newline
bitfld.long 0x30 23. "AR23,Add request" "0,1"
bitfld.long 0x30 22. "AR22,Add request" "0,1"
bitfld.long 0x30 21. "AR21,Add request" "0,1"
bitfld.long 0x30 20. "AR20,Add request" "0,1"
newline
bitfld.long 0x30 19. "AR19,Add request" "0,1"
bitfld.long 0x30 18. "AR18,Add request" "0,1"
bitfld.long 0x30 17. "AR17,Add request" "0,1"
bitfld.long 0x30 16. "AR16,Add request" "0,1"
newline
bitfld.long 0x30 15. "AR15,Add request" "0,1"
bitfld.long 0x30 14. "AR14,Add request" "0,1"
bitfld.long 0x30 13. "AR13,Add request" "0,1"
bitfld.long 0x30 12. "AR12,Add request" "0,1"
newline
bitfld.long 0x30 11. "AR11,Add request" "0,1"
bitfld.long 0x30 10. "AR10,Add request" "0,1"
bitfld.long 0x30 9. "AR9,Add request" "0,1"
bitfld.long 0x30 8. "AR8,Add request" "0,1"
newline
bitfld.long 0x30 7. "AR7,Add request" "0,1"
bitfld.long 0x30 6. "AR6,Add request" "0,1"
bitfld.long 0x30 5. "AR5,Add request" "0,1"
bitfld.long 0x30 4. "AR4,Add request" "0,1"
newline
bitfld.long 0x30 3. "AR3,Add request" "0,1"
bitfld.long 0x30 2. "AR2,Add request" "0,1"
bitfld.long 0x30 1. "AR1,Add request" "0,1"
bitfld.long 0x30 0. "AR0,Add request" "0,1"
line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions"
bitfld.long 0x34 31. "CR31,Cancellation Request" "0,1"
bitfld.long 0x34 30. "CR30,Cancellation Request" "0,1"
bitfld.long 0x34 29. "CR29,Cancellation Request" "0,1"
bitfld.long 0x34 28. "CR28,Cancellation Request" "0,1"
newline
bitfld.long 0x34 27. "CR27,Cancellation Request" "0,1"
bitfld.long 0x34 26. "CR26,Cancellation Request" "0,1"
bitfld.long 0x34 25. "CR25,Cancellation Request" "0,1"
bitfld.long 0x34 24. "CR24,Cancellation Request" "0,1"
newline
bitfld.long 0x34 23. "CR23,Cancellation Request" "0,1"
bitfld.long 0x34 22. "CR22,Cancellation Request" "0,1"
bitfld.long 0x34 21. "CR21,Cancellation Request" "0,1"
bitfld.long 0x34 20. "CR20,Cancellation Request" "0,1"
newline
bitfld.long 0x34 19. "CR19,Cancellation Request" "0,1"
bitfld.long 0x34 18. "CR18,Cancellation Request" "0,1"
bitfld.long 0x34 17. "CR17,Cancellation Request" "0,1"
bitfld.long 0x34 16. "CR16,Cancellation Request" "0,1"
newline
bitfld.long 0x34 15. "CR15,Cancellation Request" "0,1"
bitfld.long 0x34 14. "CR14,Cancellation Request" "0,1"
bitfld.long 0x34 13. "CR13,Cancellation Request" "0,1"
bitfld.long 0x34 12. "CR12,Cancellation Request" "0,1"
newline
bitfld.long 0x34 11. "CR11,Cancellation Request" "0,1"
bitfld.long 0x34 10. "CR10,Cancellation Request" "0,1"
bitfld.long 0x34 9. "CR9,Cancellation Request" "0,1"
bitfld.long 0x34 8. "CR8,Cancellation Request" "0,1"
newline
bitfld.long 0x34 7. "CR7,Cancellation Request" "0,1"
bitfld.long 0x34 6. "CR6,Cancellation Request" "0,1"
bitfld.long 0x34 5. "CR5,Cancellation Request" "0,1"
bitfld.long 0x34 4. "CR4,Cancellation Request" "0,1"
newline
bitfld.long 0x34 3. "CR3,Cancellation Request" "0,1"
bitfld.long 0x34 2. "CR2,Cancellation Request" "0,1"
bitfld.long 0x34 1. "CR1,Cancellation Request" "0,1"
bitfld.long 0x34 0. "CR0,Cancellation Request" "0,1"
line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared"
bitfld.long 0x38 31. "TO31,Transmission Occurred" "0,1"
bitfld.long 0x38 30. "TO30,Transmission Occurred" "0,1"
bitfld.long 0x38 29. "TO29,Transmission Occurred" "0,1"
bitfld.long 0x38 28. "TO28,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 27. "TO27,Transmission Occurred" "0,1"
bitfld.long 0x38 26. "TO26,Transmission Occurred" "0,1"
bitfld.long 0x38 25. "TO25,Transmission Occurred" "0,1"
bitfld.long 0x38 24. "TO24,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 23. "TO23,Transmission Occurred" "0,1"
bitfld.long 0x38 22. "TO22,Transmission Occurred" "0,1"
bitfld.long 0x38 21. "TO21,Transmission Occurred" "0,1"
bitfld.long 0x38 20. "TO20,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 19. "TO19,Transmission Occurred" "0,1"
bitfld.long 0x38 18. "TO18,Transmission Occurred" "0,1"
bitfld.long 0x38 17. "TO17,Transmission Occurred" "0,1"
bitfld.long 0x38 16. "TO16,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 15. "TO15,Transmission Occurred" "0,1"
bitfld.long 0x38 14. "TO14,Transmission Occurred" "0,1"
bitfld.long 0x38 13. "TO13,Transmission Occurred" "0,1"
bitfld.long 0x38 12. "TO12,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 11. "TO11,Transmission Occurred" "0,1"
bitfld.long 0x38 10. "TO10,Transmission Occurred" "0,1"
bitfld.long 0x38 9. "TO9,Transmission Occurred" "0,1"
bitfld.long 0x38 8. "TO8,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 7. "TO7,Transmission Occurred" "0,1"
bitfld.long 0x38 6. "TO6,Transmission Occurred" "0,1"
bitfld.long 0x38 5. "TO5,Transmission Occurred" "0,1"
bitfld.long 0x38 4. "TO4,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 3. "TO3,Transmission Occurred" "0,1"
bitfld.long 0x38 2. "TO2,Transmission Occurred" "0,1"
bitfld.long 0x38 1. "TO1,Transmission Occurred" "0,1"
bitfld.long 0x38 0. "TO0,Transmission Occurred" "0,1"
line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request"
bitfld.long 0x3C 31. "CF31,Cancellation Finished" "0,1"
bitfld.long 0x3C 30. "CF30,Cancellation Finished" "0,1"
bitfld.long 0x3C 29. "CF29,Cancellation Finished" "0,1"
bitfld.long 0x3C 28. "CF28,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 27. "CF27,Cancellation Finished" "0,1"
bitfld.long 0x3C 26. "CF26,Cancellation Finished" "0,1"
bitfld.long 0x3C 25. "CF25,Cancellation Finished" "0,1"
bitfld.long 0x3C 24. "CF24,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 23. "CF23,Cancellation Finished" "0,1"
bitfld.long 0x3C 22. "CF22,Cancellation Finished" "0,1"
bitfld.long 0x3C 21. "CF21,Cancellation Finished" "0,1"
bitfld.long 0x3C 20. "CF20,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 19. "CF19,Cancellation Finished" "0,1"
bitfld.long 0x3C 18. "CF18,Cancellation Finished" "0,1"
bitfld.long 0x3C 17. "CF17,Cancellation Finished" "0,1"
bitfld.long 0x3C 16. "CF16,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 15. "CF15,Cancellation Finished" "0,1"
bitfld.long 0x3C 14. "CF14,Cancellation Finished" "0,1"
bitfld.long 0x3C 13. "CF13,Cancellation Finished" "0,1"
bitfld.long 0x3C 12. "CF12,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 11. "CF11,Cancellation Finished" "0,1"
bitfld.long 0x3C 10. "CF10,Cancellation Finished" "0,1"
bitfld.long 0x3C 9. "CF9,Cancellation Finished" "0,1"
bitfld.long 0x3C 8. "CF8,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 7. "CF7,Cancellation Finished" "0,1"
bitfld.long 0x3C 6. "CF6,Cancellation Finished" "0,1"
bitfld.long 0x3C 5. "CF5,Cancellation Finished" "0,1"
bitfld.long 0x3C 4. "CF4,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 3. "CF3,Cancellation Finished" "0,1"
bitfld.long 0x3C 2. "CF2,Cancellation Finished" "0,1"
bitfld.long 0x3C 1. "CF1,Cancellation Finished" "0,1"
bitfld.long 0x3C 0. "CF0,Cancellation Finished" "0,1"
line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers"
bitfld.long 0x40 31. "TIE31,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 30. "TIE30,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 29. "TIE29,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 28. "TIE28,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 27. "TIE27,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 26. "TIE26,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 25. "TIE25,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 24. "TIE24,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 23. "TIE23,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 22. "TIE22,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 21. "TIE21,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 20. "TIE20,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 19. "TIE19,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 18. "TIE18,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 17. "TIE17,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 16. "TIE16,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 15. "TIE15,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 14. "TIE14,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 13. "TIE13,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 12. "TIE12,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 11. "TIE11,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 10. "TIE10,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 9. "TIE9,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 8. "TIE8,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 7. "TIE7,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 6. "TIE6,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 5. "TIE5,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 4. "TIE4,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 3. "TIE3,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 2. "TIE2,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 1. "TIE1,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 0. "TIE0,Transmission Interrupt Enable" "0,1"
line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers"
bitfld.long 0x44 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1"
repeat 3. (list 1414. 1515. 1616. )(list 0x00 0x04 0x14 )
hgroup.long ($2+0xE8)++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved$1,Reserved Field"
repeat.end
group.long 0xF0++0x0B
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address"
bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level"
bitfld.long 0x04 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x04 24. "EFF,Event FIFO Full" "0,1"
bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 0.--5. "EFFL,Event FIFO Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level"
bitfld.long 0x08 0.--4. "EFAI,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hgroup.long 0x100++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field"
tree.end
tree "MCU_MCAN1_ECC_AGGR"
base ad:0x4702000
rgroup.long 0x00++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCU_MCAN1_MSGMEM_RAM"
base ad:0x4E10000
group.long 0x00++0x03
line.long 0x00 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "MCU_MCAN1_SS"
base ad:0x4E19000
rgroup.long 0x00++0x2B
line.long 0x00 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS"
bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1"
bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
bitfld.long 0x04 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1"
bitfld.long 0x04 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1"
line.long 0x08 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS"
bitfld.long 0x08 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1"
bitfld.long 0x08 1. "MEM_INIT_DONE," "0,1"
line.long 0x0C "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits"
bitfld.long 0x0C 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x10 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status"
bitfld.long 0x10 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x14 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits"
bitfld.long 0x14 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x18 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable"
bitfld.long 0x18 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x1C "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts"
bitfld.long 0x1C 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x20 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register"
hexmask.long.byte 0x20 0.--7. 1. "EOI,Write with bit position of targeted interrupt"
line.long 0x24 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler"
hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value"
line.long 0x28 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter"
bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "MCU_MCRC64_0_REGS"
base ad:0x4D00000
tree.end
tree "MCU_MCSPI0_CFG"
base ad:0x4B00000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned"
bitfld.long 0x00 11.--15. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e"
hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored"
bitfld.long 0x04 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1"
group.long 0x10++0x03
line.long 0x00 "CFG_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3"
bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset [Optional]" "0,1"
rgroup.long 0x100++0x03
line.long 0x00 "CFG_REVISION,This register contains the hard coded RTL revision number"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_13,Reads returns 0"
hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21"
group.long 0x110++0x73
line.long 0x00 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface"
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED_14,Reads returns 0"
bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3"
rbitfld.long 0x00 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,WakeUp feature control" "0,1"
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bitfld.long 0x00 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1"
line.long 0x04 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0"
rbitfld.long 0x04 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x08 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1"
bitfld.long 0x08 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x08 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1"
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bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1"
bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1"
bitfld.long 0x08 11. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1"
bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1"
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bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1"
bitfld.long 0x08 7. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1"
bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1"
bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1"
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bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1"
bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1"
bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1"
bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1"
line.long 0x0C "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis"
hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reads return 0"
bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1"
bitfld.long 0x0C 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x0C 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1"
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bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1"
bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1"
bitfld.long 0x0C 11. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1"
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bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 7. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1"
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bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1"
line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis"
hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0"
bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode"
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x14 11. "SSB,Set status bit" "0,1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1"
bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1"
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bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1"
bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the CLKSPI.." "0,1"
bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface"
hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1"
bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1"
bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1"
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bitfld.long 0x18 2. "MS,Master/ Slave" "0,1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1"
bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1"
line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0"
bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x1C 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1"
line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0"
hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0"
hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EN,Channel Enable" "0,1"
line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x2C "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x30 "CFG_CH1CONF,This register is dedicated to the configuration of the channel"
bitfld.long 0x30 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x30 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x30 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x30 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x30 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x30 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x30 18. "IS,Input Select" "0,1"
bitfld.long 0x30 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x30 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x30 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x30 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x30 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x30 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x30 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x30 0. "PHA,SPICLK phase" "0,1"
line.long 0x34 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1"
hexmask.long 0x34 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x34 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x34 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x34 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x34 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x34 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x34 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x34 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x38 "CFG_CH1CTRL,This register is dedicated to enable the channel 1"
hexmask.long.word 0x38 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x38 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x38 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x38 0. "EN,Channel Enable" "0,1"
line.long 0x3C "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x40 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x44 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2"
bitfld.long 0x44 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x44 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x44 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x44 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x44 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x44 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x44 18. "IS,Input Select" "0,1"
bitfld.long 0x44 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x44 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x44 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x44 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x44 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x44 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x44 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x44 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x44 0. "PHA,SPICLK phase" "0,1"
line.long 0x48 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2"
hexmask.long 0x48 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x48 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x48 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x48 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x48 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x48 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x48 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x48 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x4C "CFG_CH2CTRL,This register is dedicated to enable the channel 2"
hexmask.long.word 0x4C 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x4C 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x4C 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x4C 0. "EN,Channel Enable" "0,1"
line.long 0x50 "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x54 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x58 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3"
bitfld.long 0x58 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x58 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x58 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x58 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x58 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x58 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x58 18. "IS,Input Select" "0,1"
bitfld.long 0x58 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x58 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x58 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x58 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x58 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x58 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x58 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x58 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x58 0. "PHA,SPICLK phase" "0,1"
line.long 0x5C "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3"
hexmask.long 0x5C 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x5C 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x5C 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x5C 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x5C 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x5C 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x5C 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x5C 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x60 "CFG_CH3CTRL,This register is dedicated to enable the channel 3"
hexmask.long.word 0x60 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x60 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x60 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x60 0. "EN,Channel Enable" "0,1"
line.long 0x64 "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x68 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x6C "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer"
hexmask.long.word 0x6C 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index"
hexmask.long.byte 0x6C 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.."
hexmask.long.byte 0x6C 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.."
line.long 0x70 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled"
rgroup.long 0x1A0++0x03
line.long 0x00 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled"
tree.end
tree "MCU_MCSPI1_CFG"
base ad:0x4B10000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned"
bitfld.long 0x00 11.--15. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e"
hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored"
bitfld.long 0x04 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1"
group.long 0x10++0x03
line.long 0x00 "CFG_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3"
bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset [Optional]" "0,1"
rgroup.long 0x100++0x03
line.long 0x00 "CFG_REVISION,This register contains the hard coded RTL revision number"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_13,Reads returns 0"
hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21"
group.long 0x110++0x73
line.long 0x00 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface"
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED_14,Reads returns 0"
bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3"
rbitfld.long 0x00 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,WakeUp feature control" "0,1"
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bitfld.long 0x00 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1"
line.long 0x04 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0"
rbitfld.long 0x04 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x08 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1"
bitfld.long 0x08 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x08 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1"
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bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1"
bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1"
bitfld.long 0x08 11. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1"
bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1"
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bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1"
bitfld.long 0x08 7. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1"
bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1"
bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1"
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bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1"
bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1"
bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1"
bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1"
line.long 0x0C "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis"
hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reads return 0"
bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1"
bitfld.long 0x0C 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x0C 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1"
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bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1"
bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1"
bitfld.long 0x0C 11. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1"
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bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 7. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1"
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bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1"
line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis"
hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0"
bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode"
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x14 11. "SSB,Set status bit" "0,1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1"
bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1"
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bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1"
bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the CLKSPI.." "0,1"
bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface"
hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1"
bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1"
bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1"
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bitfld.long 0x18 2. "MS,Master/ Slave" "0,1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1"
bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1"
line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0"
bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x1C 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1"
line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0"
hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0"
hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EN,Channel Enable" "0,1"
line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x2C "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x30 "CFG_CH1CONF,This register is dedicated to the configuration of the channel"
bitfld.long 0x30 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x30 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x30 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x30 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x30 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x30 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x30 18. "IS,Input Select" "0,1"
bitfld.long 0x30 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x30 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x30 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x30 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x30 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x30 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x30 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x30 0. "PHA,SPICLK phase" "0,1"
line.long 0x34 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1"
hexmask.long 0x34 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x34 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x34 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x34 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x34 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x34 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x34 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x34 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x38 "CFG_CH1CTRL,This register is dedicated to enable the channel 1"
hexmask.long.word 0x38 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x38 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x38 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x38 0. "EN,Channel Enable" "0,1"
line.long 0x3C "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x40 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x44 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2"
bitfld.long 0x44 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x44 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x44 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x44 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x44 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x44 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x44 18. "IS,Input Select" "0,1"
bitfld.long 0x44 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x44 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x44 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x44 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x44 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x44 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x44 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x44 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x44 0. "PHA,SPICLK phase" "0,1"
line.long 0x48 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2"
hexmask.long 0x48 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x48 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x48 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x48 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x48 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x48 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x48 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x48 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x4C "CFG_CH2CTRL,This register is dedicated to enable the channel 2"
hexmask.long.word 0x4C 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x4C 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x4C 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x4C 0. "EN,Channel Enable" "0,1"
line.long 0x50 "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x54 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x58 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3"
bitfld.long 0x58 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x58 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
newline
bitfld.long 0x58 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x58 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x58 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x58 19. "TURBO,Turbo mode" "0,1"
newline
bitfld.long 0x58 18. "IS,Input Select" "0,1"
bitfld.long 0x58 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x58 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x58 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x58 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
newline
bitfld.long 0x58 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x58 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x58 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x58 1. "POL,SPICLK polarity" "0,1"
newline
bitfld.long 0x58 0. "PHA,SPICLK phase" "0,1"
line.long 0x5C "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3"
hexmask.long 0x5C 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x5C 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x5C 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x5C 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x5C 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
newline
rbitfld.long 0x5C 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x5C 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x5C 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x60 "CFG_CH3CTRL,This register is dedicated to enable the channel 3"
hexmask.long.word 0x60 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x60 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x60 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x60 0. "EN,Channel Enable" "0,1"
line.long 0x64 "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x68 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x6C "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer"
hexmask.long.word 0x6C 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index"
hexmask.long.byte 0x6C 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.."
hexmask.long.byte 0x6C 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.."
line.long 0x70 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled"
rgroup.long 0x1A0++0x03
line.long 0x00 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled"
tree.end
tree "MCU_RTI0_CFG"
base ad:0x4880000
group.long 0x00++0x1B
line.long 0x00 "CFG_GCTRL,"
bitfld.long 0x00 16.--19. "NTUSEL,These bits determine which NTU input signal is used as external timebase" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
bitfld.long 0x00 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting" "stop counters in debug mode,continue counting in debug mode"
newline
bitfld.long 0x00 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1)" "stop counters,start counters"
bitfld.long 0x00 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters"
line.long 0x04 "CFG_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "CFG_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
bitfld.long 0x08 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "CFG_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "CFG_FRC0,"
line.long 0x14 "CFG_UC0,"
line.long 0x18 "CFG_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "CFG_CAFRC0,"
line.long 0x04 "CFG_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "CFG_FRC1,"
line.long 0x04 "CFG_UC1,"
line.long 0x08 "CFG_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "CFG_CAFRC1,"
line.long 0x04 "CFG_CAUC1,"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x08 0x10 0x18 )
group.long ($2+0x50)++0x03
line.long 0x00 "CFG_COMP$1,"
repeat.end
group.long 0x54++0x03
line.long 0x00 "CFG_UDCP0,"
group.long 0x5C++0x03
line.long 0x00 "CFG_UDCP1,"
group.long 0x64++0x03
line.long 0x00 "CFG_UDCP2,"
group.long 0x6C++0x0B
line.long 0x00 "CFG_UDCP3,"
line.long 0x04 "CFG_TBLCOMP,"
line.long 0x08 "CFG_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "CFG_SETINT,"
bitfld.long 0x00 18. "SETOVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 17. "SETOVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 11. "SETDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 3. "SETINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 2. "SETINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 1. "SETINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 0. "SETINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "CFG_CLEARINT,"
bitfld.long 0x04 18. "CLEAROVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 17. "CLEAROVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 16. "CLEARTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 11. "CLEARDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 3. "CLEARINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 2. "CLEARINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 1. "CLEARINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 0. "CLEARINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "CFG_INTFLAG,"
bitfld.long 0x08 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 3. "INT3,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "CFG_DWDCTRL,"
line.long 0x04 "CFG_DWDPRLD,"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value"
line.long 0x08 "CFG_WDSTATUS,"
bitfld.long 0x08 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 1. "DWDST,status flag and is maintained for compatibility reasons" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 0. "AWDST,User and priviledge mode (read)" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "CFG_WDKEY,"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate"
line.long 0x10 "CFG_DWDCNTR,"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF"
line.long 0x14 "CFG_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,User and privilege mode (read) privileged mode (write)" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "CFG_WWDSIZECTRL,"
line.long 0x1C "CFG_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "CFG_COMP0CLR,"
line.long 0x24 "CFG_COMP1CLR,"
line.long 0x28 "CFG_COMP2CLR,"
line.long 0x2C "CFG_COMP3CLR,"
tree.end
tree "MCU_TIMEOUT0_CFG"
base ad:0x4300000
rgroup.long 0x00++0x1B
line.long 0x00 "CFG_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket"
hexmask.long.byte 0x04 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard"
hexmask.long.byte 0x04 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard"
line.long 0x08 "CFG_INFO,The Info Register contains information about the current state of the gasket"
hexmask.long.word 0x08 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard"
hexmask.long.word 0x08 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard"
line.long 0x0C "CFG_ENABLE,The Enable Register contains the gasket enable"
bitfld.long 0x0C 0.--3. "EN,Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CFG_FLUSH,The Flush Register contains software flush control"
rbitfld.long 0x10 31. "EXT_FL,External Flush Value" "0,1"
bitfld.long 0x10 0.--3. "FL,Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions"
hexmask.long 0x14 0.--29. 1. "TO,The number of cycles in each eon"
line.long 0x18 "CFG_TIMER,The Timer Register contains the current value for free-running timer"
rbitfld.long 0x18 30.--31. "EON,Current eon" "0,1,2,3"
hexmask.long 0x18 0.--29. 1. "CNTR,Current value of the free-running timer"
group.long 0x20++0x2B
line.long 0x00 "CFG_ERR_RAW,This register contains the masked interrupt bits"
bitfld.long 0x00 2. "CMD,Raw Command Error Interrupt" "0,1"
bitfld.long 0x00 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1"
bitfld.long 0x00 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1"
line.long 0x04 "CFG_ERR,This register contains the masked interrupt bits"
bitfld.long 0x04 2. "CMD,Masked Command Error Interrupt" "0,1"
bitfld.long 0x04 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1"
bitfld.long 0x04 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1"
line.long 0x08 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits"
bitfld.long 0x08 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1"
bitfld.long 0x08 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1"
bitfld.long 0x08 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1"
line.long 0x0C "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits"
bitfld.long 0x0C 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1"
bitfld.long 0x0C 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1"
bitfld.long 0x0C 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1"
line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts"
bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3"
line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts"
bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3"
line.long 0x18 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt"
hexmask.long.word 0x18 16.--27. 1. "RID,Route ID Indicator"
bitfld.long 0x18 8.--11. "OID,Order ID Indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 2. "DIR,Direction Indicator" "0,1"
bitfld.long 0x18 1. "TYP,Type Indicator" "0,1"
bitfld.long 0x18 0. "VAL,Valid Indicator" "0,1"
line.long 0x1C "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt"
hexmask.long.word 0x1C 16.--27. 1. "TAG,Command Tag Indicator"
hexmask.long.word 0x1C 0.--11. 1. "CID,Command ID Indicator"
line.long 0x20 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt"
hexmask.long.word 0x20 16.--25. 1. "CBYTECNT,Current Bytecnt"
hexmask.long.word 0x20 0.--9. 1. "OBYTECNT,Original Bytecnt"
line.long 0x24 "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt"
line.long 0x28 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt"
tree.end
tree "MCU_TIMEOUT1_CFG"
base ad:0x4301000
rgroup.long 0x00++0x1B
line.long 0x00 "CFG_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_CFG,The Configuration Register contains information about the configuration of the gasket"
hexmask.long.byte 0x04 16.--23. 1. "NUM_WRITES,Total Number of slots in the write scoreboard"
hexmask.long.byte 0x04 0.--7. 1. "NUM_READS,Total Number of slots in the read scoreboard"
line.long 0x08 "CFG_INFO,The Info Register contains information about the current state of the gasket"
hexmask.long.word 0x08 16.--24. 1. "CUR_WRITES,Total Number of slots in the write scoreboard"
hexmask.long.word 0x08 0.--8. 1. "CUR_READS,Total Number of slots in the read scoreboard"
line.long 0x0C "CFG_ENABLE,The Enable Register contains the gasket enable"
bitfld.long 0x0C 0.--3. "EN,Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CFG_FLUSH,The Flush Register contains software flush control"
rbitfld.long 0x10 31. "EXT_FL,External Flush Value" "0,1"
bitfld.long 0x10 0.--3. "FL,Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "CFG_TIMEOUT,The Timeout Value Register contains the timeout value for scoreboarded transactions"
hexmask.long 0x14 0.--29. 1. "TO,The number of cycles in each eon"
line.long 0x18 "CFG_TIMER,The Timer Register contains the current value for free-running timer"
rbitfld.long 0x18 30.--31. "EON,Current eon" "0,1,2,3"
hexmask.long 0x18 0.--29. 1. "CNTR,Current value of the free-running timer"
group.long 0x20++0x2B
line.long 0x00 "CFG_ERR_RAW,This register contains the masked interrupt bits"
bitfld.long 0x00 2. "CMD,Raw Command Error Interrupt" "0,1"
bitfld.long 0x00 1. "UNEXP,Raw Unexpected Error Interrupt" "0,1"
bitfld.long 0x00 0. "TIMEOUT,Raw Timeout Error Interrupt" "0,1"
line.long 0x04 "CFG_ERR,This register contains the masked interrupt bits"
bitfld.long 0x04 2. "CMD,Masked Command Error Interrupt" "0,1"
bitfld.long 0x04 1. "UNEXP,Masked Unexpected Error Interrupt" "0,1"
bitfld.long 0x04 0. "TIMEOUT,Masked Timeout Error Interrupt" "0,1"
line.long 0x08 "CFG_ERR_MSK_SET,This register contains interrupt mask set bits"
bitfld.long 0x08 2. "CMD,Raw Command Error Interrupt Mask Set" "0,1"
bitfld.long 0x08 1. "UNEXP,Raw Unexpected Error Interrupt Mask Set" "0,1"
bitfld.long 0x08 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Set" "0,1"
line.long 0x0C "CFG_ERR_MSK_CLR,This register contains interrupt mask clear bits"
bitfld.long 0x0C 2. "CMD,Raw Command Error Interrupt Mask Clear" "0,1"
bitfld.long 0x0C 1. "UNEXP,Raw Unexpected Error Interrupt Mask Clear" "0,1"
bitfld.long 0x0C 0. "TIMEOUT,Raw Timeout Error Interrupt Mask Clear" "0,1"
line.long 0x10 "CFG_ERR_TM_INFO,This register contains information about timeout interrupts"
bitfld.long 0x10 0.--1. "CNT,Timeout Interrupt Count" "0,1,2,3"
line.long 0x14 "CFG_ERR_UN_INFO,This register contains information about unexpected interrupts"
bitfld.long 0x14 0.--1. "CNT,Unexpected Interrupt Count" "0,1,2,3"
line.long 0x18 "CFG_ERR_VAL,This register contains information about transaction that caused the interrupt"
hexmask.long.word 0x18 16.--27. 1. "RID,Route ID Indicator"
bitfld.long 0x18 8.--11. "OID,Order ID Indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 2. "DIR,Direction Indicator" "0,1"
bitfld.long 0x18 1. "TYP,Type Indicator" "0,1"
bitfld.long 0x18 0. "VAL,Valid Indicator" "0,1"
line.long 0x1C "CFG_ERR_TAG,This register contains information about transaction that caused the interrupt"
hexmask.long.word 0x1C 16.--27. 1. "TAG,Command Tag Indicator"
hexmask.long.word 0x1C 0.--11. 1. "CID,Command ID Indicator"
line.long 0x20 "CFG_ERR_BYT,This register contains information about transaction that caused the interrupt"
hexmask.long.word 0x20 16.--25. 1. "CBYTECNT,Current Bytecnt"
hexmask.long.word 0x20 0.--9. 1. "OBYTECNT,Original Bytecnt"
line.long 0x24 "CFG_ERR_ADDR_U,This register contains information about transaction that caused the interrupt"
line.long 0x28 "CFG_ERR_ADDR_L,This register contains information about transaction that caused the interrupt"
tree.end
tree "MCU_TIMER0_CFG"
base ad:0x4800000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "MCU_TIMER1_CFG"
base ad:0x4810000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "MCU_TIMER2_CFG"
base ad:0x4820000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "MCU_TIMER3_CFG"
base ad:0x4830000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "MCU_UART0"
base ad:0x4A00000
group.long 0x00++0x03
line.long 0x00 "MEM_DLL,Divisor Latches Low Register"
hexmask.long.byte 0x00 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value"
rgroup.long 0x00++0x03
line.long 0x00 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "RHR,Receive holding register"
group.long 0x00++0x07
line.long 0x00 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER"
line.long 0x04 "MEM_DLH,Divisor Latches High Register"
hexmask.long.byte 0x04 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value"
group.long 0x04++0x03
line.long 0x00 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt"
bitfld.long 0x00 6.--7. "NOT_USED2," "0,1,2,3"
newline
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x00 4. "NOT_USED1," "0,1"
newline
bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x03
line.long 0x00 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt"
bitfld.long 0x00 7. "EOF_IT," "0,1"
newline
bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x00 4. "STS_FIFO_TRIG_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x00 2. "LAST_RX_BYTE_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x07
line.long 0x00 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 7. "CTS_IT," "0,1"
newline
bitfld.long 0x00 6. "RTS_IT," "0,1"
newline
bitfld.long 0x00 5. "XOFF_IT," "0,1"
newline
bitfld.long 0x00 4. "SLEEP_MODE," "0,1"
newline
bitfld.long 0x00 3. "MODEM_STS_IT," "0,1"
newline
bitfld.long 0x00 2. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
line.long 0x04 "MEM_EFR,Enhanced Feature Register"
bitfld.long 0x04 7. "AUTO_CTS_EN,Auto-CTS enable bit" "Normal operation,Auto-CTS flow control is enabled i.e"
newline
bitfld.long 0x04 6. "AUTO_RTS_EN,Auto-RTS enable bit" "Normal operation,Auto- RTS flow control is enabled i.e"
newline
bitfld.long 0x04 5. "SPECIAL_CHAR_DETECT," "0,1"
newline
bitfld.long 0x04 4. "ENHANCED_EN,Enhanced functions write enable bit" "Disables writing to IER bits 4-7 FCR bits 4-5..,Enables writing to IER bits 4-7 FCR bits 4-5 and.."
newline
bitfld.long 0x04 0.--3. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "MEM_FCR,Notes: Bits 4 and 5 can only be written to when EFR[4] = 1 Bits 0 to 3 can be changed only when the baud clock is not running (DLL and DLH set to 0) See Table 31 for FCR[5:4] setting restriction when SCR[6]=1 See Table 32 for FCR[7:6] setting.."
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] =" "8 characters,16 characters,56 characters,60 characters If SCR[7] = 0 and.."
newline
bitfld.long 0x00 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] =" "8 spaces,16 spaces,32 spaces,56 spaces If SCR[6] = 0.."
newline
bitfld.long 0x00 3. "DMA_MODE,This register is considered if SCR[0] = 0" "0,1"
newline
bitfld.long 0x00 2. "TX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x00 1. "RX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x00 0. "FIFO_EN," "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner"
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner"
bitfld.long 0x00 7. "EOF_IT," "0,1"
newline
bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x00 4. "STS_FIFO_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x00 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x0B
line.long 0x00 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
newline
bitfld.long 0x00 1.--5. "IT_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0. "IT_PENDING," "0,1"
line.long 0x04 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception.Note: As soon as LCR[6] is set to 1. the TX line is forced to 0 and remains in this state as long as LCR[6] = 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "DIV_EN," "0,1"
newline
bitfld.long 0x04 6. "BREAK_EN,Break control bit" "0,1"
newline
bitfld.long 0x04 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]" "0,1"
newline
bitfld.long 0x04 4. "PARITY_TYPE1," "0,1"
newline
bitfld.long 0x04 3. "PARITY_EN," "0,1"
newline
bitfld.long 0x04 2. "NB_STOP,Specifies the number of stop bits" "0,1"
newline
bitfld.long 0x04 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3"
line.long 0x08 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x08 7. "RESERVED," "0,1"
newline
bitfld.long 0x08 6. "TCR_TLR," "0,1"
newline
bitfld.long 0x08 5. "XON_EN," "0,1"
newline
bitfld.long 0x08 4. "LOOPBACK_EN," "0,1"
newline
bitfld.long 0x08 3. "CD_STS_CH," "0,1"
newline
bitfld.long 0x08 2. "RI_STS_CH," "0,1"
newline
bitfld.long 0x08 1. "RTS,In loop back controls MSR[4]" "0,1"
newline
bitfld.long 0x08 0. "DTR," "0,1"
group.long 0x10++0x07
line.long 0x00 "MEM_XON1_ADDR1,XON1/ADDR1 Register"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes"
line.long 0x04 "MEM_LSR_CIR,"
bitfld.long 0x04 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x04 6. "RESERVED," "0,1"
newline
bitfld.long 0x04 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR)" "0,1"
newline
bitfld.long 0x04 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "MEM_LSR_IRDA,"
bitfld.long 0x00 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x00 6. "STS_FIFO_FULL," "0,1"
newline
bitfld.long 0x00 5. "RX_LAST_BYTE," "0,1"
newline
bitfld.long 0x00 4. "FRAME_TOO_LONG," "0,1"
newline
bitfld.long 0x00 3. "ABORT," "0,1"
newline
bitfld.long 0x00 2. "CRC," "0,1"
newline
bitfld.long 0x00 1. "STS_FIFO_E," "0,1"
newline
bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "MEM_LSR_UART,"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 7. "RX_FIFO_STS," "0,1"
newline
bitfld.long 0x00 6. "TX_SR_E," "0,1"
newline
bitfld.long 0x00 5. "TX_FIFO_E," "0,1"
newline
bitfld.long 0x00 4. "RX_BI," "0,1"
newline
bitfld.long 0x00 3. "RX_FE," "0,1"
newline
bitfld.long 0x00 2. "RX_PE," "0,1"
newline
bitfld.long 0x00 1. "RX_OE," "0,1"
newline
bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x07
line.long 0x00 "MEM_XON2_ADDR2,XON2/ADDR2 Register"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes"
line.long 0x04 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "NCD_STS,This bit is the complement of the DCD* input" "0,1"
newline
bitfld.long 0x04 6. "NRI_STS,This bit is the complement of the RI* input" "0,1"
newline
bitfld.long 0x04 5. "NDSR_STS,This bit is the complement of the DSR* input" "0,1"
newline
bitfld.long 0x04 4. "NCTS_STS,This bit is the complement of the CTS* input" "0,1"
newline
bitfld.long 0x04 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed" "0,1"
newline
bitfld.long 0x04 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high" "0,1"
newline
bitfld.long 0x04 1. "DSR_STS," "0,1"
newline
bitfld.long 0x04 0. "CTS_STS," "0,1"
group.long 0x18++0x03
line.long 0x00 "MEM_TCR,Transmission Control Register"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x07
line.long 0x00 "MEM_XOFF1,XOFF1 Register"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes"
line.long 0x04 "MEM_SPR,This read/write register does not control the module in anyway"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x04 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x03
line.long 0x00 "MEM_TLR,Trigger Level Register"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x0F
line.long 0x00 "MEM_XOFF2,XOFF2 Register"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes"
line.long 0x04 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR)"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "FRAME_END_MODE,IrDA mode only" "0,1"
newline
bitfld.long 0x04 6. "SIP_MODE,MIR/FIR modes only" "0,1"
newline
bitfld.long 0x04 5. "SCT,Store and control the transmission" "0,1"
newline
bitfld.long 0x04 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1"
newline
bitfld.long 0x04 3. "IR_SLEEP," "0,1"
newline
bitfld.long 0x04 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7"
line.long 0x08 "MEM_MDR2,IR-IrDA and IR-CIR modes only.MDR2[0] describes the status of the interrupt in IIR[5]"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x08 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1"
newline
bitfld.long 0x08 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block" "0,1"
newline
bitfld.long 0x08 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition" "0,1,2,3"
newline
bitfld.long 0x08 3. "UART_PULSE,UART mode only" "0,1"
newline
bitfld.long 0x08 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode" "0,1,2,3"
newline
rbitfld.long 0x08 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is" "0,1"
line.long 0x0C "MEM_SFLSR,IrDA modes only.Reading this register effectively reads frame status information from the status FIFO (this register doesn't physically exist)"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0C 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 4. "OE_ERROR," "0,1"
newline
bitfld.long 0x0C 3. "FRAME_TOO_LONG_ERROR," "0,1"
newline
bitfld.long 0x0C 2. "ABORT_DETECT," "0,1"
newline
bitfld.long 0x0C 1. "CRC_ERROR," "0,1"
newline
bitfld.long 0x0C 0. "RESERVED0," "0,1"
group.long 0x28++0x07
line.long 0x00 "MEM_TXFLL,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes)"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
line.long 0x04 "MEM_RESUME,IR-IrDA and IR-CIR modes only.This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x04 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x07
line.long 0x00 "MEM_TXFLH,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes)"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "TXFLH,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "MEM_RXFLL,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x04 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x07
line.long 0x00 "MEM_SFREGL,IrDA modes only.The frame lengths of received frames are written into the status FIFO"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "SFREGL,LSB part of the frame length"
line.long 0x04 "MEM_RXFLH,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x04 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--3. "RXFLH,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x34++0x07
line.long 0x00 "MEM_SFREGH,IrDA modes only.The frame lengths of received frames are written into the status FIFO"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "SFREGH,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MEM_BLR,IrDA modes only.Note that BLR[6] is used to select whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR Mode"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "STS_FIFO_RESET,Status FIFO reset" "0,1"
newline
bitfld.long 0x04 6. "XBOF_TYPE,SIR xBOF select" "0,1"
newline
rbitfld.long 0x04 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x38++0x13
line.long 0x00 "MEM_UASR,UART Autobauding Status Register"
bitfld.long 0x00 6.--7. "PARITY_TYPE," "?,Parity space,Even Parity,Odd Parity"
newline
bitfld.long 0x00 5. "BIT_BY_CHAR," "0,1"
newline
bitfld.long 0x00 0.--4. "SPEED,Used to report the speed identified" "No speed identified,115200 bauds,57600 bauds,38400 bauds,28800 bauds,19200 bauds,14400 bauds,9600 bauds,4800 bauds,2400 bauds,1200 bauds,?..."
line.long 0x04 "MEM_ACREG,IR-IrDA and IR-CIR modes only"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "PULSE_TYPE,SIR pulse width select" "0,1"
newline
bitfld.long 0x04 6. "SD_MOD,Primary output used to configure transceivers" "0,1"
newline
bitfld.long 0x04 5. "DIS_IR_RX," "0,1"
newline
bitfld.long 0x04 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt" "0,1"
newline
bitfld.long 0x04 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission" "0,1"
newline
bitfld.long 0x04 2. "SCTX_EN,Store and controlled TX start" "0,1"
newline
bitfld.long 0x04 1. "ABORT_EN,Frame Abort" "0,1"
newline
bitfld.long 0x04 0. "EOT_EN,EOT [end of transmission] bit" "0,1"
line.long 0x08 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x08 7. "RX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x08 6. "TX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x08 5. "DSR_IT," "0,1"
newline
bitfld.long 0x08 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1"
newline
bitfld.long 0x08 3. "TX_EMPTY_CTL_IT," "0,1"
newline
bitfld.long 0x08 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3"
newline
bitfld.long 0x08 0. "DMA_MODE_CTL," "0,1"
line.long 0x0C "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0C 3.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 2. "DMA_COUNTER_RST," "0,1"
newline
rbitfld.long 0x0C 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1"
newline
rbitfld.long 0x0C 0. "TX_FIFO_FULL," "0,1"
line.long 0x10 "MEM_EBLR,IR-IrDA and IR-CIR modes only.In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,"
newline
abitfld.long 0x10 0.--7. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification" "0x00=feature disabled,0x01=generate RX_STOP interrupt after receiving..,0xFF=generate RX_STOP interrupt after receiving.."
rgroup.long 0x50++0x57
line.long 0x00 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module"
bitfld.long 0x00 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function revision number of module"
newline
bitfld.long 0x00 11.--15. "RTL,Rtl revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x04 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3"
newline
bitfld.long 0x04 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1"
newline
bitfld.long 0x04 1. "SOFTRESET,Software reset" "0,1"
newline
bitfld.long 0x04 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
line.long 0x08 "MEM_SYSS,"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x08 1.--7. 1. "RESERVED,"
newline
bitfld.long 0x08 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x0C "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0C 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
newline
bitfld.long 0x0C 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0C 5. "EVENT_5_RHR_INTERRUPT," "0,1"
newline
bitfld.long 0x0C 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 1. "EVENT_1_DSR_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x10 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x10 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]"
line.long 0x14 "MEM_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x14 0.--7. 1. "RXFIFO_LVL,"
line.long 0x18 "MEM_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x18 0.--7. 1. "TXFIFO_LVL,"
line.long 0x1C "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x1C 3.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 2. "RHR_IT_DIS," "0,1"
newline
bitfld.long 0x1C 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt" "0,1"
newline
bitfld.long 0x1C 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt" "0,1"
line.long 0x20 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,"
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rbitfld.long 0x20 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x20 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1"
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bitfld.long 0x20 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1"
line.long 0x24 "MEM_FREQ_SEL,Sample per bit value selector"
hexmask.long.byte 0x24 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used"
line.long 0x28 "MEM_ABAUD_1ST_CHAR,Unused"
line.long 0x2C "MEM_BAUD_2ND_CHAR,Unused"
line.long 0x30 "MEM_MDR3,Mode definition register 3"
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED2,"
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bitfld.long 0x30 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
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bitfld.long 0x30 3. "DIR_POL,RS-485 External Transceiver Direction Polarity" "TX,TX"
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bitfld.long 0x30 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1"
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bitfld.long 0x30 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1"
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bitfld.long 0x30 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1"
line.long 0x34 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level.MDR3[2] SET_TX_DMA_THRESHOLD must be one and must be value + tx_trigger_level <= 64 (TX FIFO size).If not. 64-tx_trigger_level will be used w/o modifying the value of this register"
bitfld.long 0x34 0.--5. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "MEM_MDR4,Mode definition register 4"
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED1,"
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rbitfld.long 0x38 7. "RESERVED," "0,1"
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bitfld.long 0x38 6. "MODE9,9-bit character length" "0,1"
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bitfld.long 0x38 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7"
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bitfld.long 0x38 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7"
line.long 0x3C "MEM_EFR2,Enhanced Features Register 2"
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED1,"
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bitfld.long 0x3C 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
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bitfld.long 0x3C 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
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bitfld.long 0x3C 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
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bitfld.long 0x3C 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
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bitfld.long 0x3C 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
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bitfld.long 0x3C 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1"
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bitfld.long 0x3C 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1"
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bitfld.long 0x3C 0. "ENDIAN,Endianness" "0,1"
line.long 0x40 "MEM_ECR,Enhanced Control register"
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED1,"
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rbitfld.long 0x40 6.--7. "RESERVED," "0,1,2,3"
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bitfld.long 0x40 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
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bitfld.long 0x40 4. "TX_EN,Enables/Disables the transmitter" "0,1"
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bitfld.long 0x40 3. "RX_EN,Enables/Disables the receiver" "0,1"
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bitfld.long 0x40 2. "TX_RST,Writing '1' resets the transmitter" "0,1"
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bitfld.long 0x40 1. "RX_RST,Writing '1' resets the receiver" "0,1"
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bitfld.long 0x40 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1"
line.long 0x44 "MEM_TIMEGUARD,Timeguard"
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,"
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hexmask.long.byte 0x44 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices"
line.long 0x48 "MEM_TIMEOUTL,Timeout lower byte"
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,"
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hexmask.long.byte 0x48 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0"
line.long 0x4C "MEM_TIMEOUTH,Timeout higher byte"
hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,"
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hexmask.long.byte 0x4C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0"
line.long 0x50 "MEM_SCCR,Smartcard (ISO7816) mode Control Register"
hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED1,"
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bitfld.long 0x50 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error" "0,1"
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bitfld.long 0x50 6. "INACK,Inhibit NACK when receiving even if an error is received" "0,1"
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rbitfld.long 0x50 3.--5. "RESERVED," "0,1,2,3,4,5,6,7"
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bitfld.long 0x50 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge" "0,1,2,3,4,5,6,7"
line.long 0x54 "MEM_ERHR,Extended Receive Holding Register"
hexmask.long.tbyte 0x54 9.--31. 1. "RESERVED,"
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hexmask.long.word 0x54 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR"
group.long 0xA4++0x0F
line.long 0x00 "MEM_ETHR,Extended Transmit Holding Register"
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,"
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hexmask.long.word 0x00 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR"
line.long 0x04 "MEM_MAR,Multidrop Address Register"
hexmask.long.byte 0x04 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x08 "MEM_MMR,Multidrop Mask Register"
hexmask.long.byte 0x08 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0x0C "MEM_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0x0C 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
tree "MMCSD0_CTL_CFG"
base ad:0xFA10000
group.word 0x00++0x11
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_lo, This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10. "
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_hi, This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10. "
line.word 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_block_size,This register is used to configure the number of bytes in a data block"
bitfld.word 0x04 12.--14. "SDMA_BUF_SIZE, To perform long DMA transfer System Address register shall be updated at every system boundary during DMA transfer" "0,1,2,3,4,5,6,7"
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hexmask.word 0x04 0.--11. 1. "XFER_BLK_SIZE, This field specifies the block size for block data transfers for CMD17 CMD18 CMD24 CMD25 and CMD53"
line.word 0x06 "SDHC_WRAP__CTL_CFG__CTLCFG_block_count,This register is used to configure the number of data blocks"
line.word 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_lo,This register contains Lower bits of SD Command Argument"
line.word 0x0A "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_hi,This register contains higher bits of SD Command Argument"
line.word 0x0C "SDHC_WRAP__CTL_CFG__CTLCFG_transfer_mode,This register is used to control the operations of data transfers"
bitfld.word 0x0C 8. "RESP_INTR_DIS, Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "0,1"
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bitfld.word 0x0C 7. "RESP_ERR_CHK_ENA, Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "0,1"
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bitfld.word 0x0C 6. "RESP_TYPE, When response error check is enabled this bit selects either R1 or R5 response types" "0,1"
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bitfld.word 0x0C 5. "MULTI_BLK_SEL, This bit enables multiple block data transfers" "0,1"
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bitfld.word 0x0C 4. "DATA_XFER_DIR, This bit defines the direction of data transfers" "0,1"
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bitfld.word 0x0C 2.--3. "AUTO_CMD_ENA, There are three methods to stop Multiple-block read and write operation" "0,1,2,3"
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bitfld.word 0x0C 1. "BLK_CNT_ENA, This bit is used to enable the Block count register which is only relevant for multiple block transfers" "0,1"
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bitfld.word 0x0C 0. "DMA_ENA,DMA can be enabled only if DMA Support bit in the Capabilities register is set" "0,1"
line.word 0x0E "SDHC_WRAP__CTL_CFG__CTLCFG_command,This register is used to program the Command for host controller"
bitfld.word 0x0E 8.--13. "CMD_INDEX, This bit shall be set to the command number [CMD0-63 ACMD0-63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x0E 6.--7. "CMD_TYPE, There are three types of special commands" "0,1,2,3"
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bitfld.word 0x0E 5. "DATA_PRESENT, This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line" "0,1"
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bitfld.word 0x0E 4. "CMD_INDEX_CHK_ENA, If this bit is set to 1 the HC shall check the index field in the response to see if it has the same value as the command index" "0,1"
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bitfld.word 0x0E 3. "CMD_CRC_CHK_ENA, If this bit is set to 1 the HC shall check the CRC field in the response" "0,1"
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bitfld.word 0x0E 2. "SUB_CMD,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17]" "0,1"
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bitfld.word 0x0E 0.--1. "RESP_TYPE_SEL, Response Type Select" "0,1,2,3"
line.word 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_response,This register is used to store responses from SD Cards"
group.long 0x20++0x07
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_data_port,This register is used to access internal buffer"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_presentstate,The Host Driver can get status of the Host Controller from this 32-bit read-only register"
bitfld.long 0x04 31. "UHS2_IF_DETECTION, This status indicates whether a card supports UHS-II IF" "0,1"
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bitfld.long 0x04 30. "UHS2_IF_LANE_SYNC, This status indicates whether lane is synchronized in UHS-II mode" "0,1"
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bitfld.long 0x04 29. "UHS2_DORMANT, This status indicates whether UHS-II Ianes enterDormant state" "0,1"
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bitfld.long 0x04 28. "SUB_COMMAND_STS, The Command register and Response register are commonly used for main command and sub command" "Main Command Status,Sub Command Status"
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bitfld.long 0x04 27. "CMD_NOT_ISS_BY_ERR, Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error" "No error for issuing a command,Command cannot be issued"
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bitfld.long 0x04 24. "SDIF_CMDIN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 23. "SDIF_DAT3IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 22. "SDIF_DAT2IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 21. "SDIF_DAT1IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 20. "SDIF_DAT0IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 19. "WRITE_PROTECT, The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin" "0,1"
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bitfld.long 0x04 18. "CARD_DETECT, This bit reflects the inverse value of the SDCD# pin" "0,1"
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bitfld.long 0x04 17. "CARD_STATE_STABLE, This bit is used for testing" "0,1"
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bitfld.long 0x04 16. "CARD_INSERTED, This bit indicates whether a card has been inserted" "0,1"
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bitfld.long 0x04 11. "BUF_RD_ENA, This status is used for non-DMA read transfers.This read only flag indicates that valid data exists in the host side buffer status" "0,1"
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bitfld.long 0x04 10. "BUF_WR_ENA, This status is used for non-DMA write transfers.This read only flag indicates if space is available for write data" "0,1"
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bitfld.long 0x04 9. "RD_XFER_ACTIVE, This status is used for detecting completion of a read transfer" "0,1"
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bitfld.long 0x04 8. "WR_XFER_ACTIVE, This status indicates a write transfer is active" "0,1"
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bitfld.long 0x04 7. "SDIF_DAT7IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 6. "SDIF_DAT6IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 5. "SDIF_DAT5IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 4. "SDIF_DAT4IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 3. "RETUNING_REQ, Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data" "0,1"
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bitfld.long 0x04 2. "DATA_LINE_ACTIVE, This bit indicates whether one of the DAT line on SD bus is in use" "0,1"
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bitfld.long 0x04 1. "INHIBIT_DAT, This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1" "0,1"
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bitfld.long 0x04 0. "INHIBIT_CMD, SD Mode If this bit is 0 it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line" "0,1"
group.byte 0x28++0x03
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control1,This register is used to program DMA modes. LED Control. Data Transfer Width. High Speed Enable. Card detect test level and signal selection"
bitfld.byte 0x00 7. "CD_SIG_SEL, This bit selects source for card detection" "0,1"
newline
bitfld.byte 0x00 6. "CD_TEST_LEVEL, This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not" "0,1"
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bitfld.byte 0x00 5. "EXT_DATA_WIDTH, This bit controls 8-bit bus width mode for embedded device" "0,1"
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bitfld.byte 0x00 3.--4. "DMA_SELECT, This field is used to select DMA type" "SDMA is selected,Not Used [New assignment is not allowed],?..."
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bitfld.byte 0x00 2. "HIGH_SPEED_ENA, This bit is optional" "0,1"
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bitfld.byte 0x00 1. "DATA_WIDTH, This bit selects the data width of the HC" "0,1"
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bitfld.byte 0x00 0. "LED_CONTROL, This bit is used to caution the user not to remove the card while the SD card is being accessed" "0,1"
line.byte 0x01 "SDHC_WRAP__CTL_CFG__CTLCFG_power_control,This register is used to program the SD Bus power and voltage level"
bitfld.byte 0x01 5.--7. "UHS2_VOLTAGE, This field determines supply voltage range to VDD2" "0,1,2,3,4,5,6,7"
newline
bitfld.byte 0x01 4. "UHS2_POWER, Setting this bit enables providing VDD2" "0,1"
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bitfld.byte 0x01 1.--3. "SD_BUS_VOLTAGE, By setting these bits the HD selects the voltage level for the SD card" "0,1,2,3,4,5,6,7"
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bitfld.byte 0x01 0. "SD_BUS_POWER, Before setting this bit the SD host driver shall set SD Bus Voltage Select" "0,1"
line.byte 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_block_gap_control,This register is used to program the block gap request. read wait control and interrupt at block gap"
bitfld.byte 0x02 7. "BOOT_ACK_ENA, To check for the boot acknowledge in boot operation" "0,1"
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bitfld.byte 0x02 6. "ALT_BOOT_MODE, To start boot code access in alternative mode" "0,1"
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bitfld.byte 0x02 5. "BOOT_ENABLE, To start boot code access" "0,1"
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bitfld.byte 0x02 4. "SPI_MODE, SPI mode enable bit" "0,1"
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bitfld.byte 0x02 3. "INTRPT_AT_BLK_GAP, This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle" "0,1"
newline
bitfld.byte 0x02 2. "RDWAIT_CTRL, The read wait function is optional for SDIO cards" "0,1"
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bitfld.byte 0x02 1. "CONTINUE, This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request" "0,1"
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bitfld.byte 0x02 0. "STOP_AT_BLK_GAP, This bit is used to stop executing a transaction at the next block gap for non- DMA SDMA and ADMA transfers" "0,1"
line.byte 0x03 "SDHC_WRAP__CTL_CFG__CTLCFG_wakeup_control,This register is used to program the wakeup functionality"
bitfld.byte 0x03 2. "CARD_REMOVAL, This bit enables wakeup event via Card removal assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit" "0,1"
newline
bitfld.byte 0x03 1. "CARD_INSERTION, This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit" "0,1"
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bitfld.byte 0x03 0. "CARD_INTERRUPT, This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status register.This bit can be set to 1 if FN_WUS [Wake Up Support] in CIS is set to 1" "0,1"
group.word 0x2C++0x01
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_clock_control,This register is used to program the Clock frequency select. generator select. Clock enable. Internal Clock state fields This register controls SDCLK in SD Mode and RCLK in UHS-II mode. "
abitfld.word 0x00 8.--15. "SDCLK_FRQSEL, This register is used to select the frequency of the SDCLK pin" "0x00=base clock[10MHz-63MHz] Setting 00h..,0x01=base clock divided by 2,0x02=base clock divided by 4,0x04=base clock divided by 8,0x08=base clock divided by 16,0x10=base clock divided by 32,0x20=base clock divided by 64,0x40=base clock divided by 128,0x80=base clock divided by 256"
newline
bitfld.word 0x00 6.--7. "SDCLK_FRQSEL_UPBITS, Bit 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select" "0,1,2,3"
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bitfld.word 0x00 5. "CLKGEN_SEL, This bit is used to select the clock generator mode in SDCLK Frequency Select" "0,1"
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bitfld.word 0x00 3. "PLL_ENA,This bit is added from Version 4.10 for Host Controller using PLL" "0,1"
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bitfld.word 0x00 2. "SD_CLK_ENA, The HC shall stop SDCLK when writing this bit to 0" "0,1"
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rbitfld.word 0x00 1. "INT_CLK_STABLE, This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1" "0,1"
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bitfld.word 0x00 0. "INT_CLK_ENA, This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event" "0,1"
group.byte 0x2E++0x01
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_timeout_control,The register sets the Data Timeout counter value"
bitfld.byte 0x00 0.--3. "COUNTER_VALUE, This value determines the interval by which DAT line time-outs are detected" "TMCLK * 2^13,TMCLK * 2^14,?..."
line.byte 0x01 "SDHC_WRAP__CTL_CFG__CTLCFG_software_reset,This register is used to program the software reset for data. command and for all"
bitfld.byte 0x01 2. "SWRST_FOR_DAT, Only part of data circuit is reset" "0,1"
newline
bitfld.byte 0x01 1. "SWRST_FOR_CMD, Software Reset For CMD Line Only part of command circuit is reset to be able to issue a command" "0,1"
newline
bitfld.byte 0x01 0. "SWRST_FOR_ALL, This reset affects the entire HC except for the card detection circuit" "0,1"
group.word 0x30++0x0F
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts,This register gives the status of all the interrupts"
rbitfld.word 0x00 15. "ERROR_INTR, If any of the bits in the Error Interrupt Status Register are set then this bit is set" "0,1"
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bitfld.word 0x00 14. "BOOT_COMPLETE, This status is set if the boot operation gets terminated" "0,1"
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bitfld.word 0x00 13. "RCV_BOOT_ACK, This status is set if the boot acknowledge is received from device" "0,1"
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rbitfld.word 0x00 12. "RETUNING_EVENT, This status is set if Re-Tuning Request in the Present State register changes from 0 to 1" "0,1"
newline
rbitfld.word 0x00 11. "INTC, This status is set if INT_C is enabled and INT_C# pin is in low level" "0,1"
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rbitfld.word 0x00 10. "INTB, This status is set if INT_B is enabled and INT_B# pin is in low level" "0,1"
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rbitfld.word 0x00 9. "INTA, This status is set if INT_A is enabled and INT_A# pin is in low level" "0,1"
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rbitfld.word 0x00 8. "CARD_INTR,When this status has been set and the Host Driver needs to start this interrupt service Card Interrupt Status Enable in the Normal Interrupt Status Enable register may be set to 0 in order to clear the card interrupt status latched in the.." "0,1"
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bitfld.word 0x00 7. "CARD_REM, This status is set if the Card Inserted in the Present State register changes from 1 to 0" "0,1"
newline
bitfld.word 0x00 6. "CARD_INS, This status is set if the Card Inserted in the Present State register changes from 0 to 1.When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed" "0,1"
newline
bitfld.word 0x00 5. "BUF_RD_READY, This status is set if the Buffer Read Enable changes from 0 to 1" "0,1"
newline
bitfld.word 0x00 4. "BUF_WR_READY, This status is set if the Buffer Write Enable changes from 0 to 1.In UHS-II mode this bit is set at FC [Flow Control] unit basis" "0,1"
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bitfld.word 0x00 3. "DMA_INTERRUPT, This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size regiser" "0,1"
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bitfld.word 0x00 2. "BLK_GAP_EVENT, If the Stop At Block Gap Request in the BlockGap Control Register is set this bit is set" "0,1"
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bitfld.word 0x00 1. "XFER_COMPLETE, This bit is set when a read / write transaction is completed" "Not complete,Command execution is completed"
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bitfld.word 0x00 0. "CMD_COMPLETE, SD Mode This bit is set when we get the end bit of the command response [Except Auto CMD12 and Auto CMD23] Note: Command Time-out Error has higher priority than Command Complete" "0,1"
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts,This register gives the status of the error interrupts"
bitfld.word 0x02 12. "HOST, Occurs when detecting ERROR in m_hresp[dma transaction] " "0,1"
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bitfld.word 0x02 11. "RESP,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution" "0,1"
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bitfld.word 0x02 10. "TUNING,This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure [Occurrence of an error during tuning procedure is indicated by Sampling Select]" "0,1"
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bitfld.word 0x02 9. "ADMA, This bit is set when the Host Controller detects errors during ADMA based data transfer" "0,1"
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bitfld.word 0x02 8. "AUTO_CMD, Auto CMD12 and Auto CMD23 use this error status.This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1" "0,1"
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bitfld.word 0x02 7. "CURR_LIMIT, By setting the SD Bus Power bit in the Power Control Register the HC is requested to supply power for the SD Bus" "0,1"
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bitfld.word 0x02 6. "DATA_ENDBIT, Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status" "0,1"
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bitfld.word 0x02 5. "DATA_CRC, Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 010" "0,1"
newline
bitfld.word 0x02 4. "DATA_TIMEOUT, Occurs when detecting one of following timeout conditions: 1" "0,1"
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bitfld.word 0x02 3. "CMD_INDEX, Occurs if a Command Index error occurs in the Command Response" "0,1"
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bitfld.word 0x02 2. "CMD_ENDBIT, Occurs when detecting that the end bit of a command response is 0" "0,1"
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bitfld.word 0x02 1. "CMD_CRC, Command CRC Error is generated in two cases" "0,1"
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bitfld.word 0x02 0. "CMD_TIMEOUT, Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command" "0,1"
line.word 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts_ena,This register is used to enable the normal interrupt status register fields"
rbitfld.word 0x04 15. "BIT15_FIXED0, The HC shall control error Interrupts using the Error Interrupt Status Enable register" "0,1"
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bitfld.word 0x04 14. "BOOT_COMPLETE, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x04 13. "RCV_BOOT_ACK, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x04 12. "RETUNING_EVENT," "Masked,Enabled"
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bitfld.word 0x04 11. "INTC, If this bit is set to 0 the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 10. "INTB, If this bit is set to 0 the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 9. "INTA, If this bit is set to 0 the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 8. "CARD_INTERRUPT, If this bit is set to 0 the HC shall clear Interrupt request to the System" "0,1"
newline
bitfld.word 0x04 7. "CARD_REMOVAL, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x04 6. "CARD_INSERTION, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x04 5. "BUF_RD_READY, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x04 4. "BUF_WR_READY, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x04 3. "DMA_INTERRUPT, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x04 2. "BLK_GAP_EVENT, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x04 1. "XFER_COMPLETE, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x04 0. "CMD_COMPLETE, '0' Masked '1' Enabled " "0,1"
line.word 0x06 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts_ena,This register is used to enable the Error Interrupt Status register fields"
bitfld.word 0x06 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3"
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bitfld.word 0x06 12. "HOST, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x06 11. "RESP, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 10. "TUNING, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 9. "ADMA, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 8. "AUTO_CMD, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 7. "CURR_LIMIT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 6. "DATA_ENDBIT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 5. "DATA_CRC, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 4. "DATA_TIMEOUT, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x06 3. "CMD_INDEX, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x06 2. "CMD_ENDBIT, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x06 1. "CMD_CRC, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 0. "CMD_TIMEOUT, '0' Masked '1' Enabled " "0,1"
line.word 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sig_ena,This register is used to enable the Normal Interrupt Signal register"
rbitfld.word 0x08 15. "BIT15_FIXED0, The HD shall control error Interrupts using the Error Interrupt Signal Enable register" "0,1"
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bitfld.word 0x08 14. "BOOT_COMPLETE, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 13. "RCV_BOOT_ACK, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x08 12. "RETUNING_EVENT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 11. "INTC, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x08 10. "INTB, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x08 9. "INTA, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 8. "CARD_INTERRUPT, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x08 7. "CARD_REMOVAL, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x08 6. "CARD_INSERTION, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x08 5. "BUF_RD_READY, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x08 4. "BUF_WR_READY, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 3. "DMA_INTERRUPT, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x08 2. "BLK_GAP_EVENT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 1. "XFER_COMPLETE, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 0. "CMD_COMPLETE, '0' Masked '1' Enabled " "0,1"
line.word 0x0A "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sig_ena,This register is used to enable Error Interrupt Signal register"
bitfld.word 0x0A 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3"
newline
bitfld.word 0x0A 12. "HOST, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x0A 11. "RESP, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 10. "TUNING, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 9. "ADMA, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 8. "AUTO_CMD, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 7. "CURR_LIMIT, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x0A 6. "DATA_ENDBIT, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x0A 5. "DATA_CRC, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x0A 4. "DATA_TIMEOUT, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x0A 3. "CMD_INDEX, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x0A 2. "CMD_ENDBIT, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x0A 1. "CMD_CRC, '0' Masked '1' Enabled " "0,1"
newline
bitfld.word 0x0A 0. "CMD_TIMEOUT, '0' Masked '1' Enabled " "0,1"
line.word 0x0C "SDHC_WRAP__CTL_CFG__CTLCFG_autocmd_err_sts, This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD 23 "
bitfld.word 0x0C 7. "CMD_NOT_ISSUED, Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error [D04- D01] in this register" "0,1"
newline
bitfld.word 0x0C 5. "RESP, This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or Auto CMD23" "0,1"
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bitfld.word 0x0C 4. "INDEX, Occurs if the Command Index error occurs in response to a command" "0,1"
newline
bitfld.word 0x0C 3. "ENDBIT, Occurs when detecting that the end bit of command response is 0" "0,1"
newline
bitfld.word 0x0C 2. "CRC, Occurs when detecting a CRC error in the command response" "0,1"
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bitfld.word 0x0C 1. "TIMEOUT, Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command.If this bit is set to 1 the other error status bits [D04 - D02] are meaningless" "0,1"
newline
bitfld.word 0x0C 0. "ACMD12_NOT_EXEC, If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12" "0,1"
line.word 0x0E "SDHC_WRAP__CTL_CFG__CTLCFG_host_control2,This register is used to program UHS Select Mode.UHS Select Mode.Driver Strength Select.Execute Tuning.Sampling Clock Select.Asynchronous Interrupt Enable and Preset value enable "
bitfld.word 0x0E 15. "PRESET_VALUE_ENA, Host Controller Version 3.00 supports this bit" "0,1"
newline
bitfld.word 0x0E 14. "ASYNCH_INTR_ENA, This bit can be set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the Capabilities register" "0,1"
newline
bitfld.word 0x0E 13. "BIT64_ADDRESSING, This field is effective when Host Version 4.00 Enable is set to 1" "0,1"
newline
bitfld.word 0x0E 12. "HOST_VER40_ENA, This bit selects either Version 3.00 compatible mode or Ver4.mode" "0,1"
newline
bitfld.word 0x0E 11. "CMD23_ENA, In memory card initialization Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]" "0,1"
newline
bitfld.word 0x0E 10. "ADMA2_LEN_MODE, This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit" "0,1"
newline
bitfld.word 0x0E 9. "DRIVER_STRENGTH2, This is the programmed Drive STrength output and Bit[2] of the sdhccore_drivestrength value" "0,1"
newline
bitfld.word 0x0E 8. "UHS2_INTF_ENABLE, This bit is used to enable UHS-II Interface" "0,1"
newline
bitfld.word 0x0E 7. "SAMPLING_CLK_SELECT, This bit is set by tuning procedure when Execute Tuning is cleared" "0,1"
newline
bitfld.word 0x0E 6. "EXECUTE_TUNING, This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed" "0,1"
newline
bitfld.word 0x0E 4.--5. "DRIVER_STRENGTH1, Host Controller output driver in 1.8V signaling is selected by this bit" "0,1,2,3"
newline
bitfld.word 0x0E 3. "V1P8_SIGNAL_ENA, This bit controls voltage regulator for I/O cell" "0,1"
newline
bitfld.word 0x0E 0.--2. "UHS_MODE_SELECT, This field is used to select one of UHS-I modes or UHS-II mode.In case of UHS-I mode this field is effective when 1.8V Signal-ing Enable is set to 1" "0,1,2,3,4,5,6,7"
rgroup.quad 0x40++0x0F
line.quad 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_capabilities, This register provides the HD with information specific to the HC implementation"
bitfld.quad 0x00 63. "HS400_SUPPORT, 1 HS400 is Supported 0 HS400 is Not Supported " "0,1"
newline
bitfld.quad 0x00 60. "VDD2_1P8_SUPPORT, This field indicates that support of VDD2 on Host system" "0,1"
newline
bitfld.quad 0x00 59. "ADMA3_SUPPORT, This field indicates that support of ADMA3 on Host Controller" "0,1"
newline
bitfld.quad 0x00 57. "SPI_BLK_MODE, This field indicates whether SPI Block Mode is supported or not" "0,1"
newline
bitfld.quad 0x00 56. "SPI_SUPPORT, This field indicates whether SPI Mode is supported or not" "0,1"
newline
hexmask.quad.byte 0x00 48.--55. 1. "CLOCK_MULTIPLIER, This field indicates clock multiplier value of programmable clock generator"
newline
bitfld.quad 0x00 46.--47. "RETUNING_MODES, This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver" "0,1,2,3"
newline
bitfld.quad 0x00 45. "TUNING_FOR_SDR50, If this bit is set to 1 this Host Controller requires tuning to operate SDR50" "0,1"
newline
bitfld.quad 0x00 40.--43. "RETUNING_TIMER_CNT, This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3" "Get information via other source,1 seconds,2 seconds,4 seconds,8 seconds ------ n = 2[n-1] seconds,?,?,?,?,?,?,1024 seconds,?,?,?,Ch = Reserved"
newline
bitfld.quad 0x00 38. "DRIVERD_SUPPORT, This bit indicates support of Driver Type D for 1.8 Signaling" "0,1"
newline
bitfld.quad 0x00 37. "DRIVERC_SUPPORT, This bit indicates support of Driver Type C for 1.8 Signaling" "0,1"
newline
bitfld.quad 0x00 36. "DRIVERA_SUPPORT, This bit indicates support of Driver Type A for 1.8 Signaling" "0,1"
newline
bitfld.quad 0x00 35. "UHS2_SUPPORT, This bit indicates whether Host controller supports UHS-II" "0,1"
newline
bitfld.quad 0x00 34. "DDR50_SUPPORT, This bit indicates whether DDR50 is supported or not" "0,1"
newline
bitfld.quad 0x00 33. "SDR104_SUPPORT, This bit indicates whether SDR104 is supported or not.SDR104 requires tuning" "0,1"
newline
bitfld.quad 0x00 32. "SDR50_SUPPORT, If SDR104 is supported this bit shall be set to 1" "0,1"
newline
bitfld.quad 0x00 30.--31. "SLOT_TYPE, This field indicates usage of a slot by a specific Host System" "0,1,2,3"
newline
bitfld.quad 0x00 29. "ASYNCH_INTR_SUPPORT, Refer to SDIO Specification Version 3.00 about asynchronous interrupt" "0,1"
newline
bitfld.quad 0x00 28. "ADDR_64BIT_SUPPORT_V3, IMeaning of this bit is different depends on Versions [Refer to Table 2-35 for more details]" "0,1"
newline
bitfld.quad 0x00 27. "ADDR_64BIT_SUPPORT_V4, This bit is added from Version 4.10" "0,1"
newline
bitfld.quad 0x00 26. "VOLT_1P8_SUPPORT, This bit indicates whether the HC supports 1.8V" "0,1"
newline
bitfld.quad 0x00 25. "VOLT_3P0_SUPPORT, This bit indicates whether the HC supports 3.0V" "0,1"
newline
bitfld.quad 0x00 24. "VOLT_3P3_SUPPORT, This bit indicates whether the HC supports 3.3V" "0,1"
newline
bitfld.quad 0x00 23. "SUSP_RES_SUPPORT, This bit indicates whether the HC supports Suspend / Resume functionality" "0,1"
newline
bitfld.quad 0x00 22. "SDMA_SUPPORT, This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly.Version 4.10 Host Controller shall support SDMA if ADMA2 is supported" "0,1"
newline
bitfld.quad 0x00 21. "HIGH_SPEED_SUPPORT, This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz [for SD]/ 20MHz to 52MHz [for MMC]" "0,1"
newline
bitfld.quad 0x00 19. "ADMA2_SUPPORT, '0' ADMA2 Not Supported '1' ADMA2 Supported " "0,1"
newline
bitfld.quad 0x00 18. "BUS_8BIT_SUPPORT, This bit indicates whether the Host Controller is capable of using 8-bit bus width mode" "0,1"
newline
bitfld.quad 0x00 16.--17. "MAX_BLK_LENGTH, This value indicates the maximum block size that the HD can read and write to the buffer in the HC" "0,1,2,3"
newline
hexmask.quad.byte 0x00 8.--15. 1. "BASE_CLK_FREQ, [1]6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00"
newline
bitfld.quad 0x00 7. "TIMEOUT_CLK_UNIT, This bit shows the unit of base clock frequency used to detect Data Timeout Error" "0,1"
newline
bitfld.quad 0x00 0.--5. "TIMEOUT_CLK_FREQ, This bit shows the base clock frequency used to detect Data Timeout Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.quad 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_max_current_cap,This register indicates maximum current capability for each voltage"
hexmask.quad.byte 0x08 32.--39. 1. "VDD2_1P8V,Maximum Current for 1.8V VDD2"
newline
hexmask.quad.byte 0x08 16.--23. 1. "VDD1_1P8V,Maximum Current for 1.8V VDD1"
newline
hexmask.quad.byte 0x08 8.--15. 1. "VDD1_3P0V, Maximum Current for 3.0V VDD1 "
newline
hexmask.quad.byte 0x08 0.--7. 1. "VDD1_3P3V, Maximum Current for 3.3V VDD1 "
group.word 0x50++0x03
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_ACMD_Err_Sts,This register is not physically implemented. rather it is an address where Auto CMD Error Status register can be written. Writing"
bitfld.word 0x00 7. "CMD_NOT_ISS, Force Event for Command Not Issued by AUTO CMD12 Error" "0,1"
newline
bitfld.word 0x00 5. "RESP, Force Event for AUTO CMD Response Error" "0,1"
newline
bitfld.word 0x00 4. "INDEX, Force Event for AUTO CMD Index Error" "0,1"
newline
bitfld.word 0x00 3. "ENDBIT, Force Event for AUTO CMD End Bit Error" "0,1"
newline
bitfld.word 0x00 2. "CRC, Force Event for AUTO CMD Timeout Error" "0,1"
newline
bitfld.word 0x00 1. "TIMEOUT, Force Event for AUTO CMD Timeout Error" "0,1"
newline
bitfld.word 0x00 0. "ACMD_NOT_EXEC, Force Event for AUTO CMD12 Not Executed" "0,1"
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_Err_Int_Sts,This register is not physically implemented. rather it is an address where Error Interrupt Status register can be written"
bitfld.word 0x02 12. "HOST, Force Event for Host Error " "0,1"
newline
bitfld.word 0x02 11. "RESP, Force Event for Response Error " "0,1"
newline
bitfld.word 0x02 10. "TUNING, Force Event for Tuning Error" "0,1"
newline
bitfld.word 0x02 9. "ADMA, Force Event for ADMA Error" "0,1"
newline
bitfld.word 0x02 8. "AUTO_CMD, Force Event for Auto CMD Error" "0,1"
newline
bitfld.word 0x02 7. "CURR_LIM, Force Event for Current Limit Error" "0,1"
newline
bitfld.word 0x02 6. "DAT_ENDBIT, Force Event for Data End Bit Error" "0,1"
newline
bitfld.word 0x02 5. "DAT_CRC, Force Event for Data CRC Error" "0,1"
newline
bitfld.word 0x02 4. "DAT_TIMEOUT, Force Event for Data Timeout Error" "0,1"
newline
bitfld.word 0x02 3. "CMD_INDEX, Force Event for Command Index Error " "0,1"
newline
bitfld.word 0x02 2. "CMD_ENDBIT, Force Event for Command End Bit Error" "0,1"
newline
bitfld.word 0x02 1. "CMD_CRC, Force Event for Command CRC Error" "0,1"
newline
bitfld.word 0x02 0. "CMD_TIMEOUT, Force Event for CMD Timeout Error" "0,1"
rgroup.byte 0x54++0x00
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_err_status,When the ADMA Error interrupt occur. this register holds the ADMA State in ADMA Error States field and ADMA System Address holds address around the error descriptor"
bitfld.byte 0x00 2. "ADMA_LENGTH_ERR, This error occurs in the following 2 cases" "0,1"
newline
bitfld.byte 0x00 0.--1. "ADMA_ERR_STATE, This field indicates the state of ADMA when error is occurred during ADMA data transfer" "0,1,2,3"
group.quad 0x58++0x07
line.quad 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_sys_address,This register contains the physical address used for ADMA data transfer"
repeat 10. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 10. )(list 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x12 0x14 )
rgroup.word ($2+0x60)++0x01
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value$1, This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value "
bitfld.word 0x00 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes" "0,1,2,3"
newline
bitfld.word 0x00 10. "CLOCK_GENSEL, This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator " "0,1"
newline
hexmask.word 0x00 0.--9. 1. "SDCLK_FRQSEL, 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system"
repeat.end
group.quad 0x78++0x07
line.quad 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_adma3_desc_address,The start address of Integrated DMA Descriptor is set to this register"
group.word 0x80++0x01
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_size,This register is used to configure the number of bytes in a data block"
bitfld.word 0x00 12.--14. "SDMA_BUF_BOUNDARY, When system memory is managed by paging SDMA data transfer is performed in unit of paging" "0,1,2,3,4,5,6,7"
newline
hexmask.word 0x00 0.--11. 1. "XFER_BLK_SIZE,This register specifies the block size of data packet"
group.long 0x84++0x03
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_count,This register is used to configure the number of data blocks"
group.byte 0x88++0x00
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command_pkt,UHS-II Command Packet image is set to this register"
group.word 0x9C++0x03
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_xfer_mode,This register is used to control the operations of data transfers"
bitfld.word 0x00 15. "DUPLEX_SELECT, Use of 2 lane half duplex mode is determined by Host Driver" "0,1"
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bitfld.word 0x00 14. "EBSY_WAIT, This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution" "0,1"
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bitfld.word 0x00 8. "RESP_INTR_DIS, Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "0,1"
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bitfld.word 0x00 7. "RESP_ERR_CHK_ENA, Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver.Only R1 or R5 can be checked" "0,1"
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bitfld.word 0x00 6. "RESP_TYPE, When response error check is enabled this bit selects either R1 or R5 response types" "0,1"
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bitfld.word 0x00 5. "BYTE_MODE, This bit specifies whether data transfer is in byte mode or block mode when Data Present is set to 1" "0,1"
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bitfld.word 0x00 4. "DATA_XFER_DIR, This bit specifies direction of data trans-fer when Data Present is set to 1" "Read [Card to Host],Write [Host to Card]"
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bitfld.word 0x00 1. "BLK_CNT_ENA, This bit specifies whether data transfer usesUHS-II Block Count register" "0,1"
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bitfld.word 0x00 0. "DMA_ENA,This bit selects whether DMA is used or not and is effective to a command with data transfer" "0,1"
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command,This register is used to program the Command for host controller"
bitfld.word 0x02 8.--12. "PKT_LENGTH,A command packet length which is set in the UHS-II Command Packet register is set to this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.word 0x02 6.--7. "CMD_TYPE, This field is used to distinguish a spe-cific command like abort command" "0,1,2,3"
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bitfld.word 0x02 5. "DATA_PRESENT,This bit specifies whether the command is accompanied by data packet" "0,1"
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bitfld.word 0x02 2. "SUB_COMMAND,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17].When issuing a main command this bit is set to 0 and when issuing a sub com-mand this bit is set to 1" "0,1"
rgroup.byte 0xA0++0x00
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_response,This register is used to store received UHS-II RES Packet image"
group.byte 0xB4++0x00
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message_select,This register is used to access internal buffer"
bitfld.byte 0x00 0.--1. "MSG_SEL,Host Controller holds 4 MSG packets in FIFO buffer.One of 4 MSGs can be read from the UHS-II MSG register [0BB-0B8h] by setting this register.[Assumed for debug usage.] '00' The latest MSG '01' One MSG before '10' Two MSGs before '11' Three.." "0,1,2,3"
rgroup.long 0xB8++0x03
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message,This register is used to access internal buffer"
hexmask.long.byte 0x00 24.--31. 1. "MSG_BYTE3, Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 16.--23. 1. "MSG_BYTE2, Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 8.--15. 1. "MSG_BYTE1, Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 0.--7. 1. "MSG_BYTE0, Host Controller holds 4 MSG packets in FIFO buffer"
group.word 0xBC++0x01
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_intr_status,This register shows receipt of INT MSG from which device "
group.byte 0xBE++0x01
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_select,UHS-II Device Select Register "
bitfld.byte 0x00 7. "INT_MSG_ENA, This bit enables receipt of INT MSG" "0,1"
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bitfld.byte 0x00 0.--3. "DEV_SEL,Host Controller holds an INT MSG packet per device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.byte 0x01 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_int_code,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register. "
group.word 0xC0++0x03
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_software_reset,UHS-II Software Reset Register "
bitfld.word 0x00 1. "HOST_SDTRAN_RESET,Host Driver set this bit to 1 to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs" "0,1"
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bitfld.word 0x00 0. "HOST_FULL_RESET,On issuing FULL_RESET CCMD Host Driver set this bit to 1 to reset Host Controller" "0,1"
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_timer_control,UHS-II Timeout Control Register"
bitfld.word 0x02 4.--7. "DEADLOCK_TIMEOUT_CTR, This value determines the deadlock period while host expecting to receive a packet [1 second]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x02 0.--3. "CMDRESP_TIMEOUT_CTR, This value determines the interval between com-mand packet and response packet [5ms]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC4++0x0B
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts,This register gives the status of all UHS-II interrupts"
bitfld.long 0x00 27.--31. "VENDOR_SPECFIC_ERR, Vendor may use this field for vendor specific error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 17. "DEADLOCK_TIMEOUT, Setting of this bit means that deadlock timeout occurs" "0,1"
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bitfld.long 0x00 16. "CMD_RESP_TIMEOUT, Setting of this bit means that RES Packet timeout occurs" "0,1"
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bitfld.long 0x00 15. "ADMA2_ADMA3, Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode" "0,1"
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bitfld.long 0x00 8. "EBSY, On receiving EBSY packet if the packet indicates an error this bit is set to 1" "0,1"
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bitfld.long 0x00 7. "UNRECOVERABLE, Setting of this bit means that Unrecoverable Error is set in a packet from a device" "0,1"
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bitfld.long 0x00 5. "TID, Setting of this bit means that TID Error occurs" "0,1"
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bitfld.long 0x00 4. "FRAMING, Setting of this bit means that Framing Error occurs during a packet receiving" "0,1"
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bitfld.long 0x00 3. "CRC, Setting of this bit means that CRC Error occurs during a packet receiving" "0,1"
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bitfld.long 0x00 2. "RETRY_EXPIRED, Setting of this bit means that Retry Counter Expired Error occurs during data transfer.If this bit is set either Framing Error or CRC Error in this register shall be set" "0,1"
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bitfld.long 0x00 1. "RESP_PKT, Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution" "0,1"
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bitfld.long 0x00 0. "HEADER, Setting of this bit means that Header Error occurs in a received packet" "0,1"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts_ena,This register is used to enable the UHS-II Error Interrupt Status register fields"
bitfld.long 0x04 27.--31. "VENDOR_SPECFIC, Setting this bit to 1 enables setting of Vendor Specific Error bit in the UHS-II Error Interrupt Status register" "Status is Disabled,Status is Enabled,?..."
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bitfld.long 0x04 17. "DEADLOCK_TIMEOUT, Setting this bit to 1 enables setting of Timeout for Dead lock bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 16. "CMD_RESP_TIMEOUT, Setting this bit to 1 enables setting of Timeout for CMD_RES bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 15. "ADMA2_ADMA3, Setting this bit to 1 enables setting of ADMA2/3 Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 8. "EBSY, Setting this bit to 1 enables setting of EBSY Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 7. "UNRECOVERABLE, Setting this bit to 1 enables setting of Unrecoverable Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 5. "TID, Setting this bit to 1 enables setting of TID Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 4. "FRAMING, Setting this bit to 1 enables setting of Framing Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 3. "CRC, Setting this bit to 1 enables setting of CRC Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 2. "RETRY_EXPIRED, Setting this bit to 1 enables setting of Retry Expired bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 1. "RESP_PKT, Setting this bit to 1 enables setting of RES Packet Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 0. "HEADER, Setting this bit to 1 enables setting of Header Error bit in the UHS-II Error Interrupt Status Register" "0,1"
line.long 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sig_ena,This register is used to generate UHS-II Interrupt signals"
bitfld.long 0x08 27.--31. "VENDOR_SPECFIC, Setting of a bit to 1 in this field enables generating interrupt signal when corre-spondent bit of Vendor Specific Error is set in the UHS-II Error Interrupt Status Register" "Interrupt Signal is Disabled,Interrupt Signal is Enabled,?..."
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bitfld.long 0x08 17. "DEADLOCK_TIMEOUT, Setting this bit to 1 enables generating interrupt signal when Timeout for Dead lock bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 16. "CMD_RESP_TIMEOUT, Setting this bit to 1 enables generating interrupt signal when Timeout for CMD_RES bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 15. "ADMA2_ADMA3, Setting this bit to 1 enables generating interrupt signal when ADMA2/3 Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 8. "EBSY, Setting this bit to 1 enables generating interrupt signal when EBSY Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 7. "UNRECOVERABLE, Setting this bit to 1 enables generating interrupt signal when Unrecoverable Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 5. "TID, Setting this bit to 1 enables generating interrupt signal when TID Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 4. "FRAMING, Setting this bit to 1 enables generating interrupt signal when Framing Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 3. "CRC, Setting this bit to 1 enables generating interrupt signal when CRC Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 2. "RETRY_EXPIRED_SIG_ENA, Setting this bit to 1 enables generating interrupt signal when Retry Expired bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 1. "RESP_PKT, Setting this bit to 1 enables generating interrupt signal when RES Packet Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 0. "HEADER,Setting this bit to 1 enables generating interrupt signal when Header Error bit is set in the UHS-II Error Interrupt Status Register" "0,1"
rgroup.word 0xE0++0x09
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_settings_ptr, This register is pointer for UHS-II settings. "
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_capabilities_ptr, This register is pointer for UHS-II Capabilities Register. "
line.word 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_test_ptr, This register is pointer for UHS-II Test Register. "
line.word 0x06 "SDHC_WRAP__CTL_CFG__CTLCFG_shared_bus_ctrl_ptr, This register is pointer for UHS-II Shared Bus Control Register. "
line.word 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_specfic_ptr, This register is pointer for UHS-II Vendor Specific Pointer Register. "
group.long 0xF4++0x07
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_boot_timeout_control,This is used to program the boot timeout value counter"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_register,Vendor register added for autogate sdclk. cmd11 power down timer. enhancedstrobe and eMMC hardware reset"
bitfld.long 0x04 16. "AUTOGATE_SDCLK,If this bit is set SD CLK will be gated automatically when there is no transfer" "0,1"
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hexmask.long.word 0x04 2.--15. 1. "CMD11_PD_TIMER,cmd11 power-down timer value "
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bitfld.long 0x04 1. "EMMC_HW_RESET,Hardware reset signal is generared for eMMC card when this bit is set " "0,1"
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bitfld.long 0x04 0. "ENHANCED_STROBE,This bit enables the enhanced strobe logic of the Host Controller" "0,1"
rgroup.word 0xFC++0x03
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_slot_int_sts,This register is used to read the interrupt signal for each slot"
hexmask.word.byte 0x00 0.--7. 1. "INTR_SIG, These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot"
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_host_controller_ver,This register is used to read the vendor version number and specification version number "
hexmask.word.byte 0x02 8.--15. 1. "VEN_VER_NUM, The Vendor Version Number is set to 0x10 [1.0] "
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abitfld.word 0x02 0.--7. "SPEC_VER_NUM, This status indicates the Host Controller Spec" "0x00=SD Host Controller Specification Version 1.00,0x01=SD Host Controller Specification Version..,0x02=SD Host Controller Specification Version 3.00,0x03=SD Host Controller Specification Version 4.00,0x04=SD Host Controller Specification Version.."
group.long 0x100++0x07
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_settings,Start Address of General settings is pointed by Pointer for UHS-II Setting Register. "
bitfld.long 0x00 8.--13. "NUMLANES, The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0. "POWER_MODE, This field determines either Fast mode or Low Power mode.Host and all devices connected to the host shall be set to the same mode" "0,1"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_settings,Start Address of PHY settings is pointed by Pointer for UHS-II Setting Register. "
bitfld.long 0x04 20.--23. "N_LSS_DIR,The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "N_LSS_SYN,The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 15. "HIBERNATE_ENA,After checking card capability of Hibernate mode if all devices support Hibernate mode this bit may be set" "0,1"
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bitfld.long 0x04 6.--7. "SPEED_RANGE,PLL multiplier is selected by this field.Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State" "0,1,2,3"
group.quad 0x108++0x07
line.quad 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_settings,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Setting Register. "
hexmask.quad.byte 0x00 32.--39. 1. "N_DATA_GAP, The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field"
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bitfld.quad 0x00 16.--17. "RETRY_COUNT, Data Burst retry count is set to this field" "0,1,2,3"
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hexmask.quad.byte 0x00 8.--15. 1. "HOST_NFCU, Host Driver sets the number of blocks in Data Burst [Flow Control] to this field.The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices"
rgroup.long 0x110++0x07
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_cap,Start Address of General Capabilities is pointed by Pointer for UHS-II Host Capabilities Register. "
bitfld.long 0x00 22.--23. "CORECFG_UHS2_BUS_TOPLOGY,This field indicates one of bus topologies configured by a Host system" "0,1,2,3"
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bitfld.long 0x00 18.--21. "CORECFG_UHS2_MAX_DEVICES,This field indicates the maximum number of devices supported by the Host Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--17. "DEVICE_TYPE,This field indicates device type configured by a Host system" "0,1,2,3"
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bitfld.long 0x00 14. "CFG_64BIT_ADDRESSING,This field indicates support of 64-bit addressing by the Host Controller" "0,1"
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bitfld.long 0x00 8.--13. "NUM_LANES,This field indicates support of lanes by the Host Controller.0 mean not supported and 1 means supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 4.--7. "GAP,This field indicates the maximum capability of host power supply for a group configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -Not used" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "DAP,This field indicates the maximum capability of host power supply for a device configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -360 mW [Default]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_cap,Start Address of PHY Capabilities is pointed by Pointer for UHS-II Host Capabilities Register. "
bitfld.long 0x04 20.--23. "N_LSS_DIR, This field indicates the minimum N_LSS_DIR required by the Host Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "N_LSS_SYN,This field indicates the minimum N_LSS_SYN required by the Host Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 6.--7. "SPEED_RANGE,This field indicates supported Speed Range by the Host Controller '00' Range A [Default] '01' Range A and Range B '10' Reserved '11' Reserved " "0,1,2,3"
rgroup.quad 0x118++0x07
line.quad 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_cap,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Capabilities Register. "
hexmask.quad.byte 0x00 32.--39. 1. "N_DATA_GAP,This field indicates the minimum number of data gap[DIDL] supported by the Host Controller. "
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hexmask.quad.word 0x00 20.--31. 1. "MAX_BLK_LENGTH,This field indicates maximum block length by the Host Controller"
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hexmask.quad.byte 0x00 8.--15. 1. "N_FCU, This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller.This value is determined by supported buffer size"
group.long 0x120++0x03
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_force_UHSII_Err_Int_Sts,This register is not physically implemented. rather it is an address where UHS-II Error Interrupt Status register can be written. "
bitfld.long 0x00 27.--31. "VENDOR_SPECIFIC,Force Event for Vendor Specific Error " "Not Affected,Vendor Specific Error Status is set,?..."
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bitfld.long 0x00 17. "TIMEOUT_DEADLOCK,Setting this bit forces the Host Controller to set Timeout for Deadlock in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 16. "TIMEOUT_CMD_RES,Setting this bit forces the Host Controller to set Timeout for CMD_RES in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 15. "ADMA,Setting this bit forces the Host Controller to set ADMA Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 8. "EBSY,Setting this bit forces the Host Controller to set EBSY Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 7. "UNRECOVERABLE,Setting this bit forces the Host Controller to set Unrecover-able Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 5. "TID,Setting this bit forces the Host Controller to set TID Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 4. "FRAMING,Setting this bit forces the Host Controller to set Framing Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 3. "CRC,Setting this bit forces the Host Controller to set CRC Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 2. "RETRY_EXPIRED,Setting this bit forces the Host Controller to set Retry Expired in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 1. "RES_PKT,Setting this bit forces the Host Controller to set RES Packet Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 0. "HEADER,Setting this bit forces the Host Controller to set Header Error in the UHS-II Error Interrupt Status register" "0,1"
rgroup.long 0x200++0x3B
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_version,This register provides information about the version of the eMMC CQ standard which is 285 implemented by the CQE. in BCD format"
bitfld.long 0x00 8.--11. "EMMC_MAJOR_VER_NUM, eMMC Major Version Number [digit left of decimal point] in BCD format " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "EMMC_MINOR_VER_NUM, eMMC Minor Version Number [digit right of decimal point] in BCD format " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EMMC_VERSION_SUFFIX, eMMC Version Suffix [2nd digit right of decimal point] in BCD format " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_capabilities,This register is reserved for capability indication. "
bitfld.long 0x04 12.--15. "CF_MUL, Internal Timer Clock Frequency Multiplier [ITCFMUL] ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the SQS polling period" "0.001 MHz,0.01 MHz,0.1 MHz,1 MHz,10 MHz Other values..,?..."
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hexmask.long.word 0x04 0.--9. 1. "CF_VAL, Internal Timer Clock Frequency Value [ITCFVAL] TCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the polling period when using periodic SEND_QUEUE_ STATUS [CMD13] polling"
line.long 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_config,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time. "
bitfld.long 0x08 12. "DCMD_ENA, Direct Command [DCMD] Enable This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor or a Direct Command Task Descriptor" "Task descriptor in slot #31 is a Data Transfer..,Task descriptor in slot #31 is a DCMD Task.."
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bitfld.long 0x08 8. "TASK_DESC_SIZE, Task Descriptor Size This bit indicates whether the task descriptor size is 128 bits or 64 bits as detailed in Data Structures section" "Task descriptor size is 64 bits,Task descriptor size is 128 bits"
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bitfld.long 0x08 0. "CQ_ENABLE, Command Queueing Enable Software shall write 1 this bit when in order to enable command queueing mode [i.e. enable CQE]" "0,1"
line.long 0x0C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_control,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time. "
bitfld.long 0x0C 8. "CLEAR_ALL_TASKS, Clear All Tasks Software shall write 1 this bit when it wants to clear all the tasks sent to the device" "0,1"
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bitfld.long 0x0C 0. "HALT_BIT, Halt Host software shall write 1 to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus" "0,1"
line.long 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts,This register indicates pending interrupts that require service"
bitfld.long 0x10 4. "TASK_ERROR, Task Error Interrupt [TERR] This bit is asserted when task error is detected due to invalid task descriptor " "0,1"
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bitfld.long 0x10 3. "TASK_CLEARED, Task Cleared [TCL] This status bit is asserted [if CQISTE.TCL=1] when a task clear operation is completed by CQE" "0,1"
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bitfld.long 0x10 2. "RESP_ERR_DET, Response Error Detected Interrupt [RED] This status bit is asserted [if CQISTE.RED=1] when a response is received with an error bit set in the device status field" "0,1"
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bitfld.long 0x10 1. "TASK_COMPLETE,Task Complete Interrupt [TCC] This status bit is asserted [if CQISTE.TCC=1] when atleast one of the following two conditions are met: [1] A task is completed and the INT bit is set in its Task Descriptor [2] Interrupt caused by Interrupt.." "0,1"
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bitfld.long 0x10 0. "HALT_COMPLETE, Halt Complete Interrupt [HAC] This status bit is asserted [if CQISTE.HAC=1] when halt bit in CQCTL register transitions from 0 to 1 indicating that host controller has completed its current ongoing task and has entered halt state" "0,1"
line.long 0x14 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts_ena,This register enables and disables the reporting of the corresponding interrupt to host soft-ware in 299 CQIS register"
bitfld.long 0x14 4. "TASK_ERROR, Task Error Interrupt Status Enable" "CQIS.TERR is disabled,CQIS.TERR will be set when its interrupt.."
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bitfld.long 0x14 3. "TASK_CLEARED, Task Cleared Status Enable [TCL]" "CQIS.TCL is disabled,CQIS.TCL will be set when its interrupt.."
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bitfld.long 0x14 2. "RESP_ERR_DET, Response Error Detected Status Enable [RED]" "CQIS.RED is disabled,CQIS.RED will be set when its interrupt.."
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bitfld.long 0x14 1. "TASK_COMPLETE, Task Complete Status Enable [TCC]" "CQIS.TCC is disabled,CQIS.TCC will be set when its interrupt.."
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bitfld.long 0x14 0. "HALT_COMPLETE, Halt Complete Status Enable [HAC]" "CQIS.HAC is disabled,CQIS.HAC will be set when its interrupt.."
line.long 0x18 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sig_ena,This register enables and disables the generation of interrupts to host software"
bitfld.long 0x18 4. "TASK_ERROR, Task Error Interrupt Signal Enable [TERR] When set and CQIS.TERR is asserted the CQE shall generate an interrupt " "0,1"
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bitfld.long 0x18 3. "TASK_CLEARED, Task Cleared Signal Enable [TCL] When set and CQIS.TCL is asserted the CQE shall generate an interrupt " "0,1"
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bitfld.long 0x18 2. "RESP_ERR_DET, Response Error Detected Signal Enable [TCC] When set and CQIS.RED is asserted the CQE shall generate an interrupt " "0,1"
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bitfld.long 0x18 1. "TASK_COMPLETE, Task Complete Signal Enable [TCC] When set and CQIS.TCC is asserted the CQE shall generate an interrupt " "0,1"
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bitfld.long 0x18 0. "HALT_COMPLETE, Halt Complete Signal Enable [HAC] When set and CQIS.HAC is asserted the CQE shall generate an interrupt " "0,1"
line.long 0x1C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_coalescing,This register controls the interrupt coalescing feature. "
bitfld.long 0x1C 31. "CQINTCOALESC_ENABLE, When set to 0 by software command responses are neither counted nor timed" "0,1"
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bitfld.long 0x1C 20. "IC_STATUS, This bit indicates to software whether any tasks [with INT=0] have completed and counted towards interrupt coalescing [i.e. ICSB is set if and only if IC counter > 0]" "No task completions have occurred since last..,At least one task completion has been counted.."
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bitfld.long 0x1C 8.--12. "CTR_THRESHOLD, Interrupt Coalescing Counter Threshold [ICCTH]: Software uses this field to configure the number of task completions [only tasks with INT=0 in the Task Descriptor] which are required in order to generate an interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x1C 0.--6. 1. "TIMEOUT_VAL, Interrupt Coalescing Timeout Value [ICTOVAL]: Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt"
line.long 0x20 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory. "
line.long 0x24 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr_upbits,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory. "
line.long 0x28 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_door_bell,Using this register. software triggers CQE to process a new task. "
line.long 0x2C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_comp_notif,This register is used by CQE to notify software about completed tasks. "
line.long 0x30 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_queue_status,This register stores the most recent value of the device s queue status. "
line.long 0x34 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_pending_tasks,This register indicates to software which tasks are queued in the device. awaiting execution. "
line.long 0x38 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_clear,This register is used for removing an outstanding task in the CQE"
group.long 0x240++0x0B
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config1,The register controls the when SEND_QUEUE_STATUS commands are sent. "
bitfld.long 0x00 16.--19. "CMD_BLK_CNTR,This field indicates to CQE when to send SEND_QUEUE_STATUS [CMD13] command to inquire the status of the devices task queue.A value of n means CQE shall send status command on the CMD line during the transfer of data block BLOCK_CNT-n on the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "CMD_IDLE_TIMER,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS [CMD13] polling.Periodic polling is used when tasks are pending in the device but no data transfer is in progress"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argu-ment. "
hexmask.long.word 0x04 0.--15. 1. "QUEUE_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_ STATUS [CMD13] com-mand"
line.long 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dcmd_response,This register is used for passing the response of a DCMD task to software. "
group.long 0x250++0x13
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_resp_err_mask,This register controls the generation of Response Error Detection (RED) interrupt. "
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_err_info,This register is updated by CQE when an error occurs on data or command related to a task activity"
bitfld.long 0x04 31. "DATERR_VALID, Data Transfer Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller" "0,1"
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bitfld.long 0x04 24.--28. "DATERR_TASK_ID, Data Transfer Error Task ID This field indicates the ID of the task which was executed on the data lines when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 16.--21. "DATERR_CMD_INDEX, Data Transfer Error Command Index This field indicates the index of the command which was executed on the data lines when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 15. "RESP_MODE_VALID, Response Mode Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller" "0,1"
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bitfld.long 0x04 8.--12. "RESP_MODE_TASK_ID, Response Mode Error Task ID This field indicates the ID of the task which was executed on the command line when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--5. "RESP_MODE_CMD_INDEX, Response Mode Error Command Index This field indicates the index of the command which was executed on the command line when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_index,This register stores the index of the last received command response. "
bitfld.long 0x08 0.--5. "LAST_CRI,This field stores the index of the last received command response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_arg,This register stores the index of the last received command response. "
line.long 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_error_task_id,CQ Error Task ID Register "
bitfld.long 0x10 0.--4. "TERR_ID,Task Error ID " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "MMCSD0_ECC_AGGR_RXMEM"
base ad:0x706000
rgroup.long 0x00++0x03
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ECC_AGGR_RXMEM__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ECC_AGGR_RXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_RXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_RXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MMCSD0_ECC_AGGR_TXMEM"
base ad:0x707000
rgroup.long 0x00++0x03
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ECC_AGGR_TXMEM__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ECC_AGGR_TXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_TXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_TXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MMCSD0_SS_CFG"
base ad:0xFA18000
rgroup.long 0x00++0x03
line.long 0x00 "REGS__SS_CFG__SSCFG_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem"
hexmask.long.word 0x00 16.--31. 1. "MOD_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJ_REV,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MIN_REV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x33
line.long 0x00 "REGS__SS_CFG__SSCFG_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
bitfld.long 0x00 24.--29. "TUNINGCOUNT,Configures the Number of Taps (Phases) of the RX clock that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 20. "ASYNCWKUPENA,Determines the Wakeup Signal Generation Mode" "Synchronous Wakeup Mode,Asyncrhonous Wakeup Mode"
bitfld.long 0x00 12.--15. "CQFMUL,FMUL for the CQ Internal Timer Clock Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--9. 1. "CQFVAL,FVAL for the CQ Internal Timer Clock Frequency"
line.long 0x04 "REGS__SS_CFG__SSCFG_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
bitfld.long 0x04 30.--31. "SLOTTYPE,Slot Type" "Removable SCard Slot,Embedded Slot for One Device,Shared Bus Slot,Reserved"
bitfld.long 0x04 29. "ASYNCHINTRSUPPORT,Asynchronous Interrupt Support" "0,1"
bitfld.long 0x04 26. "SUPPORT1P8VOLT,1.8V Support" "0,1"
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bitfld.long 0x04 25. "SUPPORT3P0VOLT,3.0V Support" "0,1"
bitfld.long 0x04 24. "SUPPORT3P3VOLT,3.3V Support" "0,1"
bitfld.long 0x04 23. "SUSPRESSUPPORT,Suspend/Resume Support" "0,1"
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bitfld.long 0x04 22. "SDMASUPPORT,SDMA Support" "0,1"
bitfld.long 0x04 21. "HIGHSPEEDSUPPORT,High Speed Support" "0,1"
bitfld.long 0x04 19. "ADMA2SUPPORT,ADMA2 Support" "0,1"
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bitfld.long 0x04 18. "SUPPORT8BIT,8-bit Support for Embedded Device" "0,1"
bitfld.long 0x04 16.--17. "MAXBLKLENGTH,Max Block Length" "512 (Bytes),1024,2048,Reserved"
hexmask.long.byte 0x04 8.--15. 1. "BASECLKFREQ,Base Clock Frequency for SD Clock"
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bitfld.long 0x04 7. "TIMEOUTCLKUNIT,Timeout Clock Unit" "0,1"
bitfld.long 0x04 0.--5. "TIMEOUTCLKFREQ,Timeout Clock Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "REGS__SS_CFG__SSCFG_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
bitfld.long 0x08 28. "SUPPORT1P8VDD2,1.8V VDD2 Support" "0,1"
bitfld.long 0x08 27. "ADMA3SUPPORT,ADMA3 Support" "0,1"
hexmask.long.byte 0x08 16.--23. 1. "CLOCKMULTIPLIER,Clock Multiplier"
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bitfld.long 0x08 14.--15. "RETUNINGMODES,Re-Tuning Modes" "0,1,2,3"
bitfld.long 0x08 13. "TUNINGFORSDR50,Use Tuning for SDR50" "0,1"
bitfld.long 0x08 8.--11. "RETUNINGTIMERCNT,Timer Count for Re-Tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 7. "TYPE4SUPPORT,Driver Type 4 Support" "0,1"
bitfld.long 0x08 6. "DDRIVERSUPPORT,Driver Type D Support" "0,1"
bitfld.long 0x08 5. "CDRIVERSUPPORT,Driver Type C Support" "0,1"
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bitfld.long 0x08 4. "ADRIVERSUPPORT,Driver Type A Support" "0,1"
bitfld.long 0x08 2. "DDR50SUPPORT,DDR50 Support" "0,1"
bitfld.long 0x08 1. "SDR104SUPPORT,SDR104 Support" "0,1"
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bitfld.long 0x08 0. "SDR50SUPPORT,SDR50 Support" "0,1"
line.long 0x0C "REGS__SS_CFG__SSCFG_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.byte 0x0C 16.--23. 1. "MAXCURRENT1P8V,Maximum Current for 1.8V"
hexmask.long.byte 0x0C 8.--15. 1. "MAXCURRENT3P0V,Maximum Current for 3.0V"
hexmask.long.byte 0x0C 0.--7. 1. "MAXCURRENT3P3V,Maximum Current for 3.3V"
line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.byte 0x10 0.--7. 1. "MAXCURRENTVDD2,Maximum Current for 1.8 V (VDD2)"
line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x14 0.--12. 1. "INITPRESETVAL,Preset Value for Initialization"
line.long 0x18 "REGS__SS_CFG__SSCFG_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x18 0.--12. 1. "DSPDPRESETVAL,Preset Value for Default Speed"
line.long 0x1C "REGS__SS_CFG__SSCFG_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x1C 0.--12. 1. "HSPDPRESETVAL,Preset Value for High Speed"
line.long 0x20 "REGS__SS_CFG__SSCFG_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x20 0.--12. 1. "SDR12PRESETVAL,Preset Value for SDR12"
line.long 0x24 "REGS__SS_CFG__SSCFG_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x24 0.--12. 1. "SDR25PRESETVAL,Preset Value for SDR25"
line.long 0x28 "REGS__SS_CFG__SSCFG_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x28 0.--12. 1. "SDR50PRESETVAL,Preset Value for SDR50"
line.long 0x2C "REGS__SS_CFG__SSCFG_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x2C 0.--12. 1. "SDR104PRESETVAL,Preset Value for SDR104"
line.long 0x30 "REGS__SS_CFG__SSCFG_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x30 0.--12. 1. "DDR50PRESETVAL,Preset Value for DDR50"
hgroup.long 0x44++0x03
hide.long 0x00 "REGS__SS_CFG__SSCFG_CTL_CFG_14_REG,The Controller Config 14 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
rgroup.long 0x60++0x17
line.long 0x00 "REGS__SS_CFG__SSCFG_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
bitfld.long 0x00 31. "SDHC_CMDIDLE,Idle signal to enable S/W to gate off the clocks" "0,1"
bitfld.long 0x00 24.--28. "RXCLKTAPSEL,Controller HW tunning RX clock tap selection value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "DMADEBUGBUS,DMA_CTRL Debug Bus"
line.long 0x04 "REGS__SS_CFG__SSCFG_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x04 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL Debug Bus"
line.long 0x08 "REGS__SS_CFG__SSCFG_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x08 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL Debug Bus"
line.long 0x0C "REGS__SS_CFG__SSCFG_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x0C 0.--15. 1. "RXDDEBUGBUS0,RXD_CTRL Debug Bus (SD CLK)"
line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x10 0.--15. 1. "RXDDEBUGBUS1,RXD_CTRL Debug Bus (RX CLK)"
line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x14 0.--15. 1. "TUNDEBUGBUS,TUN_CTRL Debug Bus"
group.long 0x100++0x03
line.long 0x00 "REGS__SS_CFG__SSCFG_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
bitfld.long 0x00 31. "IOMUX_ENABLE,IO mux enable" "0,1"
hgroup.long 0x104++0x07
hide.long 0x00 "REGS__SS_CFG__SSCFG_PHY_CTRL_2_REG,The PHY Control 2 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
hide.long 0x04 "REGS__SS_CFG__SSCFG_PHY_CTRL_3_REG,The PHY Control 3 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
group.long 0x10C++0x07
line.long 0x00 "REGS__SS_CFG__SSCFG_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
bitfld.long 0x00 20. "OTAPDLYENA,Output Tap Delay Enable" "0,1"
bitfld.long 0x00 12.--15. "OTAPDLYSEL,Output Tap Delay Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9. "ITAPCHGWIN,Input Tap Change Window" "0,1"
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bitfld.long 0x00 8. "ITAPDLYENA,Input Tap Delay Enable" "0,1"
bitfld.long 0x00 0.--4. "ITAPDLYSEL,Input Tap Delay Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "REGS__SS_CFG__SSCFG_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
bitfld.long 0x04 0.--2. "CLKBUFSEL,Clock Delay Buffer Select" "0,1,2,3,4,5,6,7"
hgroup.long 0x114++0x03
hide.long 0x00 "REGS__SS_CFG__SSCFG_PHY_CTRL_6_REG,The PHY Control 6 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
hgroup.long 0x130++0x07
hide.long 0x00 "REGS__SS_CFG__SSCFG_PHY_STAT_1_REG,The PHY Status 1 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports"
hide.long 0x04 "REGS__SS_CFG__SSCFG_PHY_STAT_2_REG,The PHY Status 2 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports"
tree.end
tree "MMCSD1_CTL_CFG"
base ad:0xFA00000
group.word 0x00++0x11
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_lo, This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10. "
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_hi, This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10. "
line.word 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_block_size,This register is used to configure the number of bytes in a data block"
bitfld.word 0x04 12.--14. "SDMA_BUF_SIZE, To perform long DMA transfer System Address register shall be updated at every system boundary during DMA transfer" "0,1,2,3,4,5,6,7"
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hexmask.word 0x04 0.--11. 1. "XFER_BLK_SIZE, This field specifies the block size for block data transfers for CMD17 CMD18 CMD24 CMD25 and CMD53"
line.word 0x06 "SDHC_WRAP__CTL_CFG__CTLCFG_block_count,This register is used to configure the number of data blocks"
line.word 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_lo,This register contains Lower bits of SD Command Argument"
line.word 0x0A "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_hi,This register contains higher bits of SD Command Argument"
line.word 0x0C "SDHC_WRAP__CTL_CFG__CTLCFG_transfer_mode,This register is used to control the operations of data transfers"
bitfld.word 0x0C 8. "RESP_INTR_DIS, Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "0,1"
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bitfld.word 0x0C 7. "RESP_ERR_CHK_ENA, Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "0,1"
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bitfld.word 0x0C 6. "RESP_TYPE, When response error check is enabled this bit selects either R1 or R5 response types" "0,1"
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bitfld.word 0x0C 5. "MULTI_BLK_SEL, This bit enables multiple block data transfers" "0,1"
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bitfld.word 0x0C 4. "DATA_XFER_DIR, This bit defines the direction of data transfers" "0,1"
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bitfld.word 0x0C 2.--3. "AUTO_CMD_ENA, There are three methods to stop Multiple-block read and write operation" "0,1,2,3"
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bitfld.word 0x0C 1. "BLK_CNT_ENA, This bit is used to enable the Block count register which is only relevant for multiple block transfers" "0,1"
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bitfld.word 0x0C 0. "DMA_ENA,DMA can be enabled only if DMA Support bit in the Capabilities register is set" "0,1"
line.word 0x0E "SDHC_WRAP__CTL_CFG__CTLCFG_command,This register is used to program the Command for host controller"
bitfld.word 0x0E 8.--13. "CMD_INDEX, This bit shall be set to the command number [CMD0-63 ACMD0-63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x0E 6.--7. "CMD_TYPE, There are three types of special commands" "0,1,2,3"
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bitfld.word 0x0E 5. "DATA_PRESENT, This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line" "0,1"
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bitfld.word 0x0E 4. "CMD_INDEX_CHK_ENA, If this bit is set to 1 the HC shall check the index field in the response to see if it has the same value as the command index" "0,1"
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bitfld.word 0x0E 3. "CMD_CRC_CHK_ENA, If this bit is set to 1 the HC shall check the CRC field in the response" "0,1"
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bitfld.word 0x0E 2. "SUB_CMD,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17]" "0,1"
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bitfld.word 0x0E 0.--1. "RESP_TYPE_SEL, Response Type Select" "0,1,2,3"
line.word 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_response,This register is used to store responses from SD Cards"
group.long 0x20++0x07
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_data_port,This register is used to access internal buffer"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_presentstate,The Host Driver can get status of the Host Controller from this 32-bit read-only register"
bitfld.long 0x04 31. "UHS2_IF_DETECTION, This status indicates whether a card supports UHS-II IF" "0,1"
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bitfld.long 0x04 30. "UHS2_IF_LANE_SYNC, This status indicates whether lane is synchronized in UHS-II mode" "0,1"
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bitfld.long 0x04 29. "UHS2_DORMANT, This status indicates whether UHS-II Ianes enterDormant state" "0,1"
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bitfld.long 0x04 28. "SUB_COMMAND_STS, The Command register and Response register are commonly used for main command and sub command" "Main Command Status,Sub Command Status"
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bitfld.long 0x04 27. "CMD_NOT_ISS_BY_ERR, Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error" "No error for issuing a command,Command cannot be issued"
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bitfld.long 0x04 24. "SDIF_CMDIN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 23. "SDIF_DAT3IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 22. "SDIF_DAT2IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 21. "SDIF_DAT1IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 20. "SDIF_DAT0IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 19. "WRITE_PROTECT, The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin" "0,1"
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bitfld.long 0x04 18. "CARD_DETECT, This bit reflects the inverse value of the SDCD# pin" "0,1"
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bitfld.long 0x04 17. "CARD_STATE_STABLE, This bit is used for testing" "0,1"
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bitfld.long 0x04 16. "CARD_INSERTED, This bit indicates whether a card has been inserted" "0,1"
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bitfld.long 0x04 11. "BUF_RD_ENA, This status is used for non-DMA read transfers.This read only flag indicates that valid data exists in the host side buffer status" "0,1"
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bitfld.long 0x04 10. "BUF_WR_ENA, This status is used for non-DMA write transfers.This read only flag indicates if space is available for write data" "0,1"
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bitfld.long 0x04 9. "RD_XFER_ACTIVE, This status is used for detecting completion of a read transfer" "0,1"
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bitfld.long 0x04 8. "WR_XFER_ACTIVE, This status indicates a write transfer is active" "0,1"
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bitfld.long 0x04 7. "SDIF_DAT7IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 6. "SDIF_DAT6IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 5. "SDIF_DAT5IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 4. "SDIF_DAT4IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 3. "RETUNING_REQ, Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data" "0,1"
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bitfld.long 0x04 2. "DATA_LINE_ACTIVE, This bit indicates whether one of the DAT line on SD bus is in use" "0,1"
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bitfld.long 0x04 1. "INHIBIT_DAT, This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1" "0,1"
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bitfld.long 0x04 0. "INHIBIT_CMD, SD Mode If this bit is 0 it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line" "0,1"
group.byte 0x28++0x03
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control1,This register is used to program DMA modes. LED Control. Data Transfer Width. High Speed Enable. Card detect test level and signal selection"
bitfld.byte 0x00 7. "CD_SIG_SEL, This bit selects source for card detection" "0,1"
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bitfld.byte 0x00 6. "CD_TEST_LEVEL, This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not" "0,1"
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bitfld.byte 0x00 5. "EXT_DATA_WIDTH, This bit controls 8-bit bus width mode for embedded device" "0,1"
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bitfld.byte 0x00 3.--4. "DMA_SELECT, This field is used to select DMA type" "SDMA is selected,Not Used [New assignment is not allowed],?..."
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bitfld.byte 0x00 2. "HIGH_SPEED_ENA, This bit is optional" "0,1"
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bitfld.byte 0x00 1. "DATA_WIDTH, This bit selects the data width of the HC" "0,1"
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bitfld.byte 0x00 0. "LED_CONTROL, This bit is used to caution the user not to remove the card while the SD card is being accessed" "0,1"
line.byte 0x01 "SDHC_WRAP__CTL_CFG__CTLCFG_power_control,This register is used to program the SD Bus power and voltage level"
bitfld.byte 0x01 5.--7. "UHS2_VOLTAGE, This field determines supply voltage range to VDD2" "0,1,2,3,4,5,6,7"
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bitfld.byte 0x01 4. "UHS2_POWER, Setting this bit enables providing VDD2" "0,1"
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bitfld.byte 0x01 1.--3. "SD_BUS_VOLTAGE, By setting these bits the HD selects the voltage level for the SD card" "0,1,2,3,4,5,6,7"
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bitfld.byte 0x01 0. "SD_BUS_POWER, Before setting this bit the SD host driver shall set SD Bus Voltage Select" "0,1"
line.byte 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_block_gap_control,This register is used to program the block gap request. read wait control and interrupt at block gap"
bitfld.byte 0x02 7. "BOOT_ACK_ENA, To check for the boot acknowledge in boot operation" "0,1"
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bitfld.byte 0x02 6. "ALT_BOOT_MODE, To start boot code access in alternative mode" "0,1"
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bitfld.byte 0x02 5. "BOOT_ENABLE, To start boot code access" "0,1"
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bitfld.byte 0x02 4. "SPI_MODE, SPI mode enable bit" "0,1"
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bitfld.byte 0x02 3. "INTRPT_AT_BLK_GAP, This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle" "0,1"
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bitfld.byte 0x02 2. "RDWAIT_CTRL, The read wait function is optional for SDIO cards" "0,1"
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bitfld.byte 0x02 1. "CONTINUE, This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request" "0,1"
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bitfld.byte 0x02 0. "STOP_AT_BLK_GAP, This bit is used to stop executing a transaction at the next block gap for non- DMA SDMA and ADMA transfers" "0,1"
line.byte 0x03 "SDHC_WRAP__CTL_CFG__CTLCFG_wakeup_control,This register is used to program the wakeup functionality"
bitfld.byte 0x03 2. "CARD_REMOVAL, This bit enables wakeup event via Card removal assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit" "0,1"
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bitfld.byte 0x03 1. "CARD_INSERTION, This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit" "0,1"
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bitfld.byte 0x03 0. "CARD_INTERRUPT, This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status register.This bit can be set to 1 if FN_WUS [Wake Up Support] in CIS is set to 1" "0,1"
group.word 0x2C++0x01
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_clock_control,This register is used to program the Clock frequency select. generator select. Clock enable. Internal Clock state fields This register controls SDCLK in SD Mode and RCLK in UHS-II mode. "
abitfld.word 0x00 8.--15. "SDCLK_FRQSEL, This register is used to select the frequency of the SDCLK pin" "0x00=base clock[10MHz-63MHz] Setting 00h..,0x01=base clock divided by 2,0x02=base clock divided by 4,0x04=base clock divided by 8,0x08=base clock divided by 16,0x10=base clock divided by 32,0x20=base clock divided by 64,0x40=base clock divided by 128,0x80=base clock divided by 256"
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bitfld.word 0x00 6.--7. "SDCLK_FRQSEL_UPBITS, Bit 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select" "0,1,2,3"
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bitfld.word 0x00 5. "CLKGEN_SEL, This bit is used to select the clock generator mode in SDCLK Frequency Select" "0,1"
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bitfld.word 0x00 3. "PLL_ENA,This bit is added from Version 4.10 for Host Controller using PLL" "0,1"
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bitfld.word 0x00 2. "SD_CLK_ENA, The HC shall stop SDCLK when writing this bit to 0" "0,1"
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rbitfld.word 0x00 1. "INT_CLK_STABLE, This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1" "0,1"
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bitfld.word 0x00 0. "INT_CLK_ENA, This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event" "0,1"
group.byte 0x2E++0x01
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_timeout_control,The register sets the Data Timeout counter value"
bitfld.byte 0x00 0.--3. "COUNTER_VALUE, This value determines the interval by which DAT line time-outs are detected" "TMCLK * 2^13,TMCLK * 2^14,?..."
line.byte 0x01 "SDHC_WRAP__CTL_CFG__CTLCFG_software_reset,This register is used to program the software reset for data. command and for all"
bitfld.byte 0x01 2. "SWRST_FOR_DAT, Only part of data circuit is reset" "0,1"
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bitfld.byte 0x01 1. "SWRST_FOR_CMD, Software Reset For CMD Line Only part of command circuit is reset to be able to issue a command" "0,1"
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bitfld.byte 0x01 0. "SWRST_FOR_ALL, This reset affects the entire HC except for the card detection circuit" "0,1"
group.word 0x30++0x0F
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts,This register gives the status of all the interrupts"
rbitfld.word 0x00 15. "ERROR_INTR, If any of the bits in the Error Interrupt Status Register are set then this bit is set" "0,1"
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bitfld.word 0x00 14. "BOOT_COMPLETE, This status is set if the boot operation gets terminated" "0,1"
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bitfld.word 0x00 13. "RCV_BOOT_ACK, This status is set if the boot acknowledge is received from device" "0,1"
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rbitfld.word 0x00 12. "RETUNING_EVENT, This status is set if Re-Tuning Request in the Present State register changes from 0 to 1" "0,1"
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rbitfld.word 0x00 11. "INTC, This status is set if INT_C is enabled and INT_C# pin is in low level" "0,1"
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rbitfld.word 0x00 10. "INTB, This status is set if INT_B is enabled and INT_B# pin is in low level" "0,1"
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rbitfld.word 0x00 9. "INTA, This status is set if INT_A is enabled and INT_A# pin is in low level" "0,1"
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rbitfld.word 0x00 8. "CARD_INTR,When this status has been set and the Host Driver needs to start this interrupt service Card Interrupt Status Enable in the Normal Interrupt Status Enable register may be set to 0 in order to clear the card interrupt status latched in the.." "0,1"
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bitfld.word 0x00 7. "CARD_REM, This status is set if the Card Inserted in the Present State register changes from 1 to 0" "0,1"
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bitfld.word 0x00 6. "CARD_INS, This status is set if the Card Inserted in the Present State register changes from 0 to 1.When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed" "0,1"
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bitfld.word 0x00 5. "BUF_RD_READY, This status is set if the Buffer Read Enable changes from 0 to 1" "0,1"
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bitfld.word 0x00 4. "BUF_WR_READY, This status is set if the Buffer Write Enable changes from 0 to 1.In UHS-II mode this bit is set at FC [Flow Control] unit basis" "0,1"
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bitfld.word 0x00 3. "DMA_INTERRUPT, This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size regiser" "0,1"
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bitfld.word 0x00 2. "BLK_GAP_EVENT, If the Stop At Block Gap Request in the BlockGap Control Register is set this bit is set" "0,1"
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bitfld.word 0x00 1. "XFER_COMPLETE, This bit is set when a read / write transaction is completed" "Not complete,Command execution is completed"
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bitfld.word 0x00 0. "CMD_COMPLETE, SD Mode This bit is set when we get the end bit of the command response [Except Auto CMD12 and Auto CMD23] Note: Command Time-out Error has higher priority than Command Complete" "0,1"
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts,This register gives the status of the error interrupts"
bitfld.word 0x02 12. "HOST, Occurs when detecting ERROR in m_hresp[dma transaction] " "0,1"
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bitfld.word 0x02 11. "RESP,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution" "0,1"
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bitfld.word 0x02 10. "TUNING,This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure [Occurrence of an error during tuning procedure is indicated by Sampling Select]" "0,1"
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bitfld.word 0x02 9. "ADMA, This bit is set when the Host Controller detects errors during ADMA based data transfer" "0,1"
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bitfld.word 0x02 8. "AUTO_CMD, Auto CMD12 and Auto CMD23 use this error status.This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1" "0,1"
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bitfld.word 0x02 7. "CURR_LIMIT, By setting the SD Bus Power bit in the Power Control Register the HC is requested to supply power for the SD Bus" "0,1"
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bitfld.word 0x02 6. "DATA_ENDBIT, Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status" "0,1"
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bitfld.word 0x02 5. "DATA_CRC, Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 010" "0,1"
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bitfld.word 0x02 4. "DATA_TIMEOUT, Occurs when detecting one of following timeout conditions: 1" "0,1"
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bitfld.word 0x02 3. "CMD_INDEX, Occurs if a Command Index error occurs in the Command Response" "0,1"
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bitfld.word 0x02 2. "CMD_ENDBIT, Occurs when detecting that the end bit of a command response is 0" "0,1"
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bitfld.word 0x02 1. "CMD_CRC, Command CRC Error is generated in two cases" "0,1"
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bitfld.word 0x02 0. "CMD_TIMEOUT, Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command" "0,1"
line.word 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts_ena,This register is used to enable the normal interrupt status register fields"
rbitfld.word 0x04 15. "BIT15_FIXED0, The HC shall control error Interrupts using the Error Interrupt Status Enable register" "0,1"
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bitfld.word 0x04 14. "BOOT_COMPLETE, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 13. "RCV_BOOT_ACK, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 12. "RETUNING_EVENT," "Masked,Enabled"
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bitfld.word 0x04 11. "INTC, If this bit is set to 0 the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 10. "INTB, If this bit is set to 0 the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 9. "INTA, If this bit is set to 0 the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 8. "CARD_INTERRUPT, If this bit is set to 0 the HC shall clear Interrupt request to the System" "0,1"
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bitfld.word 0x04 7. "CARD_REMOVAL, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 6. "CARD_INSERTION, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 5. "BUF_RD_READY, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 4. "BUF_WR_READY, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 3. "DMA_INTERRUPT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 2. "BLK_GAP_EVENT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 1. "XFER_COMPLETE, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 0. "CMD_COMPLETE, '0' Masked '1' Enabled " "0,1"
line.word 0x06 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts_ena,This register is used to enable the Error Interrupt Status register fields"
bitfld.word 0x06 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3"
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bitfld.word 0x06 12. "HOST, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 11. "RESP, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 10. "TUNING, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 9. "ADMA, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 8. "AUTO_CMD, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 7. "CURR_LIMIT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 6. "DATA_ENDBIT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 5. "DATA_CRC, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 4. "DATA_TIMEOUT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 3. "CMD_INDEX, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 2. "CMD_ENDBIT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 1. "CMD_CRC, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 0. "CMD_TIMEOUT, '0' Masked '1' Enabled " "0,1"
line.word 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sig_ena,This register is used to enable the Normal Interrupt Signal register"
rbitfld.word 0x08 15. "BIT15_FIXED0, The HD shall control error Interrupts using the Error Interrupt Signal Enable register" "0,1"
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bitfld.word 0x08 14. "BOOT_COMPLETE, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 13. "RCV_BOOT_ACK, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 12. "RETUNING_EVENT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 11. "INTC, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 10. "INTB, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 9. "INTA, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 8. "CARD_INTERRUPT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 7. "CARD_REMOVAL, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 6. "CARD_INSERTION, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 5. "BUF_RD_READY, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 4. "BUF_WR_READY, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 3. "DMA_INTERRUPT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 2. "BLK_GAP_EVENT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 1. "XFER_COMPLETE, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 0. "CMD_COMPLETE, '0' Masked '1' Enabled " "0,1"
line.word 0x0A "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sig_ena,This register is used to enable Error Interrupt Signal register"
bitfld.word 0x0A 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3"
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bitfld.word 0x0A 12. "HOST, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 11. "RESP, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 10. "TUNING, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 9. "ADMA, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 8. "AUTO_CMD, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 7. "CURR_LIMIT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 6. "DATA_ENDBIT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 5. "DATA_CRC, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 4. "DATA_TIMEOUT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 3. "CMD_INDEX, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 2. "CMD_ENDBIT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 1. "CMD_CRC, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 0. "CMD_TIMEOUT, '0' Masked '1' Enabled " "0,1"
line.word 0x0C "SDHC_WRAP__CTL_CFG__CTLCFG_autocmd_err_sts, This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD 23 "
bitfld.word 0x0C 7. "CMD_NOT_ISSUED, Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error [D04- D01] in this register" "0,1"
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bitfld.word 0x0C 5. "RESP, This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or Auto CMD23" "0,1"
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bitfld.word 0x0C 4. "INDEX, Occurs if the Command Index error occurs in response to a command" "0,1"
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bitfld.word 0x0C 3. "ENDBIT, Occurs when detecting that the end bit of command response is 0" "0,1"
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bitfld.word 0x0C 2. "CRC, Occurs when detecting a CRC error in the command response" "0,1"
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bitfld.word 0x0C 1. "TIMEOUT, Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command.If this bit is set to 1 the other error status bits [D04 - D02] are meaningless" "0,1"
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bitfld.word 0x0C 0. "ACMD12_NOT_EXEC, If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12" "0,1"
line.word 0x0E "SDHC_WRAP__CTL_CFG__CTLCFG_host_control2,This register is used to program UHS Select Mode.UHS Select Mode.Driver Strength Select.Execute Tuning.Sampling Clock Select.Asynchronous Interrupt Enable and Preset value enable "
bitfld.word 0x0E 15. "PRESET_VALUE_ENA, Host Controller Version 3.00 supports this bit" "0,1"
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bitfld.word 0x0E 14. "ASYNCH_INTR_ENA, This bit can be set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the Capabilities register" "0,1"
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bitfld.word 0x0E 13. "BIT64_ADDRESSING, This field is effective when Host Version 4.00 Enable is set to 1" "0,1"
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bitfld.word 0x0E 12. "HOST_VER40_ENA, This bit selects either Version 3.00 compatible mode or Ver4.mode" "0,1"
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bitfld.word 0x0E 11. "CMD23_ENA, In memory card initialization Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]" "0,1"
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bitfld.word 0x0E 10. "ADMA2_LEN_MODE, This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit" "0,1"
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bitfld.word 0x0E 9. "DRIVER_STRENGTH2, This is the programmed Drive STrength output and Bit[2] of the sdhccore_drivestrength value" "0,1"
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bitfld.word 0x0E 8. "UHS2_INTF_ENABLE, This bit is used to enable UHS-II Interface" "0,1"
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bitfld.word 0x0E 7. "SAMPLING_CLK_SELECT, This bit is set by tuning procedure when Execute Tuning is cleared" "0,1"
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bitfld.word 0x0E 6. "EXECUTE_TUNING, This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed" "0,1"
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bitfld.word 0x0E 4.--5. "DRIVER_STRENGTH1, Host Controller output driver in 1.8V signaling is selected by this bit" "0,1,2,3"
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bitfld.word 0x0E 3. "V1P8_SIGNAL_ENA, This bit controls voltage regulator for I/O cell" "0,1"
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bitfld.word 0x0E 0.--2. "UHS_MODE_SELECT, This field is used to select one of UHS-I modes or UHS-II mode.In case of UHS-I mode this field is effective when 1.8V Signal-ing Enable is set to 1" "0,1,2,3,4,5,6,7"
rgroup.quad 0x40++0x0F
line.quad 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_capabilities, This register provides the HD with information specific to the HC implementation"
bitfld.quad 0x00 63. "HS400_SUPPORT, 1 HS400 is Supported 0 HS400 is Not Supported " "0,1"
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bitfld.quad 0x00 60. "VDD2_1P8_SUPPORT, This field indicates that support of VDD2 on Host system" "0,1"
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bitfld.quad 0x00 59. "ADMA3_SUPPORT, This field indicates that support of ADMA3 on Host Controller" "0,1"
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bitfld.quad 0x00 57. "SPI_BLK_MODE, This field indicates whether SPI Block Mode is supported or not" "0,1"
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bitfld.quad 0x00 56. "SPI_SUPPORT, This field indicates whether SPI Mode is supported or not" "0,1"
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hexmask.quad.byte 0x00 48.--55. 1. "CLOCK_MULTIPLIER, This field indicates clock multiplier value of programmable clock generator"
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bitfld.quad 0x00 46.--47. "RETUNING_MODES, This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver" "0,1,2,3"
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bitfld.quad 0x00 45. "TUNING_FOR_SDR50, If this bit is set to 1 this Host Controller requires tuning to operate SDR50" "0,1"
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bitfld.quad 0x00 40.--43. "RETUNING_TIMER_CNT, This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3" "Get information via other source,1 seconds,2 seconds,4 seconds,8 seconds ------ n = 2[n-1] seconds,?,?,?,?,?,?,1024 seconds,?,?,?,Ch = Reserved"
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bitfld.quad 0x00 38. "DRIVERD_SUPPORT, This bit indicates support of Driver Type D for 1.8 Signaling" "0,1"
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bitfld.quad 0x00 37. "DRIVERC_SUPPORT, This bit indicates support of Driver Type C for 1.8 Signaling" "0,1"
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bitfld.quad 0x00 36. "DRIVERA_SUPPORT, This bit indicates support of Driver Type A for 1.8 Signaling" "0,1"
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bitfld.quad 0x00 35. "UHS2_SUPPORT, This bit indicates whether Host controller supports UHS-II" "0,1"
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bitfld.quad 0x00 34. "DDR50_SUPPORT, This bit indicates whether DDR50 is supported or not" "0,1"
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bitfld.quad 0x00 33. "SDR104_SUPPORT, This bit indicates whether SDR104 is supported or not.SDR104 requires tuning" "0,1"
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bitfld.quad 0x00 32. "SDR50_SUPPORT, If SDR104 is supported this bit shall be set to 1" "0,1"
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bitfld.quad 0x00 30.--31. "SLOT_TYPE, This field indicates usage of a slot by a specific Host System" "0,1,2,3"
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bitfld.quad 0x00 29. "ASYNCH_INTR_SUPPORT, Refer to SDIO Specification Version 3.00 about asynchronous interrupt" "0,1"
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bitfld.quad 0x00 28. "ADDR_64BIT_SUPPORT_V3, IMeaning of this bit is different depends on Versions [Refer to Table 2-35 for more details]" "0,1"
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bitfld.quad 0x00 27. "ADDR_64BIT_SUPPORT_V4, This bit is added from Version 4.10" "0,1"
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bitfld.quad 0x00 26. "VOLT_1P8_SUPPORT, This bit indicates whether the HC supports 1.8V" "0,1"
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bitfld.quad 0x00 25. "VOLT_3P0_SUPPORT, This bit indicates whether the HC supports 3.0V" "0,1"
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bitfld.quad 0x00 24. "VOLT_3P3_SUPPORT, This bit indicates whether the HC supports 3.3V" "0,1"
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bitfld.quad 0x00 23. "SUSP_RES_SUPPORT, This bit indicates whether the HC supports Suspend / Resume functionality" "0,1"
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bitfld.quad 0x00 22. "SDMA_SUPPORT, This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly.Version 4.10 Host Controller shall support SDMA if ADMA2 is supported" "0,1"
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bitfld.quad 0x00 21. "HIGH_SPEED_SUPPORT, This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz [for SD]/ 20MHz to 52MHz [for MMC]" "0,1"
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bitfld.quad 0x00 19. "ADMA2_SUPPORT, '0' ADMA2 Not Supported '1' ADMA2 Supported " "0,1"
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bitfld.quad 0x00 18. "BUS_8BIT_SUPPORT, This bit indicates whether the Host Controller is capable of using 8-bit bus width mode" "0,1"
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bitfld.quad 0x00 16.--17. "MAX_BLK_LENGTH, This value indicates the maximum block size that the HD can read and write to the buffer in the HC" "0,1,2,3"
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hexmask.quad.byte 0x00 8.--15. 1. "BASE_CLK_FREQ, [1]6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00"
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bitfld.quad 0x00 7. "TIMEOUT_CLK_UNIT, This bit shows the unit of base clock frequency used to detect Data Timeout Error" "0,1"
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bitfld.quad 0x00 0.--5. "TIMEOUT_CLK_FREQ, This bit shows the base clock frequency used to detect Data Timeout Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.quad 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_max_current_cap,This register indicates maximum current capability for each voltage"
hexmask.quad.byte 0x08 32.--39. 1. "VDD2_1P8V,Maximum Current for 1.8V VDD2"
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hexmask.quad.byte 0x08 16.--23. 1. "VDD1_1P8V,Maximum Current for 1.8V VDD1"
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hexmask.quad.byte 0x08 8.--15. 1. "VDD1_3P0V, Maximum Current for 3.0V VDD1 "
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hexmask.quad.byte 0x08 0.--7. 1. "VDD1_3P3V, Maximum Current for 3.3V VDD1 "
group.word 0x50++0x03
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_ACMD_Err_Sts,This register is not physically implemented. rather it is an address where Auto CMD Error Status register can be written. Writing"
bitfld.word 0x00 7. "CMD_NOT_ISS, Force Event for Command Not Issued by AUTO CMD12 Error" "0,1"
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bitfld.word 0x00 5. "RESP, Force Event for AUTO CMD Response Error" "0,1"
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bitfld.word 0x00 4. "INDEX, Force Event for AUTO CMD Index Error" "0,1"
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bitfld.word 0x00 3. "ENDBIT, Force Event for AUTO CMD End Bit Error" "0,1"
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bitfld.word 0x00 2. "CRC, Force Event for AUTO CMD Timeout Error" "0,1"
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bitfld.word 0x00 1. "TIMEOUT, Force Event for AUTO CMD Timeout Error" "0,1"
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bitfld.word 0x00 0. "ACMD_NOT_EXEC, Force Event for AUTO CMD12 Not Executed" "0,1"
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_Err_Int_Sts,This register is not physically implemented. rather it is an address where Error Interrupt Status register can be written"
bitfld.word 0x02 12. "HOST, Force Event for Host Error " "0,1"
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bitfld.word 0x02 11. "RESP, Force Event for Response Error " "0,1"
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bitfld.word 0x02 10. "TUNING, Force Event for Tuning Error" "0,1"
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bitfld.word 0x02 9. "ADMA, Force Event for ADMA Error" "0,1"
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bitfld.word 0x02 8. "AUTO_CMD, Force Event for Auto CMD Error" "0,1"
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bitfld.word 0x02 7. "CURR_LIM, Force Event for Current Limit Error" "0,1"
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bitfld.word 0x02 6. "DAT_ENDBIT, Force Event for Data End Bit Error" "0,1"
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bitfld.word 0x02 5. "DAT_CRC, Force Event for Data CRC Error" "0,1"
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bitfld.word 0x02 4. "DAT_TIMEOUT, Force Event for Data Timeout Error" "0,1"
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bitfld.word 0x02 3. "CMD_INDEX, Force Event for Command Index Error " "0,1"
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bitfld.word 0x02 2. "CMD_ENDBIT, Force Event for Command End Bit Error" "0,1"
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bitfld.word 0x02 1. "CMD_CRC, Force Event for Command CRC Error" "0,1"
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bitfld.word 0x02 0. "CMD_TIMEOUT, Force Event for CMD Timeout Error" "0,1"
rgroup.byte 0x54++0x00
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_err_status,When the ADMA Error interrupt occur. this register holds the ADMA State in ADMA Error States field and ADMA System Address holds address around the error descriptor"
bitfld.byte 0x00 2. "ADMA_LENGTH_ERR, This error occurs in the following 2 cases" "0,1"
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bitfld.byte 0x00 0.--1. "ADMA_ERR_STATE, This field indicates the state of ADMA when error is occurred during ADMA data transfer" "0,1,2,3"
group.quad 0x58++0x07
line.quad 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_sys_address,This register contains the physical address used for ADMA data transfer"
repeat 10. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 10. )(list 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x12 0x14 )
rgroup.word ($2+0x60)++0x01
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value$1, This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value "
bitfld.word 0x00 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes" "0,1,2,3"
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bitfld.word 0x00 10. "CLOCK_GENSEL, This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator " "0,1"
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hexmask.word 0x00 0.--9. 1. "SDCLK_FRQSEL, 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system"
repeat.end
group.quad 0x78++0x07
line.quad 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_adma3_desc_address,The start address of Integrated DMA Descriptor is set to this register"
group.word 0x80++0x01
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_size,This register is used to configure the number of bytes in a data block"
bitfld.word 0x00 12.--14. "SDMA_BUF_BOUNDARY, When system memory is managed by paging SDMA data transfer is performed in unit of paging" "0,1,2,3,4,5,6,7"
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hexmask.word 0x00 0.--11. 1. "XFER_BLK_SIZE,This register specifies the block size of data packet"
group.long 0x84++0x03
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_count,This register is used to configure the number of data blocks"
group.byte 0x88++0x00
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command_pkt,UHS-II Command Packet image is set to this register"
group.word 0x9C++0x03
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_xfer_mode,This register is used to control the operations of data transfers"
bitfld.word 0x00 15. "DUPLEX_SELECT, Use of 2 lane half duplex mode is determined by Host Driver" "0,1"
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bitfld.word 0x00 14. "EBSY_WAIT, This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution" "0,1"
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bitfld.word 0x00 8. "RESP_INTR_DIS, Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "0,1"
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bitfld.word 0x00 7. "RESP_ERR_CHK_ENA, Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver.Only R1 or R5 can be checked" "0,1"
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bitfld.word 0x00 6. "RESP_TYPE, When response error check is enabled this bit selects either R1 or R5 response types" "0,1"
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bitfld.word 0x00 5. "BYTE_MODE, This bit specifies whether data transfer is in byte mode or block mode when Data Present is set to 1" "0,1"
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bitfld.word 0x00 4. "DATA_XFER_DIR, This bit specifies direction of data trans-fer when Data Present is set to 1" "Read [Card to Host],Write [Host to Card]"
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bitfld.word 0x00 1. "BLK_CNT_ENA, This bit specifies whether data transfer usesUHS-II Block Count register" "0,1"
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bitfld.word 0x00 0. "DMA_ENA,This bit selects whether DMA is used or not and is effective to a command with data transfer" "0,1"
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command,This register is used to program the Command for host controller"
bitfld.word 0x02 8.--12. "PKT_LENGTH,A command packet length which is set in the UHS-II Command Packet register is set to this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.word 0x02 6.--7. "CMD_TYPE, This field is used to distinguish a spe-cific command like abort command" "0,1,2,3"
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bitfld.word 0x02 5. "DATA_PRESENT,This bit specifies whether the command is accompanied by data packet" "0,1"
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bitfld.word 0x02 2. "SUB_COMMAND,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17].When issuing a main command this bit is set to 0 and when issuing a sub com-mand this bit is set to 1" "0,1"
rgroup.byte 0xA0++0x00
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_response,This register is used to store received UHS-II RES Packet image"
group.byte 0xB4++0x00
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message_select,This register is used to access internal buffer"
bitfld.byte 0x00 0.--1. "MSG_SEL,Host Controller holds 4 MSG packets in FIFO buffer.One of 4 MSGs can be read from the UHS-II MSG register [0BB-0B8h] by setting this register.[Assumed for debug usage.] '00' The latest MSG '01' One MSG before '10' Two MSGs before '11' Three.." "0,1,2,3"
rgroup.long 0xB8++0x03
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message,This register is used to access internal buffer"
hexmask.long.byte 0x00 24.--31. 1. "MSG_BYTE3, Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 16.--23. 1. "MSG_BYTE2, Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 8.--15. 1. "MSG_BYTE1, Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 0.--7. 1. "MSG_BYTE0, Host Controller holds 4 MSG packets in FIFO buffer"
group.word 0xBC++0x01
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_intr_status,This register shows receipt of INT MSG from which device "
group.byte 0xBE++0x01
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_select,UHS-II Device Select Register "
bitfld.byte 0x00 7. "INT_MSG_ENA, This bit enables receipt of INT MSG" "0,1"
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bitfld.byte 0x00 0.--3. "DEV_SEL,Host Controller holds an INT MSG packet per device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.byte 0x01 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_int_code,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register. "
group.word 0xC0++0x03
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_software_reset,UHS-II Software Reset Register "
bitfld.word 0x00 1. "HOST_SDTRAN_RESET,Host Driver set this bit to 1 to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs" "0,1"
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bitfld.word 0x00 0. "HOST_FULL_RESET,On issuing FULL_RESET CCMD Host Driver set this bit to 1 to reset Host Controller" "0,1"
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_timer_control,UHS-II Timeout Control Register"
bitfld.word 0x02 4.--7. "DEADLOCK_TIMEOUT_CTR, This value determines the deadlock period while host expecting to receive a packet [1 second]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x02 0.--3. "CMDRESP_TIMEOUT_CTR, This value determines the interval between com-mand packet and response packet [5ms]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC4++0x0B
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts,This register gives the status of all UHS-II interrupts"
bitfld.long 0x00 27.--31. "VENDOR_SPECFIC_ERR, Vendor may use this field for vendor specific error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 17. "DEADLOCK_TIMEOUT, Setting of this bit means that deadlock timeout occurs" "0,1"
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bitfld.long 0x00 16. "CMD_RESP_TIMEOUT, Setting of this bit means that RES Packet timeout occurs" "0,1"
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bitfld.long 0x00 15. "ADMA2_ADMA3, Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode" "0,1"
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bitfld.long 0x00 8. "EBSY, On receiving EBSY packet if the packet indicates an error this bit is set to 1" "0,1"
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bitfld.long 0x00 7. "UNRECOVERABLE, Setting of this bit means that Unrecoverable Error is set in a packet from a device" "0,1"
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bitfld.long 0x00 5. "TID, Setting of this bit means that TID Error occurs" "0,1"
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bitfld.long 0x00 4. "FRAMING, Setting of this bit means that Framing Error occurs during a packet receiving" "0,1"
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bitfld.long 0x00 3. "CRC, Setting of this bit means that CRC Error occurs during a packet receiving" "0,1"
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bitfld.long 0x00 2. "RETRY_EXPIRED, Setting of this bit means that Retry Counter Expired Error occurs during data transfer.If this bit is set either Framing Error or CRC Error in this register shall be set" "0,1"
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bitfld.long 0x00 1. "RESP_PKT, Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution" "0,1"
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bitfld.long 0x00 0. "HEADER, Setting of this bit means that Header Error occurs in a received packet" "0,1"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts_ena,This register is used to enable the UHS-II Error Interrupt Status register fields"
bitfld.long 0x04 27.--31. "VENDOR_SPECFIC, Setting this bit to 1 enables setting of Vendor Specific Error bit in the UHS-II Error Interrupt Status register" "Status is Disabled,Status is Enabled,?..."
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bitfld.long 0x04 17. "DEADLOCK_TIMEOUT, Setting this bit to 1 enables setting of Timeout for Dead lock bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 16. "CMD_RESP_TIMEOUT, Setting this bit to 1 enables setting of Timeout for CMD_RES bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 15. "ADMA2_ADMA3, Setting this bit to 1 enables setting of ADMA2/3 Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 8. "EBSY, Setting this bit to 1 enables setting of EBSY Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 7. "UNRECOVERABLE, Setting this bit to 1 enables setting of Unrecoverable Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 5. "TID, Setting this bit to 1 enables setting of TID Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 4. "FRAMING, Setting this bit to 1 enables setting of Framing Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 3. "CRC, Setting this bit to 1 enables setting of CRC Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 2. "RETRY_EXPIRED, Setting this bit to 1 enables setting of Retry Expired bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 1. "RESP_PKT, Setting this bit to 1 enables setting of RES Packet Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 0. "HEADER, Setting this bit to 1 enables setting of Header Error bit in the UHS-II Error Interrupt Status Register" "0,1"
line.long 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sig_ena,This register is used to generate UHS-II Interrupt signals"
bitfld.long 0x08 27.--31. "VENDOR_SPECFIC, Setting of a bit to 1 in this field enables generating interrupt signal when corre-spondent bit of Vendor Specific Error is set in the UHS-II Error Interrupt Status Register" "Interrupt Signal is Disabled,Interrupt Signal is Enabled,?..."
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bitfld.long 0x08 17. "DEADLOCK_TIMEOUT, Setting this bit to 1 enables generating interrupt signal when Timeout for Dead lock bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 16. "CMD_RESP_TIMEOUT, Setting this bit to 1 enables generating interrupt signal when Timeout for CMD_RES bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 15. "ADMA2_ADMA3, Setting this bit to 1 enables generating interrupt signal when ADMA2/3 Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 8. "EBSY, Setting this bit to 1 enables generating interrupt signal when EBSY Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 7. "UNRECOVERABLE, Setting this bit to 1 enables generating interrupt signal when Unrecoverable Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 5. "TID, Setting this bit to 1 enables generating interrupt signal when TID Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 4. "FRAMING, Setting this bit to 1 enables generating interrupt signal when Framing Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 3. "CRC, Setting this bit to 1 enables generating interrupt signal when CRC Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 2. "RETRY_EXPIRED_SIG_ENA, Setting this bit to 1 enables generating interrupt signal when Retry Expired bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 1. "RESP_PKT, Setting this bit to 1 enables generating interrupt signal when RES Packet Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 0. "HEADER,Setting this bit to 1 enables generating interrupt signal when Header Error bit is set in the UHS-II Error Interrupt Status Register" "0,1"
rgroup.word 0xE0++0x09
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_settings_ptr, This register is pointer for UHS-II settings. "
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_capabilities_ptr, This register is pointer for UHS-II Capabilities Register. "
line.word 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_test_ptr, This register is pointer for UHS-II Test Register. "
line.word 0x06 "SDHC_WRAP__CTL_CFG__CTLCFG_shared_bus_ctrl_ptr, This register is pointer for UHS-II Shared Bus Control Register. "
line.word 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_specfic_ptr, This register is pointer for UHS-II Vendor Specific Pointer Register. "
group.long 0xF4++0x07
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_boot_timeout_control,This is used to program the boot timeout value counter"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_register,Vendor register added for autogate sdclk. cmd11 power down timer. enhancedstrobe and eMMC hardware reset"
bitfld.long 0x04 16. "AUTOGATE_SDCLK,If this bit is set SD CLK will be gated automatically when there is no transfer" "0,1"
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hexmask.long.word 0x04 2.--15. 1. "CMD11_PD_TIMER,cmd11 power-down timer value "
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bitfld.long 0x04 1. "EMMC_HW_RESET,Hardware reset signal is generared for eMMC card when this bit is set " "0,1"
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bitfld.long 0x04 0. "ENHANCED_STROBE,This bit enables the enhanced strobe logic of the Host Controller" "0,1"
rgroup.word 0xFC++0x03
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_slot_int_sts,This register is used to read the interrupt signal for each slot"
hexmask.word.byte 0x00 0.--7. 1. "INTR_SIG, These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot"
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_host_controller_ver,This register is used to read the vendor version number and specification version number "
hexmask.word.byte 0x02 8.--15. 1. "VEN_VER_NUM, The Vendor Version Number is set to 0x10 [1.0] "
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abitfld.word 0x02 0.--7. "SPEC_VER_NUM, This status indicates the Host Controller Spec" "0x00=SD Host Controller Specification Version 1.00,0x01=SD Host Controller Specification Version..,0x02=SD Host Controller Specification Version 3.00,0x03=SD Host Controller Specification Version 4.00,0x04=SD Host Controller Specification Version.."
group.long 0x100++0x07
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_settings,Start Address of General settings is pointed by Pointer for UHS-II Setting Register. "
bitfld.long 0x00 8.--13. "NUMLANES, The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0. "POWER_MODE, This field determines either Fast mode or Low Power mode.Host and all devices connected to the host shall be set to the same mode" "0,1"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_settings,Start Address of PHY settings is pointed by Pointer for UHS-II Setting Register. "
bitfld.long 0x04 20.--23. "N_LSS_DIR,The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "N_LSS_SYN,The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 15. "HIBERNATE_ENA,After checking card capability of Hibernate mode if all devices support Hibernate mode this bit may be set" "0,1"
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bitfld.long 0x04 6.--7. "SPEED_RANGE,PLL multiplier is selected by this field.Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State" "0,1,2,3"
group.quad 0x108++0x07
line.quad 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_settings,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Setting Register. "
hexmask.quad.byte 0x00 32.--39. 1. "N_DATA_GAP, The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field"
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bitfld.quad 0x00 16.--17. "RETRY_COUNT, Data Burst retry count is set to this field" "0,1,2,3"
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hexmask.quad.byte 0x00 8.--15. 1. "HOST_NFCU, Host Driver sets the number of blocks in Data Burst [Flow Control] to this field.The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices"
rgroup.long 0x110++0x07
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_cap,Start Address of General Capabilities is pointed by Pointer for UHS-II Host Capabilities Register. "
bitfld.long 0x00 22.--23. "CORECFG_UHS2_BUS_TOPLOGY,This field indicates one of bus topologies configured by a Host system" "0,1,2,3"
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bitfld.long 0x00 18.--21. "CORECFG_UHS2_MAX_DEVICES,This field indicates the maximum number of devices supported by the Host Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--17. "DEVICE_TYPE,This field indicates device type configured by a Host system" "0,1,2,3"
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bitfld.long 0x00 14. "CFG_64BIT_ADDRESSING,This field indicates support of 64-bit addressing by the Host Controller" "0,1"
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bitfld.long 0x00 8.--13. "NUM_LANES,This field indicates support of lanes by the Host Controller.0 mean not supported and 1 means supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 4.--7. "GAP,This field indicates the maximum capability of host power supply for a group configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -Not used" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "DAP,This field indicates the maximum capability of host power supply for a device configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -360 mW [Default]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_cap,Start Address of PHY Capabilities is pointed by Pointer for UHS-II Host Capabilities Register. "
bitfld.long 0x04 20.--23. "N_LSS_DIR, This field indicates the minimum N_LSS_DIR required by the Host Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "N_LSS_SYN,This field indicates the minimum N_LSS_SYN required by the Host Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 6.--7. "SPEED_RANGE,This field indicates supported Speed Range by the Host Controller '00' Range A [Default] '01' Range A and Range B '10' Reserved '11' Reserved " "0,1,2,3"
rgroup.quad 0x118++0x07
line.quad 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_cap,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Capabilities Register. "
hexmask.quad.byte 0x00 32.--39. 1. "N_DATA_GAP,This field indicates the minimum number of data gap[DIDL] supported by the Host Controller. "
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hexmask.quad.word 0x00 20.--31. 1. "MAX_BLK_LENGTH,This field indicates maximum block length by the Host Controller"
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hexmask.quad.byte 0x00 8.--15. 1. "N_FCU, This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller.This value is determined by supported buffer size"
group.long 0x120++0x03
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_force_UHSII_Err_Int_Sts,This register is not physically implemented. rather it is an address where UHS-II Error Interrupt Status register can be written. "
bitfld.long 0x00 27.--31. "VENDOR_SPECIFIC,Force Event for Vendor Specific Error " "Not Affected,Vendor Specific Error Status is set,?..."
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bitfld.long 0x00 17. "TIMEOUT_DEADLOCK,Setting this bit forces the Host Controller to set Timeout for Deadlock in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 16. "TIMEOUT_CMD_RES,Setting this bit forces the Host Controller to set Timeout for CMD_RES in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 15. "ADMA,Setting this bit forces the Host Controller to set ADMA Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 8. "EBSY,Setting this bit forces the Host Controller to set EBSY Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 7. "UNRECOVERABLE,Setting this bit forces the Host Controller to set Unrecover-able Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 5. "TID,Setting this bit forces the Host Controller to set TID Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 4. "FRAMING,Setting this bit forces the Host Controller to set Framing Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 3. "CRC,Setting this bit forces the Host Controller to set CRC Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 2. "RETRY_EXPIRED,Setting this bit forces the Host Controller to set Retry Expired in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 1. "RES_PKT,Setting this bit forces the Host Controller to set RES Packet Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 0. "HEADER,Setting this bit forces the Host Controller to set Header Error in the UHS-II Error Interrupt Status register" "0,1"
rgroup.long 0x200++0x3B
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_version,This register provides information about the version of the eMMC CQ standard which is 285 implemented by the CQE. in BCD format"
bitfld.long 0x00 8.--11. "EMMC_MAJOR_VER_NUM, eMMC Major Version Number [digit left of decimal point] in BCD format " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "EMMC_MINOR_VER_NUM, eMMC Minor Version Number [digit right of decimal point] in BCD format " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EMMC_VERSION_SUFFIX, eMMC Version Suffix [2nd digit right of decimal point] in BCD format " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_capabilities,This register is reserved for capability indication. "
bitfld.long 0x04 12.--15. "CF_MUL, Internal Timer Clock Frequency Multiplier [ITCFMUL] ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the SQS polling period" "0.001 MHz,0.01 MHz,0.1 MHz,1 MHz,10 MHz Other values..,?..."
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hexmask.long.word 0x04 0.--9. 1. "CF_VAL, Internal Timer Clock Frequency Value [ITCFVAL] TCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the polling period when using periodic SEND_QUEUE_ STATUS [CMD13] polling"
line.long 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_config,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time. "
bitfld.long 0x08 12. "DCMD_ENA, Direct Command [DCMD] Enable This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor or a Direct Command Task Descriptor" "Task descriptor in slot #31 is a Data Transfer..,Task descriptor in slot #31 is a DCMD Task.."
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bitfld.long 0x08 8. "TASK_DESC_SIZE, Task Descriptor Size This bit indicates whether the task descriptor size is 128 bits or 64 bits as detailed in Data Structures section" "Task descriptor size is 64 bits,Task descriptor size is 128 bits"
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bitfld.long 0x08 0. "CQ_ENABLE, Command Queueing Enable Software shall write 1 this bit when in order to enable command queueing mode [i.e. enable CQE]" "0,1"
line.long 0x0C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_control,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time. "
bitfld.long 0x0C 8. "CLEAR_ALL_TASKS, Clear All Tasks Software shall write 1 this bit when it wants to clear all the tasks sent to the device" "0,1"
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bitfld.long 0x0C 0. "HALT_BIT, Halt Host software shall write 1 to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus" "0,1"
line.long 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts,This register indicates pending interrupts that require service"
bitfld.long 0x10 4. "TASK_ERROR, Task Error Interrupt [TERR] This bit is asserted when task error is detected due to invalid task descriptor " "0,1"
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bitfld.long 0x10 3. "TASK_CLEARED, Task Cleared [TCL] This status bit is asserted [if CQISTE.TCL=1] when a task clear operation is completed by CQE" "0,1"
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bitfld.long 0x10 2. "RESP_ERR_DET, Response Error Detected Interrupt [RED] This status bit is asserted [if CQISTE.RED=1] when a response is received with an error bit set in the device status field" "0,1"
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bitfld.long 0x10 1. "TASK_COMPLETE,Task Complete Interrupt [TCC] This status bit is asserted [if CQISTE.TCC=1] when atleast one of the following two conditions are met: [1] A task is completed and the INT bit is set in its Task Descriptor [2] Interrupt caused by Interrupt.." "0,1"
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bitfld.long 0x10 0. "HALT_COMPLETE, Halt Complete Interrupt [HAC] This status bit is asserted [if CQISTE.HAC=1] when halt bit in CQCTL register transitions from 0 to 1 indicating that host controller has completed its current ongoing task and has entered halt state" "0,1"
line.long 0x14 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts_ena,This register enables and disables the reporting of the corresponding interrupt to host soft-ware in 299 CQIS register"
bitfld.long 0x14 4. "TASK_ERROR, Task Error Interrupt Status Enable" "CQIS.TERR is disabled,CQIS.TERR will be set when its interrupt.."
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bitfld.long 0x14 3. "TASK_CLEARED, Task Cleared Status Enable [TCL]" "CQIS.TCL is disabled,CQIS.TCL will be set when its interrupt.."
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bitfld.long 0x14 2. "RESP_ERR_DET, Response Error Detected Status Enable [RED]" "CQIS.RED is disabled,CQIS.RED will be set when its interrupt.."
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bitfld.long 0x14 1. "TASK_COMPLETE, Task Complete Status Enable [TCC]" "CQIS.TCC is disabled,CQIS.TCC will be set when its interrupt.."
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bitfld.long 0x14 0. "HALT_COMPLETE, Halt Complete Status Enable [HAC]" "CQIS.HAC is disabled,CQIS.HAC will be set when its interrupt.."
line.long 0x18 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sig_ena,This register enables and disables the generation of interrupts to host software"
bitfld.long 0x18 4. "TASK_ERROR, Task Error Interrupt Signal Enable [TERR] When set and CQIS.TERR is asserted the CQE shall generate an interrupt " "0,1"
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bitfld.long 0x18 3. "TASK_CLEARED, Task Cleared Signal Enable [TCL] When set and CQIS.TCL is asserted the CQE shall generate an interrupt " "0,1"
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bitfld.long 0x18 2. "RESP_ERR_DET, Response Error Detected Signal Enable [TCC] When set and CQIS.RED is asserted the CQE shall generate an interrupt " "0,1"
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bitfld.long 0x18 1. "TASK_COMPLETE, Task Complete Signal Enable [TCC] When set and CQIS.TCC is asserted the CQE shall generate an interrupt " "0,1"
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bitfld.long 0x18 0. "HALT_COMPLETE, Halt Complete Signal Enable [HAC] When set and CQIS.HAC is asserted the CQE shall generate an interrupt " "0,1"
line.long 0x1C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_coalescing,This register controls the interrupt coalescing feature. "
bitfld.long 0x1C 31. "CQINTCOALESC_ENABLE, When set to 0 by software command responses are neither counted nor timed" "0,1"
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bitfld.long 0x1C 20. "IC_STATUS, This bit indicates to software whether any tasks [with INT=0] have completed and counted towards interrupt coalescing [i.e. ICSB is set if and only if IC counter > 0]" "No task completions have occurred since last..,At least one task completion has been counted.."
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bitfld.long 0x1C 8.--12. "CTR_THRESHOLD, Interrupt Coalescing Counter Threshold [ICCTH]: Software uses this field to configure the number of task completions [only tasks with INT=0 in the Task Descriptor] which are required in order to generate an interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x1C 0.--6. 1. "TIMEOUT_VAL, Interrupt Coalescing Timeout Value [ICTOVAL]: Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt"
line.long 0x20 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory. "
line.long 0x24 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr_upbits,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory. "
line.long 0x28 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_door_bell,Using this register. software triggers CQE to process a new task. "
line.long 0x2C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_comp_notif,This register is used by CQE to notify software about completed tasks. "
line.long 0x30 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_queue_status,This register stores the most recent value of the device s queue status. "
line.long 0x34 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_pending_tasks,This register indicates to software which tasks are queued in the device. awaiting execution. "
line.long 0x38 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_clear,This register is used for removing an outstanding task in the CQE"
group.long 0x240++0x0B
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config1,The register controls the when SEND_QUEUE_STATUS commands are sent. "
bitfld.long 0x00 16.--19. "CMD_BLK_CNTR,This field indicates to CQE when to send SEND_QUEUE_STATUS [CMD13] command to inquire the status of the devices task queue.A value of n means CQE shall send status command on the CMD line during the transfer of data block BLOCK_CNT-n on the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "CMD_IDLE_TIMER,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS [CMD13] polling.Periodic polling is used when tasks are pending in the device but no data transfer is in progress"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argu-ment. "
hexmask.long.word 0x04 0.--15. 1. "QUEUE_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_ STATUS [CMD13] com-mand"
line.long 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dcmd_response,This register is used for passing the response of a DCMD task to software. "
group.long 0x250++0x13
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_resp_err_mask,This register controls the generation of Response Error Detection (RED) interrupt. "
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_err_info,This register is updated by CQE when an error occurs on data or command related to a task activity"
bitfld.long 0x04 31. "DATERR_VALID, Data Transfer Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller" "0,1"
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bitfld.long 0x04 24.--28. "DATERR_TASK_ID, Data Transfer Error Task ID This field indicates the ID of the task which was executed on the data lines when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 16.--21. "DATERR_CMD_INDEX, Data Transfer Error Command Index This field indicates the index of the command which was executed on the data lines when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 15. "RESP_MODE_VALID, Response Mode Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller" "0,1"
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bitfld.long 0x04 8.--12. "RESP_MODE_TASK_ID, Response Mode Error Task ID This field indicates the ID of the task which was executed on the command line when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--5. "RESP_MODE_CMD_INDEX, Response Mode Error Command Index This field indicates the index of the command which was executed on the command line when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_index,This register stores the index of the last received command response. "
bitfld.long 0x08 0.--5. "LAST_CRI,This field stores the index of the last received command response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_arg,This register stores the index of the last received command response. "
line.long 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_error_task_id,CQ Error Task ID Register "
bitfld.long 0x10 0.--4. "TERR_ID,Task Error ID " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "MMCSD1_ECC_AGGR_RXMEM"
base ad:0x708000
rgroup.long 0x00++0x03
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ECC_AGGR_RXMEM__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ECC_AGGR_RXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_RXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_RXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MMCSD1_ECC_AGGR_TXMEM"
base ad:0x709000
rgroup.long 0x00++0x03
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ECC_AGGR_TXMEM__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ECC_AGGR_TXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_TXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_TXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MMCSD1_SS_CFG"
base ad:0xFA08000
rgroup.long 0x00++0x03
line.long 0x00 "REGS__SS_CFG__SSCFG_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem"
hexmask.long.word 0x00 16.--31. 1. "MOD_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJ_REV,Major revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MIN_REV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x33
line.long 0x00 "REGS__SS_CFG__SSCFG_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
bitfld.long 0x00 24.--29. "TUNINGCOUNT,Configures the Number of Taps (Phases) of the RX clock that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 20. "ASYNCWKUPENA,Determines the Wakeup Signal Generation Mode" "Synchronous Wakeup Mode,Asyncrhonous Wakeup Mode"
bitfld.long 0x00 12.--15. "CQFMUL,FMUL for the CQ Internal Timer Clock Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--9. 1. "CQFVAL,FVAL for the CQ Internal Timer Clock Frequency"
line.long 0x04 "REGS__SS_CFG__SSCFG_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
bitfld.long 0x04 30.--31. "SLOTTYPE,Slot Type" "Removable SCard Slot,Embedded Slot for One Device,Shared Bus Slot,Reserved"
bitfld.long 0x04 29. "ASYNCHINTRSUPPORT,Asynchronous Interrupt Support" "0,1"
bitfld.long 0x04 26. "SUPPORT1P8VOLT,1.8V Support" "0,1"
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bitfld.long 0x04 25. "SUPPORT3P0VOLT,3.0V Support" "0,1"
bitfld.long 0x04 24. "SUPPORT3P3VOLT,3.3V Support" "0,1"
bitfld.long 0x04 23. "SUSPRESSUPPORT,Suspend/Resume Support" "0,1"
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bitfld.long 0x04 22. "SDMASUPPORT,SDMA Support" "0,1"
bitfld.long 0x04 21. "HIGHSPEEDSUPPORT,High Speed Support" "0,1"
bitfld.long 0x04 19. "ADMA2SUPPORT,ADMA2 Support" "0,1"
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bitfld.long 0x04 18. "SUPPORT8BIT,8-bit Support for Embedded Device" "0,1"
bitfld.long 0x04 16.--17. "MAXBLKLENGTH,Max Block Length" "512 (Bytes),1024,2048,Reserved"
hexmask.long.byte 0x04 8.--15. 1. "BASECLKFREQ,Base Clock Frequency for SD Clock"
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bitfld.long 0x04 7. "TIMEOUTCLKUNIT,Timeout Clock Unit" "0,1"
bitfld.long 0x04 0.--5. "TIMEOUTCLKFREQ,Timeout Clock Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "REGS__SS_CFG__SSCFG_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
bitfld.long 0x08 28. "SUPPORT1P8VDD2,1.8V VDD2 Support" "0,1"
bitfld.long 0x08 27. "ADMA3SUPPORT,ADMA3 Support" "0,1"
hexmask.long.byte 0x08 16.--23. 1. "CLOCKMULTIPLIER,Clock Multiplier"
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bitfld.long 0x08 14.--15. "RETUNINGMODES,Re-Tuning Modes" "0,1,2,3"
bitfld.long 0x08 13. "TUNINGFORSDR50,Use Tuning for SDR50" "0,1"
bitfld.long 0x08 8.--11. "RETUNINGTIMERCNT,Timer Count for Re-Tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 7. "TYPE4SUPPORT,Driver Type 4 Support" "0,1"
bitfld.long 0x08 6. "DDRIVERSUPPORT,Driver Type D Support" "0,1"
bitfld.long 0x08 5. "CDRIVERSUPPORT,Driver Type C Support" "0,1"
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bitfld.long 0x08 4. "ADRIVERSUPPORT,Driver Type A Support" "0,1"
bitfld.long 0x08 2. "DDR50SUPPORT,DDR50 Support" "0,1"
bitfld.long 0x08 1. "SDR104SUPPORT,SDR104 Support" "0,1"
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bitfld.long 0x08 0. "SDR50SUPPORT,SDR50 Support" "0,1"
line.long 0x0C "REGS__SS_CFG__SSCFG_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.byte 0x0C 16.--23. 1. "MAXCURRENT1P8V,Maximum Current for 1.8V"
hexmask.long.byte 0x0C 8.--15. 1. "MAXCURRENT3P0V,Maximum Current for 3.0V"
hexmask.long.byte 0x0C 0.--7. 1. "MAXCURRENT3P3V,Maximum Current for 3.3V"
line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.byte 0x10 0.--7. 1. "MAXCURRENTVDD2,Maximum Current for 1.8 V (VDD2)"
line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x14 0.--12. 1. "INITPRESETVAL,Preset Value for Initialization"
line.long 0x18 "REGS__SS_CFG__SSCFG_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x18 0.--12. 1. "DSPDPRESETVAL,Preset Value for Default Speed"
line.long 0x1C "REGS__SS_CFG__SSCFG_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x1C 0.--12. 1. "HSPDPRESETVAL,Preset Value for High Speed"
line.long 0x20 "REGS__SS_CFG__SSCFG_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x20 0.--12. 1. "SDR12PRESETVAL,Preset Value for SDR12"
line.long 0x24 "REGS__SS_CFG__SSCFG_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x24 0.--12. 1. "SDR25PRESETVAL,Preset Value for SDR25"
line.long 0x28 "REGS__SS_CFG__SSCFG_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x28 0.--12. 1. "SDR50PRESETVAL,Preset Value for SDR50"
line.long 0x2C "REGS__SS_CFG__SSCFG_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x2C 0.--12. 1. "SDR104PRESETVAL,Preset Value for SDR104"
line.long 0x30 "REGS__SS_CFG__SSCFG_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x30 0.--12. 1. "DDR50PRESETVAL,Preset Value for DDR50"
hgroup.long 0x44++0x03
hide.long 0x00 "REGS__SS_CFG__SSCFG_CTL_CFG_14_REG,The Controller Config 14 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
rgroup.long 0x60++0x17
line.long 0x00 "REGS__SS_CFG__SSCFG_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
bitfld.long 0x00 31. "SDHC_CMDIDLE,Idle signal to enable S/W to gate off the clocks" "0,1"
hexmask.long.word 0x00 0.--15. 1. "DMADEBUGBUS,DMA_CTRL Debug Bus"
line.long 0x04 "REGS__SS_CFG__SSCFG_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x04 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL Debug Bus"
line.long 0x08 "REGS__SS_CFG__SSCFG_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x08 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL Debug Bus"
line.long 0x0C "REGS__SS_CFG__SSCFG_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x0C 0.--15. 1. "RXDDEBUGBUS0,RXD_CTRL Debug Bus (SD CLK)"
line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x10 0.--15. 1. "RXDDEBUGBUS1,RXD_CTRL Debug Bus (RX CLK)"
line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x14 0.--15. 1. "TUNDEBUGBUS,TUN_CTRL Debug Bus"
group.long 0x100++0x03
line.long 0x00 "REGS__SS_CFG__SSCFG_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
bitfld.long 0x00 31. "IOMUX_ENABLE,IO mux enable" "0,1"
hgroup.long 0x104++0x07
hide.long 0x00 "REGS__SS_CFG__SSCFG_PHY_CTRL_2_REG,The PHY Control 2 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
hide.long 0x04 "REGS__SS_CFG__SSCFG_PHY_CTRL_3_REG,The PHY Control 3 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
group.long 0x10C++0x07
line.long 0x00 "REGS__SS_CFG__SSCFG_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
bitfld.long 0x00 20. "OTAPDLYENA,Output Tap Delay Enable" "0,1"
bitfld.long 0x00 12.--15. "OTAPDLYSEL,Output Tap Delay Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9. "ITAPCHGWIN,Input Tap Change Window" "0,1"
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bitfld.long 0x00 8. "ITAPDLYENA,Input Tap Delay Enable" "0,1"
bitfld.long 0x00 0.--4. "ITAPDLYSEL,Input Tap Delay Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "REGS__SS_CFG__SSCFG_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
bitfld.long 0x04 0.--2. "CLKBUFSEL,Clock Delay Buffer Select" "0,1,2,3,4,5,6,7"
hgroup.long 0x114++0x03
hide.long 0x00 "REGS__SS_CFG__SSCFG_PHY_CTRL_6_REG,The PHY Control 6 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
hgroup.long 0x130++0x07
hide.long 0x00 "REGS__SS_CFG__SSCFG_PHY_STAT_1_REG,The PHY Status 1 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports"
hide.long 0x04 "REGS__SS_CFG__SSCFG_PHY_STAT_2_REG,The PHY Status 2 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports"
tree.end
tree "MMCSD2_CTL_CFG"
base ad:0xFA20000
group.word 0x00++0x11
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_lo, This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10. "
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_sdma_sys_addr_hi, This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10. "
line.word 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_block_size,This register is used to configure the number of bytes in a data block"
bitfld.word 0x04 12.--14. "SDMA_BUF_SIZE, To perform long DMA transfer System Address register shall be updated at every system boundary during DMA transfer" "0,1,2,3,4,5,6,7"
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hexmask.word 0x04 0.--11. 1. "XFER_BLK_SIZE, This field specifies the block size for block data transfers for CMD17 CMD18 CMD24 CMD25 and CMD53"
line.word 0x06 "SDHC_WRAP__CTL_CFG__CTLCFG_block_count,This register is used to configure the number of data blocks"
line.word 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_lo,This register contains Lower bits of SD Command Argument"
line.word 0x0A "SDHC_WRAP__CTL_CFG__CTLCFG_argument1_hi,This register contains higher bits of SD Command Argument"
line.word 0x0C "SDHC_WRAP__CTL_CFG__CTLCFG_transfer_mode,This register is used to control the operations of data transfers"
bitfld.word 0x0C 8. "RESP_INTR_DIS, Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "0,1"
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bitfld.word 0x0C 7. "RESP_ERR_CHK_ENA, Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "0,1"
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bitfld.word 0x0C 6. "RESP_TYPE, When response error check is enabled this bit selects either R1 or R5 response types" "0,1"
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bitfld.word 0x0C 5. "MULTI_BLK_SEL, This bit enables multiple block data transfers" "0,1"
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bitfld.word 0x0C 4. "DATA_XFER_DIR, This bit defines the direction of data transfers" "0,1"
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bitfld.word 0x0C 2.--3. "AUTO_CMD_ENA, There are three methods to stop Multiple-block read and write operation" "0,1,2,3"
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bitfld.word 0x0C 1. "BLK_CNT_ENA, This bit is used to enable the Block count register which is only relevant for multiple block transfers" "0,1"
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bitfld.word 0x0C 0. "DMA_ENA,DMA can be enabled only if DMA Support bit in the Capabilities register is set" "0,1"
line.word 0x0E "SDHC_WRAP__CTL_CFG__CTLCFG_command,This register is used to program the Command for host controller"
bitfld.word 0x0E 8.--13. "CMD_INDEX, This bit shall be set to the command number [CMD0-63 ACMD0-63]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.word 0x0E 6.--7. "CMD_TYPE, There are three types of special commands" "0,1,2,3"
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bitfld.word 0x0E 5. "DATA_PRESENT, This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line" "0,1"
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bitfld.word 0x0E 4. "CMD_INDEX_CHK_ENA, If this bit is set to 1 the HC shall check the index field in the response to see if it has the same value as the command index" "0,1"
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bitfld.word 0x0E 3. "CMD_CRC_CHK_ENA, If this bit is set to 1 the HC shall check the CRC field in the response" "0,1"
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bitfld.word 0x0E 2. "SUB_CMD,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17]" "0,1"
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bitfld.word 0x0E 0.--1. "RESP_TYPE_SEL, Response Type Select" "0,1,2,3"
line.word 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_response,This register is used to store responses from SD Cards"
group.long 0x20++0x07
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_data_port,This register is used to access internal buffer"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_presentstate,The Host Driver can get status of the Host Controller from this 32-bit read-only register"
bitfld.long 0x04 31. "UHS2_IF_DETECTION, This status indicates whether a card supports UHS-II IF" "0,1"
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bitfld.long 0x04 30. "UHS2_IF_LANE_SYNC, This status indicates whether lane is synchronized in UHS-II mode" "0,1"
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bitfld.long 0x04 29. "UHS2_DORMANT, This status indicates whether UHS-II Ianes enterDormant state" "0,1"
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bitfld.long 0x04 28. "SUB_COMMAND_STS, The Command register and Response register are commonly used for main command and sub command" "Main Command Status,Sub Command Status"
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bitfld.long 0x04 27. "CMD_NOT_ISS_BY_ERR, Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error" "No error for issuing a command,Command cannot be issued"
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bitfld.long 0x04 24. "SDIF_CMDIN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 23. "SDIF_DAT3IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 22. "SDIF_DAT2IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 21. "SDIF_DAT1IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 20. "SDIF_DAT0IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 19. "WRITE_PROTECT, The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin" "0,1"
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bitfld.long 0x04 18. "CARD_DETECT, This bit reflects the inverse value of the SDCD# pin" "0,1"
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bitfld.long 0x04 17. "CARD_STATE_STABLE, This bit is used for testing" "0,1"
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bitfld.long 0x04 16. "CARD_INSERTED, This bit indicates whether a card has been inserted" "0,1"
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bitfld.long 0x04 11. "BUF_RD_ENA, This status is used for non-DMA read transfers.This read only flag indicates that valid data exists in the host side buffer status" "0,1"
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bitfld.long 0x04 10. "BUF_WR_ENA, This status is used for non-DMA write transfers.This read only flag indicates if space is available for write data" "0,1"
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bitfld.long 0x04 9. "RD_XFER_ACTIVE, This status is used for detecting completion of a read transfer" "0,1"
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bitfld.long 0x04 8. "WR_XFER_ACTIVE, This status indicates a write transfer is active" "0,1"
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bitfld.long 0x04 7. "SDIF_DAT7IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 6. "SDIF_DAT6IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 5. "SDIF_DAT5IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 4. "SDIF_DAT4IN, This status is used to check DAT line level to recover from errors and for debugging" "0,1"
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bitfld.long 0x04 3. "RETUNING_REQ, Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data" "0,1"
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bitfld.long 0x04 2. "DATA_LINE_ACTIVE, This bit indicates whether one of the DAT line on SD bus is in use" "0,1"
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bitfld.long 0x04 1. "INHIBIT_DAT, This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1" "0,1"
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bitfld.long 0x04 0. "INHIBIT_CMD, SD Mode If this bit is 0 it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line" "0,1"
group.byte 0x28++0x03
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_host_control1,This register is used to program DMA modes. LED Control. Data Transfer Width. High Speed Enable. Card detect test level and signal selection"
bitfld.byte 0x00 7. "CD_SIG_SEL, This bit selects source for card detection" "0,1"
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bitfld.byte 0x00 6. "CD_TEST_LEVEL, This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not" "0,1"
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bitfld.byte 0x00 5. "EXT_DATA_WIDTH, This bit controls 8-bit bus width mode for embedded device" "0,1"
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bitfld.byte 0x00 3.--4. "DMA_SELECT, This field is used to select DMA type" "SDMA is selected,Not Used [New assignment is not allowed],?..."
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bitfld.byte 0x00 2. "HIGH_SPEED_ENA, This bit is optional" "0,1"
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bitfld.byte 0x00 1. "DATA_WIDTH, This bit selects the data width of the HC" "0,1"
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bitfld.byte 0x00 0. "LED_CONTROL, This bit is used to caution the user not to remove the card while the SD card is being accessed" "0,1"
line.byte 0x01 "SDHC_WRAP__CTL_CFG__CTLCFG_power_control,This register is used to program the SD Bus power and voltage level"
bitfld.byte 0x01 5.--7. "UHS2_VOLTAGE, This field determines supply voltage range to VDD2" "0,1,2,3,4,5,6,7"
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bitfld.byte 0x01 4. "UHS2_POWER, Setting this bit enables providing VDD2" "0,1"
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bitfld.byte 0x01 1.--3. "SD_BUS_VOLTAGE, By setting these bits the HD selects the voltage level for the SD card" "0,1,2,3,4,5,6,7"
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bitfld.byte 0x01 0. "SD_BUS_POWER, Before setting this bit the SD host driver shall set SD Bus Voltage Select" "0,1"
line.byte 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_block_gap_control,This register is used to program the block gap request. read wait control and interrupt at block gap"
bitfld.byte 0x02 7. "BOOT_ACK_ENA, To check for the boot acknowledge in boot operation" "0,1"
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bitfld.byte 0x02 6. "ALT_BOOT_MODE, To start boot code access in alternative mode" "0,1"
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bitfld.byte 0x02 5. "BOOT_ENABLE, To start boot code access" "0,1"
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bitfld.byte 0x02 4. "SPI_MODE, SPI mode enable bit" "0,1"
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bitfld.byte 0x02 3. "INTRPT_AT_BLK_GAP, This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle" "0,1"
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bitfld.byte 0x02 2. "RDWAIT_CTRL, The read wait function is optional for SDIO cards" "0,1"
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bitfld.byte 0x02 1. "CONTINUE, This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request" "0,1"
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bitfld.byte 0x02 0. "STOP_AT_BLK_GAP, This bit is used to stop executing a transaction at the next block gap for non- DMA SDMA and ADMA transfers" "0,1"
line.byte 0x03 "SDHC_WRAP__CTL_CFG__CTLCFG_wakeup_control,This register is used to program the wakeup functionality"
bitfld.byte 0x03 2. "CARD_REMOVAL, This bit enables wakeup event via Card removal assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit" "0,1"
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bitfld.byte 0x03 1. "CARD_INSERTION, This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register.FN_WUS [Wake up Support] in CIS does not affect this bit" "0,1"
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bitfld.byte 0x03 0. "CARD_INTERRUPT, This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status register.This bit can be set to 1 if FN_WUS [Wake Up Support] in CIS is set to 1" "0,1"
group.word 0x2C++0x01
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_clock_control,This register is used to program the Clock frequency select. generator select. Clock enable. Internal Clock state fields This register controls SDCLK in SD Mode and RCLK in UHS-II mode. "
abitfld.word 0x00 8.--15. "SDCLK_FRQSEL, This register is used to select the frequency of the SDCLK pin" "0x00=base clock[10MHz-63MHz] Setting 00h..,0x01=base clock divided by 2,0x02=base clock divided by 4,0x04=base clock divided by 8,0x08=base clock divided by 16,0x10=base clock divided by 32,0x20=base clock divided by 64,0x40=base clock divided by 128,0x80=base clock divided by 256"
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bitfld.word 0x00 6.--7. "SDCLK_FRQSEL_UPBITS, Bit 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select" "0,1,2,3"
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bitfld.word 0x00 5. "CLKGEN_SEL, This bit is used to select the clock generator mode in SDCLK Frequency Select" "0,1"
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bitfld.word 0x00 3. "PLL_ENA,This bit is added from Version 4.10 for Host Controller using PLL" "0,1"
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bitfld.word 0x00 2. "SD_CLK_ENA, The HC shall stop SDCLK when writing this bit to 0" "0,1"
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rbitfld.word 0x00 1. "INT_CLK_STABLE, This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1" "0,1"
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bitfld.word 0x00 0. "INT_CLK_ENA, This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event" "0,1"
group.byte 0x2E++0x01
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_timeout_control,The register sets the Data Timeout counter value"
bitfld.byte 0x00 0.--3. "COUNTER_VALUE, This value determines the interval by which DAT line time-outs are detected" "TMCLK * 2^13,TMCLK * 2^14,?..."
line.byte 0x01 "SDHC_WRAP__CTL_CFG__CTLCFG_software_reset,This register is used to program the software reset for data. command and for all"
bitfld.byte 0x01 2. "SWRST_FOR_DAT, Only part of data circuit is reset" "0,1"
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bitfld.byte 0x01 1. "SWRST_FOR_CMD, Software Reset For CMD Line Only part of command circuit is reset to be able to issue a command" "0,1"
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bitfld.byte 0x01 0. "SWRST_FOR_ALL, This reset affects the entire HC except for the card detection circuit" "0,1"
group.word 0x30++0x0F
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts,This register gives the status of all the interrupts"
rbitfld.word 0x00 15. "ERROR_INTR, If any of the bits in the Error Interrupt Status Register are set then this bit is set" "0,1"
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bitfld.word 0x00 14. "BOOT_COMPLETE, This status is set if the boot operation gets terminated" "0,1"
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bitfld.word 0x00 13. "RCV_BOOT_ACK, This status is set if the boot acknowledge is received from device" "0,1"
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rbitfld.word 0x00 12. "RETUNING_EVENT, This status is set if Re-Tuning Request in the Present State register changes from 0 to 1" "0,1"
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rbitfld.word 0x00 11. "INTC, This status is set if INT_C is enabled and INT_C# pin is in low level" "0,1"
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rbitfld.word 0x00 10. "INTB, This status is set if INT_B is enabled and INT_B# pin is in low level" "0,1"
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rbitfld.word 0x00 9. "INTA, This status is set if INT_A is enabled and INT_A# pin is in low level" "0,1"
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rbitfld.word 0x00 8. "CARD_INTR,When this status has been set and the Host Driver needs to start this interrupt service Card Interrupt Status Enable in the Normal Interrupt Status Enable register may be set to 0 in order to clear the card interrupt status latched in the.." "0,1"
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bitfld.word 0x00 7. "CARD_REM, This status is set if the Card Inserted in the Present State register changes from 1 to 0" "0,1"
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bitfld.word 0x00 6. "CARD_INS, This status is set if the Card Inserted in the Present State register changes from 0 to 1.When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed" "0,1"
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bitfld.word 0x00 5. "BUF_RD_READY, This status is set if the Buffer Read Enable changes from 0 to 1" "0,1"
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bitfld.word 0x00 4. "BUF_WR_READY, This status is set if the Buffer Write Enable changes from 0 to 1.In UHS-II mode this bit is set at FC [Flow Control] unit basis" "0,1"
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bitfld.word 0x00 3. "DMA_INTERRUPT, This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size regiser" "0,1"
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bitfld.word 0x00 2. "BLK_GAP_EVENT, If the Stop At Block Gap Request in the BlockGap Control Register is set this bit is set" "0,1"
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bitfld.word 0x00 1. "XFER_COMPLETE, This bit is set when a read / write transaction is completed" "Not complete,Command execution is completed"
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bitfld.word 0x00 0. "CMD_COMPLETE, SD Mode This bit is set when we get the end bit of the command response [Except Auto CMD12 and Auto CMD23] Note: Command Time-out Error has higher priority than Command Complete" "0,1"
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts,This register gives the status of the error interrupts"
bitfld.word 0x02 12. "HOST, Occurs when detecting ERROR in m_hresp[dma transaction] " "0,1"
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bitfld.word 0x02 11. "RESP,Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution" "0,1"
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bitfld.word 0x02 10. "TUNING,This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure [Occurrence of an error during tuning procedure is indicated by Sampling Select]" "0,1"
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bitfld.word 0x02 9. "ADMA, This bit is set when the Host Controller detects errors during ADMA based data transfer" "0,1"
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bitfld.word 0x02 8. "AUTO_CMD, Auto CMD12 and Auto CMD23 use this error status.This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1" "0,1"
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bitfld.word 0x02 7. "CURR_LIMIT, By setting the SD Bus Power bit in the Power Control Register the HC is requested to supply power for the SD Bus" "0,1"
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bitfld.word 0x02 6. "DATA_ENDBIT, Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status" "0,1"
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bitfld.word 0x02 5. "DATA_CRC, Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 010" "0,1"
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bitfld.word 0x02 4. "DATA_TIMEOUT, Occurs when detecting one of following timeout conditions: 1" "0,1"
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bitfld.word 0x02 3. "CMD_INDEX, Occurs if a Command Index error occurs in the Command Response" "0,1"
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bitfld.word 0x02 2. "CMD_ENDBIT, Occurs when detecting that the end bit of a command response is 0" "0,1"
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bitfld.word 0x02 1. "CMD_CRC, Command CRC Error is generated in two cases" "0,1"
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bitfld.word 0x02 0. "CMD_TIMEOUT, Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command" "0,1"
line.word 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sts_ena,This register is used to enable the normal interrupt status register fields"
rbitfld.word 0x04 15. "BIT15_FIXED0, The HC shall control error Interrupts using the Error Interrupt Status Enable register" "0,1"
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bitfld.word 0x04 14. "BOOT_COMPLETE, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 13. "RCV_BOOT_ACK, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 12. "RETUNING_EVENT," "Masked,Enabled"
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bitfld.word 0x04 11. "INTC, If this bit is set to 0 the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 10. "INTB, If this bit is set to 0 the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 9. "INTA, If this bit is set to 0 the Host Controller shall clear the interrupt request to the System" "0,1"
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bitfld.word 0x04 8. "CARD_INTERRUPT, If this bit is set to 0 the HC shall clear Interrupt request to the System" "0,1"
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bitfld.word 0x04 7. "CARD_REMOVAL, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 6. "CARD_INSERTION, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 5. "BUF_RD_READY, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 4. "BUF_WR_READY, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 3. "DMA_INTERRUPT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 2. "BLK_GAP_EVENT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 1. "XFER_COMPLETE, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x04 0. "CMD_COMPLETE, '0' Masked '1' Enabled " "0,1"
line.word 0x06 "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sts_ena,This register is used to enable the Error Interrupt Status register fields"
bitfld.word 0x06 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3"
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bitfld.word 0x06 12. "HOST, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 11. "RESP, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 10. "TUNING, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 9. "ADMA, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 8. "AUTO_CMD, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 7. "CURR_LIMIT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 6. "DATA_ENDBIT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 5. "DATA_CRC, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 4. "DATA_TIMEOUT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 3. "CMD_INDEX, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 2. "CMD_ENDBIT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 1. "CMD_CRC, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x06 0. "CMD_TIMEOUT, '0' Masked '1' Enabled " "0,1"
line.word 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_normal_intr_sig_ena,This register is used to enable the Normal Interrupt Signal register"
rbitfld.word 0x08 15. "BIT15_FIXED0, The HD shall control error Interrupts using the Error Interrupt Signal Enable register" "0,1"
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bitfld.word 0x08 14. "BOOT_COMPLETE, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 13. "RCV_BOOT_ACK, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 12. "RETUNING_EVENT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 11. "INTC, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 10. "INTB, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 9. "INTA, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 8. "CARD_INTERRUPT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 7. "CARD_REMOVAL, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 6. "CARD_INSERTION, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 5. "BUF_RD_READY, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 4. "BUF_WR_READY, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 3. "DMA_INTERRUPT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 2. "BLK_GAP_EVENT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 1. "XFER_COMPLETE, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x08 0. "CMD_COMPLETE, '0' Masked '1' Enabled " "0,1"
line.word 0x0A "SDHC_WRAP__CTL_CFG__CTLCFG_error_intr_sig_ena,This register is used to enable Error Interrupt Signal register"
bitfld.word 0x0A 13.--14. "VENDOR_SPECIFIC,N/A" "0,1,2,3"
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bitfld.word 0x0A 12. "HOST, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 11. "RESP, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 10. "TUNING, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 9. "ADMA, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 8. "AUTO_CMD, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 7. "CURR_LIMIT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 6. "DATA_ENDBIT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 5. "DATA_CRC, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 4. "DATA_TIMEOUT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 3. "CMD_INDEX, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 2. "CMD_ENDBIT, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 1. "CMD_CRC, '0' Masked '1' Enabled " "0,1"
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bitfld.word 0x0A 0. "CMD_TIMEOUT, '0' Masked '1' Enabled " "0,1"
line.word 0x0C "SDHC_WRAP__CTL_CFG__CTLCFG_autocmd_err_sts, This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD 23 "
bitfld.word 0x0C 7. "CMD_NOT_ISSUED, Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error [D04- D01] in this register" "0,1"
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bitfld.word 0x0C 5. "RESP, This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or Auto CMD23" "0,1"
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bitfld.word 0x0C 4. "INDEX, Occurs if the Command Index error occurs in response to a command" "0,1"
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bitfld.word 0x0C 3. "ENDBIT, Occurs when detecting that the end bit of command response is 0" "0,1"
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bitfld.word 0x0C 2. "CRC, Occurs when detecting a CRC error in the command response" "0,1"
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bitfld.word 0x0C 1. "TIMEOUT, Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command.If this bit is set to 1 the other error status bits [D04 - D02] are meaningless" "0,1"
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bitfld.word 0x0C 0. "ACMD12_NOT_EXEC, If memory multiple block data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12" "0,1"
line.word 0x0E "SDHC_WRAP__CTL_CFG__CTLCFG_host_control2,This register is used to program UHS Select Mode.UHS Select Mode.Driver Strength Select.Execute Tuning.Sampling Clock Select.Asynchronous Interrupt Enable and Preset value enable "
bitfld.word 0x0E 15. "PRESET_VALUE_ENA, Host Controller Version 3.00 supports this bit" "0,1"
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bitfld.word 0x0E 14. "ASYNCH_INTR_ENA, This bit can be set to 1 if a card support asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the Capabilities register" "0,1"
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bitfld.word 0x0E 13. "BIT64_ADDRESSING, This field is effective when Host Version 4.00 Enable is set to 1" "0,1"
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bitfld.word 0x0E 12. "HOST_VER40_ENA, This bit selects either Version 3.00 compatible mode or Ver4.mode" "0,1"
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bitfld.word 0x0E 11. "CMD23_ENA, In memory card initialization Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]" "0,1"
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bitfld.word 0x0E 10. "ADMA2_LEN_MODE, This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit" "0,1"
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bitfld.word 0x0E 9. "DRIVER_STRENGTH2, This is the programmed Drive STrength output and Bit[2] of the sdhccore_drivestrength value" "0,1"
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bitfld.word 0x0E 8. "UHS2_INTF_ENABLE, This bit is used to enable UHS-II Interface" "0,1"
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bitfld.word 0x0E 7. "SAMPLING_CLK_SELECT, This bit is set by tuning procedure when Execute Tuning is cleared" "0,1"
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bitfld.word 0x0E 6. "EXECUTE_TUNING, This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed" "0,1"
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bitfld.word 0x0E 4.--5. "DRIVER_STRENGTH1, Host Controller output driver in 1.8V signaling is selected by this bit" "0,1,2,3"
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bitfld.word 0x0E 3. "V1P8_SIGNAL_ENA, This bit controls voltage regulator for I/O cell" "0,1"
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bitfld.word 0x0E 0.--2. "UHS_MODE_SELECT, This field is used to select one of UHS-I modes or UHS-II mode.In case of UHS-I mode this field is effective when 1.8V Signal-ing Enable is set to 1" "0,1,2,3,4,5,6,7"
rgroup.quad 0x40++0x0F
line.quad 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_capabilities, This register provides the HD with information specific to the HC implementation"
bitfld.quad 0x00 63. "HS400_SUPPORT, 1 HS400 is Supported 0 HS400 is Not Supported " "0,1"
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bitfld.quad 0x00 60. "VDD2_1P8_SUPPORT, This field indicates that support of VDD2 on Host system" "0,1"
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bitfld.quad 0x00 59. "ADMA3_SUPPORT, This field indicates that support of ADMA3 on Host Controller" "0,1"
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bitfld.quad 0x00 57. "SPI_BLK_MODE, This field indicates whether SPI Block Mode is supported or not" "0,1"
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bitfld.quad 0x00 56. "SPI_SUPPORT, This field indicates whether SPI Mode is supported or not" "0,1"
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hexmask.quad.byte 0x00 48.--55. 1. "CLOCK_MULTIPLIER, This field indicates clock multiplier value of programmable clock generator"
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bitfld.quad 0x00 46.--47. "RETUNING_MODES, This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver" "0,1,2,3"
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bitfld.quad 0x00 45. "TUNING_FOR_SDR50, If this bit is set to 1 this Host Controller requires tuning to operate SDR50" "0,1"
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bitfld.quad 0x00 40.--43. "RETUNING_TIMER_CNT, This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3" "Get information via other source,1 seconds,2 seconds,4 seconds,8 seconds ------ n = 2[n-1] seconds,?,?,?,?,?,?,1024 seconds,?,?,?,Ch = Reserved"
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bitfld.quad 0x00 38. "DRIVERD_SUPPORT, This bit indicates support of Driver Type D for 1.8 Signaling" "0,1"
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bitfld.quad 0x00 37. "DRIVERC_SUPPORT, This bit indicates support of Driver Type C for 1.8 Signaling" "0,1"
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bitfld.quad 0x00 36. "DRIVERA_SUPPORT, This bit indicates support of Driver Type A for 1.8 Signaling" "0,1"
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bitfld.quad 0x00 35. "UHS2_SUPPORT, This bit indicates whether Host controller supports UHS-II" "0,1"
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bitfld.quad 0x00 34. "DDR50_SUPPORT, This bit indicates whether DDR50 is supported or not" "0,1"
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bitfld.quad 0x00 33. "SDR104_SUPPORT, This bit indicates whether SDR104 is supported or not.SDR104 requires tuning" "0,1"
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bitfld.quad 0x00 32. "SDR50_SUPPORT, If SDR104 is supported this bit shall be set to 1" "0,1"
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bitfld.quad 0x00 30.--31. "SLOT_TYPE, This field indicates usage of a slot by a specific Host System" "0,1,2,3"
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bitfld.quad 0x00 29. "ASYNCH_INTR_SUPPORT, Refer to SDIO Specification Version 3.00 about asynchronous interrupt" "0,1"
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bitfld.quad 0x00 28. "ADDR_64BIT_SUPPORT_V3, IMeaning of this bit is different depends on Versions [Refer to Table 2-35 for more details]" "0,1"
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bitfld.quad 0x00 27. "ADDR_64BIT_SUPPORT_V4, This bit is added from Version 4.10" "0,1"
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bitfld.quad 0x00 26. "VOLT_1P8_SUPPORT, This bit indicates whether the HC supports 1.8V" "0,1"
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bitfld.quad 0x00 25. "VOLT_3P0_SUPPORT, This bit indicates whether the HC supports 3.0V" "0,1"
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bitfld.quad 0x00 24. "VOLT_3P3_SUPPORT, This bit indicates whether the HC supports 3.3V" "0,1"
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bitfld.quad 0x00 23. "SUSP_RES_SUPPORT, This bit indicates whether the HC supports Suspend / Resume functionality" "0,1"
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bitfld.quad 0x00 22. "SDMA_SUPPORT, This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly.Version 4.10 Host Controller shall support SDMA if ADMA2 is supported" "0,1"
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bitfld.quad 0x00 21. "HIGH_SPEED_SUPPORT, This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25Mhz to 50 Mhz [for SD]/ 20MHz to 52MHz [for MMC]" "0,1"
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bitfld.quad 0x00 19. "ADMA2_SUPPORT, '0' ADMA2 Not Supported '1' ADMA2 Supported " "0,1"
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bitfld.quad 0x00 18. "BUS_8BIT_SUPPORT, This bit indicates whether the Host Controller is capable of using 8-bit bus width mode" "0,1"
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bitfld.quad 0x00 16.--17. "MAX_BLK_LENGTH, This value indicates the maximum block size that the HD can read and write to the buffer in the HC" "0,1,2,3"
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hexmask.quad.byte 0x00 8.--15. 1. "BASE_CLK_FREQ, [1]6-bit Base Clock Frequency: This mode is supported by the Host Controller Version 1.00 and 2.00"
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bitfld.quad 0x00 7. "TIMEOUT_CLK_UNIT, This bit shows the unit of base clock frequency used to detect Data Timeout Error" "0,1"
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bitfld.quad 0x00 0.--5. "TIMEOUT_CLK_FREQ, This bit shows the base clock frequency used to detect Data Timeout Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.quad 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_max_current_cap,This register indicates maximum current capability for each voltage"
hexmask.quad.byte 0x08 32.--39. 1. "VDD2_1P8V,Maximum Current for 1.8V VDD2"
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hexmask.quad.byte 0x08 16.--23. 1. "VDD1_1P8V,Maximum Current for 1.8V VDD1"
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hexmask.quad.byte 0x08 8.--15. 1. "VDD1_3P0V, Maximum Current for 3.0V VDD1 "
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hexmask.quad.byte 0x08 0.--7. 1. "VDD1_3P3V, Maximum Current for 3.3V VDD1 "
group.word 0x50++0x03
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_ACMD_Err_Sts,This register is not physically implemented. rather it is an address where Auto CMD Error Status register can be written. Writing"
bitfld.word 0x00 7. "CMD_NOT_ISS, Force Event for Command Not Issued by AUTO CMD12 Error" "0,1"
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bitfld.word 0x00 5. "RESP, Force Event for AUTO CMD Response Error" "0,1"
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bitfld.word 0x00 4. "INDEX, Force Event for AUTO CMD Index Error" "0,1"
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bitfld.word 0x00 3. "ENDBIT, Force Event for AUTO CMD End Bit Error" "0,1"
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bitfld.word 0x00 2. "CRC, Force Event for AUTO CMD Timeout Error" "0,1"
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bitfld.word 0x00 1. "TIMEOUT, Force Event for AUTO CMD Timeout Error" "0,1"
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bitfld.word 0x00 0. "ACMD_NOT_EXEC, Force Event for AUTO CMD12 Not Executed" "0,1"
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_force_evnt_Err_Int_Sts,This register is not physically implemented. rather it is an address where Error Interrupt Status register can be written"
bitfld.word 0x02 12. "HOST, Force Event for Host Error " "0,1"
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bitfld.word 0x02 11. "RESP, Force Event for Response Error " "0,1"
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bitfld.word 0x02 10. "TUNING, Force Event for Tuning Error" "0,1"
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bitfld.word 0x02 9. "ADMA, Force Event for ADMA Error" "0,1"
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bitfld.word 0x02 8. "AUTO_CMD, Force Event for Auto CMD Error" "0,1"
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bitfld.word 0x02 7. "CURR_LIM, Force Event for Current Limit Error" "0,1"
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bitfld.word 0x02 6. "DAT_ENDBIT, Force Event for Data End Bit Error" "0,1"
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bitfld.word 0x02 5. "DAT_CRC, Force Event for Data CRC Error" "0,1"
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bitfld.word 0x02 4. "DAT_TIMEOUT, Force Event for Data Timeout Error" "0,1"
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bitfld.word 0x02 3. "CMD_INDEX, Force Event for Command Index Error " "0,1"
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bitfld.word 0x02 2. "CMD_ENDBIT, Force Event for Command End Bit Error" "0,1"
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bitfld.word 0x02 1. "CMD_CRC, Force Event for Command CRC Error" "0,1"
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bitfld.word 0x02 0. "CMD_TIMEOUT, Force Event for CMD Timeout Error" "0,1"
rgroup.byte 0x54++0x00
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_err_status,When the ADMA Error interrupt occur. this register holds the ADMA State in ADMA Error States field and ADMA System Address holds address around the error descriptor"
bitfld.byte 0x00 2. "ADMA_LENGTH_ERR, This error occurs in the following 2 cases" "0,1"
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bitfld.byte 0x00 0.--1. "ADMA_ERR_STATE, This field indicates the state of ADMA when error is occurred during ADMA data transfer" "0,1,2,3"
group.quad 0x58++0x07
line.quad 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_adma_sys_address,This register contains the physical address used for ADMA data transfer"
repeat 10. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 10. )(list 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x12 0x14 )
rgroup.word ($2+0x60)++0x01
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_preset_value$1, This register is used to read the SDCLK Frequency Select Value.Clock Generator Select Value.Driver Strength Select Value "
bitfld.word 0x00 14.--15. "DRIVER_STRENGTH_SEL,Driver Strength is supported by 1.8V signaling bus speed modes" "0,1,2,3"
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bitfld.word 0x00 10. "CLOCK_GENSEL, This bit is effective when Host Controller supports programmable clock '0' Host Controller Ver2.00 Compatible Clock Generator '1' Programmable Clock Generator " "0,1"
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hexmask.word 0x00 0.--9. 1. "SDCLK_FRQSEL, 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system"
repeat.end
group.quad 0x78++0x07
line.quad 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_adma3_desc_address,The start address of Integrated DMA Descriptor is set to this register"
group.word 0x80++0x01
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_size,This register is used to configure the number of bytes in a data block"
bitfld.word 0x00 12.--14. "SDMA_BUF_BOUNDARY, When system memory is managed by paging SDMA data transfer is performed in unit of paging" "0,1,2,3,4,5,6,7"
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hexmask.word 0x00 0.--11. 1. "XFER_BLK_SIZE,This register specifies the block size of data packet"
group.long 0x84++0x03
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_block_count,This register is used to configure the number of data blocks"
group.byte 0x88++0x00
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command_pkt,UHS-II Command Packet image is set to this register"
group.word 0x9C++0x03
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_xfer_mode,This register is used to control the operations of data transfers"
bitfld.word 0x00 15. "DUPLEX_SELECT, Use of 2 lane half duplex mode is determined by Host Driver" "0,1"
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bitfld.word 0x00 14. "EBSY_WAIT, This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution" "0,1"
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bitfld.word 0x00 8. "RESP_INTR_DIS, Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver" "0,1"
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bitfld.word 0x00 7. "RESP_ERR_CHK_ENA, Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver.Only R1 or R5 can be checked" "0,1"
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bitfld.word 0x00 6. "RESP_TYPE, When response error check is enabled this bit selects either R1 or R5 response types" "0,1"
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bitfld.word 0x00 5. "BYTE_MODE, This bit specifies whether data transfer is in byte mode or block mode when Data Present is set to 1" "0,1"
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bitfld.word 0x00 4. "DATA_XFER_DIR, This bit specifies direction of data trans-fer when Data Present is set to 1" "Read [Card to Host],Write [Host to Card]"
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bitfld.word 0x00 1. "BLK_CNT_ENA, This bit specifies whether data transfer usesUHS-II Block Count register" "0,1"
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bitfld.word 0x00 0. "DMA_ENA,This bit selects whether DMA is used or not and is effective to a command with data transfer" "0,1"
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_command,This register is used to program the Command for host controller"
bitfld.word 0x02 8.--12. "PKT_LENGTH,A command packet length which is set in the UHS-II Command Packet register is set to this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.word 0x02 6.--7. "CMD_TYPE, This field is used to distinguish a spe-cific command like abort command" "0,1,2,3"
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bitfld.word 0x02 5. "DATA_PRESENT,This bit specifies whether the command is accompanied by data packet" "0,1"
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bitfld.word 0x02 2. "SUB_COMMAND,This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17].When issuing a main command this bit is set to 0 and when issuing a sub com-mand this bit is set to 1" "0,1"
rgroup.byte 0xA0++0x00
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_response,This register is used to store received UHS-II RES Packet image"
group.byte 0xB4++0x00
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message_select,This register is used to access internal buffer"
bitfld.byte 0x00 0.--1. "MSG_SEL,Host Controller holds 4 MSG packets in FIFO buffer.One of 4 MSGs can be read from the UHS-II MSG register [0BB-0B8h] by setting this register.[Assumed for debug usage.] '00' The latest MSG '01' One MSG before '10' Two MSGs before '11' Three.." "0,1,2,3"
rgroup.long 0xB8++0x03
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_message,This register is used to access internal buffer"
hexmask.long.byte 0x00 24.--31. 1. "MSG_BYTE3, Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 16.--23. 1. "MSG_BYTE2, Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 8.--15. 1. "MSG_BYTE1, Host Controller holds 4 MSG packets in FIFO buffer"
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hexmask.long.byte 0x00 0.--7. 1. "MSG_BYTE0, Host Controller holds 4 MSG packets in FIFO buffer"
group.word 0xBC++0x01
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_intr_status,This register shows receipt of INT MSG from which device "
group.byte 0xBE++0x01
line.byte 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_select,UHS-II Device Select Register "
bitfld.byte 0x00 7. "INT_MSG_ENA, This bit enables receipt of INT MSG" "0,1"
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bitfld.byte 0x00 0.--3. "DEV_SEL,Host Controller holds an INT MSG packet per device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.byte 0x01 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_device_int_code,This register is effective when INT MSG Enable is set to 1 in the UHS-II Device Select register. "
group.word 0xC0++0x03
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_software_reset,UHS-II Software Reset Register "
bitfld.word 0x00 1. "HOST_SDTRAN_RESET,Host Driver set this bit to 1 to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs" "0,1"
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bitfld.word 0x00 0. "HOST_FULL_RESET,On issuing FULL_RESET CCMD Host Driver set this bit to 1 to reset Host Controller" "0,1"
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_timer_control,UHS-II Timeout Control Register"
bitfld.word 0x02 4.--7. "DEADLOCK_TIMEOUT_CTR, This value determines the deadlock period while host expecting to receive a packet [1 second]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x02 0.--3. "CMDRESP_TIMEOUT_CTR, This value determines the interval between com-mand packet and response packet [5ms]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC4++0x0B
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts,This register gives the status of all UHS-II interrupts"
bitfld.long 0x00 27.--31. "VENDOR_SPECFIC_ERR, Vendor may use this field for vendor specific error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 17. "DEADLOCK_TIMEOUT, Setting of this bit means that deadlock timeout occurs" "0,1"
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bitfld.long 0x00 16. "CMD_RESP_TIMEOUT, Setting of this bit means that RES Packet timeout occurs" "0,1"
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bitfld.long 0x00 15. "ADMA2_ADMA3, Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode" "0,1"
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bitfld.long 0x00 8. "EBSY, On receiving EBSY packet if the packet indicates an error this bit is set to 1" "0,1"
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bitfld.long 0x00 7. "UNRECOVERABLE, Setting of this bit means that Unrecoverable Error is set in a packet from a device" "0,1"
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bitfld.long 0x00 5. "TID, Setting of this bit means that TID Error occurs" "0,1"
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bitfld.long 0x00 4. "FRAMING, Setting of this bit means that Framing Error occurs during a packet receiving" "0,1"
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bitfld.long 0x00 3. "CRC, Setting of this bit means that CRC Error occurs during a packet receiving" "0,1"
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bitfld.long 0x00 2. "RETRY_EXPIRED, Setting of this bit means that Retry Counter Expired Error occurs during data transfer.If this bit is set either Framing Error or CRC Error in this register shall be set" "0,1"
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bitfld.long 0x00 1. "RESP_PKT, Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution" "0,1"
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bitfld.long 0x00 0. "HEADER, Setting of this bit means that Header Error occurs in a received packet" "0,1"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sts_ena,This register is used to enable the UHS-II Error Interrupt Status register fields"
bitfld.long 0x04 27.--31. "VENDOR_SPECFIC, Setting this bit to 1 enables setting of Vendor Specific Error bit in the UHS-II Error Interrupt Status register" "Status is Disabled,Status is Enabled,?..."
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bitfld.long 0x04 17. "DEADLOCK_TIMEOUT, Setting this bit to 1 enables setting of Timeout for Dead lock bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 16. "CMD_RESP_TIMEOUT, Setting this bit to 1 enables setting of Timeout for CMD_RES bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 15. "ADMA2_ADMA3, Setting this bit to 1 enables setting of ADMA2/3 Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 8. "EBSY, Setting this bit to 1 enables setting of EBSY Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 7. "UNRECOVERABLE, Setting this bit to 1 enables setting of Unrecoverable Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 5. "TID, Setting this bit to 1 enables setting of TID Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 4. "FRAMING, Setting this bit to 1 enables setting of Framing Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 3. "CRC, Setting this bit to 1 enables setting of CRC Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 2. "RETRY_EXPIRED, Setting this bit to 1 enables setting of Retry Expired bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 1. "RESP_PKT, Setting this bit to 1 enables setting of RES Packet Error bit in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x04 0. "HEADER, Setting this bit to 1 enables setting of Header Error bit in the UHS-II Error Interrupt Status Register" "0,1"
line.long 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_err_intr_sig_ena,This register is used to generate UHS-II Interrupt signals"
bitfld.long 0x08 27.--31. "VENDOR_SPECFIC, Setting of a bit to 1 in this field enables generating interrupt signal when corre-spondent bit of Vendor Specific Error is set in the UHS-II Error Interrupt Status Register" "Interrupt Signal is Disabled,Interrupt Signal is Enabled,?..."
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bitfld.long 0x08 17. "DEADLOCK_TIMEOUT, Setting this bit to 1 enables generating interrupt signal when Timeout for Dead lock bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 16. "CMD_RESP_TIMEOUT, Setting this bit to 1 enables generating interrupt signal when Timeout for CMD_RES bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 15. "ADMA2_ADMA3, Setting this bit to 1 enables generating interrupt signal when ADMA2/3 Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 8. "EBSY, Setting this bit to 1 enables generating interrupt signal when EBSY Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 7. "UNRECOVERABLE, Setting this bit to 1 enables generating interrupt signal when Unrecoverable Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 5. "TID, Setting this bit to 1 enables generating interrupt signal when TID Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 4. "FRAMING, Setting this bit to 1 enables generating interrupt signal when Framing Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 3. "CRC, Setting this bit to 1 enables generating interrupt signal when CRC Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 2. "RETRY_EXPIRED_SIG_ENA, Setting this bit to 1 enables generating interrupt signal when Retry Expired bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 1. "RESP_PKT, Setting this bit to 1 enables generating interrupt signal when RES Packet Error bit is set in the UHS-II Error InterruptStatus Register" "0,1"
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bitfld.long 0x08 0. "HEADER,Setting this bit to 1 enables generating interrupt signal when Header Error bit is set in the UHS-II Error Interrupt Status Register" "0,1"
rgroup.word 0xE0++0x09
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_settings_ptr, This register is pointer for UHS-II settings. "
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_capabilities_ptr, This register is pointer for UHS-II Capabilities Register. "
line.word 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_test_ptr, This register is pointer for UHS-II Test Register. "
line.word 0x06 "SDHC_WRAP__CTL_CFG__CTLCFG_shared_bus_ctrl_ptr, This register is pointer for UHS-II Shared Bus Control Register. "
line.word 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_specfic_ptr, This register is pointer for UHS-II Vendor Specific Pointer Register. "
group.long 0xF4++0x07
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_boot_timeout_control,This is used to program the boot timeout value counter"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_vendor_register,Vendor register added for autogate sdclk. cmd11 power down timer. enhancedstrobe and eMMC hardware reset"
bitfld.long 0x04 16. "AUTOGATE_SDCLK,If this bit is set SD CLK will be gated automatically when there is no transfer" "0,1"
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hexmask.long.word 0x04 2.--15. 1. "CMD11_PD_TIMER,cmd11 power-down timer value "
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bitfld.long 0x04 1. "EMMC_HW_RESET,Hardware reset signal is generared for eMMC card when this bit is set " "0,1"
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bitfld.long 0x04 0. "ENHANCED_STROBE,This bit enables the enhanced strobe logic of the Host Controller" "0,1"
rgroup.word 0xFC++0x03
line.word 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_slot_int_sts,This register is used to read the interrupt signal for each slot"
hexmask.word.byte 0x00 0.--7. 1. "INTR_SIG, These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot"
line.word 0x02 "SDHC_WRAP__CTL_CFG__CTLCFG_host_controller_ver,This register is used to read the vendor version number and specification version number "
hexmask.word.byte 0x02 8.--15. 1. "VEN_VER_NUM, The Vendor Version Number is set to 0x10 [1.0] "
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abitfld.word 0x02 0.--7. "SPEC_VER_NUM, This status indicates the Host Controller Spec" "0x00=SD Host Controller Specification Version 1.00,0x01=SD Host Controller Specification Version..,0x02=SD Host Controller Specification Version 3.00,0x03=SD Host Controller Specification Version 4.00,0x04=SD Host Controller Specification Version.."
group.long 0x100++0x07
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_settings,Start Address of General settings is pointed by Pointer for UHS-II Setting Register. "
bitfld.long 0x00 8.--13. "NUMLANES, The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0. "POWER_MODE, This field determines either Fast mode or Low Power mode.Host and all devices connected to the host shall be set to the same mode" "0,1"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_settings,Start Address of PHY settings is pointed by Pointer for UHS-II Setting Register. "
bitfld.long 0x04 20.--23. "N_LSS_DIR,The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "N_LSS_SYN,The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 15. "HIBERNATE_ENA,After checking card capability of Hibernate mode if all devices support Hibernate mode this bit may be set" "0,1"
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bitfld.long 0x04 6.--7. "SPEED_RANGE,PLL multiplier is selected by this field.Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State" "0,1,2,3"
group.quad 0x108++0x07
line.quad 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_settings,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Setting Register. "
hexmask.quad.byte 0x00 32.--39. 1. "N_DATA_GAP, The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field"
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bitfld.quad 0x00 16.--17. "RETRY_COUNT, Data Burst retry count is set to this field" "0,1,2,3"
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hexmask.quad.byte 0x00 8.--15. 1. "HOST_NFCU, Host Driver sets the number of blocks in Data Burst [Flow Control] to this field.The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices"
rgroup.long 0x110++0x07
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_gen_cap,Start Address of General Capabilities is pointed by Pointer for UHS-II Host Capabilities Register. "
bitfld.long 0x00 22.--23. "CORECFG_UHS2_BUS_TOPLOGY,This field indicates one of bus topologies configured by a Host system" "0,1,2,3"
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bitfld.long 0x00 18.--21. "CORECFG_UHS2_MAX_DEVICES,This field indicates the maximum number of devices supported by the Host Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--17. "DEVICE_TYPE,This field indicates device type configured by a Host system" "0,1,2,3"
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bitfld.long 0x00 14. "CFG_64BIT_ADDRESSING,This field indicates support of 64-bit addressing by the Host Controller" "0,1"
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bitfld.long 0x00 8.--13. "NUM_LANES,This field indicates support of lanes by the Host Controller.0 mean not supported and 1 means supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 4.--7. "GAP,This field indicates the maximum capability of host power supply for a group configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -Not used" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "DAP,This field indicates the maximum capability of host power supply for a device configured by a Host system.This field is used to set the argument of DEVICE_INIT CCMD 0h -360 mW [Default]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_phy_cap,Start Address of PHY Capabilities is pointed by Pointer for UHS-II Host Capabilities Register. "
bitfld.long 0x04 20.--23. "N_LSS_DIR, This field indicates the minimum N_LSS_DIR required by the Host Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "N_LSS_SYN,This field indicates the minimum N_LSS_SYN required by the Host Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 6.--7. "SPEED_RANGE,This field indicates supported Speed Range by the Host Controller '00' Range A [Default] '01' Range A and Range B '10' Reserved '11' Reserved " "0,1,2,3"
rgroup.quad 0x118++0x07
line.quad 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_uhs2_lnk_trn_cap,Start Address of LINK/TRAN settings is pointed by Pointer for UHS-II Capabilities Register. "
hexmask.quad.byte 0x00 32.--39. 1. "N_DATA_GAP,This field indicates the minimum number of data gap[DIDL] supported by the Host Controller. "
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hexmask.quad.word 0x00 20.--31. 1. "MAX_BLK_LENGTH,This field indicates maximum block length by the Host Controller"
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hexmask.quad.byte 0x00 8.--15. 1. "N_FCU, This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller.This value is determined by supported buffer size"
group.long 0x120++0x03
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_force_UHSII_Err_Int_Sts,This register is not physically implemented. rather it is an address where UHS-II Error Interrupt Status register can be written. "
bitfld.long 0x00 27.--31. "VENDOR_SPECIFIC,Force Event for Vendor Specific Error " "Not Affected,Vendor Specific Error Status is set,?..."
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bitfld.long 0x00 17. "TIMEOUT_DEADLOCK,Setting this bit forces the Host Controller to set Timeout for Deadlock in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 16. "TIMEOUT_CMD_RES,Setting this bit forces the Host Controller to set Timeout for CMD_RES in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 15. "ADMA,Setting this bit forces the Host Controller to set ADMA Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 8. "EBSY,Setting this bit forces the Host Controller to set EBSY Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 7. "UNRECOVERABLE,Setting this bit forces the Host Controller to set Unrecover-able Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 5. "TID,Setting this bit forces the Host Controller to set TID Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 4. "FRAMING,Setting this bit forces the Host Controller to set Framing Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 3. "CRC,Setting this bit forces the Host Controller to set CRC Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 2. "RETRY_EXPIRED,Setting this bit forces the Host Controller to set Retry Expired in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 1. "RES_PKT,Setting this bit forces the Host Controller to set RES Packet Error in the UHS-II Error Interrupt Status register" "0,1"
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bitfld.long 0x00 0. "HEADER,Setting this bit forces the Host Controller to set Header Error in the UHS-II Error Interrupt Status register" "0,1"
rgroup.long 0x200++0x3B
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_version,This register provides information about the version of the eMMC CQ standard which is 285 implemented by the CQE. in BCD format"
bitfld.long 0x00 8.--11. "EMMC_MAJOR_VER_NUM, eMMC Major Version Number [digit left of decimal point] in BCD format " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "EMMC_MINOR_VER_NUM, eMMC Minor Version Number [digit right of decimal point] in BCD format " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EMMC_VERSION_SUFFIX, eMMC Version Suffix [2nd digit right of decimal point] in BCD format " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_capabilities,This register is reserved for capability indication. "
bitfld.long 0x04 12.--15. "CF_MUL, Internal Timer Clock Frequency Multiplier [ITCFMUL] ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the SQS polling period" "0.001 MHz,0.01 MHz,0.1 MHz,1 MHz,10 MHz Other values..,?..."
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hexmask.long.word 0x04 0.--9. 1. "CF_VAL, Internal Timer Clock Frequency Value [ITCFVAL] TCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for deter-mining the polling period when using periodic SEND_QUEUE_ STATUS [CMD13] polling"
line.long 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_config,This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time. "
bitfld.long 0x08 12. "DCMD_ENA, Direct Command [DCMD] Enable This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor or a Direct Command Task Descriptor" "Task descriptor in slot #31 is a Data Transfer..,Task descriptor in slot #31 is a DCMD Task.."
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bitfld.long 0x08 8. "TASK_DESC_SIZE, Task Descriptor Size This bit indicates whether the task descriptor size is 128 bits or 64 bits as detailed in Data Structures section" "Task descriptor size is 64 bits,Task descriptor size is 128 bits"
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bitfld.long 0x08 0. "CQ_ENABLE, Command Queueing Enable Software shall write 1 this bit when in order to enable command queueing mode [i.e. enable CQE]" "0,1"
line.long 0x0C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_control,This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time. "
bitfld.long 0x0C 8. "CLEAR_ALL_TASKS, Clear All Tasks Software shall write 1 this bit when it wants to clear all the tasks sent to the device" "0,1"
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bitfld.long 0x0C 0. "HALT_BIT, Halt Host software shall write 1 to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus" "0,1"
line.long 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts,This register indicates pending interrupts that require service"
bitfld.long 0x10 4. "TASK_ERROR, Task Error Interrupt [TERR] This bit is asserted when task error is detected due to invalid task descriptor " "0,1"
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bitfld.long 0x10 3. "TASK_CLEARED, Task Cleared [TCL] This status bit is asserted [if CQISTE.TCL=1] when a task clear operation is completed by CQE" "0,1"
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bitfld.long 0x10 2. "RESP_ERR_DET, Response Error Detected Interrupt [RED] This status bit is asserted [if CQISTE.RED=1] when a response is received with an error bit set in the device status field" "0,1"
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bitfld.long 0x10 1. "TASK_COMPLETE,Task Complete Interrupt [TCC] This status bit is asserted [if CQISTE.TCC=1] when atleast one of the following two conditions are met: [1] A task is completed and the INT bit is set in its Task Descriptor [2] Interrupt caused by Interrupt.." "0,1"
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bitfld.long 0x10 0. "HALT_COMPLETE, Halt Complete Interrupt [HAC] This status bit is asserted [if CQISTE.HAC=1] when halt bit in CQCTL register transitions from 0 to 1 indicating that host controller has completed its current ongoing task and has entered halt state" "0,1"
line.long 0x14 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sts_ena,This register enables and disables the reporting of the corresponding interrupt to host soft-ware in 299 CQIS register"
bitfld.long 0x14 4. "TASK_ERROR, Task Error Interrupt Status Enable" "CQIS.TERR is disabled,CQIS.TERR will be set when its interrupt.."
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bitfld.long 0x14 3. "TASK_CLEARED, Task Cleared Status Enable [TCL]" "CQIS.TCL is disabled,CQIS.TCL will be set when its interrupt.."
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bitfld.long 0x14 2. "RESP_ERR_DET, Response Error Detected Status Enable [RED]" "CQIS.RED is disabled,CQIS.RED will be set when its interrupt.."
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bitfld.long 0x14 1. "TASK_COMPLETE, Task Complete Status Enable [TCC]" "CQIS.TCC is disabled,CQIS.TCC will be set when its interrupt.."
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bitfld.long 0x14 0. "HALT_COMPLETE, Halt Complete Status Enable [HAC]" "CQIS.HAC is disabled,CQIS.HAC will be set when its interrupt.."
line.long 0x18 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_sig_ena,This register enables and disables the generation of interrupts to host software"
bitfld.long 0x18 4. "TASK_ERROR, Task Error Interrupt Signal Enable [TERR] When set and CQIS.TERR is asserted the CQE shall generate an interrupt " "0,1"
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bitfld.long 0x18 3. "TASK_CLEARED, Task Cleared Signal Enable [TCL] When set and CQIS.TCL is asserted the CQE shall generate an interrupt " "0,1"
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bitfld.long 0x18 2. "RESP_ERR_DET, Response Error Detected Signal Enable [TCC] When set and CQIS.RED is asserted the CQE shall generate an interrupt " "0,1"
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bitfld.long 0x18 1. "TASK_COMPLETE, Task Complete Signal Enable [TCC] When set and CQIS.TCC is asserted the CQE shall generate an interrupt " "0,1"
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bitfld.long 0x18 0. "HALT_COMPLETE, Halt Complete Signal Enable [HAC] When set and CQIS.HAC is asserted the CQE shall generate an interrupt " "0,1"
line.long 0x1C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_intr_coalescing,This register controls the interrupt coalescing feature. "
bitfld.long 0x1C 31. "CQINTCOALESC_ENABLE, When set to 0 by software command responses are neither counted nor timed" "0,1"
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bitfld.long 0x1C 20. "IC_STATUS, This bit indicates to software whether any tasks [with INT=0] have completed and counted towards interrupt coalescing [i.e. ICSB is set if and only if IC counter > 0]" "No task completions have occurred since last..,At least one task completion has been counted.."
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bitfld.long 0x1C 8.--12. "CTR_THRESHOLD, Interrupt Coalescing Counter Threshold [ICCTH]: Software uses this field to configure the number of task completions [only tasks with INT=0 in the Task Descriptor] which are required in order to generate an interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x1C 0.--6. 1. "TIMEOUT_VAL, Interrupt Coalescing Timeout Value [ICTOVAL]: Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt"
line.long 0x20 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr,This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory. "
line.long 0x24 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_tdl_base_addr_upbits,This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory. "
line.long 0x28 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_door_bell,Using this register. software triggers CQE to process a new task. "
line.long 0x2C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_comp_notif,This register is used by CQE to notify software about completed tasks. "
line.long 0x30 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_queue_status,This register stores the most recent value of the device s queue status. "
line.long 0x34 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dev_pending_tasks,This register indicates to software which tasks are queued in the device. awaiting execution. "
line.long 0x38 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_clear,This register is used for removing an outstanding task in the CQE"
group.long 0x240++0x0B
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config1,The register controls the when SEND_QUEUE_STATUS commands are sent. "
bitfld.long 0x00 16.--19. "CMD_BLK_CNTR,This field indicates to CQE when to send SEND_QUEUE_STATUS [CMD13] command to inquire the status of the devices task queue.A value of n means CQE shall send status command on the CMD line during the transfer of data block BLOCK_CNT-n on the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "CMD_IDLE_TIMER,This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS [CMD13] polling.Periodic polling is used when tasks are pending in the device but no data transfer is in progress"
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_send_sts_config2,This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argu-ment. "
hexmask.long.word 0x04 0.--15. 1. "QUEUE_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_ STATUS [CMD13] com-mand"
line.long 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_dcmd_response,This register is used for passing the response of a DCMD task to software. "
group.long 0x250++0x13
line.long 0x00 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_resp_err_mask,This register controls the generation of Response Error Detection (RED) interrupt. "
line.long 0x04 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_task_err_info,This register is updated by CQE when an error occurs on data or command related to a task activity"
bitfld.long 0x04 31. "DATERR_VALID, Data Transfer Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller" "0,1"
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bitfld.long 0x04 24.--28. "DATERR_TASK_ID, Data Transfer Error Task ID This field indicates the ID of the task which was executed on the data lines when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 16.--21. "DATERR_CMD_INDEX, Data Transfer Error Command Index This field indicates the index of the command which was executed on the data lines when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 15. "RESP_MODE_VALID, Response Mode Error Fields Valid This bit is updated when an error is detected by CQE or indicated by eMMC controller" "0,1"
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bitfld.long 0x04 8.--12. "RESP_MODE_TASK_ID, Response Mode Error Task ID This field indicates the ID of the task which was executed on the command line when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--5. "RESP_MODE_CMD_INDEX, Response Mode Error Command Index This field indicates the index of the command which was executed on the command line when an error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_index,This register stores the index of the last received command response. "
bitfld.long 0x08 0.--5. "LAST_CRI,This field stores the index of the last received command response" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "SDHC_WRAP__CTL_CFG__CTLCFG_cq_cmd_resp_arg,This register stores the index of the last received command response. "
line.long 0x10 "SDHC_WRAP__CTL_CFG__CTLCFG_cq_error_task_id,CQ Error Task ID Register "
bitfld.long 0x10 0.--4. "TERR_ID,Task Error ID " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "MMCSD2_ECC_AGGR_RXMEM"
base ad:0x70B000
rgroup.long 0x00++0x03
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ECC_AGGR_RXMEM__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ECC_AGGR_RXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_RXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_RXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "RXMEM_PEND,Interrupt Pending Status for rxmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_SET,Interrupt Enable Set Register for rxmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "RXMEM_ENABLE_CLR,Interrupt Enable Clear Register for rxmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ECC_AGGR_RXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ECC_AGGR_RXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MMCSD2_ECC_AGGR_TXMEM"
base ad:0x70A000
rgroup.long 0x00++0x03
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "ECC_AGGR_TXMEM__CFG__REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "ECC_AGGR_TXMEM__CFG__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_TXMEM__CFG__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ECC_AGGR_TXMEM__CFG__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "TXMEM_PEND,Interrupt Pending Status for txmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_SET,Interrupt Enable Set Register for txmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "TXMEM_ENABLE_CLR,Interrupt Enable Clear Register for txmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "ECC_AGGR_TXMEM__CFG__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "ECC_AGGR_TXMEM__CFG__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MMCSD2_SS_CFG"
base ad:0xFA28000
rgroup.long 0x00++0x03
line.long 0x00 "REGS__SS_CFG__SSCFG_SS_ID_REV_REG,The Subsystem ID and Revision Register contains the module ID. major. and minor revisions for the subsystem"
hexmask.long.word 0x00 16.--31. 1. "MOD_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJ_REV,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MIN_REV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x33
line.long 0x00 "REGS__SS_CFG__SSCFG_CTL_CFG_1_REG,The Controller Config 1 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
bitfld.long 0x00 24.--29. "TUNINGCOUNT,Configures the Number of Taps (Phases) of the RX clock that is supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 20. "ASYNCWKUPENA,Determines the Wakeup Signal Generation Mode" "Synchronous Wakeup Mode,Asyncrhonous Wakeup Mode"
bitfld.long 0x00 12.--15. "CQFMUL,FMUL for the CQ Internal Timer Clock Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 0.--9. 1. "CQFVAL,FVAL for the CQ Internal Timer Clock Frequency"
line.long 0x04 "REGS__SS_CFG__SSCFG_CTL_CFG_2_REG,The Controller Config 2 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
bitfld.long 0x04 30.--31. "SLOTTYPE,Slot Type" "Removable SCard Slot,Embedded Slot for One Device,Shared Bus Slot,Reserved"
bitfld.long 0x04 29. "ASYNCHINTRSUPPORT,Asynchronous Interrupt Support" "0,1"
bitfld.long 0x04 26. "SUPPORT1P8VOLT,1.8V Support" "0,1"
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bitfld.long 0x04 25. "SUPPORT3P0VOLT,3.0V Support" "0,1"
bitfld.long 0x04 24. "SUPPORT3P3VOLT,3.3V Support" "0,1"
bitfld.long 0x04 23. "SUSPRESSUPPORT,Suspend/Resume Support" "0,1"
newline
bitfld.long 0x04 22. "SDMASUPPORT,SDMA Support" "0,1"
bitfld.long 0x04 21. "HIGHSPEEDSUPPORT,High Speed Support" "0,1"
bitfld.long 0x04 19. "ADMA2SUPPORT,ADMA2 Support" "0,1"
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bitfld.long 0x04 18. "SUPPORT8BIT,8-bit Support for Embedded Device" "0,1"
bitfld.long 0x04 16.--17. "MAXBLKLENGTH,Max Block Length" "512 (Bytes),1024,2048,Reserved"
hexmask.long.byte 0x04 8.--15. 1. "BASECLKFREQ,Base Clock Frequency for SD Clock"
newline
bitfld.long 0x04 7. "TIMEOUTCLKUNIT,Timeout Clock Unit" "0,1"
bitfld.long 0x04 0.--5. "TIMEOUTCLKFREQ,Timeout Clock Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "REGS__SS_CFG__SSCFG_CTL_CFG_3_REG,The Controller Config 3 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
bitfld.long 0x08 28. "SUPPORT1P8VDD2,1.8V VDD2 Support" "0,1"
bitfld.long 0x08 27. "ADMA3SUPPORT,ADMA3 Support" "0,1"
hexmask.long.byte 0x08 16.--23. 1. "CLOCKMULTIPLIER,Clock Multiplier"
newline
bitfld.long 0x08 14.--15. "RETUNINGMODES,Re-Tuning Modes" "0,1,2,3"
bitfld.long 0x08 13. "TUNINGFORSDR50,Use Tuning for SDR50" "0,1"
bitfld.long 0x08 8.--11. "RETUNINGTIMERCNT,Timer Count for Re-Tuning" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 7. "TYPE4SUPPORT,Driver Type 4 Support" "0,1"
bitfld.long 0x08 6. "DDRIVERSUPPORT,Driver Type D Support" "0,1"
bitfld.long 0x08 5. "CDRIVERSUPPORT,Driver Type C Support" "0,1"
newline
bitfld.long 0x08 4. "ADRIVERSUPPORT,Driver Type A Support" "0,1"
bitfld.long 0x08 2. "DDR50SUPPORT,DDR50 Support" "0,1"
bitfld.long 0x08 1. "SDR104SUPPORT,SDR104 Support" "0,1"
newline
bitfld.long 0x08 0. "SDR50SUPPORT,SDR50 Support" "0,1"
line.long 0x0C "REGS__SS_CFG__SSCFG_CTL_CFG_4_REG,The Controller Config 4 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.byte 0x0C 16.--23. 1. "MAXCURRENT1P8V,Maximum Current for 1.8V"
hexmask.long.byte 0x0C 8.--15. 1. "MAXCURRENT3P0V,Maximum Current for 3.0V"
hexmask.long.byte 0x0C 0.--7. 1. "MAXCURRENT3P3V,Maximum Current for 3.3V"
line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_CFG_5_REG,The Controller Config 5 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.byte 0x10 0.--7. 1. "MAXCURRENTVDD2,Maximum Current for 1.8 V (VDD2)"
line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_CFG_6_REG,The Controller Config 6 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x14 0.--12. 1. "INITPRESETVAL,Preset Value for Initialization"
line.long 0x18 "REGS__SS_CFG__SSCFG_CTL_CFG_7_REG,The Controller Config 7 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x18 0.--12. 1. "DSPDPRESETVAL,Preset Value for Default Speed"
line.long 0x1C "REGS__SS_CFG__SSCFG_CTL_CFG_8_REG,The Controller Config 8 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x1C 0.--12. 1. "HSPDPRESETVAL,Preset Value for High Speed"
line.long 0x20 "REGS__SS_CFG__SSCFG_CTL_CFG_9_REG,The Controller Config 9 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x20 0.--12. 1. "SDR12PRESETVAL,Preset Value for SDR12"
line.long 0x24 "REGS__SS_CFG__SSCFG_CTL_CFG_10_REG,The Controller Config 10 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x24 0.--12. 1. "SDR25PRESETVAL,Preset Value for SDR25"
line.long 0x28 "REGS__SS_CFG__SSCFG_CTL_CFG_11_REG,The Controller Config 11 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x28 0.--12. 1. "SDR50PRESETVAL,Preset Value for SDR50"
line.long 0x2C "REGS__SS_CFG__SSCFG_CTL_CFG_12_REG,The Controller Config 12 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x2C 0.--12. 1. "SDR104PRESETVAL,Preset Value for SDR104"
line.long 0x30 "REGS__SS_CFG__SSCFG_CTL_CFG_13_REG,The Controller Config 13 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x30 0.--12. 1. "DDR50PRESETVAL,Preset Value for DDR50"
hgroup.long 0x44++0x03
hide.long 0x00 "REGS__SS_CFG__SSCFG_CTL_CFG_14_REG,The Controller Config 14 Register contains various fields to control the configuration ports on the Arasan eMMC/SD Controller"
rgroup.long 0x60++0x17
line.long 0x00 "REGS__SS_CFG__SSCFG_CTL_STAT_1_REG,The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
bitfld.long 0x00 31. "SDHC_CMDIDLE,Idle signal to enable S/W to gate off the clocks" "0,1"
hexmask.long.word 0x00 0.--15. 1. "DMADEBUGBUS,DMA_CTRL Debug Bus"
line.long 0x04 "REGS__SS_CFG__SSCFG_CTL_STAT_2_REG,The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x04 0.--15. 1. "CMDDEBUGBUS,CMD_CTRL Debug Bus"
line.long 0x08 "REGS__SS_CFG__SSCFG_CTL_STAT_3_REG,The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x08 0.--15. 1. "TXDDEBUGBUS,TXD_CTRL Debug Bus"
line.long 0x0C "REGS__SS_CFG__SSCFG_CTL_STAT_4_REG,The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x0C 0.--15. 1. "RXDDEBUGBUS0,RXD_CTRL Debug Bus (SD CLK)"
line.long 0x10 "REGS__SS_CFG__SSCFG_CTL_STAT_5_REG,The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x10 0.--15. 1. "RXDDEBUGBUS1,RXD_CTRL Debug Bus (RX CLK)"
line.long 0x14 "REGS__SS_CFG__SSCFG_CTL_STAT_6_REG,The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Arasan eMMC/SD Controller"
hexmask.long.word 0x14 0.--15. 1. "TUNDEBUGBUS,TUN_CTRL Debug Bus"
group.long 0x100++0x03
line.long 0x00 "REGS__SS_CFG__SSCFG_PHY_CTRL_1_REG,The PHY Control 1 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
bitfld.long 0x00 31. "IOMUX_ENABLE,IO mux enable" "0,1"
hgroup.long 0x104++0x07
hide.long 0x00 "REGS__SS_CFG__SSCFG_PHY_CTRL_2_REG,The PHY Control 2 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
hide.long 0x04 "REGS__SS_CFG__SSCFG_PHY_CTRL_3_REG,The PHY Control 3 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
group.long 0x10C++0x07
line.long 0x00 "REGS__SS_CFG__SSCFG_PHY_CTRL_4_REG,The PHY Control 4 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
bitfld.long 0x00 20. "OTAPDLYENA,Output Tap Delay Enable" "0,1"
bitfld.long 0x00 12.--15. "OTAPDLYSEL,Output Tap Delay Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9. "ITAPCHGWIN,Input Tap Change Window" "0,1"
newline
bitfld.long 0x00 8. "ITAPDLYENA,Input Tap Delay Enable" "0,1"
bitfld.long 0x00 0.--4. "ITAPDLYSEL,Input Tap Delay Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "REGS__SS_CFG__SSCFG_PHY_CTRL_5_REG,The PHY Control 5 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
bitfld.long 0x04 0.--2. "CLKBUFSEL,Clock Delay Buffer Select" "0,1,2,3,4,5,6,7"
hgroup.long 0x114++0x03
hide.long 0x00 "REGS__SS_CFG__SSCFG_PHY_CTRL_6_REG,The PHY Control 6 Register contains various fields to control the ports on the Arasan eMMC/SD PHY"
hgroup.long 0x130++0x07
hide.long 0x00 "REGS__SS_CFG__SSCFG_PHY_STAT_1_REG,The PHY Status 1 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports"
hide.long 0x04 "REGS__SS_CFG__SSCFG_PHY_STAT_2_REG,The PHY Status 2 Register contains various fields to reflect the status of the Arasan eMMC/SD PHY ports"
tree.end
tree "PADCFG_CTRL0_CFG0"
base ad:0xF0000
rgroup.long 0x00++0x0B
line.long 0x00 "CFG0_PID,"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16,"
newline
bitfld.long 0x00 11.--15. "PID_MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "PID_CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG0_MMR_CFG0,"
hexmask.long.word 0x04 16.--31. 1. "MMR_CFG0_CFG_REV,Major configuration release"
newline
hexmask.long.word 0x04 0.--15. 1. "MMR_CFG0_SPEC_REV,Minor spec-only revision"
line.long 0x08 "CFG0_MMR_CFG1,"
bitfld.long 0x08 31. "MMR_CFG1_PROXY_EN,Proxy addressing enabled" "0,1"
newline
hexmask.long.byte 0x08 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions"
group.long 0x1008++0x2B
line.long 0x00 "CFG0_LOCK0_KICK0,"
line.long 0x04 "CFG0_LOCK0_KICK1,"
line.long 0x08 "CFG0_intr_raw_status,"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "CFG0_intr_enabled_status_clear,"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "CFG0_intr_enable,"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "CFG0_intr_enable_clear,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "CFG0_eoi,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value"
line.long 0x1C "CFG0_fault_address,"
line.long 0x20 "CFG0_fault_type_status,"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "CFG0_fault_attr_status,"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "CFG0_fault_clear,"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
rgroup.long 0x1100++0x03
line.long 0x00 "CFG0_CLAIMREG_P0_R0_READONLY,"
rgroup.long 0x2000++0x0B
line.long 0x00 "CFG0_PID_PROXY,"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16_PROXY,"
newline
bitfld.long 0x00 11.--15. "PID_MISC_PROXY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR_PROXY," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "PID_CUSTOM_PROXY," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR_PROXY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG0_MMR_CFG0_PROXY,"
hexmask.long.word 0x04 16.--31. 1. "MMR_CFG0_CFG_REV_PROXY,Major configuration release"
newline
hexmask.long.word 0x04 0.--15. 1. "MMR_CFG0_SPEC_REV_PROXY,Minor spec-only revision"
line.long 0x08 "CFG0_MMR_CFG1_PROXY,"
bitfld.long 0x08 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing enabled" "0,1"
newline
hexmask.long.byte 0x08 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions"
group.long 0x3008++0x2B
line.long 0x00 "CFG0_LOCK0_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK0_KICK1_PROXY,"
line.long 0x08 "CFG0_intr_raw_status_PROXY,"
bitfld.long 0x08 3. "PROXY_ERR_PROXY,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR_PROXY,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR_PROXY,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR_PROXY,Protection violation error" "0,1"
line.long 0x0C "CFG0_intr_enabled_status_clear_PROXY,"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR_PROXY,Protection violation error" "0,1"
line.long 0x10 "CFG0_intr_enable_PROXY,"
bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable" "0,1"
line.long 0x14 "CFG0_intr_enable_clear_PROXY,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear" "0,1"
line.long 0x18 "CFG0_eoi_PROXY,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value"
line.long 0x1C "CFG0_fault_address_PROXY,"
line.long 0x20 "CFG0_fault_type_status_PROXY,"
bitfld.long 0x20 6. "FAULT_NS_PROXY,Non-secure access" "0,1"
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bitfld.long 0x20 0.--5. "FAULT_TYPE_PROXY,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "CFG0_fault_attr_status_PROXY,"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID_PROXY,XID"
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hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID"
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hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID"
line.long 0x28 "CFG0_fault_clear_PROXY,"
bitfld.long 0x28 0. "FAULT_CLR_PROXY,Fault clear" "0,1"
group.long 0x3100++0x03
line.long 0x00 "CFG0_CLAIMREG_P0_R0,"
group.long 0x4000++0x2AB
line.long 0x00 "CFG0_PADCONFIG0,"
bitfld.long 0x00 31. "PADCONFIG0_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x00 30. "PADCONFIG0_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x00 29. "PADCONFIG0_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x00 28. "PADCONFIG0_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x00 27. "PADCONFIG0_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x00 26. "PADCONFIG0_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x00 25. "PADCONFIG0_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x00 24. "PADCONFIG0_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x00 23. "PADCONFIG0_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x00 22. "PADCONFIG0_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x00 21. "PADCONFIG0_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x00 19.--20. "PADCONFIG0_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x00 18. "PADCONFIG0_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x00 17. "PADCONFIG0_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x00 16. "PADCONFIG0_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x00 15. "PADCONFIG0_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x00 14. "PADCONFIG0_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x00 11.--13. "PADCONFIG0_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8. "PADCONFIG0_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x00 7. "PADCONFIG0_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x00 0.--3. "PADCONFIG0_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x04 "CFG0_PADCONFIG1,"
bitfld.long 0x04 31. "PADCONFIG1_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x04 30. "PADCONFIG1_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x04 29. "PADCONFIG1_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x04 28. "PADCONFIG1_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x04 27. "PADCONFIG1_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x04 26. "PADCONFIG1_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x04 25. "PADCONFIG1_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x04 24. "PADCONFIG1_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x04 23. "PADCONFIG1_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x04 22. "PADCONFIG1_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x04 21. "PADCONFIG1_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x04 19.--20. "PADCONFIG1_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x04 18. "PADCONFIG1_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x04 17. "PADCONFIG1_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x04 16. "PADCONFIG1_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x04 15. "PADCONFIG1_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x04 14. "PADCONFIG1_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x04 11.--13. "PADCONFIG1_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 8. "PADCONFIG1_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x04 7. "PADCONFIG1_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x04 0.--3. "PADCONFIG1_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x08 "CFG0_PADCONFIG2,"
bitfld.long 0x08 31. "PADCONFIG2_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x08 30. "PADCONFIG2_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x08 29. "PADCONFIG2_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x08 28. "PADCONFIG2_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x08 27. "PADCONFIG2_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x08 26. "PADCONFIG2_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x08 25. "PADCONFIG2_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x08 24. "PADCONFIG2_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x08 23. "PADCONFIG2_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x08 22. "PADCONFIG2_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x08 21. "PADCONFIG2_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x08 19.--20. "PADCONFIG2_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x08 18. "PADCONFIG2_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x08 17. "PADCONFIG2_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x08 16. "PADCONFIG2_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x08 15. "PADCONFIG2_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x08 14. "PADCONFIG2_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x08 11.--13. "PADCONFIG2_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 8. "PADCONFIG2_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x08 7. "PADCONFIG2_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x08 0.--3. "PADCONFIG2_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x0C "CFG0_PADCONFIG3,"
bitfld.long 0x0C 31. "PADCONFIG3_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x0C 30. "PADCONFIG3_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x0C 29. "PADCONFIG3_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x0C 28. "PADCONFIG3_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x0C 27. "PADCONFIG3_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x0C 26. "PADCONFIG3_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x0C 25. "PADCONFIG3_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x0C 24. "PADCONFIG3_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x0C 23. "PADCONFIG3_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x0C 22. "PADCONFIG3_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x0C 21. "PADCONFIG3_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x0C 19.--20. "PADCONFIG3_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x0C 18. "PADCONFIG3_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x0C 17. "PADCONFIG3_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x0C 16. "PADCONFIG3_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x0C 15. "PADCONFIG3_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x0C 14. "PADCONFIG3_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x0C 11.--13. "PADCONFIG3_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 8. "PADCONFIG3_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x0C 7. "PADCONFIG3_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x0C 0.--3. "PADCONFIG3_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x10 "CFG0_PADCONFIG4,"
bitfld.long 0x10 31. "PADCONFIG4_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x10 30. "PADCONFIG4_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x10 29. "PADCONFIG4_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x10 28. "PADCONFIG4_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x10 27. "PADCONFIG4_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x10 26. "PADCONFIG4_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x10 25. "PADCONFIG4_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x10 24. "PADCONFIG4_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x10 23. "PADCONFIG4_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x10 22. "PADCONFIG4_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x10 21. "PADCONFIG4_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x10 15. "PADCONFIG4_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x10 14. "PADCONFIG4_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 8. "PADCONFIG4_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x10 7. "PADCONFIG4_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x10 0.--3. "PADCONFIG4_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x14 "CFG0_PADCONFIG5,"
bitfld.long 0x14 31. "PADCONFIG5_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x14 30. "PADCONFIG5_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x14 29. "PADCONFIG5_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x14 28. "PADCONFIG5_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x14 27. "PADCONFIG5_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x14 26. "PADCONFIG5_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x14 25. "PADCONFIG5_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x14 24. "PADCONFIG5_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x14 23. "PADCONFIG5_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x14 22. "PADCONFIG5_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x14 21. "PADCONFIG5_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x14 15. "PADCONFIG5_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x14 14. "PADCONFIG5_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 8. "PADCONFIG5_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x14 7. "PADCONFIG5_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x14 0.--3. "PADCONFIG5_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x18 "CFG0_PADCONFIG6,"
bitfld.long 0x18 31. "PADCONFIG6_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x18 30. "PADCONFIG6_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x18 29. "PADCONFIG6_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x18 28. "PADCONFIG6_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x18 27. "PADCONFIG6_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x18 26. "PADCONFIG6_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x18 25. "PADCONFIG6_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x18 24. "PADCONFIG6_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x18 23. "PADCONFIG6_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x18 22. "PADCONFIG6_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x18 21. "PADCONFIG6_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x18 15. "PADCONFIG6_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x18 14. "PADCONFIG6_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 8. "PADCONFIG6_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x18 7. "PADCONFIG6_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x18 0.--3. "PADCONFIG6_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C "CFG0_PADCONFIG7,"
bitfld.long 0x1C 31. "PADCONFIG7_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C 30. "PADCONFIG7_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C 29. "PADCONFIG7_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1C 28. "PADCONFIG7_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1C 27. "PADCONFIG7_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C 26. "PADCONFIG7_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1C 25. "PADCONFIG7_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C 24. "PADCONFIG7_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1C 23. "PADCONFIG7_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1C 22. "PADCONFIG7_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C 15. "PADCONFIG7_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1C 14. "PADCONFIG7_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 8. "PADCONFIG7_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1C 7. "PADCONFIG7_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1C 0.--3. "PADCONFIG7_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x20 "CFG0_PADCONFIG8,"
bitfld.long 0x20 31. "PADCONFIG8_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x20 30. "PADCONFIG8_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x20 29. "PADCONFIG8_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x20 28. "PADCONFIG8_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x20 27. "PADCONFIG8_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x20 26. "PADCONFIG8_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x20 25. "PADCONFIG8_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x20 24. "PADCONFIG8_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x20 23. "PADCONFIG8_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x20 22. "PADCONFIG8_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x20 21. "PADCONFIG8_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x20 15. "PADCONFIG8_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x20 14. "PADCONFIG8_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 8. "PADCONFIG8_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x20 7. "PADCONFIG8_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x20 0.--3. "PADCONFIG8_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x24 "CFG0_PADCONFIG9,"
bitfld.long 0x24 31. "PADCONFIG9_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x24 30. "PADCONFIG9_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x24 29. "PADCONFIG9_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x24 28. "PADCONFIG9_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x24 27. "PADCONFIG9_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x24 26. "PADCONFIG9_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x24 25. "PADCONFIG9_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x24 24. "PADCONFIG9_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x24 23. "PADCONFIG9_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x24 22. "PADCONFIG9_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x24 21. "PADCONFIG9_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x24 15. "PADCONFIG9_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x24 14. "PADCONFIG9_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 8. "PADCONFIG9_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x24 7. "PADCONFIG9_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x24 0.--3. "PADCONFIG9_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x28 "CFG0_PADCONFIG10,"
bitfld.long 0x28 31. "PADCONFIG10_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x28 30. "PADCONFIG10_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x28 29. "PADCONFIG10_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x28 28. "PADCONFIG10_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x28 27. "PADCONFIG10_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x28 26. "PADCONFIG10_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x28 25. "PADCONFIG10_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x28 24. "PADCONFIG10_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x28 23. "PADCONFIG10_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x28 22. "PADCONFIG10_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x28 21. "PADCONFIG10_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x28 15. "PADCONFIG10_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x28 14. "PADCONFIG10_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 8. "PADCONFIG10_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x28 7. "PADCONFIG10_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x28 0.--3. "PADCONFIG10_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2C "CFG0_PADCONFIG11,"
bitfld.long 0x2C 31. "PADCONFIG11_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x2C 30. "PADCONFIG11_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x2C 29. "PADCONFIG11_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x2C 28. "PADCONFIG11_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x2C 27. "PADCONFIG11_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x2C 26. "PADCONFIG11_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2C 25. "PADCONFIG11_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x2C 24. "PADCONFIG11_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x2C 23. "PADCONFIG11_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x2C 22. "PADCONFIG11_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x2C 15. "PADCONFIG11_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x2C 14. "PADCONFIG11_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x2C 8. "PADCONFIG11_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x2C 7. "PADCONFIG11_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x2C 0.--3. "PADCONFIG11_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x30 "CFG0_PADCONFIG12,"
bitfld.long 0x30 31. "PADCONFIG12_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x30 30. "PADCONFIG12_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x30 29. "PADCONFIG12_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x30 28. "PADCONFIG12_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x30 27. "PADCONFIG12_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x30 26. "PADCONFIG12_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x30 25. "PADCONFIG12_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x30 24. "PADCONFIG12_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x30 23. "PADCONFIG12_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x30 22. "PADCONFIG12_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x30 21. "PADCONFIG12_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x30 15. "PADCONFIG12_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x30 14. "PADCONFIG12_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 8. "PADCONFIG12_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x30 7. "PADCONFIG12_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x30 0.--3. "PADCONFIG12_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x34 "CFG0_PADCONFIG13,"
bitfld.long 0x34 31. "PADCONFIG13_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x34 30. "PADCONFIG13_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x34 29. "PADCONFIG13_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x34 28. "PADCONFIG13_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x34 27. "PADCONFIG13_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x34 26. "PADCONFIG13_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x34 25. "PADCONFIG13_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x34 24. "PADCONFIG13_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x34 23. "PADCONFIG13_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x34 22. "PADCONFIG13_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x34 21. "PADCONFIG13_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x34 15. "PADCONFIG13_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x34 14. "PADCONFIG13_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 8. "PADCONFIG13_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x34 7. "PADCONFIG13_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x34 0.--3. "PADCONFIG13_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x38 "CFG0_PADCONFIG14,"
bitfld.long 0x38 31. "PADCONFIG14_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x38 30. "PADCONFIG14_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x38 29. "PADCONFIG14_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x38 28. "PADCONFIG14_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x38 27. "PADCONFIG14_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x38 26. "PADCONFIG14_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x38 25. "PADCONFIG14_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x38 24. "PADCONFIG14_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x38 23. "PADCONFIG14_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x38 22. "PADCONFIG14_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x38 21. "PADCONFIG14_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x38 15. "PADCONFIG14_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x38 14. "PADCONFIG14_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x38 8. "PADCONFIG14_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x38 7. "PADCONFIG14_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x38 0.--3. "PADCONFIG14_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x3C "CFG0_PADCONFIG15,"
bitfld.long 0x3C 31. "PADCONFIG15_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x3C 30. "PADCONFIG15_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x3C 29. "PADCONFIG15_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x3C 28. "PADCONFIG15_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x3C 27. "PADCONFIG15_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x3C 26. "PADCONFIG15_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x3C 25. "PADCONFIG15_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x3C 24. "PADCONFIG15_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x3C 23. "PADCONFIG15_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x3C 22. "PADCONFIG15_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x3C 15. "PADCONFIG15_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x3C 14. "PADCONFIG15_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x3C 8. "PADCONFIG15_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x3C 7. "PADCONFIG15_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x3C 0.--3. "PADCONFIG15_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x40 "CFG0_PADCONFIG16,"
bitfld.long 0x40 31. "PADCONFIG16_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x40 30. "PADCONFIG16_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x40 29. "PADCONFIG16_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x40 28. "PADCONFIG16_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x40 27. "PADCONFIG16_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x40 26. "PADCONFIG16_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x40 25. "PADCONFIG16_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x40 24. "PADCONFIG16_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x40 23. "PADCONFIG16_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x40 22. "PADCONFIG16_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x40 21. "PADCONFIG16_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x40 15. "PADCONFIG16_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x40 14. "PADCONFIG16_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x40 8. "PADCONFIG16_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x40 7. "PADCONFIG16_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x40 0.--3. "PADCONFIG16_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x44 "CFG0_PADCONFIG17,"
bitfld.long 0x44 31. "PADCONFIG17_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x44 30. "PADCONFIG17_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x44 29. "PADCONFIG17_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x44 28. "PADCONFIG17_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x44 27. "PADCONFIG17_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x44 26. "PADCONFIG17_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x44 25. "PADCONFIG17_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x44 24. "PADCONFIG17_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x44 23. "PADCONFIG17_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x44 22. "PADCONFIG17_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x44 21. "PADCONFIG17_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x44 15. "PADCONFIG17_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x44 14. "PADCONFIG17_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x44 8. "PADCONFIG17_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x44 7. "PADCONFIG17_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x44 0.--3. "PADCONFIG17_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x48 "CFG0_PADCONFIG18,"
bitfld.long 0x48 31. "PADCONFIG18_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x48 30. "PADCONFIG18_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x48 29. "PADCONFIG18_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x48 28. "PADCONFIG18_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x48 27. "PADCONFIG18_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x48 26. "PADCONFIG18_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x48 25. "PADCONFIG18_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x48 24. "PADCONFIG18_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x48 23. "PADCONFIG18_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x48 22. "PADCONFIG18_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x48 21. "PADCONFIG18_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x48 15. "PADCONFIG18_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x48 14. "PADCONFIG18_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x48 8. "PADCONFIG18_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x48 7. "PADCONFIG18_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x48 0.--3. "PADCONFIG18_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x4C "CFG0_PADCONFIG19,"
bitfld.long 0x4C 31. "PADCONFIG19_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x4C 30. "PADCONFIG19_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x4C 29. "PADCONFIG19_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x4C 28. "PADCONFIG19_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x4C 27. "PADCONFIG19_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x4C 26. "PADCONFIG19_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x4C 25. "PADCONFIG19_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x4C 24. "PADCONFIG19_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x4C 23. "PADCONFIG19_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x4C 22. "PADCONFIG19_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x4C 15. "PADCONFIG19_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x4C 14. "PADCONFIG19_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4C 8. "PADCONFIG19_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x4C 7. "PADCONFIG19_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x4C 0.--3. "PADCONFIG19_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x50 "CFG0_PADCONFIG20,"
bitfld.long 0x50 31. "PADCONFIG20_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x50 30. "PADCONFIG20_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x50 29. "PADCONFIG20_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x50 28. "PADCONFIG20_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x50 27. "PADCONFIG20_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x50 26. "PADCONFIG20_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x50 25. "PADCONFIG20_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x50 24. "PADCONFIG20_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x50 23. "PADCONFIG20_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x50 22. "PADCONFIG20_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x50 21. "PADCONFIG20_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x50 15. "PADCONFIG20_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x50 14. "PADCONFIG20_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x50 8. "PADCONFIG20_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x50 7. "PADCONFIG20_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x50 0.--3. "PADCONFIG20_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x54 "CFG0_PADCONFIG21,"
bitfld.long 0x54 31. "PADCONFIG21_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x54 30. "PADCONFIG21_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x54 29. "PADCONFIG21_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x54 28. "PADCONFIG21_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x54 27. "PADCONFIG21_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x54 26. "PADCONFIG21_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x54 25. "PADCONFIG21_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x54 24. "PADCONFIG21_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x54 23. "PADCONFIG21_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x54 22. "PADCONFIG21_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x54 21. "PADCONFIG21_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x54 15. "PADCONFIG21_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x54 14. "PADCONFIG21_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x54 8. "PADCONFIG21_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x54 7. "PADCONFIG21_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x54 0.--3. "PADCONFIG21_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x58 "CFG0_PADCONFIG22,"
bitfld.long 0x58 31. "PADCONFIG22_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x58 30. "PADCONFIG22_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x58 29. "PADCONFIG22_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x58 28. "PADCONFIG22_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x58 27. "PADCONFIG22_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x58 26. "PADCONFIG22_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x58 25. "PADCONFIG22_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x58 24. "PADCONFIG22_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x58 23. "PADCONFIG22_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x58 22. "PADCONFIG22_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x58 21. "PADCONFIG22_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x58 15. "PADCONFIG22_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x58 14. "PADCONFIG22_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x58 8. "PADCONFIG22_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x58 7. "PADCONFIG22_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x58 0.--3. "PADCONFIG22_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x5C "CFG0_PADCONFIG23,"
bitfld.long 0x5C 31. "PADCONFIG23_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x5C 30. "PADCONFIG23_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x5C 29. "PADCONFIG23_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x5C 28. "PADCONFIG23_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x5C 27. "PADCONFIG23_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x5C 26. "PADCONFIG23_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x5C 25. "PADCONFIG23_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x5C 24. "PADCONFIG23_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x5C 23. "PADCONFIG23_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x5C 22. "PADCONFIG23_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x5C 15. "PADCONFIG23_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x5C 14. "PADCONFIG23_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x5C 8. "PADCONFIG23_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x5C 7. "PADCONFIG23_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x5C 0.--3. "PADCONFIG23_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x60 "CFG0_PADCONFIG24,"
bitfld.long 0x60 31. "PADCONFIG24_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x60 30. "PADCONFIG24_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x60 29. "PADCONFIG24_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x60 28. "PADCONFIG24_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x60 27. "PADCONFIG24_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x60 26. "PADCONFIG24_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x60 25. "PADCONFIG24_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x60 24. "PADCONFIG24_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x60 23. "PADCONFIG24_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x60 22. "PADCONFIG24_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x60 21. "PADCONFIG24_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x60 15. "PADCONFIG24_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x60 14. "PADCONFIG24_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x60 8. "PADCONFIG24_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x60 7. "PADCONFIG24_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x60 0.--3. "PADCONFIG24_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x64 "CFG0_PADCONFIG25,"
bitfld.long 0x64 31. "PADCONFIG25_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x64 30. "PADCONFIG25_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x64 29. "PADCONFIG25_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x64 28. "PADCONFIG25_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x64 27. "PADCONFIG25_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x64 26. "PADCONFIG25_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x64 25. "PADCONFIG25_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x64 24. "PADCONFIG25_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x64 23. "PADCONFIG25_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x64 22. "PADCONFIG25_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x64 21. "PADCONFIG25_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x64 15. "PADCONFIG25_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x64 14. "PADCONFIG25_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x64 8. "PADCONFIG25_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x64 7. "PADCONFIG25_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x64 0.--3. "PADCONFIG25_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x68 "CFG0_PADCONFIG26,"
bitfld.long 0x68 31. "PADCONFIG26_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x68 30. "PADCONFIG26_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x68 29. "PADCONFIG26_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x68 28. "PADCONFIG26_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x68 27. "PADCONFIG26_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x68 26. "PADCONFIG26_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x68 25. "PADCONFIG26_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x68 24. "PADCONFIG26_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x68 23. "PADCONFIG26_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x68 22. "PADCONFIG26_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x68 21. "PADCONFIG26_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x68 15. "PADCONFIG26_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x68 14. "PADCONFIG26_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x68 8. "PADCONFIG26_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x68 7. "PADCONFIG26_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x68 0.--3. "PADCONFIG26_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x6C "CFG0_PADCONFIG27,"
bitfld.long 0x6C 31. "PADCONFIG27_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x6C 30. "PADCONFIG27_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x6C 29. "PADCONFIG27_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x6C 28. "PADCONFIG27_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x6C 27. "PADCONFIG27_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x6C 26. "PADCONFIG27_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x6C 25. "PADCONFIG27_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x6C 24. "PADCONFIG27_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x6C 23. "PADCONFIG27_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x6C 22. "PADCONFIG27_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x6C 15. "PADCONFIG27_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x6C 14. "PADCONFIG27_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x6C 8. "PADCONFIG27_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x6C 7. "PADCONFIG27_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x6C 0.--3. "PADCONFIG27_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x70 "CFG0_PADCONFIG28,"
bitfld.long 0x70 31. "PADCONFIG28_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x70 30. "PADCONFIG28_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x70 29. "PADCONFIG28_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x70 28. "PADCONFIG28_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x70 27. "PADCONFIG28_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x70 26. "PADCONFIG28_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x70 25. "PADCONFIG28_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x70 24. "PADCONFIG28_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x70 23. "PADCONFIG28_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x70 22. "PADCONFIG28_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x70 21. "PADCONFIG28_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x70 15. "PADCONFIG28_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x70 14. "PADCONFIG28_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x70 8. "PADCONFIG28_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x70 7. "PADCONFIG28_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x70 0.--3. "PADCONFIG28_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x74 "CFG0_PADCONFIG29,"
bitfld.long 0x74 31. "PADCONFIG29_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x74 30. "PADCONFIG29_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x74 29. "PADCONFIG29_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x74 28. "PADCONFIG29_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x74 27. "PADCONFIG29_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x74 26. "PADCONFIG29_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x74 25. "PADCONFIG29_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x74 24. "PADCONFIG29_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x74 23. "PADCONFIG29_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x74 22. "PADCONFIG29_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x74 21. "PADCONFIG29_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x74 15. "PADCONFIG29_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x74 14. "PADCONFIG29_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x74 8. "PADCONFIG29_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x74 7. "PADCONFIG29_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x74 0.--3. "PADCONFIG29_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x78 "CFG0_PADCONFIG30,"
bitfld.long 0x78 31. "PADCONFIG30_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x78 30. "PADCONFIG30_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x78 29. "PADCONFIG30_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x78 28. "PADCONFIG30_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x78 27. "PADCONFIG30_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x78 26. "PADCONFIG30_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x78 25. "PADCONFIG30_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x78 24. "PADCONFIG30_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x78 23. "PADCONFIG30_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x78 22. "PADCONFIG30_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x78 21. "PADCONFIG30_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x78 15. "PADCONFIG30_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x78 14. "PADCONFIG30_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x78 8. "PADCONFIG30_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x78 7. "PADCONFIG30_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x78 0.--3. "PADCONFIG30_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x7C "CFG0_PADCONFIG31,"
bitfld.long 0x7C 31. "PADCONFIG31_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x7C 30. "PADCONFIG31_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x7C 29. "PADCONFIG31_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x7C 28. "PADCONFIG31_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x7C 27. "PADCONFIG31_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x7C 26. "PADCONFIG31_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x7C 25. "PADCONFIG31_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x7C 24. "PADCONFIG31_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x7C 23. "PADCONFIG31_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x7C 22. "PADCONFIG31_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x7C 15. "PADCONFIG31_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x7C 14. "PADCONFIG31_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x7C 8. "PADCONFIG31_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x7C 7. "PADCONFIG31_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x7C 0.--3. "PADCONFIG31_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x80 "CFG0_PADCONFIG32,"
bitfld.long 0x80 31. "PADCONFIG32_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x80 30. "PADCONFIG32_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x80 29. "PADCONFIG32_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x80 28. "PADCONFIG32_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x80 27. "PADCONFIG32_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x80 26. "PADCONFIG32_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x80 25. "PADCONFIG32_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x80 24. "PADCONFIG32_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x80 23. "PADCONFIG32_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x80 22. "PADCONFIG32_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x80 21. "PADCONFIG32_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x80 15. "PADCONFIG32_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x80 14. "PADCONFIG32_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x80 8. "PADCONFIG32_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x80 7. "PADCONFIG32_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x80 0.--3. "PADCONFIG32_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x84 "CFG0_PADCONFIG33,"
bitfld.long 0x84 31. "PADCONFIG33_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x84 30. "PADCONFIG33_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x84 29. "PADCONFIG33_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x84 28. "PADCONFIG33_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x84 27. "PADCONFIG33_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x84 26. "PADCONFIG33_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x84 25. "PADCONFIG33_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x84 24. "PADCONFIG33_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x84 23. "PADCONFIG33_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x84 22. "PADCONFIG33_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x84 21. "PADCONFIG33_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x84 19.--20. "PADCONFIG33_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x84 18. "PADCONFIG33_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x84 17. "PADCONFIG33_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x84 16. "PADCONFIG33_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x84 15. "PADCONFIG33_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x84 14. "PADCONFIG33_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x84 11.--13. "PADCONFIG33_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x84 8. "PADCONFIG33_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x84 7. "PADCONFIG33_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x84 0.--3. "PADCONFIG33_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x88 "CFG0_PADCONFIG34,"
bitfld.long 0x88 31. "PADCONFIG34_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x88 30. "PADCONFIG34_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x88 29. "PADCONFIG34_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x88 28. "PADCONFIG34_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x88 27. "PADCONFIG34_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x88 26. "PADCONFIG34_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x88 25. "PADCONFIG34_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x88 24. "PADCONFIG34_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x88 23. "PADCONFIG34_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x88 22. "PADCONFIG34_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x88 21. "PADCONFIG34_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x88 19.--20. "PADCONFIG34_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x88 18. "PADCONFIG34_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x88 17. "PADCONFIG34_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x88 16. "PADCONFIG34_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x88 15. "PADCONFIG34_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x88 14. "PADCONFIG34_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x88 11.--13. "PADCONFIG34_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x88 8. "PADCONFIG34_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x88 7. "PADCONFIG34_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x88 0.--3. "PADCONFIG34_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x8C "CFG0_PADCONFIG35,"
bitfld.long 0x8C 31. "PADCONFIG35_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x8C 30. "PADCONFIG35_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x8C 29. "PADCONFIG35_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x8C 28. "PADCONFIG35_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x8C 27. "PADCONFIG35_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x8C 26. "PADCONFIG35_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x8C 25. "PADCONFIG35_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x8C 24. "PADCONFIG35_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x8C 23. "PADCONFIG35_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x8C 22. "PADCONFIG35_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x8C 21. "PADCONFIG35_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x8C 19.--20. "PADCONFIG35_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x8C 18. "PADCONFIG35_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x8C 17. "PADCONFIG35_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x8C 16. "PADCONFIG35_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x8C 15. "PADCONFIG35_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x8C 14. "PADCONFIG35_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x8C 11.--13. "PADCONFIG35_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8C 8. "PADCONFIG35_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x8C 7. "PADCONFIG35_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x8C 0.--3. "PADCONFIG35_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x90 "CFG0_PADCONFIG36,"
bitfld.long 0x90 31. "PADCONFIG36_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x90 30. "PADCONFIG36_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x90 29. "PADCONFIG36_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x90 28. "PADCONFIG36_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x90 27. "PADCONFIG36_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x90 26. "PADCONFIG36_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x90 25. "PADCONFIG36_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x90 24. "PADCONFIG36_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x90 23. "PADCONFIG36_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x90 22. "PADCONFIG36_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x90 21. "PADCONFIG36_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x90 19.--20. "PADCONFIG36_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x90 18. "PADCONFIG36_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x90 17. "PADCONFIG36_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x90 16. "PADCONFIG36_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x90 15. "PADCONFIG36_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x90 14. "PADCONFIG36_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x90 11.--13. "PADCONFIG36_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x90 8. "PADCONFIG36_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x90 7. "PADCONFIG36_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x90 0.--3. "PADCONFIG36_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x94 "CFG0_PADCONFIG37,"
bitfld.long 0x94 31. "PADCONFIG37_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x94 30. "PADCONFIG37_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x94 29. "PADCONFIG37_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x94 28. "PADCONFIG37_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x94 27. "PADCONFIG37_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x94 26. "PADCONFIG37_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x94 25. "PADCONFIG37_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x94 24. "PADCONFIG37_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x94 23. "PADCONFIG37_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x94 22. "PADCONFIG37_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x94 21. "PADCONFIG37_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x94 19.--20. "PADCONFIG37_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x94 18. "PADCONFIG37_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x94 17. "PADCONFIG37_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x94 16. "PADCONFIG37_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x94 15. "PADCONFIG37_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x94 14. "PADCONFIG37_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x94 11.--13. "PADCONFIG37_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x94 8. "PADCONFIG37_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x94 7. "PADCONFIG37_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x94 0.--3. "PADCONFIG37_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x98 "CFG0_PADCONFIG38,"
bitfld.long 0x98 31. "PADCONFIG38_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x98 30. "PADCONFIG38_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x98 29. "PADCONFIG38_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x98 28. "PADCONFIG38_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x98 27. "PADCONFIG38_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x98 26. "PADCONFIG38_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x98 25. "PADCONFIG38_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x98 24. "PADCONFIG38_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x98 23. "PADCONFIG38_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x98 22. "PADCONFIG38_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x98 21. "PADCONFIG38_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x98 19.--20. "PADCONFIG38_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x98 18. "PADCONFIG38_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x98 17. "PADCONFIG38_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x98 16. "PADCONFIG38_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x98 15. "PADCONFIG38_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x98 14. "PADCONFIG38_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x98 11.--13. "PADCONFIG38_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x98 8. "PADCONFIG38_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x98 7. "PADCONFIG38_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x98 0.--3. "PADCONFIG38_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x9C "CFG0_PADCONFIG39,"
bitfld.long 0x9C 31. "PADCONFIG39_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x9C 30. "PADCONFIG39_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x9C 29. "PADCONFIG39_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x9C 28. "PADCONFIG39_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x9C 27. "PADCONFIG39_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x9C 26. "PADCONFIG39_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x9C 25. "PADCONFIG39_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x9C 24. "PADCONFIG39_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x9C 23. "PADCONFIG39_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x9C 22. "PADCONFIG39_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x9C 21. "PADCONFIG39_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x9C 19.--20. "PADCONFIG39_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x9C 18. "PADCONFIG39_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x9C 17. "PADCONFIG39_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x9C 16. "PADCONFIG39_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x9C 15. "PADCONFIG39_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x9C 14. "PADCONFIG39_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x9C 11.--13. "PADCONFIG39_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x9C 8. "PADCONFIG39_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x9C 7. "PADCONFIG39_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x9C 0.--3. "PADCONFIG39_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xA0 "CFG0_PADCONFIG40,"
bitfld.long 0xA0 31. "PADCONFIG40_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xA0 30. "PADCONFIG40_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xA0 29. "PADCONFIG40_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xA0 28. "PADCONFIG40_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xA0 27. "PADCONFIG40_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xA0 26. "PADCONFIG40_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xA0 25. "PADCONFIG40_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xA0 24. "PADCONFIG40_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xA0 23. "PADCONFIG40_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xA0 22. "PADCONFIG40_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xA0 21. "PADCONFIG40_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xA0 19.--20. "PADCONFIG40_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xA0 18. "PADCONFIG40_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xA0 17. "PADCONFIG40_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xA0 16. "PADCONFIG40_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xA0 15. "PADCONFIG40_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xA0 14. "PADCONFIG40_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xA0 11.--13. "PADCONFIG40_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xA0 8. "PADCONFIG40_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xA0 7. "PADCONFIG40_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xA0 0.--3. "PADCONFIG40_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xA4 "CFG0_PADCONFIG41,"
bitfld.long 0xA4 31. "PADCONFIG41_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xA4 30. "PADCONFIG41_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xA4 29. "PADCONFIG41_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xA4 28. "PADCONFIG41_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xA4 27. "PADCONFIG41_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xA4 26. "PADCONFIG41_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xA4 25. "PADCONFIG41_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xA4 24. "PADCONFIG41_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xA4 23. "PADCONFIG41_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xA4 22. "PADCONFIG41_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xA4 21. "PADCONFIG41_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xA4 19.--20. "PADCONFIG41_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xA4 18. "PADCONFIG41_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xA4 17. "PADCONFIG41_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xA4 16. "PADCONFIG41_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xA4 15. "PADCONFIG41_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xA4 14. "PADCONFIG41_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xA4 11.--13. "PADCONFIG41_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xA4 8. "PADCONFIG41_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xA4 7. "PADCONFIG41_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xA4 0.--3. "PADCONFIG41_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xA8 "CFG0_PADCONFIG42,"
bitfld.long 0xA8 31. "PADCONFIG42_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xA8 30. "PADCONFIG42_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xA8 29. "PADCONFIG42_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xA8 28. "PADCONFIG42_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xA8 27. "PADCONFIG42_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xA8 26. "PADCONFIG42_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xA8 25. "PADCONFIG42_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xA8 24. "PADCONFIG42_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xA8 23. "PADCONFIG42_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xA8 22. "PADCONFIG42_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xA8 21. "PADCONFIG42_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xA8 19.--20. "PADCONFIG42_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xA8 18. "PADCONFIG42_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xA8 17. "PADCONFIG42_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xA8 16. "PADCONFIG42_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xA8 15. "PADCONFIG42_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xA8 14. "PADCONFIG42_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xA8 11.--13. "PADCONFIG42_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xA8 8. "PADCONFIG42_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xA8 7. "PADCONFIG42_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xA8 0.--3. "PADCONFIG42_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xAC "CFG0_PADCONFIG43,"
bitfld.long 0xAC 31. "PADCONFIG43_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xAC 30. "PADCONFIG43_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xAC 29. "PADCONFIG43_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xAC 28. "PADCONFIG43_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xAC 27. "PADCONFIG43_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xAC 26. "PADCONFIG43_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xAC 25. "PADCONFIG43_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xAC 24. "PADCONFIG43_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xAC 23. "PADCONFIG43_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xAC 22. "PADCONFIG43_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xAC 21. "PADCONFIG43_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xAC 19.--20. "PADCONFIG43_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xAC 18. "PADCONFIG43_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xAC 17. "PADCONFIG43_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xAC 16. "PADCONFIG43_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xAC 15. "PADCONFIG43_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xAC 14. "PADCONFIG43_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xAC 11.--13. "PADCONFIG43_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xAC 8. "PADCONFIG43_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xAC 7. "PADCONFIG43_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xAC 0.--3. "PADCONFIG43_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xB0 "CFG0_PADCONFIG44,"
bitfld.long 0xB0 31. "PADCONFIG44_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xB0 30. "PADCONFIG44_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xB0 29. "PADCONFIG44_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xB0 28. "PADCONFIG44_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xB0 27. "PADCONFIG44_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xB0 26. "PADCONFIG44_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xB0 25. "PADCONFIG44_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xB0 24. "PADCONFIG44_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xB0 23. "PADCONFIG44_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xB0 22. "PADCONFIG44_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xB0 21. "PADCONFIG44_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xB0 19.--20. "PADCONFIG44_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xB0 18. "PADCONFIG44_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xB0 17. "PADCONFIG44_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xB0 16. "PADCONFIG44_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xB0 15. "PADCONFIG44_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xB0 14. "PADCONFIG44_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xB0 11.--13. "PADCONFIG44_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xB0 8. "PADCONFIG44_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xB0 7. "PADCONFIG44_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xB0 0.--3. "PADCONFIG44_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xB4 "CFG0_PADCONFIG45,"
bitfld.long 0xB4 31. "PADCONFIG45_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xB4 30. "PADCONFIG45_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xB4 29. "PADCONFIG45_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xB4 28. "PADCONFIG45_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xB4 27. "PADCONFIG45_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xB4 26. "PADCONFIG45_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xB4 25. "PADCONFIG45_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xB4 24. "PADCONFIG45_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xB4 23. "PADCONFIG45_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xB4 22. "PADCONFIG45_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xB4 21. "PADCONFIG45_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xB4 19.--20. "PADCONFIG45_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xB4 18. "PADCONFIG45_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xB4 17. "PADCONFIG45_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xB4 16. "PADCONFIG45_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xB4 15. "PADCONFIG45_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xB4 14. "PADCONFIG45_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xB4 11.--13. "PADCONFIG45_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xB4 8. "PADCONFIG45_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xB4 7. "PADCONFIG45_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xB4 0.--3. "PADCONFIG45_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xB8 "CFG0_PADCONFIG46,"
bitfld.long 0xB8 31. "PADCONFIG46_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xB8 30. "PADCONFIG46_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xB8 29. "PADCONFIG46_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xB8 28. "PADCONFIG46_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xB8 27. "PADCONFIG46_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xB8 26. "PADCONFIG46_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xB8 25. "PADCONFIG46_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xB8 24. "PADCONFIG46_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xB8 23. "PADCONFIG46_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xB8 22. "PADCONFIG46_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xB8 21. "PADCONFIG46_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xB8 19.--20. "PADCONFIG46_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xB8 18. "PADCONFIG46_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xB8 17. "PADCONFIG46_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xB8 16. "PADCONFIG46_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xB8 15. "PADCONFIG46_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xB8 14. "PADCONFIG46_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xB8 11.--13. "PADCONFIG46_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xB8 8. "PADCONFIG46_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xB8 7. "PADCONFIG46_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xB8 0.--3. "PADCONFIG46_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xBC "CFG0_PADCONFIG47,"
bitfld.long 0xBC 31. "PADCONFIG47_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xBC 30. "PADCONFIG47_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xBC 29. "PADCONFIG47_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xBC 28. "PADCONFIG47_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xBC 27. "PADCONFIG47_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xBC 26. "PADCONFIG47_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xBC 25. "PADCONFIG47_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xBC 24. "PADCONFIG47_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xBC 23. "PADCONFIG47_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xBC 22. "PADCONFIG47_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xBC 21. "PADCONFIG47_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xBC 19.--20. "PADCONFIG47_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xBC 18. "PADCONFIG47_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xBC 17. "PADCONFIG47_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xBC 16. "PADCONFIG47_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xBC 15. "PADCONFIG47_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xBC 14. "PADCONFIG47_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xBC 11.--13. "PADCONFIG47_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xBC 8. "PADCONFIG47_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xBC 7. "PADCONFIG47_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xBC 0.--3. "PADCONFIG47_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xC0 "CFG0_PADCONFIG48,"
bitfld.long 0xC0 31. "PADCONFIG48_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xC0 30. "PADCONFIG48_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xC0 29. "PADCONFIG48_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xC0 28. "PADCONFIG48_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xC0 27. "PADCONFIG48_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xC0 26. "PADCONFIG48_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xC0 25. "PADCONFIG48_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xC0 24. "PADCONFIG48_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xC0 23. "PADCONFIG48_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xC0 22. "PADCONFIG48_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xC0 21. "PADCONFIG48_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xC0 19.--20. "PADCONFIG48_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xC0 18. "PADCONFIG48_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xC0 17. "PADCONFIG48_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xC0 16. "PADCONFIG48_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xC0 15. "PADCONFIG48_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xC0 14. "PADCONFIG48_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xC0 11.--13. "PADCONFIG48_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC0 8. "PADCONFIG48_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xC0 7. "PADCONFIG48_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xC0 0.--3. "PADCONFIG48_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xC4 "CFG0_PADCONFIG49,"
bitfld.long 0xC4 31. "PADCONFIG49_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xC4 30. "PADCONFIG49_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xC4 29. "PADCONFIG49_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xC4 28. "PADCONFIG49_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xC4 27. "PADCONFIG49_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xC4 26. "PADCONFIG49_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xC4 25. "PADCONFIG49_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xC4 24. "PADCONFIG49_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xC4 23. "PADCONFIG49_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xC4 22. "PADCONFIG49_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xC4 21. "PADCONFIG49_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xC4 19.--20. "PADCONFIG49_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xC4 18. "PADCONFIG49_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xC4 17. "PADCONFIG49_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xC4 16. "PADCONFIG49_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xC4 15. "PADCONFIG49_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xC4 14. "PADCONFIG49_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xC4 11.--13. "PADCONFIG49_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC4 8. "PADCONFIG49_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xC4 7. "PADCONFIG49_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xC4 0.--3. "PADCONFIG49_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xC8 "CFG0_PADCONFIG50,"
bitfld.long 0xC8 31. "PADCONFIG50_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xC8 30. "PADCONFIG50_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xC8 29. "PADCONFIG50_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xC8 28. "PADCONFIG50_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xC8 27. "PADCONFIG50_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xC8 26. "PADCONFIG50_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xC8 25. "PADCONFIG50_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xC8 24. "PADCONFIG50_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xC8 23. "PADCONFIG50_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xC8 22. "PADCONFIG50_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xC8 21. "PADCONFIG50_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xC8 19.--20. "PADCONFIG50_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xC8 18. "PADCONFIG50_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xC8 17. "PADCONFIG50_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xC8 16. "PADCONFIG50_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xC8 15. "PADCONFIG50_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xC8 14. "PADCONFIG50_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xC8 11.--13. "PADCONFIG50_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC8 8. "PADCONFIG50_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xC8 7. "PADCONFIG50_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xC8 0.--3. "PADCONFIG50_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xCC "CFG0_PADCONFIG51,"
bitfld.long 0xCC 31. "PADCONFIG51_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xCC 30. "PADCONFIG51_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xCC 29. "PADCONFIG51_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xCC 28. "PADCONFIG51_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xCC 27. "PADCONFIG51_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xCC 26. "PADCONFIG51_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xCC 25. "PADCONFIG51_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xCC 24. "PADCONFIG51_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xCC 23. "PADCONFIG51_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xCC 22. "PADCONFIG51_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xCC 21. "PADCONFIG51_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xCC 19.--20. "PADCONFIG51_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xCC 18. "PADCONFIG51_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xCC 17. "PADCONFIG51_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xCC 16. "PADCONFIG51_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xCC 15. "PADCONFIG51_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xCC 14. "PADCONFIG51_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xCC 11.--13. "PADCONFIG51_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xCC 8. "PADCONFIG51_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xCC 7. "PADCONFIG51_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xCC 0.--3. "PADCONFIG51_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xD0 "CFG0_PADCONFIG52,"
bitfld.long 0xD0 31. "PADCONFIG52_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xD0 30. "PADCONFIG52_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xD0 29. "PADCONFIG52_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xD0 28. "PADCONFIG52_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xD0 27. "PADCONFIG52_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xD0 26. "PADCONFIG52_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xD0 25. "PADCONFIG52_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xD0 24. "PADCONFIG52_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xD0 23. "PADCONFIG52_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xD0 22. "PADCONFIG52_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xD0 21. "PADCONFIG52_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xD0 19.--20. "PADCONFIG52_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xD0 18. "PADCONFIG52_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xD0 17. "PADCONFIG52_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xD0 16. "PADCONFIG52_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xD0 15. "PADCONFIG52_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xD0 14. "PADCONFIG52_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xD0 11.--13. "PADCONFIG52_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xD0 8. "PADCONFIG52_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xD0 7. "PADCONFIG52_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xD0 0.--3. "PADCONFIG52_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xD4 "CFG0_PADCONFIG53,"
bitfld.long 0xD4 31. "PADCONFIG53_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xD4 30. "PADCONFIG53_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xD4 29. "PADCONFIG53_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xD4 28. "PADCONFIG53_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xD4 27. "PADCONFIG53_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xD4 26. "PADCONFIG53_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xD4 25. "PADCONFIG53_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xD4 24. "PADCONFIG53_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xD4 23. "PADCONFIG53_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xD4 22. "PADCONFIG53_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xD4 21. "PADCONFIG53_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xD4 19.--20. "PADCONFIG53_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xD4 18. "PADCONFIG53_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xD4 17. "PADCONFIG53_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xD4 16. "PADCONFIG53_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xD4 15. "PADCONFIG53_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xD4 14. "PADCONFIG53_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xD4 11.--13. "PADCONFIG53_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xD4 8. "PADCONFIG53_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xD4 7. "PADCONFIG53_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xD4 0.--3. "PADCONFIG53_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xD8 "CFG0_PADCONFIG54,"
bitfld.long 0xD8 31. "PADCONFIG54_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xD8 30. "PADCONFIG54_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xD8 29. "PADCONFIG54_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xD8 28. "PADCONFIG54_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xD8 27. "PADCONFIG54_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xD8 26. "PADCONFIG54_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xD8 25. "PADCONFIG54_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xD8 24. "PADCONFIG54_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xD8 23. "PADCONFIG54_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xD8 22. "PADCONFIG54_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xD8 21. "PADCONFIG54_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xD8 19.--20. "PADCONFIG54_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xD8 18. "PADCONFIG54_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xD8 17. "PADCONFIG54_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xD8 16. "PADCONFIG54_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xD8 15. "PADCONFIG54_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xD8 14. "PADCONFIG54_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xD8 11.--13. "PADCONFIG54_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xD8 8. "PADCONFIG54_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xD8 7. "PADCONFIG54_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xD8 0.--3. "PADCONFIG54_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xDC "CFG0_PADCONFIG55,"
bitfld.long 0xDC 31. "PADCONFIG55_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xDC 30. "PADCONFIG55_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xDC 29. "PADCONFIG55_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xDC 28. "PADCONFIG55_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xDC 27. "PADCONFIG55_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xDC 26. "PADCONFIG55_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xDC 25. "PADCONFIG55_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xDC 24. "PADCONFIG55_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xDC 23. "PADCONFIG55_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xDC 22. "PADCONFIG55_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xDC 21. "PADCONFIG55_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xDC 19.--20. "PADCONFIG55_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xDC 18. "PADCONFIG55_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xDC 17. "PADCONFIG55_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xDC 16. "PADCONFIG55_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xDC 15. "PADCONFIG55_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xDC 14. "PADCONFIG55_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xDC 11.--13. "PADCONFIG55_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xDC 8. "PADCONFIG55_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xDC 7. "PADCONFIG55_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xDC 0.--3. "PADCONFIG55_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xE0 "CFG0_PADCONFIG56,"
bitfld.long 0xE0 31. "PADCONFIG56_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xE0 30. "PADCONFIG56_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xE0 29. "PADCONFIG56_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xE0 28. "PADCONFIG56_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xE0 27. "PADCONFIG56_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xE0 26. "PADCONFIG56_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xE0 25. "PADCONFIG56_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xE0 24. "PADCONFIG56_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xE0 23. "PADCONFIG56_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xE0 22. "PADCONFIG56_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xE0 21. "PADCONFIG56_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xE0 19.--20. "PADCONFIG56_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xE0 18. "PADCONFIG56_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xE0 17. "PADCONFIG56_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xE0 16. "PADCONFIG56_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xE0 15. "PADCONFIG56_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xE0 14. "PADCONFIG56_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xE0 11.--13. "PADCONFIG56_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xE0 8. "PADCONFIG56_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xE0 7. "PADCONFIG56_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xE0 0.--3. "PADCONFIG56_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xE4 "CFG0_PADCONFIG57,"
bitfld.long 0xE4 31. "PADCONFIG57_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xE4 30. "PADCONFIG57_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xE4 29. "PADCONFIG57_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xE4 28. "PADCONFIG57_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xE4 27. "PADCONFIG57_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xE4 26. "PADCONFIG57_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xE4 25. "PADCONFIG57_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xE4 24. "PADCONFIG57_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xE4 23. "PADCONFIG57_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xE4 22. "PADCONFIG57_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xE4 21. "PADCONFIG57_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xE4 19.--20. "PADCONFIG57_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xE4 18. "PADCONFIG57_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xE4 17. "PADCONFIG57_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xE4 16. "PADCONFIG57_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xE4 15. "PADCONFIG57_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xE4 14. "PADCONFIG57_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xE4 11.--13. "PADCONFIG57_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xE4 8. "PADCONFIG57_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xE4 7. "PADCONFIG57_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xE4 0.--3. "PADCONFIG57_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xE8 "CFG0_PADCONFIG58,"
bitfld.long 0xE8 31. "PADCONFIG58_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xE8 30. "PADCONFIG58_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xE8 29. "PADCONFIG58_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xE8 28. "PADCONFIG58_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xE8 27. "PADCONFIG58_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xE8 26. "PADCONFIG58_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xE8 25. "PADCONFIG58_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xE8 24. "PADCONFIG58_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xE8 23. "PADCONFIG58_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xE8 22. "PADCONFIG58_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xE8 21. "PADCONFIG58_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xE8 19.--20. "PADCONFIG58_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xE8 18. "PADCONFIG58_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xE8 17. "PADCONFIG58_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xE8 16. "PADCONFIG58_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xE8 15. "PADCONFIG58_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xE8 14. "PADCONFIG58_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xE8 11.--13. "PADCONFIG58_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xE8 8. "PADCONFIG58_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xE8 7. "PADCONFIG58_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xE8 0.--3. "PADCONFIG58_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xEC "CFG0_PADCONFIG59,"
bitfld.long 0xEC 31. "PADCONFIG59_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xEC 30. "PADCONFIG59_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xEC 29. "PADCONFIG59_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xEC 28. "PADCONFIG59_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xEC 27. "PADCONFIG59_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xEC 26. "PADCONFIG59_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xEC 25. "PADCONFIG59_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xEC 24. "PADCONFIG59_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xEC 23. "PADCONFIG59_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xEC 22. "PADCONFIG59_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xEC 21. "PADCONFIG59_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xEC 19.--20. "PADCONFIG59_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xEC 18. "PADCONFIG59_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xEC 17. "PADCONFIG59_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xEC 16. "PADCONFIG59_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xEC 15. "PADCONFIG59_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xEC 14. "PADCONFIG59_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xEC 11.--13. "PADCONFIG59_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xEC 8. "PADCONFIG59_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xEC 7. "PADCONFIG59_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xEC 0.--3. "PADCONFIG59_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xF0 "CFG0_PADCONFIG60,"
bitfld.long 0xF0 31. "PADCONFIG60_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xF0 30. "PADCONFIG60_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xF0 29. "PADCONFIG60_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xF0 28. "PADCONFIG60_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xF0 27. "PADCONFIG60_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xF0 26. "PADCONFIG60_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xF0 25. "PADCONFIG60_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xF0 24. "PADCONFIG60_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xF0 23. "PADCONFIG60_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xF0 22. "PADCONFIG60_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xF0 21. "PADCONFIG60_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xF0 19.--20. "PADCONFIG60_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xF0 18. "PADCONFIG60_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xF0 17. "PADCONFIG60_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xF0 16. "PADCONFIG60_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xF0 15. "PADCONFIG60_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xF0 14. "PADCONFIG60_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xF0 11.--13. "PADCONFIG60_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xF0 8. "PADCONFIG60_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xF0 7. "PADCONFIG60_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xF0 0.--3. "PADCONFIG60_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xF4 "CFG0_PADCONFIG61,"
bitfld.long 0xF4 31. "PADCONFIG61_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xF4 30. "PADCONFIG61_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xF4 29. "PADCONFIG61_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xF4 28. "PADCONFIG61_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xF4 27. "PADCONFIG61_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xF4 26. "PADCONFIG61_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xF4 25. "PADCONFIG61_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xF4 24. "PADCONFIG61_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xF4 23. "PADCONFIG61_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xF4 22. "PADCONFIG61_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xF4 21. "PADCONFIG61_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xF4 19.--20. "PADCONFIG61_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xF4 18. "PADCONFIG61_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xF4 17. "PADCONFIG61_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xF4 16. "PADCONFIG61_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xF4 15. "PADCONFIG61_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xF4 14. "PADCONFIG61_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xF4 11.--13. "PADCONFIG61_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xF4 8. "PADCONFIG61_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xF4 7. "PADCONFIG61_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xF4 0.--3. "PADCONFIG61_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xF8 "CFG0_PADCONFIG62,"
bitfld.long 0xF8 31. "PADCONFIG62_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xF8 30. "PADCONFIG62_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xF8 29. "PADCONFIG62_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xF8 28. "PADCONFIG62_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xF8 27. "PADCONFIG62_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xF8 26. "PADCONFIG62_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xF8 25. "PADCONFIG62_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xF8 24. "PADCONFIG62_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xF8 23. "PADCONFIG62_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xF8 22. "PADCONFIG62_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xF8 21. "PADCONFIG62_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xF8 19.--20. "PADCONFIG62_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xF8 18. "PADCONFIG62_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xF8 17. "PADCONFIG62_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xF8 16. "PADCONFIG62_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xF8 15. "PADCONFIG62_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xF8 14. "PADCONFIG62_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xF8 11.--13. "PADCONFIG62_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xF8 8. "PADCONFIG62_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xF8 7. "PADCONFIG62_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xF8 0.--3. "PADCONFIG62_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xFC "CFG0_PADCONFIG63,"
bitfld.long 0xFC 31. "PADCONFIG63_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xFC 30. "PADCONFIG63_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xFC 29. "PADCONFIG63_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xFC 28. "PADCONFIG63_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xFC 27. "PADCONFIG63_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xFC 26. "PADCONFIG63_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xFC 25. "PADCONFIG63_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xFC 24. "PADCONFIG63_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xFC 23. "PADCONFIG63_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xFC 22. "PADCONFIG63_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xFC 21. "PADCONFIG63_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xFC 19.--20. "PADCONFIG63_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xFC 18. "PADCONFIG63_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xFC 17. "PADCONFIG63_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xFC 16. "PADCONFIG63_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xFC 15. "PADCONFIG63_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xFC 14. "PADCONFIG63_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xFC 11.--13. "PADCONFIG63_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xFC 8. "PADCONFIG63_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xFC 7. "PADCONFIG63_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xFC 0.--3. "PADCONFIG63_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x100 "CFG0_PADCONFIG64,"
bitfld.long 0x100 31. "PADCONFIG64_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x100 30. "PADCONFIG64_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x100 29. "PADCONFIG64_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x100 28. "PADCONFIG64_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x100 27. "PADCONFIG64_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x100 26. "PADCONFIG64_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x100 25. "PADCONFIG64_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x100 24. "PADCONFIG64_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x100 23. "PADCONFIG64_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x100 22. "PADCONFIG64_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x100 21. "PADCONFIG64_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x100 19.--20. "PADCONFIG64_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x100 18. "PADCONFIG64_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x100 17. "PADCONFIG64_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x100 16. "PADCONFIG64_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x100 15. "PADCONFIG64_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x100 14. "PADCONFIG64_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x100 11.--13. "PADCONFIG64_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x100 8. "PADCONFIG64_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x100 7. "PADCONFIG64_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x100 0.--3. "PADCONFIG64_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x104 "CFG0_PADCONFIG65,"
bitfld.long 0x104 31. "PADCONFIG65_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x104 30. "PADCONFIG65_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x104 29. "PADCONFIG65_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x104 28. "PADCONFIG65_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x104 27. "PADCONFIG65_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x104 26. "PADCONFIG65_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x104 25. "PADCONFIG65_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x104 24. "PADCONFIG65_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x104 23. "PADCONFIG65_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x104 22. "PADCONFIG65_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x104 21. "PADCONFIG65_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x104 19.--20. "PADCONFIG65_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x104 18. "PADCONFIG65_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x104 17. "PADCONFIG65_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x104 16. "PADCONFIG65_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x104 15. "PADCONFIG65_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x104 14. "PADCONFIG65_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x104 11.--13. "PADCONFIG65_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 8. "PADCONFIG65_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x104 7. "PADCONFIG65_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x104 0.--3. "PADCONFIG65_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x108 "CFG0_PADCONFIG66,"
bitfld.long 0x108 31. "PADCONFIG66_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x108 30. "PADCONFIG66_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x108 29. "PADCONFIG66_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x108 28. "PADCONFIG66_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x108 27. "PADCONFIG66_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x108 26. "PADCONFIG66_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x108 25. "PADCONFIG66_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x108 24. "PADCONFIG66_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x108 23. "PADCONFIG66_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x108 22. "PADCONFIG66_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x108 21. "PADCONFIG66_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x108 19.--20. "PADCONFIG66_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x108 18. "PADCONFIG66_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x108 17. "PADCONFIG66_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x108 16. "PADCONFIG66_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x108 15. "PADCONFIG66_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x108 14. "PADCONFIG66_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x108 11.--13. "PADCONFIG66_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x108 8. "PADCONFIG66_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x108 7. "PADCONFIG66_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x108 0.--3. "PADCONFIG66_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x10C "CFG0_PADCONFIG67,"
bitfld.long 0x10C 31. "PADCONFIG67_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x10C 30. "PADCONFIG67_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x10C 29. "PADCONFIG67_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x10C 28. "PADCONFIG67_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x10C 27. "PADCONFIG67_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x10C 26. "PADCONFIG67_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x10C 25. "PADCONFIG67_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x10C 24. "PADCONFIG67_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x10C 23. "PADCONFIG67_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x10C 22. "PADCONFIG67_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x10C 21. "PADCONFIG67_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x10C 19.--20. "PADCONFIG67_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x10C 18. "PADCONFIG67_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x10C 17. "PADCONFIG67_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x10C 16. "PADCONFIG67_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x10C 15. "PADCONFIG67_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x10C 14. "PADCONFIG67_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x10C 11.--13. "PADCONFIG67_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10C 8. "PADCONFIG67_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x10C 7. "PADCONFIG67_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x10C 0.--3. "PADCONFIG67_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x110 "CFG0_PADCONFIG68,"
bitfld.long 0x110 31. "PADCONFIG68_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x110 30. "PADCONFIG68_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x110 29. "PADCONFIG68_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x110 28. "PADCONFIG68_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x110 27. "PADCONFIG68_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x110 26. "PADCONFIG68_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x110 25. "PADCONFIG68_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x110 24. "PADCONFIG68_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x110 23. "PADCONFIG68_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x110 22. "PADCONFIG68_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x110 21. "PADCONFIG68_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x110 19.--20. "PADCONFIG68_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x110 18. "PADCONFIG68_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x110 17. "PADCONFIG68_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x110 16. "PADCONFIG68_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x110 15. "PADCONFIG68_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x110 14. "PADCONFIG68_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x110 11.--13. "PADCONFIG68_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x110 8. "PADCONFIG68_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x110 7. "PADCONFIG68_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x110 0.--3. "PADCONFIG68_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x114 "CFG0_PADCONFIG69,"
bitfld.long 0x114 31. "PADCONFIG69_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x114 30. "PADCONFIG69_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x114 29. "PADCONFIG69_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x114 28. "PADCONFIG69_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x114 27. "PADCONFIG69_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x114 26. "PADCONFIG69_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x114 25. "PADCONFIG69_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x114 24. "PADCONFIG69_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x114 23. "PADCONFIG69_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x114 22. "PADCONFIG69_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x114 21. "PADCONFIG69_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x114 19.--20. "PADCONFIG69_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x114 18. "PADCONFIG69_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x114 17. "PADCONFIG69_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x114 16. "PADCONFIG69_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x114 15. "PADCONFIG69_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x114 14. "PADCONFIG69_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x114 11.--13. "PADCONFIG69_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x114 8. "PADCONFIG69_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x114 7. "PADCONFIG69_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x114 0.--3. "PADCONFIG69_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x118 "CFG0_PADCONFIG70,"
bitfld.long 0x118 31. "PADCONFIG70_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x118 30. "PADCONFIG70_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x118 29. "PADCONFIG70_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x118 28. "PADCONFIG70_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x118 27. "PADCONFIG70_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x118 26. "PADCONFIG70_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x118 25. "PADCONFIG70_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x118 24. "PADCONFIG70_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x118 23. "PADCONFIG70_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x118 22. "PADCONFIG70_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x118 21. "PADCONFIG70_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x118 19.--20. "PADCONFIG70_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x118 18. "PADCONFIG70_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x118 17. "PADCONFIG70_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x118 16. "PADCONFIG70_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x118 15. "PADCONFIG70_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x118 14. "PADCONFIG70_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x118 11.--13. "PADCONFIG70_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x118 8. "PADCONFIG70_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x118 7. "PADCONFIG70_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x118 0.--3. "PADCONFIG70_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x11C "CFG0_PADCONFIG71,"
bitfld.long 0x11C 31. "PADCONFIG71_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x11C 30. "PADCONFIG71_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x11C 29. "PADCONFIG71_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x11C 28. "PADCONFIG71_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x11C 27. "PADCONFIG71_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x11C 26. "PADCONFIG71_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x11C 25. "PADCONFIG71_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x11C 24. "PADCONFIG71_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x11C 23. "PADCONFIG71_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x11C 22. "PADCONFIG71_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x11C 21. "PADCONFIG71_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x11C 19.--20. "PADCONFIG71_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x11C 18. "PADCONFIG71_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x11C 17. "PADCONFIG71_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x11C 16. "PADCONFIG71_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x11C 15. "PADCONFIG71_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x11C 14. "PADCONFIG71_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x11C 11.--13. "PADCONFIG71_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x11C 8. "PADCONFIG71_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x11C 7. "PADCONFIG71_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x11C 0.--3. "PADCONFIG71_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x120 "CFG0_PADCONFIG72,"
bitfld.long 0x120 31. "PADCONFIG72_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x120 30. "PADCONFIG72_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x120 29. "PADCONFIG72_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x120 28. "PADCONFIG72_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x120 27. "PADCONFIG72_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x120 26. "PADCONFIG72_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x120 25. "PADCONFIG72_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x120 24. "PADCONFIG72_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x120 23. "PADCONFIG72_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x120 22. "PADCONFIG72_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x120 21. "PADCONFIG72_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x120 19.--20. "PADCONFIG72_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x120 18. "PADCONFIG72_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x120 17. "PADCONFIG72_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x120 16. "PADCONFIG72_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x120 15. "PADCONFIG72_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x120 14. "PADCONFIG72_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x120 11.--13. "PADCONFIG72_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x120 8. "PADCONFIG72_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x120 7. "PADCONFIG72_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x120 0.--3. "PADCONFIG72_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x124 "CFG0_PADCONFIG73,"
bitfld.long 0x124 31. "PADCONFIG73_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x124 30. "PADCONFIG73_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x124 29. "PADCONFIG73_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x124 28. "PADCONFIG73_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x124 27. "PADCONFIG73_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x124 26. "PADCONFIG73_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x124 25. "PADCONFIG73_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x124 24. "PADCONFIG73_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x124 23. "PADCONFIG73_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x124 22. "PADCONFIG73_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x124 21. "PADCONFIG73_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x124 19.--20. "PADCONFIG73_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x124 18. "PADCONFIG73_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x124 17. "PADCONFIG73_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x124 16. "PADCONFIG73_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x124 15. "PADCONFIG73_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x124 14. "PADCONFIG73_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x124 11.--13. "PADCONFIG73_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x124 8. "PADCONFIG73_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x124 7. "PADCONFIG73_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x124 0.--3. "PADCONFIG73_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x128 "CFG0_PADCONFIG74,"
bitfld.long 0x128 31. "PADCONFIG74_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x128 30. "PADCONFIG74_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x128 29. "PADCONFIG74_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x128 28. "PADCONFIG74_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x128 27. "PADCONFIG74_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x128 26. "PADCONFIG74_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x128 25. "PADCONFIG74_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x128 24. "PADCONFIG74_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x128 23. "PADCONFIG74_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x128 22. "PADCONFIG74_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x128 21. "PADCONFIG74_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x128 19.--20. "PADCONFIG74_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x128 18. "PADCONFIG74_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x128 17. "PADCONFIG74_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x128 16. "PADCONFIG74_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x128 15. "PADCONFIG74_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x128 14. "PADCONFIG74_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x128 11.--13. "PADCONFIG74_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x128 8. "PADCONFIG74_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x128 7. "PADCONFIG74_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x128 0.--3. "PADCONFIG74_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x12C "CFG0_PADCONFIG75,"
bitfld.long 0x12C 31. "PADCONFIG75_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x12C 30. "PADCONFIG75_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x12C 29. "PADCONFIG75_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x12C 28. "PADCONFIG75_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x12C 27. "PADCONFIG75_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x12C 26. "PADCONFIG75_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x12C 25. "PADCONFIG75_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x12C 24. "PADCONFIG75_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x12C 23. "PADCONFIG75_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x12C 22. "PADCONFIG75_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x12C 21. "PADCONFIG75_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x12C 19.--20. "PADCONFIG75_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x12C 18. "PADCONFIG75_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x12C 17. "PADCONFIG75_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x12C 16. "PADCONFIG75_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x12C 15. "PADCONFIG75_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x12C 14. "PADCONFIG75_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x12C 11.--13. "PADCONFIG75_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x12C 8. "PADCONFIG75_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x12C 7. "PADCONFIG75_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x12C 0.--3. "PADCONFIG75_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x130 "CFG0_PADCONFIG76,"
bitfld.long 0x130 31. "PADCONFIG76_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x130 30. "PADCONFIG76_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x130 29. "PADCONFIG76_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x130 28. "PADCONFIG76_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x130 27. "PADCONFIG76_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x130 26. "PADCONFIG76_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x130 25. "PADCONFIG76_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x130 24. "PADCONFIG76_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x130 23. "PADCONFIG76_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x130 22. "PADCONFIG76_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x130 21. "PADCONFIG76_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x130 19.--20. "PADCONFIG76_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x130 18. "PADCONFIG76_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x130 17. "PADCONFIG76_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x130 16. "PADCONFIG76_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x130 15. "PADCONFIG76_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x130 14. "PADCONFIG76_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x130 11.--13. "PADCONFIG76_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x130 8. "PADCONFIG76_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x130 7. "PADCONFIG76_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x130 0.--3. "PADCONFIG76_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x134 "CFG0_PADCONFIG77,"
bitfld.long 0x134 31. "PADCONFIG77_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x134 30. "PADCONFIG77_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x134 29. "PADCONFIG77_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x134 28. "PADCONFIG77_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x134 27. "PADCONFIG77_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x134 26. "PADCONFIG77_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x134 25. "PADCONFIG77_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x134 24. "PADCONFIG77_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x134 23. "PADCONFIG77_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x134 22. "PADCONFIG77_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x134 21. "PADCONFIG77_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x134 19.--20. "PADCONFIG77_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x134 18. "PADCONFIG77_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x134 17. "PADCONFIG77_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x134 16. "PADCONFIG77_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x134 15. "PADCONFIG77_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x134 14. "PADCONFIG77_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x134 11.--13. "PADCONFIG77_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x134 8. "PADCONFIG77_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x134 7. "PADCONFIG77_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x134 0.--3. "PADCONFIG77_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x138 "CFG0_PADCONFIG78,"
bitfld.long 0x138 31. "PADCONFIG78_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x138 30. "PADCONFIG78_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x138 29. "PADCONFIG78_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x138 28. "PADCONFIG78_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x138 27. "PADCONFIG78_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x138 26. "PADCONFIG78_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x138 25. "PADCONFIG78_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x138 24. "PADCONFIG78_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x138 23. "PADCONFIG78_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x138 22. "PADCONFIG78_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x138 21. "PADCONFIG78_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x138 19.--20. "PADCONFIG78_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x138 18. "PADCONFIG78_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x138 17. "PADCONFIG78_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x138 16. "PADCONFIG78_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x138 15. "PADCONFIG78_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x138 14. "PADCONFIG78_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x138 11.--13. "PADCONFIG78_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x138 8. "PADCONFIG78_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x138 7. "PADCONFIG78_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x138 0.--3. "PADCONFIG78_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x13C "CFG0_PADCONFIG79,"
bitfld.long 0x13C 31. "PADCONFIG79_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x13C 30. "PADCONFIG79_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x13C 29. "PADCONFIG79_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x13C 28. "PADCONFIG79_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x13C 27. "PADCONFIG79_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x13C 26. "PADCONFIG79_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x13C 25. "PADCONFIG79_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x13C 24. "PADCONFIG79_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x13C 23. "PADCONFIG79_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x13C 22. "PADCONFIG79_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x13C 21. "PADCONFIG79_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x13C 19.--20. "PADCONFIG79_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x13C 18. "PADCONFIG79_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x13C 17. "PADCONFIG79_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x13C 16. "PADCONFIG79_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x13C 15. "PADCONFIG79_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x13C 14. "PADCONFIG79_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x13C 11.--13. "PADCONFIG79_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x13C 8. "PADCONFIG79_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x13C 7. "PADCONFIG79_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x13C 0.--3. "PADCONFIG79_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x140 "CFG0_PADCONFIG80,"
bitfld.long 0x140 31. "PADCONFIG80_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x140 30. "PADCONFIG80_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x140 29. "PADCONFIG80_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x140 28. "PADCONFIG80_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x140 27. "PADCONFIG80_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x140 26. "PADCONFIG80_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x140 25. "PADCONFIG80_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x140 24. "PADCONFIG80_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x140 23. "PADCONFIG80_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x140 22. "PADCONFIG80_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x140 21. "PADCONFIG80_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x140 19.--20. "PADCONFIG80_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x140 18. "PADCONFIG80_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x140 17. "PADCONFIG80_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x140 16. "PADCONFIG80_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x140 15. "PADCONFIG80_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x140 14. "PADCONFIG80_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x140 11.--13. "PADCONFIG80_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 8. "PADCONFIG80_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x140 7. "PADCONFIG80_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x140 0.--3. "PADCONFIG80_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x144 "CFG0_PADCONFIG81,"
bitfld.long 0x144 31. "PADCONFIG81_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x144 30. "PADCONFIG81_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x144 29. "PADCONFIG81_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x144 28. "PADCONFIG81_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x144 27. "PADCONFIG81_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x144 26. "PADCONFIG81_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x144 25. "PADCONFIG81_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x144 24. "PADCONFIG81_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x144 23. "PADCONFIG81_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x144 22. "PADCONFIG81_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x144 21. "PADCONFIG81_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x144 19.--20. "PADCONFIG81_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x144 18. "PADCONFIG81_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x144 17. "PADCONFIG81_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x144 16. "PADCONFIG81_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x144 15. "PADCONFIG81_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x144 14. "PADCONFIG81_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x144 11.--13. "PADCONFIG81_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 8. "PADCONFIG81_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x144 7. "PADCONFIG81_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x144 0.--3. "PADCONFIG81_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x148 "CFG0_PADCONFIG82,"
bitfld.long 0x148 31. "PADCONFIG82_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x148 30. "PADCONFIG82_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x148 29. "PADCONFIG82_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x148 28. "PADCONFIG82_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x148 27. "PADCONFIG82_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x148 26. "PADCONFIG82_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x148 25. "PADCONFIG82_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x148 24. "PADCONFIG82_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x148 23. "PADCONFIG82_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x148 22. "PADCONFIG82_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x148 21. "PADCONFIG82_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x148 19.--20. "PADCONFIG82_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x148 18. "PADCONFIG82_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x148 17. "PADCONFIG82_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x148 16. "PADCONFIG82_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x148 15. "PADCONFIG82_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x148 14. "PADCONFIG82_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x148 11.--13. "PADCONFIG82_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x148 8. "PADCONFIG82_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x148 7. "PADCONFIG82_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x148 0.--3. "PADCONFIG82_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x14C "CFG0_PADCONFIG83,"
bitfld.long 0x14C 31. "PADCONFIG83_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x14C 30. "PADCONFIG83_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x14C 29. "PADCONFIG83_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x14C 28. "PADCONFIG83_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x14C 27. "PADCONFIG83_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x14C 26. "PADCONFIG83_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x14C 25. "PADCONFIG83_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x14C 24. "PADCONFIG83_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x14C 23. "PADCONFIG83_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x14C 22. "PADCONFIG83_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x14C 21. "PADCONFIG83_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x14C 19.--20. "PADCONFIG83_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x14C 18. "PADCONFIG83_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x14C 17. "PADCONFIG83_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x14C 16. "PADCONFIG83_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x14C 15. "PADCONFIG83_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x14C 14. "PADCONFIG83_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x14C 11.--13. "PADCONFIG83_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14C 8. "PADCONFIG83_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x14C 7. "PADCONFIG83_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x14C 0.--3. "PADCONFIG83_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x150 "CFG0_PADCONFIG84,"
bitfld.long 0x150 31. "PADCONFIG84_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x150 30. "PADCONFIG84_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x150 29. "PADCONFIG84_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x150 28. "PADCONFIG84_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x150 27. "PADCONFIG84_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x150 26. "PADCONFIG84_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x150 25. "PADCONFIG84_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x150 24. "PADCONFIG84_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x150 23. "PADCONFIG84_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x150 22. "PADCONFIG84_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x150 21. "PADCONFIG84_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x150 19.--20. "PADCONFIG84_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x150 18. "PADCONFIG84_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x150 17. "PADCONFIG84_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x150 16. "PADCONFIG84_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x150 15. "PADCONFIG84_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x150 14. "PADCONFIG84_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x150 11.--13. "PADCONFIG84_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x150 8. "PADCONFIG84_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x150 7. "PADCONFIG84_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x150 0.--3. "PADCONFIG84_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x154 "CFG0_PADCONFIG85,"
bitfld.long 0x154 31. "PADCONFIG85_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x154 30. "PADCONFIG85_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x154 29. "PADCONFIG85_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x154 28. "PADCONFIG85_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x154 27. "PADCONFIG85_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x154 26. "PADCONFIG85_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x154 25. "PADCONFIG85_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x154 24. "PADCONFIG85_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x154 23. "PADCONFIG85_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x154 22. "PADCONFIG85_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x154 21. "PADCONFIG85_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x154 19.--20. "PADCONFIG85_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x154 18. "PADCONFIG85_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x154 17. "PADCONFIG85_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x154 16. "PADCONFIG85_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x154 15. "PADCONFIG85_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x154 14. "PADCONFIG85_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x154 11.--13. "PADCONFIG85_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x154 8. "PADCONFIG85_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x154 7. "PADCONFIG85_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x154 0.--3. "PADCONFIG85_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x158 "CFG0_PADCONFIG86,"
bitfld.long 0x158 31. "PADCONFIG86_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x158 30. "PADCONFIG86_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x158 29. "PADCONFIG86_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x158 28. "PADCONFIG86_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x158 27. "PADCONFIG86_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x158 26. "PADCONFIG86_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x158 25. "PADCONFIG86_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x158 24. "PADCONFIG86_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x158 23. "PADCONFIG86_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x158 22. "PADCONFIG86_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x158 21. "PADCONFIG86_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x158 19.--20. "PADCONFIG86_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x158 18. "PADCONFIG86_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x158 17. "PADCONFIG86_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x158 16. "PADCONFIG86_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x158 15. "PADCONFIG86_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x158 14. "PADCONFIG86_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x158 11.--13. "PADCONFIG86_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x158 8. "PADCONFIG86_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x158 7. "PADCONFIG86_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x158 0.--3. "PADCONFIG86_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x15C "CFG0_PADCONFIG87,"
bitfld.long 0x15C 31. "PADCONFIG87_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x15C 30. "PADCONFIG87_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x15C 29. "PADCONFIG87_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x15C 28. "PADCONFIG87_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x15C 27. "PADCONFIG87_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x15C 26. "PADCONFIG87_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x15C 25. "PADCONFIG87_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x15C 24. "PADCONFIG87_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x15C 23. "PADCONFIG87_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x15C 22. "PADCONFIG87_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x15C 21. "PADCONFIG87_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x15C 19.--20. "PADCONFIG87_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x15C 18. "PADCONFIG87_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x15C 17. "PADCONFIG87_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x15C 16. "PADCONFIG87_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x15C 15. "PADCONFIG87_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x15C 14. "PADCONFIG87_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x15C 11.--13. "PADCONFIG87_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x15C 8. "PADCONFIG87_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x15C 7. "PADCONFIG87_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x15C 0.--3. "PADCONFIG87_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x160 "CFG0_PADCONFIG88,"
bitfld.long 0x160 31. "PADCONFIG88_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x160 30. "PADCONFIG88_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x160 29. "PADCONFIG88_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x160 28. "PADCONFIG88_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x160 27. "PADCONFIG88_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x160 26. "PADCONFIG88_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x160 25. "PADCONFIG88_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x160 24. "PADCONFIG88_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x160 23. "PADCONFIG88_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x160 22. "PADCONFIG88_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x160 21. "PADCONFIG88_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x160 19.--20. "PADCONFIG88_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x160 18. "PADCONFIG88_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x160 17. "PADCONFIG88_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x160 16. "PADCONFIG88_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x160 15. "PADCONFIG88_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x160 14. "PADCONFIG88_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x160 11.--13. "PADCONFIG88_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x160 8. "PADCONFIG88_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x160 7. "PADCONFIG88_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x160 0.--3. "PADCONFIG88_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x164 "CFG0_PADCONFIG89,"
bitfld.long 0x164 31. "PADCONFIG89_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x164 30. "PADCONFIG89_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x164 29. "PADCONFIG89_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x164 28. "PADCONFIG89_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x164 27. "PADCONFIG89_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x164 26. "PADCONFIG89_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x164 25. "PADCONFIG89_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x164 24. "PADCONFIG89_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x164 23. "PADCONFIG89_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x164 22. "PADCONFIG89_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x164 21. "PADCONFIG89_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x164 19.--20. "PADCONFIG89_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x164 18. "PADCONFIG89_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x164 17. "PADCONFIG89_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x164 16. "PADCONFIG89_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x164 15. "PADCONFIG89_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x164 14. "PADCONFIG89_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x164 11.--13. "PADCONFIG89_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x164 8. "PADCONFIG89_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x164 7. "PADCONFIG89_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x164 0.--3. "PADCONFIG89_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x168 "CFG0_PADCONFIG90,"
bitfld.long 0x168 31. "PADCONFIG90_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x168 30. "PADCONFIG90_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x168 29. "PADCONFIG90_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x168 28. "PADCONFIG90_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x168 27. "PADCONFIG90_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x168 26. "PADCONFIG90_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x168 25. "PADCONFIG90_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x168 24. "PADCONFIG90_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x168 23. "PADCONFIG90_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x168 22. "PADCONFIG90_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x168 21. "PADCONFIG90_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x168 19.--20. "PADCONFIG90_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x168 18. "PADCONFIG90_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x168 17. "PADCONFIG90_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x168 16. "PADCONFIG90_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x168 15. "PADCONFIG90_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x168 14. "PADCONFIG90_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x168 11.--13. "PADCONFIG90_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x168 8. "PADCONFIG90_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x168 7. "PADCONFIG90_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x168 0.--3. "PADCONFIG90_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x16C "CFG0_PADCONFIG91,"
bitfld.long 0x16C 31. "PADCONFIG91_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x16C 30. "PADCONFIG91_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x16C 29. "PADCONFIG91_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x16C 28. "PADCONFIG91_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x16C 27. "PADCONFIG91_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x16C 26. "PADCONFIG91_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x16C 25. "PADCONFIG91_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x16C 24. "PADCONFIG91_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x16C 23. "PADCONFIG91_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x16C 22. "PADCONFIG91_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x16C 21. "PADCONFIG91_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x16C 19.--20. "PADCONFIG91_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x16C 18. "PADCONFIG91_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x16C 17. "PADCONFIG91_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x16C 16. "PADCONFIG91_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x16C 15. "PADCONFIG91_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x16C 14. "PADCONFIG91_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x16C 11.--13. "PADCONFIG91_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x16C 8. "PADCONFIG91_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x16C 7. "PADCONFIG91_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x16C 0.--3. "PADCONFIG91_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x170 "CFG0_PADCONFIG92,"
bitfld.long 0x170 31. "PADCONFIG92_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x170 30. "PADCONFIG92_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x170 29. "PADCONFIG92_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x170 28. "PADCONFIG92_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x170 27. "PADCONFIG92_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x170 26. "PADCONFIG92_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x170 25. "PADCONFIG92_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x170 24. "PADCONFIG92_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x170 23. "PADCONFIG92_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x170 22. "PADCONFIG92_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x170 21. "PADCONFIG92_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x170 19.--20. "PADCONFIG92_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x170 18. "PADCONFIG92_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x170 17. "PADCONFIG92_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x170 16. "PADCONFIG92_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x170 15. "PADCONFIG92_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x170 14. "PADCONFIG92_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x170 11.--13. "PADCONFIG92_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x170 8. "PADCONFIG92_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x170 7. "PADCONFIG92_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x170 0.--3. "PADCONFIG92_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x174 "CFG0_PADCONFIG93,"
bitfld.long 0x174 31. "PADCONFIG93_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x174 30. "PADCONFIG93_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x174 29. "PADCONFIG93_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x174 28. "PADCONFIG93_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x174 27. "PADCONFIG93_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x174 26. "PADCONFIG93_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x174 25. "PADCONFIG93_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x174 24. "PADCONFIG93_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x174 23. "PADCONFIG93_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x174 22. "PADCONFIG93_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x174 21. "PADCONFIG93_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x174 19.--20. "PADCONFIG93_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x174 18. "PADCONFIG93_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x174 17. "PADCONFIG93_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x174 16. "PADCONFIG93_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x174 15. "PADCONFIG93_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x174 14. "PADCONFIG93_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x174 11.--13. "PADCONFIG93_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x174 8. "PADCONFIG93_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x174 7. "PADCONFIG93_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x174 0.--3. "PADCONFIG93_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x178 "CFG0_PADCONFIG94,"
bitfld.long 0x178 31. "PADCONFIG94_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x178 30. "PADCONFIG94_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x178 29. "PADCONFIG94_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x178 28. "PADCONFIG94_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x178 27. "PADCONFIG94_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x178 26. "PADCONFIG94_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x178 25. "PADCONFIG94_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x178 24. "PADCONFIG94_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x178 23. "PADCONFIG94_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x178 22. "PADCONFIG94_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x178 21. "PADCONFIG94_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x178 19.--20. "PADCONFIG94_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x178 18. "PADCONFIG94_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x178 17. "PADCONFIG94_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x178 16. "PADCONFIG94_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x178 15. "PADCONFIG94_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x178 14. "PADCONFIG94_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x178 11.--13. "PADCONFIG94_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x178 8. "PADCONFIG94_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x178 7. "PADCONFIG94_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x178 0.--3. "PADCONFIG94_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x17C "CFG0_PADCONFIG95,"
bitfld.long 0x17C 31. "PADCONFIG95_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x17C 30. "PADCONFIG95_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x17C 29. "PADCONFIG95_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x17C 28. "PADCONFIG95_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x17C 27. "PADCONFIG95_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x17C 26. "PADCONFIG95_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x17C 25. "PADCONFIG95_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x17C 24. "PADCONFIG95_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x17C 23. "PADCONFIG95_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x17C 22. "PADCONFIG95_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x17C 21. "PADCONFIG95_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x17C 19.--20. "PADCONFIG95_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x17C 18. "PADCONFIG95_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x17C 17. "PADCONFIG95_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x17C 16. "PADCONFIG95_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x17C 15. "PADCONFIG95_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x17C 14. "PADCONFIG95_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x17C 11.--13. "PADCONFIG95_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x17C 8. "PADCONFIG95_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x17C 7. "PADCONFIG95_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x17C 0.--3. "PADCONFIG95_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x180 "CFG0_PADCONFIG96,"
bitfld.long 0x180 31. "PADCONFIG96_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x180 30. "PADCONFIG96_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x180 29. "PADCONFIG96_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x180 28. "PADCONFIG96_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x180 27. "PADCONFIG96_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x180 26. "PADCONFIG96_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x180 25. "PADCONFIG96_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x180 24. "PADCONFIG96_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x180 23. "PADCONFIG96_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x180 22. "PADCONFIG96_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x180 21. "PADCONFIG96_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x180 19.--20. "PADCONFIG96_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x180 18. "PADCONFIG96_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x180 17. "PADCONFIG96_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x180 16. "PADCONFIG96_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x180 15. "PADCONFIG96_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x180 14. "PADCONFIG96_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x180 11.--13. "PADCONFIG96_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x180 8. "PADCONFIG96_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x180 7. "PADCONFIG96_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x180 0.--3. "PADCONFIG96_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x184 "CFG0_PADCONFIG97,"
bitfld.long 0x184 31. "PADCONFIG97_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x184 30. "PADCONFIG97_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x184 29. "PADCONFIG97_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x184 28. "PADCONFIG97_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x184 27. "PADCONFIG97_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x184 26. "PADCONFIG97_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x184 25. "PADCONFIG97_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x184 24. "PADCONFIG97_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x184 23. "PADCONFIG97_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x184 22. "PADCONFIG97_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x184 21. "PADCONFIG97_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x184 19.--20. "PADCONFIG97_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x184 18. "PADCONFIG97_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x184 17. "PADCONFIG97_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x184 16. "PADCONFIG97_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x184 15. "PADCONFIG97_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x184 14. "PADCONFIG97_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x184 11.--13. "PADCONFIG97_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x184 8. "PADCONFIG97_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x184 7. "PADCONFIG97_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x184 0.--3. "PADCONFIG97_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x188 "CFG0_PADCONFIG98,"
bitfld.long 0x188 31. "PADCONFIG98_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x188 30. "PADCONFIG98_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x188 29. "PADCONFIG98_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x188 28. "PADCONFIG98_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x188 27. "PADCONFIG98_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x188 26. "PADCONFIG98_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x188 25. "PADCONFIG98_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x188 24. "PADCONFIG98_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x188 23. "PADCONFIG98_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x188 22. "PADCONFIG98_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x188 21. "PADCONFIG98_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x188 19.--20. "PADCONFIG98_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x188 18. "PADCONFIG98_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x188 17. "PADCONFIG98_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x188 16. "PADCONFIG98_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x188 15. "PADCONFIG98_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x188 14. "PADCONFIG98_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x188 11.--13. "PADCONFIG98_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x188 8. "PADCONFIG98_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x188 7. "PADCONFIG98_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x188 0.--3. "PADCONFIG98_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x18C "CFG0_PADCONFIG99,"
bitfld.long 0x18C 31. "PADCONFIG99_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x18C 30. "PADCONFIG99_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x18C 29. "PADCONFIG99_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x18C 28. "PADCONFIG99_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x18C 27. "PADCONFIG99_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x18C 26. "PADCONFIG99_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x18C 25. "PADCONFIG99_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x18C 24. "PADCONFIG99_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x18C 23. "PADCONFIG99_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x18C 22. "PADCONFIG99_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x18C 21. "PADCONFIG99_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x18C 19.--20. "PADCONFIG99_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x18C 18. "PADCONFIG99_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x18C 17. "PADCONFIG99_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x18C 16. "PADCONFIG99_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x18C 15. "PADCONFIG99_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x18C 14. "PADCONFIG99_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x18C 11.--13. "PADCONFIG99_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18C 8. "PADCONFIG99_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x18C 7. "PADCONFIG99_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x18C 0.--3. "PADCONFIG99_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x190 "CFG0_PADCONFIG100,"
bitfld.long 0x190 31. "PADCONFIG100_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x190 30. "PADCONFIG100_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x190 29. "PADCONFIG100_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x190 28. "PADCONFIG100_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x190 27. "PADCONFIG100_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x190 26. "PADCONFIG100_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x190 25. "PADCONFIG100_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x190 24. "PADCONFIG100_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x190 23. "PADCONFIG100_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x190 22. "PADCONFIG100_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x190 21. "PADCONFIG100_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x190 19.--20. "PADCONFIG100_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x190 18. "PADCONFIG100_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x190 17. "PADCONFIG100_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x190 16. "PADCONFIG100_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x190 15. "PADCONFIG100_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x190 14. "PADCONFIG100_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x190 11.--13. "PADCONFIG100_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x190 8. "PADCONFIG100_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x190 7. "PADCONFIG100_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x190 0.--3. "PADCONFIG100_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x194 "CFG0_PADCONFIG101,"
bitfld.long 0x194 31. "PADCONFIG101_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x194 30. "PADCONFIG101_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x194 29. "PADCONFIG101_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x194 28. "PADCONFIG101_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x194 27. "PADCONFIG101_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x194 26. "PADCONFIG101_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x194 25. "PADCONFIG101_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x194 24. "PADCONFIG101_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x194 23. "PADCONFIG101_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x194 22. "PADCONFIG101_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x194 21. "PADCONFIG101_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x194 19.--20. "PADCONFIG101_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x194 18. "PADCONFIG101_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x194 17. "PADCONFIG101_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x194 16. "PADCONFIG101_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x194 15. "PADCONFIG101_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x194 14. "PADCONFIG101_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x194 11.--13. "PADCONFIG101_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x194 8. "PADCONFIG101_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x194 7. "PADCONFIG101_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x194 0.--3. "PADCONFIG101_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x198 "CFG0_PADCONFIG102,"
bitfld.long 0x198 31. "PADCONFIG102_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x198 30. "PADCONFIG102_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x198 29. "PADCONFIG102_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x198 28. "PADCONFIG102_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x198 27. "PADCONFIG102_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x198 26. "PADCONFIG102_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x198 25. "PADCONFIG102_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x198 24. "PADCONFIG102_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x198 23. "PADCONFIG102_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x198 22. "PADCONFIG102_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x198 21. "PADCONFIG102_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x198 19.--20. "PADCONFIG102_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x198 18. "PADCONFIG102_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x198 17. "PADCONFIG102_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x198 16. "PADCONFIG102_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x198 15. "PADCONFIG102_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x198 14. "PADCONFIG102_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x198 11.--13. "PADCONFIG102_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x198 8. "PADCONFIG102_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x198 7. "PADCONFIG102_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x198 0.--3. "PADCONFIG102_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x19C "CFG0_PADCONFIG103,"
bitfld.long 0x19C 31. "PADCONFIG103_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x19C 30. "PADCONFIG103_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x19C 29. "PADCONFIG103_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x19C 28. "PADCONFIG103_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x19C 27. "PADCONFIG103_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x19C 26. "PADCONFIG103_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x19C 25. "PADCONFIG103_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x19C 24. "PADCONFIG103_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x19C 23. "PADCONFIG103_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x19C 22. "PADCONFIG103_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x19C 21. "PADCONFIG103_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x19C 19.--20. "PADCONFIG103_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x19C 18. "PADCONFIG103_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x19C 17. "PADCONFIG103_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x19C 16. "PADCONFIG103_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x19C 15. "PADCONFIG103_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x19C 14. "PADCONFIG103_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x19C 11.--13. "PADCONFIG103_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x19C 8. "PADCONFIG103_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x19C 7. "PADCONFIG103_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x19C 0.--3. "PADCONFIG103_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1A0 "CFG0_PADCONFIG104,"
bitfld.long 0x1A0 31. "PADCONFIG104_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1A0 30. "PADCONFIG104_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1A0 29. "PADCONFIG104_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1A0 28. "PADCONFIG104_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1A0 27. "PADCONFIG104_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1A0 26. "PADCONFIG104_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1A0 25. "PADCONFIG104_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1A0 24. "PADCONFIG104_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1A0 23. "PADCONFIG104_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1A0 22. "PADCONFIG104_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1A0 21. "PADCONFIG104_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1A0 19.--20. "PADCONFIG104_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1A0 18. "PADCONFIG104_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1A0 17. "PADCONFIG104_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1A0 16. "PADCONFIG104_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1A0 15. "PADCONFIG104_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1A0 14. "PADCONFIG104_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1A0 11.--13. "PADCONFIG104_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1A0 8. "PADCONFIG104_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1A0 7. "PADCONFIG104_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1A0 0.--3. "PADCONFIG104_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1A4 "CFG0_PADCONFIG105,"
bitfld.long 0x1A4 31. "PADCONFIG105_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1A4 30. "PADCONFIG105_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1A4 29. "PADCONFIG105_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1A4 28. "PADCONFIG105_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1A4 27. "PADCONFIG105_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1A4 26. "PADCONFIG105_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1A4 25. "PADCONFIG105_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1A4 24. "PADCONFIG105_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1A4 23. "PADCONFIG105_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1A4 22. "PADCONFIG105_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1A4 21. "PADCONFIG105_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1A4 19.--20. "PADCONFIG105_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1A4 18. "PADCONFIG105_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1A4 17. "PADCONFIG105_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1A4 16. "PADCONFIG105_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1A4 15. "PADCONFIG105_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1A4 14. "PADCONFIG105_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1A4 11.--13. "PADCONFIG105_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1A4 8. "PADCONFIG105_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1A4 7. "PADCONFIG105_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1A4 0.--3. "PADCONFIG105_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1A8 "CFG0_PADCONFIG106,"
bitfld.long 0x1A8 31. "PADCONFIG106_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1A8 30. "PADCONFIG106_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1A8 29. "PADCONFIG106_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1A8 28. "PADCONFIG106_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1A8 27. "PADCONFIG106_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1A8 26. "PADCONFIG106_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1A8 25. "PADCONFIG106_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1A8 24. "PADCONFIG106_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1A8 23. "PADCONFIG106_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1A8 22. "PADCONFIG106_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1A8 21. "PADCONFIG106_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1A8 19.--20. "PADCONFIG106_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1A8 18. "PADCONFIG106_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1A8 17. "PADCONFIG106_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1A8 16. "PADCONFIG106_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1A8 15. "PADCONFIG106_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1A8 14. "PADCONFIG106_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1A8 11.--13. "PADCONFIG106_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1A8 8. "PADCONFIG106_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1A8 7. "PADCONFIG106_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1A8 0.--3. "PADCONFIG106_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1AC "CFG0_PADCONFIG107,"
bitfld.long 0x1AC 31. "PADCONFIG107_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1AC 30. "PADCONFIG107_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1AC 29. "PADCONFIG107_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1AC 28. "PADCONFIG107_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1AC 27. "PADCONFIG107_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1AC 26. "PADCONFIG107_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1AC 25. "PADCONFIG107_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1AC 24. "PADCONFIG107_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1AC 23. "PADCONFIG107_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1AC 22. "PADCONFIG107_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1AC 21. "PADCONFIG107_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1AC 19.--20. "PADCONFIG107_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1AC 18. "PADCONFIG107_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1AC 17. "PADCONFIG107_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1AC 16. "PADCONFIG107_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1AC 15. "PADCONFIG107_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1AC 14. "PADCONFIG107_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1AC 11.--13. "PADCONFIG107_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1AC 8. "PADCONFIG107_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1AC 7. "PADCONFIG107_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1AC 0.--3. "PADCONFIG107_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1B0 "CFG0_PADCONFIG108,"
bitfld.long 0x1B0 31. "PADCONFIG108_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1B0 30. "PADCONFIG108_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1B0 29. "PADCONFIG108_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1B0 28. "PADCONFIG108_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1B0 27. "PADCONFIG108_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1B0 26. "PADCONFIG108_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1B0 25. "PADCONFIG108_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1B0 24. "PADCONFIG108_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1B0 23. "PADCONFIG108_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1B0 22. "PADCONFIG108_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1B0 21. "PADCONFIG108_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1B0 19.--20. "PADCONFIG108_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1B0 18. "PADCONFIG108_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1B0 17. "PADCONFIG108_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1B0 16. "PADCONFIG108_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1B0 15. "PADCONFIG108_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1B0 14. "PADCONFIG108_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1B0 11.--13. "PADCONFIG108_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1B0 8. "PADCONFIG108_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1B0 7. "PADCONFIG108_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1B0 0.--3. "PADCONFIG108_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1B4 "CFG0_PADCONFIG109,"
bitfld.long 0x1B4 31. "PADCONFIG109_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1B4 30. "PADCONFIG109_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1B4 29. "PADCONFIG109_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1B4 28. "PADCONFIG109_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1B4 27. "PADCONFIG109_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1B4 26. "PADCONFIG109_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1B4 25. "PADCONFIG109_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1B4 24. "PADCONFIG109_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1B4 23. "PADCONFIG109_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1B4 22. "PADCONFIG109_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1B4 21. "PADCONFIG109_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1B4 19.--20. "PADCONFIG109_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1B4 18. "PADCONFIG109_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1B4 17. "PADCONFIG109_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1B4 16. "PADCONFIG109_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1B4 15. "PADCONFIG109_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1B4 14. "PADCONFIG109_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1B4 11.--13. "PADCONFIG109_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1B4 8. "PADCONFIG109_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1B4 7. "PADCONFIG109_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1B4 0.--3. "PADCONFIG109_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1B8 "CFG0_PADCONFIG110,"
bitfld.long 0x1B8 31. "PADCONFIG110_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1B8 30. "PADCONFIG110_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1B8 29. "PADCONFIG110_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1B8 28. "PADCONFIG110_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1B8 27. "PADCONFIG110_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1B8 26. "PADCONFIG110_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1B8 25. "PADCONFIG110_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1B8 24. "PADCONFIG110_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1B8 23. "PADCONFIG110_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1B8 22. "PADCONFIG110_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1B8 21. "PADCONFIG110_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1B8 19.--20. "PADCONFIG110_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1B8 18. "PADCONFIG110_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1B8 17. "PADCONFIG110_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1B8 16. "PADCONFIG110_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1B8 15. "PADCONFIG110_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1B8 14. "PADCONFIG110_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1B8 11.--13. "PADCONFIG110_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1B8 8. "PADCONFIG110_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1B8 7. "PADCONFIG110_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1B8 0.--3. "PADCONFIG110_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1BC "CFG0_PADCONFIG111,"
bitfld.long 0x1BC 31. "PADCONFIG111_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1BC 30. "PADCONFIG111_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1BC 29. "PADCONFIG111_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1BC 28. "PADCONFIG111_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1BC 27. "PADCONFIG111_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1BC 26. "PADCONFIG111_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1BC 25. "PADCONFIG111_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1BC 24. "PADCONFIG111_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1BC 23. "PADCONFIG111_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1BC 22. "PADCONFIG111_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1BC 21. "PADCONFIG111_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1BC 19.--20. "PADCONFIG111_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1BC 18. "PADCONFIG111_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1BC 17. "PADCONFIG111_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1BC 16. "PADCONFIG111_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1BC 15. "PADCONFIG111_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1BC 14. "PADCONFIG111_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1BC 11.--13. "PADCONFIG111_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1BC 8. "PADCONFIG111_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1BC 7. "PADCONFIG111_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1BC 0.--3. "PADCONFIG111_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C0 "CFG0_PADCONFIG112,"
bitfld.long 0x1C0 31. "PADCONFIG112_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C0 30. "PADCONFIG112_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C0 29. "PADCONFIG112_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1C0 28. "PADCONFIG112_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1C0 27. "PADCONFIG112_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C0 26. "PADCONFIG112_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1C0 25. "PADCONFIG112_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C0 24. "PADCONFIG112_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1C0 23. "PADCONFIG112_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1C0 22. "PADCONFIG112_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1C0 21. "PADCONFIG112_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1C0 19.--20. "PADCONFIG112_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1C0 18. "PADCONFIG112_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1C0 17. "PADCONFIG112_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1C0 16. "PADCONFIG112_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C0 15. "PADCONFIG112_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1C0 14. "PADCONFIG112_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C0 11.--13. "PADCONFIG112_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C0 8. "PADCONFIG112_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1C0 7. "PADCONFIG112_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1C0 0.--3. "PADCONFIG112_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C4 "CFG0_PADCONFIG113,"
bitfld.long 0x1C4 31. "PADCONFIG113_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C4 30. "PADCONFIG113_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C4 29. "PADCONFIG113_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1C4 28. "PADCONFIG113_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1C4 27. "PADCONFIG113_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C4 26. "PADCONFIG113_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1C4 25. "PADCONFIG113_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C4 24. "PADCONFIG113_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1C4 23. "PADCONFIG113_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1C4 22. "PADCONFIG113_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1C4 21. "PADCONFIG113_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1C4 19.--20. "PADCONFIG113_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1C4 18. "PADCONFIG113_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1C4 17. "PADCONFIG113_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1C4 16. "PADCONFIG113_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C4 15. "PADCONFIG113_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1C4 14. "PADCONFIG113_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C4 11.--13. "PADCONFIG113_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C4 8. "PADCONFIG113_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1C4 7. "PADCONFIG113_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1C4 0.--3. "PADCONFIG113_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C8 "CFG0_PADCONFIG114,"
bitfld.long 0x1C8 31. "PADCONFIG114_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C8 30. "PADCONFIG114_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C8 29. "PADCONFIG114_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1C8 28. "PADCONFIG114_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1C8 27. "PADCONFIG114_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C8 26. "PADCONFIG114_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1C8 25. "PADCONFIG114_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C8 24. "PADCONFIG114_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1C8 23. "PADCONFIG114_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1C8 22. "PADCONFIG114_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1C8 21. "PADCONFIG114_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1C8 19.--20. "PADCONFIG114_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1C8 18. "PADCONFIG114_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1C8 17. "PADCONFIG114_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1C8 16. "PADCONFIG114_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C8 15. "PADCONFIG114_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1C8 14. "PADCONFIG114_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C8 11.--13. "PADCONFIG114_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C8 8. "PADCONFIG114_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1C8 7. "PADCONFIG114_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1C8 0.--3. "PADCONFIG114_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1CC "CFG0_PADCONFIG115,"
bitfld.long 0x1CC 31. "PADCONFIG115_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1CC 30. "PADCONFIG115_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1CC 29. "PADCONFIG115_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1CC 28. "PADCONFIG115_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1CC 27. "PADCONFIG115_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1CC 26. "PADCONFIG115_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1CC 25. "PADCONFIG115_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1CC 24. "PADCONFIG115_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1CC 23. "PADCONFIG115_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1CC 22. "PADCONFIG115_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1CC 21. "PADCONFIG115_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1CC 19.--20. "PADCONFIG115_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1CC 18. "PADCONFIG115_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1CC 17. "PADCONFIG115_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1CC 16. "PADCONFIG115_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1CC 15. "PADCONFIG115_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1CC 14. "PADCONFIG115_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1CC 11.--13. "PADCONFIG115_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1CC 8. "PADCONFIG115_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1CC 7. "PADCONFIG115_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1CC 0.--3. "PADCONFIG115_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1D0 "CFG0_PADCONFIG116,"
bitfld.long 0x1D0 31. "PADCONFIG116_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1D0 30. "PADCONFIG116_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1D0 29. "PADCONFIG116_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1D0 28. "PADCONFIG116_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1D0 27. "PADCONFIG116_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1D0 26. "PADCONFIG116_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1D0 25. "PADCONFIG116_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1D0 24. "PADCONFIG116_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1D0 23. "PADCONFIG116_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1D0 22. "PADCONFIG116_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1D0 21. "PADCONFIG116_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1D0 19.--20. "PADCONFIG116_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1D0 18. "PADCONFIG116_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1D0 17. "PADCONFIG116_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1D0 16. "PADCONFIG116_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1D0 15. "PADCONFIG116_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1D0 14. "PADCONFIG116_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1D0 11.--13. "PADCONFIG116_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1D0 8. "PADCONFIG116_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1D0 7. "PADCONFIG116_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1D0 0.--3. "PADCONFIG116_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1D4 "CFG0_PADCONFIG117,"
bitfld.long 0x1D4 31. "PADCONFIG117_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1D4 30. "PADCONFIG117_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1D4 29. "PADCONFIG117_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1D4 28. "PADCONFIG117_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1D4 27. "PADCONFIG117_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1D4 26. "PADCONFIG117_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1D4 25. "PADCONFIG117_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1D4 24. "PADCONFIG117_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1D4 23. "PADCONFIG117_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1D4 22. "PADCONFIG117_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1D4 21. "PADCONFIG117_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1D4 19.--20. "PADCONFIG117_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1D4 18. "PADCONFIG117_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1D4 17. "PADCONFIG117_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1D4 16. "PADCONFIG117_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1D4 15. "PADCONFIG117_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1D4 14. "PADCONFIG117_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1D4 11.--13. "PADCONFIG117_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1D4 8. "PADCONFIG117_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1D4 7. "PADCONFIG117_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1D4 0.--3. "PADCONFIG117_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1D8 "CFG0_PADCONFIG118,"
bitfld.long 0x1D8 31. "PADCONFIG118_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1D8 30. "PADCONFIG118_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1D8 29. "PADCONFIG118_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1D8 28. "PADCONFIG118_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1D8 27. "PADCONFIG118_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1D8 26. "PADCONFIG118_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1D8 25. "PADCONFIG118_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1D8 24. "PADCONFIG118_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1D8 23. "PADCONFIG118_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1D8 22. "PADCONFIG118_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1D8 21. "PADCONFIG118_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1D8 19.--20. "PADCONFIG118_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1D8 18. "PADCONFIG118_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1D8 17. "PADCONFIG118_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1D8 16. "PADCONFIG118_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1D8 15. "PADCONFIG118_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1D8 14. "PADCONFIG118_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1D8 11.--13. "PADCONFIG118_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1D8 8. "PADCONFIG118_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1D8 7. "PADCONFIG118_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1D8 0.--3. "PADCONFIG118_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1DC "CFG0_PADCONFIG119,"
bitfld.long 0x1DC 31. "PADCONFIG119_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1DC 30. "PADCONFIG119_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1DC 29. "PADCONFIG119_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1DC 28. "PADCONFIG119_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1DC 27. "PADCONFIG119_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1DC 26. "PADCONFIG119_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1DC 25. "PADCONFIG119_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1DC 24. "PADCONFIG119_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1DC 23. "PADCONFIG119_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1DC 22. "PADCONFIG119_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1DC 21. "PADCONFIG119_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1DC 19.--20. "PADCONFIG119_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1DC 18. "PADCONFIG119_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1DC 17. "PADCONFIG119_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1DC 16. "PADCONFIG119_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1DC 15. "PADCONFIG119_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1DC 14. "PADCONFIG119_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1DC 11.--13. "PADCONFIG119_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1DC 8. "PADCONFIG119_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1DC 7. "PADCONFIG119_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1DC 0.--3. "PADCONFIG119_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1E0 "CFG0_PADCONFIG120,"
bitfld.long 0x1E0 31. "PADCONFIG120_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1E0 30. "PADCONFIG120_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1E0 29. "PADCONFIG120_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1E0 28. "PADCONFIG120_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1E0 27. "PADCONFIG120_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1E0 26. "PADCONFIG120_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1E0 25. "PADCONFIG120_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1E0 24. "PADCONFIG120_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1E0 23. "PADCONFIG120_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1E0 22. "PADCONFIG120_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1E0 21. "PADCONFIG120_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1E0 19.--20. "PADCONFIG120_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1E0 18. "PADCONFIG120_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1E0 17. "PADCONFIG120_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1E0 16. "PADCONFIG120_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1E0 15. "PADCONFIG120_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1E0 14. "PADCONFIG120_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1E0 11.--13. "PADCONFIG120_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1E0 8. "PADCONFIG120_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1E0 7. "PADCONFIG120_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1E0 0.--3. "PADCONFIG120_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1E4 "CFG0_PADCONFIG121,"
bitfld.long 0x1E4 31. "PADCONFIG121_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1E4 30. "PADCONFIG121_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1E4 29. "PADCONFIG121_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1E4 28. "PADCONFIG121_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1E4 27. "PADCONFIG121_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1E4 26. "PADCONFIG121_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1E4 25. "PADCONFIG121_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1E4 24. "PADCONFIG121_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1E4 23. "PADCONFIG121_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1E4 22. "PADCONFIG121_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1E4 21. "PADCONFIG121_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1E4 19.--20. "PADCONFIG121_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1E4 18. "PADCONFIG121_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1E4 17. "PADCONFIG121_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1E4 16. "PADCONFIG121_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1E4 15. "PADCONFIG121_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1E4 14. "PADCONFIG121_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1E4 11.--13. "PADCONFIG121_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1E4 8. "PADCONFIG121_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1E4 7. "PADCONFIG121_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1E4 0.--3. "PADCONFIG121_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1E8 "CFG0_PADCONFIG122,"
bitfld.long 0x1E8 31. "PADCONFIG122_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1E8 30. "PADCONFIG122_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1E8 29. "PADCONFIG122_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1E8 28. "PADCONFIG122_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1E8 27. "PADCONFIG122_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1E8 26. "PADCONFIG122_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1E8 25. "PADCONFIG122_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1E8 24. "PADCONFIG122_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1E8 23. "PADCONFIG122_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1E8 22. "PADCONFIG122_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1E8 21. "PADCONFIG122_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1E8 19.--20. "PADCONFIG122_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1E8 18. "PADCONFIG122_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1E8 17. "PADCONFIG122_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1E8 16. "PADCONFIG122_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1E8 15. "PADCONFIG122_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1E8 14. "PADCONFIG122_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1E8 11.--13. "PADCONFIG122_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1E8 8. "PADCONFIG122_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1E8 7. "PADCONFIG122_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1E8 0.--3. "PADCONFIG122_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1EC "CFG0_PADCONFIG123,"
bitfld.long 0x1EC 31. "PADCONFIG123_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1EC 30. "PADCONFIG123_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1EC 29. "PADCONFIG123_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1EC 28. "PADCONFIG123_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1EC 27. "PADCONFIG123_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1EC 26. "PADCONFIG123_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1EC 25. "PADCONFIG123_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1EC 24. "PADCONFIG123_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1EC 23. "PADCONFIG123_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1EC 22. "PADCONFIG123_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1EC 21. "PADCONFIG123_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1EC 19.--20. "PADCONFIG123_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1EC 18. "PADCONFIG123_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1EC 17. "PADCONFIG123_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1EC 16. "PADCONFIG123_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1EC 15. "PADCONFIG123_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1EC 14. "PADCONFIG123_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1EC 11.--13. "PADCONFIG123_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1EC 8. "PADCONFIG123_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1EC 7. "PADCONFIG123_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1EC 0.--3. "PADCONFIG123_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1F0 "CFG0_PADCONFIG124,"
bitfld.long 0x1F0 31. "PADCONFIG124_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1F0 30. "PADCONFIG124_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1F0 29. "PADCONFIG124_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1F0 28. "PADCONFIG124_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1F0 27. "PADCONFIG124_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1F0 26. "PADCONFIG124_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1F0 25. "PADCONFIG124_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1F0 24. "PADCONFIG124_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1F0 23. "PADCONFIG124_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1F0 22. "PADCONFIG124_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1F0 21. "PADCONFIG124_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1F0 19.--20. "PADCONFIG124_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1F0 18. "PADCONFIG124_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1F0 17. "PADCONFIG124_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1F0 16. "PADCONFIG124_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1F0 15. "PADCONFIG124_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1F0 14. "PADCONFIG124_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1F0 11.--13. "PADCONFIG124_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1F0 8. "PADCONFIG124_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1F0 7. "PADCONFIG124_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1F0 0.--3. "PADCONFIG124_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1F4 "CFG0_PADCONFIG125,"
bitfld.long 0x1F4 31. "PADCONFIG125_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1F4 30. "PADCONFIG125_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1F4 29. "PADCONFIG125_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1F4 28. "PADCONFIG125_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1F4 27. "PADCONFIG125_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1F4 26. "PADCONFIG125_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1F4 25. "PADCONFIG125_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1F4 24. "PADCONFIG125_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1F4 23. "PADCONFIG125_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1F4 22. "PADCONFIG125_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1F4 21. "PADCONFIG125_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1F4 19.--20. "PADCONFIG125_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1F4 18. "PADCONFIG125_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1F4 17. "PADCONFIG125_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1F4 16. "PADCONFIG125_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1F4 15. "PADCONFIG125_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1F4 14. "PADCONFIG125_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1F4 11.--13. "PADCONFIG125_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1F4 8. "PADCONFIG125_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1F4 7. "PADCONFIG125_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1F4 0.--3. "PADCONFIG125_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1F8 "CFG0_PADCONFIG126,"
bitfld.long 0x1F8 31. "PADCONFIG126_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1F8 30. "PADCONFIG126_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1F8 29. "PADCONFIG126_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1F8 28. "PADCONFIG126_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1F8 27. "PADCONFIG126_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1F8 26. "PADCONFIG126_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1F8 25. "PADCONFIG126_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1F8 24. "PADCONFIG126_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1F8 23. "PADCONFIG126_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1F8 22. "PADCONFIG126_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1F8 21. "PADCONFIG126_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1F8 19.--20. "PADCONFIG126_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1F8 18. "PADCONFIG126_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1F8 17. "PADCONFIG126_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1F8 16. "PADCONFIG126_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1F8 15. "PADCONFIG126_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1F8 14. "PADCONFIG126_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1F8 11.--13. "PADCONFIG126_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1F8 8. "PADCONFIG126_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1F8 7. "PADCONFIG126_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1F8 0.--3. "PADCONFIG126_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1FC "CFG0_PADCONFIG127,"
bitfld.long 0x1FC 31. "PADCONFIG127_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1FC 30. "PADCONFIG127_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1FC 29. "PADCONFIG127_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1FC 28. "PADCONFIG127_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1FC 27. "PADCONFIG127_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x1FC 26. "PADCONFIG127_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x1FC 25. "PADCONFIG127_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x1FC 24. "PADCONFIG127_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1FC 23. "PADCONFIG127_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x1FC 22. "PADCONFIG127_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1FC 21. "PADCONFIG127_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1FC 19.--20. "PADCONFIG127_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1FC 18. "PADCONFIG127_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1FC 17. "PADCONFIG127_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1FC 16. "PADCONFIG127_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1FC 15. "PADCONFIG127_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1FC 14. "PADCONFIG127_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1FC 11.--13. "PADCONFIG127_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1FC 8. "PADCONFIG127_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1FC 7. "PADCONFIG127_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1FC 0.--3. "PADCONFIG127_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x200 "CFG0_PADCONFIG128,"
bitfld.long 0x200 31. "PADCONFIG128_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x200 30. "PADCONFIG128_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x200 29. "PADCONFIG128_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x200 28. "PADCONFIG128_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x200 27. "PADCONFIG128_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x200 26. "PADCONFIG128_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x200 25. "PADCONFIG128_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x200 24. "PADCONFIG128_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x200 23. "PADCONFIG128_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x200 22. "PADCONFIG128_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x200 21. "PADCONFIG128_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x200 19.--20. "PADCONFIG128_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x200 18. "PADCONFIG128_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x200 17. "PADCONFIG128_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x200 16. "PADCONFIG128_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x200 15. "PADCONFIG128_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x200 14. "PADCONFIG128_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x200 11.--13. "PADCONFIG128_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x200 8. "PADCONFIG128_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x200 7. "PADCONFIG128_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x200 0.--3. "PADCONFIG128_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x204 "CFG0_PADCONFIG129,"
bitfld.long 0x204 31. "PADCONFIG129_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x204 30. "PADCONFIG129_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x204 29. "PADCONFIG129_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x204 28. "PADCONFIG129_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x204 27. "PADCONFIG129_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x204 26. "PADCONFIG129_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x204 25. "PADCONFIG129_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x204 24. "PADCONFIG129_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x204 23. "PADCONFIG129_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x204 22. "PADCONFIG129_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x204 21. "PADCONFIG129_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x204 19.--20. "PADCONFIG129_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x204 18. "PADCONFIG129_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x204 17. "PADCONFIG129_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x204 16. "PADCONFIG129_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x204 15. "PADCONFIG129_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x204 14. "PADCONFIG129_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x204 11.--13. "PADCONFIG129_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x204 8. "PADCONFIG129_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x204 7. "PADCONFIG129_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x204 0.--3. "PADCONFIG129_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x208 "CFG0_PADCONFIG130,"
bitfld.long 0x208 31. "PADCONFIG130_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x208 30. "PADCONFIG130_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x208 29. "PADCONFIG130_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x208 28. "PADCONFIG130_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x208 27. "PADCONFIG130_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x208 26. "PADCONFIG130_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x208 25. "PADCONFIG130_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x208 24. "PADCONFIG130_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x208 23. "PADCONFIG130_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x208 22. "PADCONFIG130_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x208 21. "PADCONFIG130_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x208 19.--20. "PADCONFIG130_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x208 18. "PADCONFIG130_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x208 17. "PADCONFIG130_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x208 16. "PADCONFIG130_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x208 15. "PADCONFIG130_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x208 14. "PADCONFIG130_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x208 11.--13. "PADCONFIG130_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x208 8. "PADCONFIG130_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x208 7. "PADCONFIG130_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x208 0.--3. "PADCONFIG130_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x20C "CFG0_PADCONFIG131,"
bitfld.long 0x20C 31. "PADCONFIG131_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x20C 30. "PADCONFIG131_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x20C 29. "PADCONFIG131_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x20C 28. "PADCONFIG131_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x20C 27. "PADCONFIG131_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x20C 26. "PADCONFIG131_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x20C 25. "PADCONFIG131_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x20C 24. "PADCONFIG131_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x20C 23. "PADCONFIG131_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x20C 22. "PADCONFIG131_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x20C 21. "PADCONFIG131_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x20C 19.--20. "PADCONFIG131_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x20C 18. "PADCONFIG131_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x20C 17. "PADCONFIG131_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x20C 16. "PADCONFIG131_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x20C 15. "PADCONFIG131_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x20C 14. "PADCONFIG131_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x20C 11.--13. "PADCONFIG131_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20C 8. "PADCONFIG131_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x20C 7. "PADCONFIG131_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x20C 0.--3. "PADCONFIG131_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x210 "CFG0_PADCONFIG132,"
bitfld.long 0x210 31. "PADCONFIG132_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x210 30. "PADCONFIG132_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x210 29. "PADCONFIG132_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x210 28. "PADCONFIG132_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x210 27. "PADCONFIG132_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x210 26. "PADCONFIG132_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x210 25. "PADCONFIG132_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x210 24. "PADCONFIG132_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x210 23. "PADCONFIG132_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x210 22. "PADCONFIG132_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x210 21. "PADCONFIG132_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x210 19.--20. "PADCONFIG132_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x210 18. "PADCONFIG132_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x210 17. "PADCONFIG132_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x210 16. "PADCONFIG132_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x210 15. "PADCONFIG132_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x210 14. "PADCONFIG132_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x210 11.--13. "PADCONFIG132_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x210 8. "PADCONFIG132_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x210 7. "PADCONFIG132_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x210 0.--3. "PADCONFIG132_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x214 "CFG0_PADCONFIG133,"
bitfld.long 0x214 31. "PADCONFIG133_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x214 30. "PADCONFIG133_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x214 29. "PADCONFIG133_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x214 28. "PADCONFIG133_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x214 27. "PADCONFIG133_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x214 26. "PADCONFIG133_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x214 25. "PADCONFIG133_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x214 24. "PADCONFIG133_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x214 23. "PADCONFIG133_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x214 22. "PADCONFIG133_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x214 21. "PADCONFIG133_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x214 19.--20. "PADCONFIG133_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x214 18. "PADCONFIG133_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x214 17. "PADCONFIG133_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x214 16. "PADCONFIG133_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x214 15. "PADCONFIG133_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x214 14. "PADCONFIG133_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x214 11.--13. "PADCONFIG133_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x214 8. "PADCONFIG133_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x214 7. "PADCONFIG133_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x214 0.--3. "PADCONFIG133_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x218 "CFG0_PADCONFIG134,"
bitfld.long 0x218 31. "PADCONFIG134_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x218 30. "PADCONFIG134_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x218 29. "PADCONFIG134_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x218 28. "PADCONFIG134_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x218 27. "PADCONFIG134_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x218 26. "PADCONFIG134_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x218 25. "PADCONFIG134_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x218 24. "PADCONFIG134_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x218 23. "PADCONFIG134_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x218 22. "PADCONFIG134_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x218 21. "PADCONFIG134_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x218 19.--20. "PADCONFIG134_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x218 18. "PADCONFIG134_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x218 17. "PADCONFIG134_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x218 16. "PADCONFIG134_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x218 15. "PADCONFIG134_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x218 14. "PADCONFIG134_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x218 11.--13. "PADCONFIG134_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x218 8. "PADCONFIG134_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x218 7. "PADCONFIG134_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x218 0.--3. "PADCONFIG134_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x21C "CFG0_PADCONFIG135,"
bitfld.long 0x21C 31. "PADCONFIG135_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x21C 30. "PADCONFIG135_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x21C 29. "PADCONFIG135_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x21C 28. "PADCONFIG135_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x21C 27. "PADCONFIG135_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x21C 26. "PADCONFIG135_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x21C 25. "PADCONFIG135_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x21C 24. "PADCONFIG135_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x21C 23. "PADCONFIG135_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x21C 22. "PADCONFIG135_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x21C 21. "PADCONFIG135_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x21C 19.--20. "PADCONFIG135_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x21C 18. "PADCONFIG135_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x21C 17. "PADCONFIG135_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x21C 16. "PADCONFIG135_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x21C 15. "PADCONFIG135_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x21C 14. "PADCONFIG135_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x21C 11.--13. "PADCONFIG135_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x21C 8. "PADCONFIG135_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x21C 7. "PADCONFIG135_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x21C 0.--3. "PADCONFIG135_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x220 "CFG0_PADCONFIG136,"
bitfld.long 0x220 31. "PADCONFIG136_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x220 30. "PADCONFIG136_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x220 29. "PADCONFIG136_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x220 28. "PADCONFIG136_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x220 27. "PADCONFIG136_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x220 26. "PADCONFIG136_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x220 25. "PADCONFIG136_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x220 24. "PADCONFIG136_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x220 23. "PADCONFIG136_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x220 22. "PADCONFIG136_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x220 21. "PADCONFIG136_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x220 19.--20. "PADCONFIG136_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x220 18. "PADCONFIG136_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x220 17. "PADCONFIG136_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x220 16. "PADCONFIG136_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x220 15. "PADCONFIG136_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x220 14. "PADCONFIG136_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x220 11.--13. "PADCONFIG136_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x220 8. "PADCONFIG136_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x220 7. "PADCONFIG136_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x220 0.--3. "PADCONFIG136_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x224 "CFG0_PADCONFIG137,"
bitfld.long 0x224 31. "PADCONFIG137_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x224 30. "PADCONFIG137_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x224 29. "PADCONFIG137_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x224 28. "PADCONFIG137_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x224 27. "PADCONFIG137_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x224 26. "PADCONFIG137_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x224 25. "PADCONFIG137_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x224 24. "PADCONFIG137_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x224 23. "PADCONFIG137_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x224 22. "PADCONFIG137_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x224 21. "PADCONFIG137_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x224 19.--20. "PADCONFIG137_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x224 18. "PADCONFIG137_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x224 17. "PADCONFIG137_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x224 16. "PADCONFIG137_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x224 15. "PADCONFIG137_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x224 14. "PADCONFIG137_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x224 11.--13. "PADCONFIG137_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x224 8. "PADCONFIG137_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x224 7. "PADCONFIG137_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x224 0.--3. "PADCONFIG137_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x228 "CFG0_PADCONFIG138,"
bitfld.long 0x228 31. "PADCONFIG138_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x228 30. "PADCONFIG138_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x228 29. "PADCONFIG138_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x228 28. "PADCONFIG138_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x228 27. "PADCONFIG138_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x228 26. "PADCONFIG138_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x228 25. "PADCONFIG138_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x228 24. "PADCONFIG138_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x228 23. "PADCONFIG138_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x228 22. "PADCONFIG138_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x228 21. "PADCONFIG138_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x228 19.--20. "PADCONFIG138_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x228 18. "PADCONFIG138_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x228 17. "PADCONFIG138_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x228 16. "PADCONFIG138_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x228 15. "PADCONFIG138_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x228 14. "PADCONFIG138_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x228 11.--13. "PADCONFIG138_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x228 8. "PADCONFIG138_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x228 7. "PADCONFIG138_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x228 0.--3. "PADCONFIG138_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x22C "CFG0_PADCONFIG139,"
bitfld.long 0x22C 31. "PADCONFIG139_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x22C 30. "PADCONFIG139_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x22C 29. "PADCONFIG139_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x22C 28. "PADCONFIG139_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x22C 27. "PADCONFIG139_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x22C 26. "PADCONFIG139_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x22C 25. "PADCONFIG139_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x22C 24. "PADCONFIG139_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x22C 23. "PADCONFIG139_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x22C 22. "PADCONFIG139_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x22C 21. "PADCONFIG139_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x22C 19.--20. "PADCONFIG139_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x22C 18. "PADCONFIG139_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x22C 17. "PADCONFIG139_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x22C 16. "PADCONFIG139_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x22C 15. "PADCONFIG139_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x22C 14. "PADCONFIG139_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x22C 11.--13. "PADCONFIG139_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x22C 8. "PADCONFIG139_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x22C 7. "PADCONFIG139_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x22C 0.--3. "PADCONFIG139_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x230 "CFG0_PADCONFIG140,"
bitfld.long 0x230 31. "PADCONFIG140_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x230 30. "PADCONFIG140_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x230 29. "PADCONFIG140_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x230 28. "PADCONFIG140_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x230 27. "PADCONFIG140_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x230 26. "PADCONFIG140_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x230 25. "PADCONFIG140_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x230 24. "PADCONFIG140_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x230 23. "PADCONFIG140_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x230 22. "PADCONFIG140_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x230 21. "PADCONFIG140_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x230 19.--20. "PADCONFIG140_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x230 18. "PADCONFIG140_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x230 17. "PADCONFIG140_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x230 16. "PADCONFIG140_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x230 15. "PADCONFIG140_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x230 14. "PADCONFIG140_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x230 11.--13. "PADCONFIG140_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x230 8. "PADCONFIG140_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x230 7. "PADCONFIG140_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x230 0.--3. "PADCONFIG140_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x234 "CFG0_PADCONFIG141,"
bitfld.long 0x234 31. "PADCONFIG141_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x234 30. "PADCONFIG141_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x234 29. "PADCONFIG141_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x234 28. "PADCONFIG141_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x234 27. "PADCONFIG141_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x234 26. "PADCONFIG141_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x234 25. "PADCONFIG141_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x234 24. "PADCONFIG141_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x234 23. "PADCONFIG141_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x234 22. "PADCONFIG141_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x234 21. "PADCONFIG141_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x234 19.--20. "PADCONFIG141_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x234 18. "PADCONFIG141_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x234 17. "PADCONFIG141_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x234 16. "PADCONFIG141_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x234 15. "PADCONFIG141_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x234 14. "PADCONFIG141_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x234 11.--13. "PADCONFIG141_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x234 8. "PADCONFIG141_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x234 7. "PADCONFIG141_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x234 0.--3. "PADCONFIG141_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x238 "CFG0_PADCONFIG142,"
bitfld.long 0x238 31. "PADCONFIG142_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x238 30. "PADCONFIG142_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x238 29. "PADCONFIG142_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x238 28. "PADCONFIG142_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x238 27. "PADCONFIG142_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x238 26. "PADCONFIG142_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x238 25. "PADCONFIG142_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x238 24. "PADCONFIG142_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x238 23. "PADCONFIG142_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x238 22. "PADCONFIG142_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x238 21. "PADCONFIG142_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x238 19.--20. "PADCONFIG142_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x238 18. "PADCONFIG142_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x238 17. "PADCONFIG142_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x238 16. "PADCONFIG142_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x238 15. "PADCONFIG142_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x238 14. "PADCONFIG142_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x238 11.--13. "PADCONFIG142_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x238 8. "PADCONFIG142_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x238 7. "PADCONFIG142_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x238 0.--3. "PADCONFIG142_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x23C "CFG0_PADCONFIG143,"
bitfld.long 0x23C 31. "PADCONFIG143_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x23C 30. "PADCONFIG143_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x23C 29. "PADCONFIG143_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x23C 28. "PADCONFIG143_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x23C 27. "PADCONFIG143_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x23C 26. "PADCONFIG143_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x23C 25. "PADCONFIG143_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x23C 24. "PADCONFIG143_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x23C 23. "PADCONFIG143_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x23C 22. "PADCONFIG143_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x23C 21. "PADCONFIG143_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x23C 19.--20. "PADCONFIG143_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x23C 18. "PADCONFIG143_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x23C 17. "PADCONFIG143_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x23C 16. "PADCONFIG143_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x23C 15. "PADCONFIG143_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x23C 14. "PADCONFIG143_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x23C 11.--13. "PADCONFIG143_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x23C 8. "PADCONFIG143_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x23C 7. "PADCONFIG143_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x23C 0.--3. "PADCONFIG143_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x240 "CFG0_PADCONFIG144,"
bitfld.long 0x240 31. "PADCONFIG144_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x240 30. "PADCONFIG144_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x240 29. "PADCONFIG144_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x240 28. "PADCONFIG144_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x240 27. "PADCONFIG144_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x240 26. "PADCONFIG144_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x240 25. "PADCONFIG144_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x240 24. "PADCONFIG144_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x240 23. "PADCONFIG144_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x240 22. "PADCONFIG144_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x240 21. "PADCONFIG144_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x240 19.--20. "PADCONFIG144_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x240 18. "PADCONFIG144_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x240 17. "PADCONFIG144_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x240 16. "PADCONFIG144_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x240 15. "PADCONFIG144_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x240 14. "PADCONFIG144_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x240 11.--13. "PADCONFIG144_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x240 8. "PADCONFIG144_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x240 7. "PADCONFIG144_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x240 0.--3. "PADCONFIG144_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x244 "CFG0_PADCONFIG145,"
bitfld.long 0x244 31. "PADCONFIG145_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x244 30. "PADCONFIG145_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x244 29. "PADCONFIG145_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x244 28. "PADCONFIG145_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x244 27. "PADCONFIG145_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x244 26. "PADCONFIG145_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x244 25. "PADCONFIG145_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x244 24. "PADCONFIG145_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x244 23. "PADCONFIG145_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x244 22. "PADCONFIG145_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x244 21. "PADCONFIG145_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x244 19.--20. "PADCONFIG145_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x244 18. "PADCONFIG145_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x244 17. "PADCONFIG145_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x244 16. "PADCONFIG145_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x244 15. "PADCONFIG145_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x244 14. "PADCONFIG145_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x244 11.--13. "PADCONFIG145_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x244 8. "PADCONFIG145_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x244 7. "PADCONFIG145_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x244 0.--3. "PADCONFIG145_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x248 "CFG0_PADCONFIG146,"
bitfld.long 0x248 31. "PADCONFIG146_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x248 30. "PADCONFIG146_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x248 29. "PADCONFIG146_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x248 28. "PADCONFIG146_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x248 27. "PADCONFIG146_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x248 26. "PADCONFIG146_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x248 25. "PADCONFIG146_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x248 24. "PADCONFIG146_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x248 23. "PADCONFIG146_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x248 22. "PADCONFIG146_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x248 21. "PADCONFIG146_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x248 19.--20. "PADCONFIG146_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x248 18. "PADCONFIG146_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x248 17. "PADCONFIG146_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x248 16. "PADCONFIG146_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x248 15. "PADCONFIG146_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x248 14. "PADCONFIG146_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x248 11.--13. "PADCONFIG146_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x248 8. "PADCONFIG146_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x248 7. "PADCONFIG146_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x248 0.--3. "PADCONFIG146_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x24C "CFG0_PADCONFIG147,"
bitfld.long 0x24C 31. "PADCONFIG147_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x24C 30. "PADCONFIG147_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x24C 29. "PADCONFIG147_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x24C 28. "PADCONFIG147_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x24C 27. "PADCONFIG147_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x24C 26. "PADCONFIG147_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x24C 25. "PADCONFIG147_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x24C 24. "PADCONFIG147_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x24C 23. "PADCONFIG147_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x24C 22. "PADCONFIG147_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x24C 21. "PADCONFIG147_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x24C 19.--20. "PADCONFIG147_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x24C 18. "PADCONFIG147_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x24C 17. "PADCONFIG147_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x24C 16. "PADCONFIG147_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x24C 15. "PADCONFIG147_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x24C 14. "PADCONFIG147_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x24C 11.--13. "PADCONFIG147_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x24C 8. "PADCONFIG147_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x24C 7. "PADCONFIG147_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x24C 0.--3. "PADCONFIG147_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x250 "CFG0_PADCONFIG148,"
bitfld.long 0x250 31. "PADCONFIG148_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x250 30. "PADCONFIG148_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x250 29. "PADCONFIG148_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x250 28. "PADCONFIG148_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x250 27. "PADCONFIG148_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x250 26. "PADCONFIG148_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x250 25. "PADCONFIG148_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x250 24. "PADCONFIG148_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x250 23. "PADCONFIG148_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x250 22. "PADCONFIG148_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x250 21. "PADCONFIG148_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x250 19.--20. "PADCONFIG148_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x250 18. "PADCONFIG148_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x250 17. "PADCONFIG148_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x250 16. "PADCONFIG148_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x250 15. "PADCONFIG148_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x250 14. "PADCONFIG148_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x250 11.--13. "PADCONFIG148_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x250 8. "PADCONFIG148_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x250 7. "PADCONFIG148_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x250 0.--3. "PADCONFIG148_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x254 "CFG0_PADCONFIG149,"
bitfld.long 0x254 31. "PADCONFIG149_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x254 30. "PADCONFIG149_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x254 29. "PADCONFIG149_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x254 28. "PADCONFIG149_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x254 27. "PADCONFIG149_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x254 26. "PADCONFIG149_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x254 25. "PADCONFIG149_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x254 24. "PADCONFIG149_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x254 23. "PADCONFIG149_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x254 22. "PADCONFIG149_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x254 21. "PADCONFIG149_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x254 19.--20. "PADCONFIG149_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x254 18. "PADCONFIG149_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x254 17. "PADCONFIG149_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x254 16. "PADCONFIG149_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x254 15. "PADCONFIG149_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x254 14. "PADCONFIG149_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x254 11.--13. "PADCONFIG149_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x254 8. "PADCONFIG149_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x254 7. "PADCONFIG149_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x254 0.--3. "PADCONFIG149_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x258 "CFG0_PADCONFIG150,"
bitfld.long 0x258 31. "PADCONFIG150_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x258 30. "PADCONFIG150_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x258 29. "PADCONFIG150_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x258 28. "PADCONFIG150_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x258 27. "PADCONFIG150_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x258 26. "PADCONFIG150_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x258 25. "PADCONFIG150_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x258 24. "PADCONFIG150_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x258 23. "PADCONFIG150_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x258 22. "PADCONFIG150_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x258 21. "PADCONFIG150_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x258 19.--20. "PADCONFIG150_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x258 18. "PADCONFIG150_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x258 17. "PADCONFIG150_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x258 16. "PADCONFIG150_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x258 15. "PADCONFIG150_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x258 14. "PADCONFIG150_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x258 11.--13. "PADCONFIG150_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x258 8. "PADCONFIG150_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x258 7. "PADCONFIG150_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x258 0.--3. "PADCONFIG150_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x25C "CFG0_PADCONFIG151,"
bitfld.long 0x25C 31. "PADCONFIG151_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x25C 30. "PADCONFIG151_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x25C 29. "PADCONFIG151_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x25C 28. "PADCONFIG151_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x25C 27. "PADCONFIG151_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x25C 26. "PADCONFIG151_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x25C 25. "PADCONFIG151_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x25C 24. "PADCONFIG151_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x25C 23. "PADCONFIG151_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x25C 22. "PADCONFIG151_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x25C 21. "PADCONFIG151_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x25C 19.--20. "PADCONFIG151_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x25C 18. "PADCONFIG151_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x25C 17. "PADCONFIG151_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x25C 16. "PADCONFIG151_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x25C 15. "PADCONFIG151_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x25C 14. "PADCONFIG151_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x25C 11.--13. "PADCONFIG151_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x25C 8. "PADCONFIG151_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x25C 7. "PADCONFIG151_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x25C 0.--3. "PADCONFIG151_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x260 "CFG0_PADCONFIG152,"
bitfld.long 0x260 31. "PADCONFIG152_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x260 30. "PADCONFIG152_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x260 29. "PADCONFIG152_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x260 28. "PADCONFIG152_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x260 27. "PADCONFIG152_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x260 26. "PADCONFIG152_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x260 25. "PADCONFIG152_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x260 24. "PADCONFIG152_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x260 23. "PADCONFIG152_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x260 22. "PADCONFIG152_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x260 21. "PADCONFIG152_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x260 19.--20. "PADCONFIG152_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x260 18. "PADCONFIG152_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x260 17. "PADCONFIG152_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x260 16. "PADCONFIG152_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x260 15. "PADCONFIG152_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x260 14. "PADCONFIG152_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x260 11.--13. "PADCONFIG152_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x260 8. "PADCONFIG152_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x260 7. "PADCONFIG152_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x260 0.--3. "PADCONFIG152_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x264 "CFG0_PADCONFIG153,"
bitfld.long 0x264 31. "PADCONFIG153_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x264 30. "PADCONFIG153_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x264 29. "PADCONFIG153_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x264 28. "PADCONFIG153_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x264 27. "PADCONFIG153_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x264 26. "PADCONFIG153_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x264 25. "PADCONFIG153_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x264 24. "PADCONFIG153_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x264 23. "PADCONFIG153_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x264 22. "PADCONFIG153_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x264 21. "PADCONFIG153_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x264 19.--20. "PADCONFIG153_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x264 18. "PADCONFIG153_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x264 17. "PADCONFIG153_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x264 16. "PADCONFIG153_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x264 15. "PADCONFIG153_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x264 14. "PADCONFIG153_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x264 11.--13. "PADCONFIG153_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x264 8. "PADCONFIG153_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x264 7. "PADCONFIG153_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x264 0.--3. "PADCONFIG153_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x268 "CFG0_PADCONFIG154,"
bitfld.long 0x268 31. "PADCONFIG154_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x268 30. "PADCONFIG154_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x268 29. "PADCONFIG154_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x268 28. "PADCONFIG154_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x268 27. "PADCONFIG154_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x268 26. "PADCONFIG154_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x268 25. "PADCONFIG154_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x268 24. "PADCONFIG154_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x268 23. "PADCONFIG154_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x268 22. "PADCONFIG154_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x268 21. "PADCONFIG154_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x268 19.--20. "PADCONFIG154_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x268 18. "PADCONFIG154_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x268 17. "PADCONFIG154_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x268 16. "PADCONFIG154_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x268 15. "PADCONFIG154_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x268 14. "PADCONFIG154_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x268 11.--13. "PADCONFIG154_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x268 8. "PADCONFIG154_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x268 7. "PADCONFIG154_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x268 0.--3. "PADCONFIG154_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x26C "CFG0_PADCONFIG155,"
bitfld.long 0x26C 31. "PADCONFIG155_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x26C 30. "PADCONFIG155_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x26C 29. "PADCONFIG155_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x26C 28. "PADCONFIG155_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x26C 27. "PADCONFIG155_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x26C 26. "PADCONFIG155_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x26C 25. "PADCONFIG155_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x26C 24. "PADCONFIG155_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x26C 23. "PADCONFIG155_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x26C 22. "PADCONFIG155_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x26C 21. "PADCONFIG155_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x26C 19.--20. "PADCONFIG155_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x26C 18. "PADCONFIG155_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x26C 17. "PADCONFIG155_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x26C 16. "PADCONFIG155_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x26C 15. "PADCONFIG155_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x26C 14. "PADCONFIG155_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x26C 11.--13. "PADCONFIG155_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x26C 8. "PADCONFIG155_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x26C 7. "PADCONFIG155_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x26C 0.--3. "PADCONFIG155_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x270 "CFG0_PADCONFIG156,"
bitfld.long 0x270 31. "PADCONFIG156_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x270 30. "PADCONFIG156_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x270 29. "PADCONFIG156_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x270 28. "PADCONFIG156_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x270 27. "PADCONFIG156_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x270 26. "PADCONFIG156_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x270 25. "PADCONFIG156_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x270 24. "PADCONFIG156_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x270 23. "PADCONFIG156_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x270 22. "PADCONFIG156_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x270 21. "PADCONFIG156_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x270 19.--20. "PADCONFIG156_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x270 18. "PADCONFIG156_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x270 17. "PADCONFIG156_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x270 16. "PADCONFIG156_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x270 15. "PADCONFIG156_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x270 14. "PADCONFIG156_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x270 11.--13. "PADCONFIG156_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x270 8. "PADCONFIG156_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x270 7. "PADCONFIG156_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x270 0.--3. "PADCONFIG156_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x274 "CFG0_PADCONFIG157,"
bitfld.long 0x274 31. "PADCONFIG157_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x274 30. "PADCONFIG157_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x274 29. "PADCONFIG157_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x274 28. "PADCONFIG157_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x274 27. "PADCONFIG157_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x274 26. "PADCONFIG157_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x274 25. "PADCONFIG157_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x274 24. "PADCONFIG157_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x274 23. "PADCONFIG157_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x274 22. "PADCONFIG157_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x274 21. "PADCONFIG157_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x274 19.--20. "PADCONFIG157_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x274 18. "PADCONFIG157_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x274 17. "PADCONFIG157_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x274 16. "PADCONFIG157_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x274 15. "PADCONFIG157_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x274 14. "PADCONFIG157_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x274 11.--13. "PADCONFIG157_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x274 8. "PADCONFIG157_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x274 7. "PADCONFIG157_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x274 0.--3. "PADCONFIG157_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x278 "CFG0_PADCONFIG158,"
bitfld.long 0x278 31. "PADCONFIG158_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x278 30. "PADCONFIG158_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x278 29. "PADCONFIG158_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x278 28. "PADCONFIG158_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x278 27. "PADCONFIG158_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x278 26. "PADCONFIG158_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x278 25. "PADCONFIG158_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x278 24. "PADCONFIG158_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x278 23. "PADCONFIG158_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x278 22. "PADCONFIG158_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x278 21. "PADCONFIG158_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x278 19.--20. "PADCONFIG158_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x278 18. "PADCONFIG158_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x278 17. "PADCONFIG158_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x278 16. "PADCONFIG158_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x278 15. "PADCONFIG158_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x278 14. "PADCONFIG158_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x278 11.--13. "PADCONFIG158_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x278 8. "PADCONFIG158_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x278 7. "PADCONFIG158_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x278 0.--3. "PADCONFIG158_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x27C "CFG0_PADCONFIG159,"
bitfld.long 0x27C 31. "PADCONFIG159_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x27C 30. "PADCONFIG159_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x27C 29. "PADCONFIG159_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x27C 28. "PADCONFIG159_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x27C 27. "PADCONFIG159_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x27C 26. "PADCONFIG159_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x27C 25. "PADCONFIG159_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x27C 24. "PADCONFIG159_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x27C 23. "PADCONFIG159_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x27C 22. "PADCONFIG159_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x27C 21. "PADCONFIG159_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x27C 19.--20. "PADCONFIG159_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x27C 18. "PADCONFIG159_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x27C 17. "PADCONFIG159_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x27C 16. "PADCONFIG159_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x27C 15. "PADCONFIG159_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x27C 14. "PADCONFIG159_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x27C 11.--13. "PADCONFIG159_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x27C 8. "PADCONFIG159_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x27C 7. "PADCONFIG159_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x27C 0.--3. "PADCONFIG159_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x280 "CFG0_PADCONFIG160,"
bitfld.long 0x280 31. "PADCONFIG160_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x280 30. "PADCONFIG160_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x280 29. "PADCONFIG160_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x280 28. "PADCONFIG160_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x280 27. "PADCONFIG160_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x280 26. "PADCONFIG160_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x280 25. "PADCONFIG160_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x280 24. "PADCONFIG160_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x280 23. "PADCONFIG160_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x280 22. "PADCONFIG160_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x280 21. "PADCONFIG160_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x280 19.--20. "PADCONFIG160_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x280 18. "PADCONFIG160_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x280 17. "PADCONFIG160_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x280 16. "PADCONFIG160_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x280 15. "PADCONFIG160_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x280 14. "PADCONFIG160_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x280 11.--13. "PADCONFIG160_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x280 8. "PADCONFIG160_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x280 7. "PADCONFIG160_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x280 0.--3. "PADCONFIG160_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x284 "CFG0_PADCONFIG161,"
bitfld.long 0x284 31. "PADCONFIG161_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x284 30. "PADCONFIG161_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x284 29. "PADCONFIG161_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x284 28. "PADCONFIG161_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x284 27. "PADCONFIG161_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x284 26. "PADCONFIG161_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x284 25. "PADCONFIG161_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x284 24. "PADCONFIG161_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x284 23. "PADCONFIG161_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x284 22. "PADCONFIG161_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x284 21. "PADCONFIG161_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x284 19.--20. "PADCONFIG161_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x284 18. "PADCONFIG161_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x284 17. "PADCONFIG161_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x284 16. "PADCONFIG161_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x284 15. "PADCONFIG161_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x284 14. "PADCONFIG161_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x284 11.--13. "PADCONFIG161_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x284 8. "PADCONFIG161_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x284 7. "PADCONFIG161_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x284 0.--3. "PADCONFIG161_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x288 "CFG0_PADCONFIG162,"
bitfld.long 0x288 31. "PADCONFIG162_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x288 30. "PADCONFIG162_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x288 29. "PADCONFIG162_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x288 28. "PADCONFIG162_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x288 27. "PADCONFIG162_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x288 26. "PADCONFIG162_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x288 25. "PADCONFIG162_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x288 24. "PADCONFIG162_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x288 23. "PADCONFIG162_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x288 22. "PADCONFIG162_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x288 21. "PADCONFIG162_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x288 19.--20. "PADCONFIG162_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x288 18. "PADCONFIG162_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x288 17. "PADCONFIG162_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x288 16. "PADCONFIG162_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x288 15. "PADCONFIG162_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x288 14. "PADCONFIG162_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x288 11.--13. "PADCONFIG162_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x288 8. "PADCONFIG162_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x288 7. "PADCONFIG162_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x288 0.--3. "PADCONFIG162_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x28C "CFG0_PADCONFIG163,"
bitfld.long 0x28C 31. "PADCONFIG163_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x28C 30. "PADCONFIG163_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x28C 29. "PADCONFIG163_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x28C 28. "PADCONFIG163_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x28C 27. "PADCONFIG163_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x28C 26. "PADCONFIG163_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x28C 25. "PADCONFIG163_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x28C 24. "PADCONFIG163_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x28C 23. "PADCONFIG163_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x28C 22. "PADCONFIG163_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x28C 21. "PADCONFIG163_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x28C 19.--20. "PADCONFIG163_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x28C 18. "PADCONFIG163_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x28C 17. "PADCONFIG163_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x28C 16. "PADCONFIG163_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x28C 15. "PADCONFIG163_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x28C 14. "PADCONFIG163_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x28C 11.--13. "PADCONFIG163_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28C 8. "PADCONFIG163_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x28C 7. "PADCONFIG163_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x28C 0.--3. "PADCONFIG163_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x290 "CFG0_PADCONFIG164,"
bitfld.long 0x290 31. "PADCONFIG164_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x290 30. "PADCONFIG164_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x290 29. "PADCONFIG164_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x290 28. "PADCONFIG164_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x290 27. "PADCONFIG164_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x290 26. "PADCONFIG164_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x290 25. "PADCONFIG164_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x290 24. "PADCONFIG164_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x290 23. "PADCONFIG164_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x290 22. "PADCONFIG164_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x290 21. "PADCONFIG164_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x290 19.--20. "PADCONFIG164_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x290 18. "PADCONFIG164_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x290 17. "PADCONFIG164_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x290 16. "PADCONFIG164_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x290 15. "PADCONFIG164_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x290 14. "PADCONFIG164_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x290 11.--13. "PADCONFIG164_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x290 8. "PADCONFIG164_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x290 7. "PADCONFIG164_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x290 0.--3. "PADCONFIG164_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x294 "CFG0_PADCONFIG165,"
bitfld.long 0x294 31. "PADCONFIG165_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x294 30. "PADCONFIG165_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x294 29. "PADCONFIG165_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x294 28. "PADCONFIG165_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x294 27. "PADCONFIG165_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x294 26. "PADCONFIG165_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x294 25. "PADCONFIG165_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x294 24. "PADCONFIG165_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x294 23. "PADCONFIG165_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x294 22. "PADCONFIG165_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x294 21. "PADCONFIG165_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x294 19.--20. "PADCONFIG165_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x294 18. "PADCONFIG165_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x294 17. "PADCONFIG165_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x294 16. "PADCONFIG165_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x294 15. "PADCONFIG165_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x294 14. "PADCONFIG165_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x294 11.--13. "PADCONFIG165_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x294 8. "PADCONFIG165_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x294 7. "PADCONFIG165_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x294 0.--3. "PADCONFIG165_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x298 "CFG0_PADCONFIG166,"
bitfld.long 0x298 31. "PADCONFIG166_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x298 30. "PADCONFIG166_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x298 29. "PADCONFIG166_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x298 28. "PADCONFIG166_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x298 27. "PADCONFIG166_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x298 26. "PADCONFIG166_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x298 25. "PADCONFIG166_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x298 24. "PADCONFIG166_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x298 23. "PADCONFIG166_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x298 22. "PADCONFIG166_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x298 21. "PADCONFIG166_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x298 19.--20. "PADCONFIG166_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x298 18. "PADCONFIG166_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x298 17. "PADCONFIG166_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x298 16. "PADCONFIG166_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x298 15. "PADCONFIG166_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x298 14. "PADCONFIG166_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x298 11.--13. "PADCONFIG166_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x298 8. "PADCONFIG166_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x298 7. "PADCONFIG166_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x298 0.--3. "PADCONFIG166_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x29C "CFG0_PADCONFIG167,"
bitfld.long 0x29C 31. "PADCONFIG167_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x29C 30. "PADCONFIG167_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x29C 29. "PADCONFIG167_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x29C 28. "PADCONFIG167_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x29C 27. "PADCONFIG167_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x29C 26. "PADCONFIG167_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x29C 25. "PADCONFIG167_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x29C 24. "PADCONFIG167_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x29C 23. "PADCONFIG167_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x29C 22. "PADCONFIG167_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x29C 21. "PADCONFIG167_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x29C 19.--20. "PADCONFIG167_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x29C 18. "PADCONFIG167_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x29C 17. "PADCONFIG167_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x29C 16. "PADCONFIG167_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x29C 15. "PADCONFIG167_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x29C 14. "PADCONFIG167_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x29C 11.--13. "PADCONFIG167_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x29C 8. "PADCONFIG167_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x29C 7. "PADCONFIG167_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x29C 0.--3. "PADCONFIG167_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2A0 "CFG0_PADCONFIG168,"
bitfld.long 0x2A0 31. "PADCONFIG168_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x2A0 30. "PADCONFIG168_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x2A0 29. "PADCONFIG168_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x2A0 28. "PADCONFIG168_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x2A0 27. "PADCONFIG168_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x2A0 26. "PADCONFIG168_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2A0 25. "PADCONFIG168_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x2A0 24. "PADCONFIG168_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x2A0 23. "PADCONFIG168_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x2A0 22. "PADCONFIG168_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x2A0 21. "PADCONFIG168_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x2A0 19.--20. "PADCONFIG168_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x2A0 18. "PADCONFIG168_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x2A0 17. "PADCONFIG168_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x2A0 16. "PADCONFIG168_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x2A0 15. "PADCONFIG168_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x2A0 14. "PADCONFIG168_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x2A0 11.--13. "PADCONFIG168_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2A0 8. "PADCONFIG168_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x2A0 7. "PADCONFIG168_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x2A0 0.--3. "PADCONFIG168_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2A4 "CFG0_PADCONFIG169,"
bitfld.long 0x2A4 31. "PADCONFIG169_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x2A4 30. "PADCONFIG169_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x2A4 29. "PADCONFIG169_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x2A4 28. "PADCONFIG169_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x2A4 27. "PADCONFIG169_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x2A4 26. "PADCONFIG169_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2A4 25. "PADCONFIG169_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x2A4 24. "PADCONFIG169_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x2A4 23. "PADCONFIG169_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x2A4 22. "PADCONFIG169_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x2A4 21. "PADCONFIG169_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x2A4 19.--20. "PADCONFIG169_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x2A4 18. "PADCONFIG169_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x2A4 17. "PADCONFIG169_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x2A4 16. "PADCONFIG169_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x2A4 15. "PADCONFIG169_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x2A4 14. "PADCONFIG169_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x2A4 11.--13. "PADCONFIG169_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x2A4 8. "PADCONFIG169_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x2A4 7. "PADCONFIG169_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x2A4 0.--3. "PADCONFIG169_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2A8 "CFG0_PADCONFIG170,"
bitfld.long 0x2A8 31. "PADCONFIG170_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x2A8 30. "PADCONFIG170_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x2A8 29. "PADCONFIG170_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x2A8 28. "PADCONFIG170_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x2A8 27. "PADCONFIG170_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x2A8 26. "PADCONFIG170_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2A8 25. "PADCONFIG170_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x2A8 24. "PADCONFIG170_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x2A8 23. "PADCONFIG170_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x2A8 22. "PADCONFIG170_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x2A8 21. "PADCONFIG170_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x2A8 19.--20. "PADCONFIG170_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x2A8 18. "PADCONFIG170_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x2A8 17. "PADCONFIG170_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x2A8 16. "PADCONFIG170_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x2A8 15. "PADCONFIG170_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x2A8 14. "PADCONFIG170_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x2A8 11.--13. "PADCONFIG170_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2A8 8. "PADCONFIG170_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x2A8 7. "PADCONFIG170_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x2A8 0.--3. "PADCONFIG170_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
group.long 0x5008++0x07
line.long 0x00 "CFG0_LOCK1_KICK0,"
line.long 0x04 "CFG0_LOCK1_KICK1,"
rgroup.long 0x5100++0x17
line.long 0x00 "CFG0_CLAIMREG_P1_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P1_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P1_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P1_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P1_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P1_R5_READONLY,"
group.long 0x6000++0x2AB
line.long 0x00 "CFG0_PADCONFIG0_PROXY,"
bitfld.long 0x00 31. "PADCONFIG0_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x00 30. "PADCONFIG0_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x00 29. "PADCONFIG0_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x00 28. "PADCONFIG0_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x00 27. "PADCONFIG0_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x00 26. "PADCONFIG0_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x00 25. "PADCONFIG0_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x00 24. "PADCONFIG0_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x00 23. "PADCONFIG0_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x00 22. "PADCONFIG0_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x00 21. "PADCONFIG0_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x00 19.--20. "PADCONFIG0_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "PADCONFIG0_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x00 17. "PADCONFIG0_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x00 16. "PADCONFIG0_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x00 15. "PADCONFIG0_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x00 14. "PADCONFIG0_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x00 11.--13. "PADCONFIG0_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8. "PADCONFIG0_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x00 7. "PADCONFIG0_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--3. "PADCONFIG0_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x04 "CFG0_PADCONFIG1_PROXY,"
bitfld.long 0x04 31. "PADCONFIG1_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x04 30. "PADCONFIG1_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x04 29. "PADCONFIG1_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x04 28. "PADCONFIG1_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x04 27. "PADCONFIG1_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x04 26. "PADCONFIG1_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x04 25. "PADCONFIG1_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x04 24. "PADCONFIG1_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x04 23. "PADCONFIG1_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x04 22. "PADCONFIG1_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x04 21. "PADCONFIG1_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x04 19.--20. "PADCONFIG1_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x04 18. "PADCONFIG1_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x04 17. "PADCONFIG1_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x04 16. "PADCONFIG1_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x04 15. "PADCONFIG1_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x04 14. "PADCONFIG1_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x04 11.--13. "PADCONFIG1_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 8. "PADCONFIG1_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x04 7. "PADCONFIG1_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x04 0.--3. "PADCONFIG1_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x08 "CFG0_PADCONFIG2_PROXY,"
bitfld.long 0x08 31. "PADCONFIG2_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x08 30. "PADCONFIG2_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x08 29. "PADCONFIG2_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x08 28. "PADCONFIG2_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x08 27. "PADCONFIG2_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x08 26. "PADCONFIG2_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x08 25. "PADCONFIG2_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x08 24. "PADCONFIG2_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x08 23. "PADCONFIG2_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x08 22. "PADCONFIG2_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x08 21. "PADCONFIG2_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x08 19.--20. "PADCONFIG2_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x08 18. "PADCONFIG2_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x08 17. "PADCONFIG2_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x08 16. "PADCONFIG2_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x08 15. "PADCONFIG2_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x08 14. "PADCONFIG2_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x08 11.--13. "PADCONFIG2_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 8. "PADCONFIG2_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x08 7. "PADCONFIG2_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x08 0.--3. "PADCONFIG2_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x0C "CFG0_PADCONFIG3_PROXY,"
bitfld.long 0x0C 31. "PADCONFIG3_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x0C 30. "PADCONFIG3_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x0C 29. "PADCONFIG3_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x0C 28. "PADCONFIG3_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x0C 27. "PADCONFIG3_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x0C 26. "PADCONFIG3_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x0C 25. "PADCONFIG3_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x0C 24. "PADCONFIG3_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x0C 23. "PADCONFIG3_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x0C 22. "PADCONFIG3_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x0C 21. "PADCONFIG3_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x0C 19.--20. "PADCONFIG3_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x0C 18. "PADCONFIG3_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x0C 17. "PADCONFIG3_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x0C 16. "PADCONFIG3_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x0C 15. "PADCONFIG3_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x0C 14. "PADCONFIG3_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x0C 11.--13. "PADCONFIG3_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 8. "PADCONFIG3_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x0C 7. "PADCONFIG3_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x0C 0.--3. "PADCONFIG3_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x10 "CFG0_PADCONFIG4_PROXY,"
bitfld.long 0x10 31. "PADCONFIG4_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x10 30. "PADCONFIG4_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x10 29. "PADCONFIG4_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x10 28. "PADCONFIG4_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x10 27. "PADCONFIG4_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x10 26. "PADCONFIG4_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x10 25. "PADCONFIG4_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x10 24. "PADCONFIG4_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x10 23. "PADCONFIG4_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x10 22. "PADCONFIG4_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x10 21. "PADCONFIG4_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x10 15. "PADCONFIG4_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x10 14. "PADCONFIG4_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 8. "PADCONFIG4_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x10 7. "PADCONFIG4_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x10 0.--3. "PADCONFIG4_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x14 "CFG0_PADCONFIG5_PROXY,"
bitfld.long 0x14 31. "PADCONFIG5_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x14 30. "PADCONFIG5_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x14 29. "PADCONFIG5_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x14 28. "PADCONFIG5_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x14 27. "PADCONFIG5_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x14 26. "PADCONFIG5_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x14 25. "PADCONFIG5_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x14 24. "PADCONFIG5_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x14 23. "PADCONFIG5_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x14 22. "PADCONFIG5_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x14 21. "PADCONFIG5_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x14 15. "PADCONFIG5_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x14 14. "PADCONFIG5_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 8. "PADCONFIG5_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x14 7. "PADCONFIG5_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x14 0.--3. "PADCONFIG5_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x18 "CFG0_PADCONFIG6_PROXY,"
bitfld.long 0x18 31. "PADCONFIG6_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x18 30. "PADCONFIG6_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x18 29. "PADCONFIG6_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x18 28. "PADCONFIG6_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x18 27. "PADCONFIG6_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x18 26. "PADCONFIG6_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x18 25. "PADCONFIG6_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x18 24. "PADCONFIG6_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x18 23. "PADCONFIG6_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x18 22. "PADCONFIG6_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x18 21. "PADCONFIG6_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x18 15. "PADCONFIG6_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x18 14. "PADCONFIG6_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 8. "PADCONFIG6_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x18 7. "PADCONFIG6_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x18 0.--3. "PADCONFIG6_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C "CFG0_PADCONFIG7_PROXY,"
bitfld.long 0x1C 31. "PADCONFIG7_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C 30. "PADCONFIG7_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C 29. "PADCONFIG7_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x1C 28. "PADCONFIG7_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x1C 27. "PADCONFIG7_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x1C 26. "PADCONFIG7_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x1C 25. "PADCONFIG7_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x1C 24. "PADCONFIG7_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x1C 23. "PADCONFIG7_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x1C 22. "PADCONFIG7_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C 15. "PADCONFIG7_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x1C 14. "PADCONFIG7_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1C 8. "PADCONFIG7_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x1C 7. "PADCONFIG7_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x1C 0.--3. "PADCONFIG7_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x20 "CFG0_PADCONFIG8_PROXY,"
bitfld.long 0x20 31. "PADCONFIG8_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x20 30. "PADCONFIG8_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x20 29. "PADCONFIG8_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x20 28. "PADCONFIG8_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x20 27. "PADCONFIG8_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x20 26. "PADCONFIG8_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x20 25. "PADCONFIG8_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x20 24. "PADCONFIG8_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x20 23. "PADCONFIG8_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x20 22. "PADCONFIG8_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x20 21. "PADCONFIG8_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x20 15. "PADCONFIG8_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x20 14. "PADCONFIG8_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 8. "PADCONFIG8_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x20 7. "PADCONFIG8_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x20 0.--3. "PADCONFIG8_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x24 "CFG0_PADCONFIG9_PROXY,"
bitfld.long 0x24 31. "PADCONFIG9_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x24 30. "PADCONFIG9_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x24 29. "PADCONFIG9_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x24 28. "PADCONFIG9_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x24 27. "PADCONFIG9_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x24 26. "PADCONFIG9_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x24 25. "PADCONFIG9_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x24 24. "PADCONFIG9_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x24 23. "PADCONFIG9_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x24 22. "PADCONFIG9_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x24 21. "PADCONFIG9_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x24 15. "PADCONFIG9_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x24 14. "PADCONFIG9_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x24 8. "PADCONFIG9_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x24 7. "PADCONFIG9_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x24 0.--3. "PADCONFIG9_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x28 "CFG0_PADCONFIG10_PROXY,"
bitfld.long 0x28 31. "PADCONFIG10_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x28 30. "PADCONFIG10_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x28 29. "PADCONFIG10_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x28 28. "PADCONFIG10_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x28 27. "PADCONFIG10_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x28 26. "PADCONFIG10_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x28 25. "PADCONFIG10_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x28 24. "PADCONFIG10_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x28 23. "PADCONFIG10_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x28 22. "PADCONFIG10_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x28 21. "PADCONFIG10_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x28 15. "PADCONFIG10_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x28 14. "PADCONFIG10_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 8. "PADCONFIG10_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x28 7. "PADCONFIG10_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x28 0.--3. "PADCONFIG10_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2C "CFG0_PADCONFIG11_PROXY,"
bitfld.long 0x2C 31. "PADCONFIG11_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x2C 30. "PADCONFIG11_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x2C 29. "PADCONFIG11_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x2C 28. "PADCONFIG11_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x2C 27. "PADCONFIG11_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x2C 26. "PADCONFIG11_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2C 25. "PADCONFIG11_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x2C 24. "PADCONFIG11_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x2C 23. "PADCONFIG11_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x2C 22. "PADCONFIG11_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x2C 15. "PADCONFIG11_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x2C 14. "PADCONFIG11_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2C 8. "PADCONFIG11_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x2C 7. "PADCONFIG11_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x2C 0.--3. "PADCONFIG11_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x30 "CFG0_PADCONFIG12_PROXY,"
bitfld.long 0x30 31. "PADCONFIG12_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x30 30. "PADCONFIG12_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x30 29. "PADCONFIG12_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x30 28. "PADCONFIG12_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x30 27. "PADCONFIG12_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x30 26. "PADCONFIG12_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x30 25. "PADCONFIG12_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x30 24. "PADCONFIG12_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x30 23. "PADCONFIG12_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x30 22. "PADCONFIG12_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x30 21. "PADCONFIG12_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x30 15. "PADCONFIG12_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x30 14. "PADCONFIG12_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 8. "PADCONFIG12_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x30 7. "PADCONFIG12_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x30 0.--3. "PADCONFIG12_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x34 "CFG0_PADCONFIG13_PROXY,"
bitfld.long 0x34 31. "PADCONFIG13_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x34 30. "PADCONFIG13_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x34 29. "PADCONFIG13_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x34 28. "PADCONFIG13_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x34 27. "PADCONFIG13_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x34 26. "PADCONFIG13_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x34 25. "PADCONFIG13_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x34 24. "PADCONFIG13_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x34 23. "PADCONFIG13_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x34 22. "PADCONFIG13_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x34 21. "PADCONFIG13_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x34 15. "PADCONFIG13_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x34 14. "PADCONFIG13_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 8. "PADCONFIG13_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x34 7. "PADCONFIG13_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x34 0.--3. "PADCONFIG13_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x38 "CFG0_PADCONFIG14_PROXY,"
bitfld.long 0x38 31. "PADCONFIG14_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x38 30. "PADCONFIG14_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x38 29. "PADCONFIG14_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x38 28. "PADCONFIG14_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x38 27. "PADCONFIG14_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x38 26. "PADCONFIG14_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x38 25. "PADCONFIG14_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x38 24. "PADCONFIG14_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x38 23. "PADCONFIG14_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x38 22. "PADCONFIG14_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x38 21. "PADCONFIG14_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x38 15. "PADCONFIG14_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x38 14. "PADCONFIG14_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 8. "PADCONFIG14_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x38 7. "PADCONFIG14_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x38 0.--3. "PADCONFIG14_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x3C "CFG0_PADCONFIG15_PROXY,"
bitfld.long 0x3C 31. "PADCONFIG15_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x3C 30. "PADCONFIG15_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x3C 29. "PADCONFIG15_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x3C 28. "PADCONFIG15_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x3C 27. "PADCONFIG15_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x3C 26. "PADCONFIG15_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x3C 25. "PADCONFIG15_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x3C 24. "PADCONFIG15_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x3C 23. "PADCONFIG15_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x3C 22. "PADCONFIG15_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x3C 15. "PADCONFIG15_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x3C 14. "PADCONFIG15_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x3C 8. "PADCONFIG15_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x3C 7. "PADCONFIG15_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x3C 0.--3. "PADCONFIG15_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x40 "CFG0_PADCONFIG16_PROXY,"
bitfld.long 0x40 31. "PADCONFIG16_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x40 30. "PADCONFIG16_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x40 29. "PADCONFIG16_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x40 28. "PADCONFIG16_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x40 27. "PADCONFIG16_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x40 26. "PADCONFIG16_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x40 25. "PADCONFIG16_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x40 24. "PADCONFIG16_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x40 23. "PADCONFIG16_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x40 22. "PADCONFIG16_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x40 21. "PADCONFIG16_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x40 15. "PADCONFIG16_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x40 14. "PADCONFIG16_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x40 8. "PADCONFIG16_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x40 7. "PADCONFIG16_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x40 0.--3. "PADCONFIG16_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x44 "CFG0_PADCONFIG17_PROXY,"
bitfld.long 0x44 31. "PADCONFIG17_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x44 30. "PADCONFIG17_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x44 29. "PADCONFIG17_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x44 28. "PADCONFIG17_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x44 27. "PADCONFIG17_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x44 26. "PADCONFIG17_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x44 25. "PADCONFIG17_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x44 24. "PADCONFIG17_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x44 23. "PADCONFIG17_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x44 22. "PADCONFIG17_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x44 21. "PADCONFIG17_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x44 15. "PADCONFIG17_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x44 14. "PADCONFIG17_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x44 8. "PADCONFIG17_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x44 7. "PADCONFIG17_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x44 0.--3. "PADCONFIG17_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x48 "CFG0_PADCONFIG18_PROXY,"
bitfld.long 0x48 31. "PADCONFIG18_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x48 30. "PADCONFIG18_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x48 29. "PADCONFIG18_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x48 28. "PADCONFIG18_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x48 27. "PADCONFIG18_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x48 26. "PADCONFIG18_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x48 25. "PADCONFIG18_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x48 24. "PADCONFIG18_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x48 23. "PADCONFIG18_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x48 22. "PADCONFIG18_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x48 21. "PADCONFIG18_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x48 15. "PADCONFIG18_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x48 14. "PADCONFIG18_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x48 8. "PADCONFIG18_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x48 7. "PADCONFIG18_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x48 0.--3. "PADCONFIG18_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x4C "CFG0_PADCONFIG19_PROXY,"
bitfld.long 0x4C 31. "PADCONFIG19_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x4C 30. "PADCONFIG19_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x4C 29. "PADCONFIG19_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x4C 28. "PADCONFIG19_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x4C 27. "PADCONFIG19_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x4C 26. "PADCONFIG19_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x4C 25. "PADCONFIG19_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x4C 24. "PADCONFIG19_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x4C 23. "PADCONFIG19_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x4C 22. "PADCONFIG19_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x4C 15. "PADCONFIG19_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x4C 14. "PADCONFIG19_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4C 8. "PADCONFIG19_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x4C 7. "PADCONFIG19_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x4C 0.--3. "PADCONFIG19_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x50 "CFG0_PADCONFIG20_PROXY,"
bitfld.long 0x50 31. "PADCONFIG20_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x50 30. "PADCONFIG20_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x50 29. "PADCONFIG20_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x50 28. "PADCONFIG20_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x50 27. "PADCONFIG20_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x50 26. "PADCONFIG20_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x50 25. "PADCONFIG20_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x50 24. "PADCONFIG20_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x50 23. "PADCONFIG20_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x50 22. "PADCONFIG20_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x50 21. "PADCONFIG20_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x50 15. "PADCONFIG20_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x50 14. "PADCONFIG20_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x50 8. "PADCONFIG20_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x50 7. "PADCONFIG20_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x50 0.--3. "PADCONFIG20_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x54 "CFG0_PADCONFIG21_PROXY,"
bitfld.long 0x54 31. "PADCONFIG21_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x54 30. "PADCONFIG21_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x54 29. "PADCONFIG21_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x54 28. "PADCONFIG21_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x54 27. "PADCONFIG21_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x54 26. "PADCONFIG21_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x54 25. "PADCONFIG21_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x54 24. "PADCONFIG21_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x54 23. "PADCONFIG21_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x54 22. "PADCONFIG21_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x54 21. "PADCONFIG21_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x54 15. "PADCONFIG21_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x54 14. "PADCONFIG21_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x54 8. "PADCONFIG21_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x54 7. "PADCONFIG21_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x54 0.--3. "PADCONFIG21_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x58 "CFG0_PADCONFIG22_PROXY,"
bitfld.long 0x58 31. "PADCONFIG22_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x58 30. "PADCONFIG22_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x58 29. "PADCONFIG22_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x58 28. "PADCONFIG22_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x58 27. "PADCONFIG22_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x58 26. "PADCONFIG22_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x58 25. "PADCONFIG22_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x58 24. "PADCONFIG22_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x58 23. "PADCONFIG22_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x58 22. "PADCONFIG22_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x58 21. "PADCONFIG22_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x58 15. "PADCONFIG22_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x58 14. "PADCONFIG22_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x58 8. "PADCONFIG22_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x58 7. "PADCONFIG22_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x58 0.--3. "PADCONFIG22_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x5C "CFG0_PADCONFIG23_PROXY,"
bitfld.long 0x5C 31. "PADCONFIG23_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x5C 30. "PADCONFIG23_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x5C 29. "PADCONFIG23_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x5C 28. "PADCONFIG23_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x5C 27. "PADCONFIG23_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x5C 26. "PADCONFIG23_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x5C 25. "PADCONFIG23_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x5C 24. "PADCONFIG23_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x5C 23. "PADCONFIG23_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x5C 22. "PADCONFIG23_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x5C 15. "PADCONFIG23_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x5C 14. "PADCONFIG23_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x5C 8. "PADCONFIG23_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x5C 7. "PADCONFIG23_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x5C 0.--3. "PADCONFIG23_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x60 "CFG0_PADCONFIG24_PROXY,"
bitfld.long 0x60 31. "PADCONFIG24_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x60 30. "PADCONFIG24_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x60 29. "PADCONFIG24_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x60 28. "PADCONFIG24_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x60 27. "PADCONFIG24_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x60 26. "PADCONFIG24_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x60 25. "PADCONFIG24_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x60 24. "PADCONFIG24_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x60 23. "PADCONFIG24_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x60 22. "PADCONFIG24_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x60 21. "PADCONFIG24_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x60 15. "PADCONFIG24_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x60 14. "PADCONFIG24_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x60 8. "PADCONFIG24_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x60 7. "PADCONFIG24_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x60 0.--3. "PADCONFIG24_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x64 "CFG0_PADCONFIG25_PROXY,"
bitfld.long 0x64 31. "PADCONFIG25_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x64 30. "PADCONFIG25_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x64 29. "PADCONFIG25_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x64 28. "PADCONFIG25_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x64 27. "PADCONFIG25_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x64 26. "PADCONFIG25_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x64 25. "PADCONFIG25_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x64 24. "PADCONFIG25_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x64 23. "PADCONFIG25_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x64 22. "PADCONFIG25_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x64 21. "PADCONFIG25_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x64 15. "PADCONFIG25_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x64 14. "PADCONFIG25_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x64 8. "PADCONFIG25_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x64 7. "PADCONFIG25_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x64 0.--3. "PADCONFIG25_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x68 "CFG0_PADCONFIG26_PROXY,"
bitfld.long 0x68 31. "PADCONFIG26_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x68 30. "PADCONFIG26_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x68 29. "PADCONFIG26_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x68 28. "PADCONFIG26_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x68 27. "PADCONFIG26_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x68 26. "PADCONFIG26_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x68 25. "PADCONFIG26_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x68 24. "PADCONFIG26_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x68 23. "PADCONFIG26_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x68 22. "PADCONFIG26_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x68 21. "PADCONFIG26_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x68 15. "PADCONFIG26_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x68 14. "PADCONFIG26_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x68 8. "PADCONFIG26_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x68 7. "PADCONFIG26_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x68 0.--3. "PADCONFIG26_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x6C "CFG0_PADCONFIG27_PROXY,"
bitfld.long 0x6C 31. "PADCONFIG27_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x6C 30. "PADCONFIG27_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x6C 29. "PADCONFIG27_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x6C 28. "PADCONFIG27_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x6C 27. "PADCONFIG27_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x6C 26. "PADCONFIG27_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x6C 25. "PADCONFIG27_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x6C 24. "PADCONFIG27_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x6C 23. "PADCONFIG27_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x6C 22. "PADCONFIG27_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x6C 15. "PADCONFIG27_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x6C 14. "PADCONFIG27_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x6C 8. "PADCONFIG27_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x6C 7. "PADCONFIG27_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x6C 0.--3. "PADCONFIG27_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x70 "CFG0_PADCONFIG28_PROXY,"
bitfld.long 0x70 31. "PADCONFIG28_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x70 30. "PADCONFIG28_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x70 29. "PADCONFIG28_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x70 28. "PADCONFIG28_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x70 27. "PADCONFIG28_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x70 26. "PADCONFIG28_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x70 25. "PADCONFIG28_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x70 24. "PADCONFIG28_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x70 23. "PADCONFIG28_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x70 22. "PADCONFIG28_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x70 21. "PADCONFIG28_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x70 15. "PADCONFIG28_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x70 14. "PADCONFIG28_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x70 8. "PADCONFIG28_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x70 7. "PADCONFIG28_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x70 0.--3. "PADCONFIG28_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x74 "CFG0_PADCONFIG29_PROXY,"
bitfld.long 0x74 31. "PADCONFIG29_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x74 30. "PADCONFIG29_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x74 29. "PADCONFIG29_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x74 28. "PADCONFIG29_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x74 27. "PADCONFIG29_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x74 26. "PADCONFIG29_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x74 25. "PADCONFIG29_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x74 24. "PADCONFIG29_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x74 23. "PADCONFIG29_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x74 22. "PADCONFIG29_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x74 21. "PADCONFIG29_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x74 15. "PADCONFIG29_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x74 14. "PADCONFIG29_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x74 8. "PADCONFIG29_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x74 7. "PADCONFIG29_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x74 0.--3. "PADCONFIG29_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x78 "CFG0_PADCONFIG30_PROXY,"
bitfld.long 0x78 31. "PADCONFIG30_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x78 30. "PADCONFIG30_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x78 29. "PADCONFIG30_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x78 28. "PADCONFIG30_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x78 27. "PADCONFIG30_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x78 26. "PADCONFIG30_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x78 25. "PADCONFIG30_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x78 24. "PADCONFIG30_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x78 23. "PADCONFIG30_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x78 22. "PADCONFIG30_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x78 21. "PADCONFIG30_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x78 15. "PADCONFIG30_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x78 14. "PADCONFIG30_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x78 8. "PADCONFIG30_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x78 7. "PADCONFIG30_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x78 0.--3. "PADCONFIG30_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x7C "CFG0_PADCONFIG31_PROXY,"
bitfld.long 0x7C 31. "PADCONFIG31_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x7C 30. "PADCONFIG31_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x7C 29. "PADCONFIG31_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x7C 28. "PADCONFIG31_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x7C 27. "PADCONFIG31_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x7C 26. "PADCONFIG31_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x7C 25. "PADCONFIG31_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x7C 24. "PADCONFIG31_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x7C 23. "PADCONFIG31_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x7C 22. "PADCONFIG31_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x7C 15. "PADCONFIG31_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x7C 14. "PADCONFIG31_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x7C 8. "PADCONFIG31_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x7C 7. "PADCONFIG31_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x7C 0.--3. "PADCONFIG31_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x80 "CFG0_PADCONFIG32_PROXY,"
bitfld.long 0x80 31. "PADCONFIG32_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x80 30. "PADCONFIG32_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x80 29. "PADCONFIG32_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x80 28. "PADCONFIG32_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x80 27. "PADCONFIG32_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x80 26. "PADCONFIG32_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x80 25. "PADCONFIG32_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x80 24. "PADCONFIG32_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x80 23. "PADCONFIG32_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x80 22. "PADCONFIG32_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x80 21. "PADCONFIG32_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x80 15. "PADCONFIG32_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x80 14. "PADCONFIG32_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x80 8. "PADCONFIG32_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x80 7. "PADCONFIG32_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x80 0.--3. "PADCONFIG32_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x84 "CFG0_PADCONFIG33_PROXY,"
bitfld.long 0x84 31. "PADCONFIG33_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x84 30. "PADCONFIG33_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x84 29. "PADCONFIG33_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x84 28. "PADCONFIG33_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x84 27. "PADCONFIG33_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x84 26. "PADCONFIG33_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x84 25. "PADCONFIG33_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x84 24. "PADCONFIG33_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x84 23. "PADCONFIG33_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x84 22. "PADCONFIG33_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x84 21. "PADCONFIG33_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x84 19.--20. "PADCONFIG33_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x84 18. "PADCONFIG33_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x84 17. "PADCONFIG33_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x84 16. "PADCONFIG33_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x84 15. "PADCONFIG33_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x84 14. "PADCONFIG33_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x84 11.--13. "PADCONFIG33_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x84 8. "PADCONFIG33_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x84 7. "PADCONFIG33_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x84 0.--3. "PADCONFIG33_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x88 "CFG0_PADCONFIG34_PROXY,"
bitfld.long 0x88 31. "PADCONFIG34_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x88 30. "PADCONFIG34_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x88 29. "PADCONFIG34_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x88 28. "PADCONFIG34_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x88 27. "PADCONFIG34_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x88 26. "PADCONFIG34_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x88 25. "PADCONFIG34_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x88 24. "PADCONFIG34_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x88 23. "PADCONFIG34_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x88 22. "PADCONFIG34_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x88 21. "PADCONFIG34_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x88 19.--20. "PADCONFIG34_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x88 18. "PADCONFIG34_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x88 17. "PADCONFIG34_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x88 16. "PADCONFIG34_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x88 15. "PADCONFIG34_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x88 14. "PADCONFIG34_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x88 11.--13. "PADCONFIG34_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x88 8. "PADCONFIG34_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x88 7. "PADCONFIG34_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x88 0.--3. "PADCONFIG34_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x8C "CFG0_PADCONFIG35_PROXY,"
bitfld.long 0x8C 31. "PADCONFIG35_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x8C 30. "PADCONFIG35_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x8C 29. "PADCONFIG35_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x8C 28. "PADCONFIG35_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x8C 27. "PADCONFIG35_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x8C 26. "PADCONFIG35_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x8C 25. "PADCONFIG35_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x8C 24. "PADCONFIG35_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x8C 23. "PADCONFIG35_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x8C 22. "PADCONFIG35_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x8C 21. "PADCONFIG35_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x8C 19.--20. "PADCONFIG35_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x8C 18. "PADCONFIG35_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x8C 17. "PADCONFIG35_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x8C 16. "PADCONFIG35_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x8C 15. "PADCONFIG35_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x8C 14. "PADCONFIG35_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x8C 11.--13. "PADCONFIG35_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8C 8. "PADCONFIG35_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x8C 7. "PADCONFIG35_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x8C 0.--3. "PADCONFIG35_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x90 "CFG0_PADCONFIG36_PROXY,"
bitfld.long 0x90 31. "PADCONFIG36_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x90 30. "PADCONFIG36_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x90 29. "PADCONFIG36_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x90 28. "PADCONFIG36_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x90 27. "PADCONFIG36_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x90 26. "PADCONFIG36_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x90 25. "PADCONFIG36_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x90 24. "PADCONFIG36_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x90 23. "PADCONFIG36_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x90 22. "PADCONFIG36_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x90 21. "PADCONFIG36_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x90 19.--20. "PADCONFIG36_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x90 18. "PADCONFIG36_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x90 17. "PADCONFIG36_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x90 16. "PADCONFIG36_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x90 15. "PADCONFIG36_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x90 14. "PADCONFIG36_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x90 11.--13. "PADCONFIG36_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x90 8. "PADCONFIG36_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x90 7. "PADCONFIG36_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x90 0.--3. "PADCONFIG36_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x94 "CFG0_PADCONFIG37_PROXY,"
bitfld.long 0x94 31. "PADCONFIG37_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x94 30. "PADCONFIG37_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x94 29. "PADCONFIG37_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x94 28. "PADCONFIG37_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x94 27. "PADCONFIG37_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x94 26. "PADCONFIG37_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x94 25. "PADCONFIG37_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x94 24. "PADCONFIG37_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x94 23. "PADCONFIG37_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x94 22. "PADCONFIG37_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x94 21. "PADCONFIG37_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x94 19.--20. "PADCONFIG37_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x94 18. "PADCONFIG37_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x94 17. "PADCONFIG37_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x94 16. "PADCONFIG37_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x94 15. "PADCONFIG37_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x94 14. "PADCONFIG37_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x94 11.--13. "PADCONFIG37_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x94 8. "PADCONFIG37_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x94 7. "PADCONFIG37_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x94 0.--3. "PADCONFIG37_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x98 "CFG0_PADCONFIG38_PROXY,"
bitfld.long 0x98 31. "PADCONFIG38_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x98 30. "PADCONFIG38_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x98 29. "PADCONFIG38_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x98 28. "PADCONFIG38_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x98 27. "PADCONFIG38_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x98 26. "PADCONFIG38_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x98 25. "PADCONFIG38_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x98 24. "PADCONFIG38_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x98 23. "PADCONFIG38_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x98 22. "PADCONFIG38_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x98 21. "PADCONFIG38_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x98 19.--20. "PADCONFIG38_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x98 18. "PADCONFIG38_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x98 17. "PADCONFIG38_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x98 16. "PADCONFIG38_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x98 15. "PADCONFIG38_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x98 14. "PADCONFIG38_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x98 11.--13. "PADCONFIG38_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x98 8. "PADCONFIG38_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x98 7. "PADCONFIG38_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x98 0.--3. "PADCONFIG38_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x9C "CFG0_PADCONFIG39_PROXY,"
bitfld.long 0x9C 31. "PADCONFIG39_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x9C 30. "PADCONFIG39_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x9C 29. "PADCONFIG39_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x9C 28. "PADCONFIG39_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x9C 27. "PADCONFIG39_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x9C 26. "PADCONFIG39_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x9C 25. "PADCONFIG39_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x9C 24. "PADCONFIG39_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x9C 23. "PADCONFIG39_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x9C 22. "PADCONFIG39_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x9C 21. "PADCONFIG39_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x9C 19.--20. "PADCONFIG39_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x9C 18. "PADCONFIG39_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x9C 17. "PADCONFIG39_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x9C 16. "PADCONFIG39_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x9C 15. "PADCONFIG39_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x9C 14. "PADCONFIG39_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x9C 11.--13. "PADCONFIG39_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x9C 8. "PADCONFIG39_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x9C 7. "PADCONFIG39_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x9C 0.--3. "PADCONFIG39_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xA0 "CFG0_PADCONFIG40_PROXY,"
bitfld.long 0xA0 31. "PADCONFIG40_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xA0 30. "PADCONFIG40_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xA0 29. "PADCONFIG40_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xA0 28. "PADCONFIG40_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xA0 27. "PADCONFIG40_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xA0 26. "PADCONFIG40_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xA0 25. "PADCONFIG40_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xA0 24. "PADCONFIG40_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xA0 23. "PADCONFIG40_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xA0 22. "PADCONFIG40_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xA0 21. "PADCONFIG40_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xA0 19.--20. "PADCONFIG40_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xA0 18. "PADCONFIG40_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xA0 17. "PADCONFIG40_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xA0 16. "PADCONFIG40_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xA0 15. "PADCONFIG40_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xA0 14. "PADCONFIG40_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xA0 11.--13. "PADCONFIG40_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xA0 8. "PADCONFIG40_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xA0 7. "PADCONFIG40_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xA0 0.--3. "PADCONFIG40_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xA4 "CFG0_PADCONFIG41_PROXY,"
bitfld.long 0xA4 31. "PADCONFIG41_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xA4 30. "PADCONFIG41_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xA4 29. "PADCONFIG41_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xA4 28. "PADCONFIG41_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xA4 27. "PADCONFIG41_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xA4 26. "PADCONFIG41_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xA4 25. "PADCONFIG41_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xA4 24. "PADCONFIG41_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xA4 23. "PADCONFIG41_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xA4 22. "PADCONFIG41_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xA4 21. "PADCONFIG41_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xA4 19.--20. "PADCONFIG41_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xA4 18. "PADCONFIG41_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xA4 17. "PADCONFIG41_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xA4 16. "PADCONFIG41_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xA4 15. "PADCONFIG41_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xA4 14. "PADCONFIG41_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xA4 11.--13. "PADCONFIG41_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xA4 8. "PADCONFIG41_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xA4 7. "PADCONFIG41_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xA4 0.--3. "PADCONFIG41_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xA8 "CFG0_PADCONFIG42_PROXY,"
bitfld.long 0xA8 31. "PADCONFIG42_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xA8 30. "PADCONFIG42_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xA8 29. "PADCONFIG42_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xA8 28. "PADCONFIG42_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xA8 27. "PADCONFIG42_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xA8 26. "PADCONFIG42_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xA8 25. "PADCONFIG42_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xA8 24. "PADCONFIG42_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xA8 23. "PADCONFIG42_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xA8 22. "PADCONFIG42_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xA8 21. "PADCONFIG42_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xA8 19.--20. "PADCONFIG42_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xA8 18. "PADCONFIG42_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xA8 17. "PADCONFIG42_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xA8 16. "PADCONFIG42_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xA8 15. "PADCONFIG42_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xA8 14. "PADCONFIG42_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xA8 11.--13. "PADCONFIG42_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xA8 8. "PADCONFIG42_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xA8 7. "PADCONFIG42_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xA8 0.--3. "PADCONFIG42_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xAC "CFG0_PADCONFIG43_PROXY,"
bitfld.long 0xAC 31. "PADCONFIG43_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xAC 30. "PADCONFIG43_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xAC 29. "PADCONFIG43_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xAC 28. "PADCONFIG43_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xAC 27. "PADCONFIG43_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xAC 26. "PADCONFIG43_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xAC 25. "PADCONFIG43_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xAC 24. "PADCONFIG43_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xAC 23. "PADCONFIG43_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xAC 22. "PADCONFIG43_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xAC 21. "PADCONFIG43_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xAC 19.--20. "PADCONFIG43_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xAC 18. "PADCONFIG43_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xAC 17. "PADCONFIG43_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xAC 16. "PADCONFIG43_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xAC 15. "PADCONFIG43_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xAC 14. "PADCONFIG43_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xAC 11.--13. "PADCONFIG43_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xAC 8. "PADCONFIG43_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xAC 7. "PADCONFIG43_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xAC 0.--3. "PADCONFIG43_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xB0 "CFG0_PADCONFIG44_PROXY,"
bitfld.long 0xB0 31. "PADCONFIG44_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xB0 30. "PADCONFIG44_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xB0 29. "PADCONFIG44_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xB0 28. "PADCONFIG44_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xB0 27. "PADCONFIG44_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xB0 26. "PADCONFIG44_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xB0 25. "PADCONFIG44_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xB0 24. "PADCONFIG44_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xB0 23. "PADCONFIG44_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xB0 22. "PADCONFIG44_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xB0 21. "PADCONFIG44_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xB0 19.--20. "PADCONFIG44_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xB0 18. "PADCONFIG44_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xB0 17. "PADCONFIG44_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xB0 16. "PADCONFIG44_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xB0 15. "PADCONFIG44_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xB0 14. "PADCONFIG44_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xB0 11.--13. "PADCONFIG44_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xB0 8. "PADCONFIG44_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xB0 7. "PADCONFIG44_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xB0 0.--3. "PADCONFIG44_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xB4 "CFG0_PADCONFIG45_PROXY,"
bitfld.long 0xB4 31. "PADCONFIG45_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xB4 30. "PADCONFIG45_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xB4 29. "PADCONFIG45_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xB4 28. "PADCONFIG45_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xB4 27. "PADCONFIG45_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xB4 26. "PADCONFIG45_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xB4 25. "PADCONFIG45_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xB4 24. "PADCONFIG45_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xB4 23. "PADCONFIG45_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xB4 22. "PADCONFIG45_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xB4 21. "PADCONFIG45_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xB4 19.--20. "PADCONFIG45_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xB4 18. "PADCONFIG45_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xB4 17. "PADCONFIG45_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xB4 16. "PADCONFIG45_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xB4 15. "PADCONFIG45_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xB4 14. "PADCONFIG45_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xB4 11.--13. "PADCONFIG45_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xB4 8. "PADCONFIG45_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xB4 7. "PADCONFIG45_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xB4 0.--3. "PADCONFIG45_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xB8 "CFG0_PADCONFIG46_PROXY,"
bitfld.long 0xB8 31. "PADCONFIG46_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xB8 30. "PADCONFIG46_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xB8 29. "PADCONFIG46_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xB8 28. "PADCONFIG46_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xB8 27. "PADCONFIG46_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xB8 26. "PADCONFIG46_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xB8 25. "PADCONFIG46_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xB8 24. "PADCONFIG46_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xB8 23. "PADCONFIG46_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xB8 22. "PADCONFIG46_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xB8 21. "PADCONFIG46_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xB8 19.--20. "PADCONFIG46_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xB8 18. "PADCONFIG46_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xB8 17. "PADCONFIG46_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xB8 16. "PADCONFIG46_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xB8 15. "PADCONFIG46_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xB8 14. "PADCONFIG46_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xB8 11.--13. "PADCONFIG46_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xB8 8. "PADCONFIG46_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xB8 7. "PADCONFIG46_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xB8 0.--3. "PADCONFIG46_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xBC "CFG0_PADCONFIG47_PROXY,"
bitfld.long 0xBC 31. "PADCONFIG47_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xBC 30. "PADCONFIG47_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xBC 29. "PADCONFIG47_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xBC 28. "PADCONFIG47_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xBC 27. "PADCONFIG47_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xBC 26. "PADCONFIG47_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xBC 25. "PADCONFIG47_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xBC 24. "PADCONFIG47_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xBC 23. "PADCONFIG47_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xBC 22. "PADCONFIG47_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xBC 21. "PADCONFIG47_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xBC 19.--20. "PADCONFIG47_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xBC 18. "PADCONFIG47_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xBC 17. "PADCONFIG47_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xBC 16. "PADCONFIG47_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xBC 15. "PADCONFIG47_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xBC 14. "PADCONFIG47_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xBC 11.--13. "PADCONFIG47_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xBC 8. "PADCONFIG47_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xBC 7. "PADCONFIG47_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xBC 0.--3. "PADCONFIG47_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xC0 "CFG0_PADCONFIG48_PROXY,"
bitfld.long 0xC0 31. "PADCONFIG48_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xC0 30. "PADCONFIG48_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xC0 29. "PADCONFIG48_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xC0 28. "PADCONFIG48_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xC0 27. "PADCONFIG48_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xC0 26. "PADCONFIG48_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xC0 25. "PADCONFIG48_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xC0 24. "PADCONFIG48_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xC0 23. "PADCONFIG48_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xC0 22. "PADCONFIG48_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xC0 21. "PADCONFIG48_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xC0 19.--20. "PADCONFIG48_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xC0 18. "PADCONFIG48_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xC0 17. "PADCONFIG48_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xC0 16. "PADCONFIG48_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xC0 15. "PADCONFIG48_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xC0 14. "PADCONFIG48_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xC0 11.--13. "PADCONFIG48_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC0 8. "PADCONFIG48_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xC0 7. "PADCONFIG48_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xC0 0.--3. "PADCONFIG48_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xC4 "CFG0_PADCONFIG49_PROXY,"
bitfld.long 0xC4 31. "PADCONFIG49_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xC4 30. "PADCONFIG49_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xC4 29. "PADCONFIG49_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xC4 28. "PADCONFIG49_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xC4 27. "PADCONFIG49_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xC4 26. "PADCONFIG49_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xC4 25. "PADCONFIG49_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xC4 24. "PADCONFIG49_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xC4 23. "PADCONFIG49_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xC4 22. "PADCONFIG49_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xC4 21. "PADCONFIG49_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xC4 19.--20. "PADCONFIG49_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xC4 18. "PADCONFIG49_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xC4 17. "PADCONFIG49_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xC4 16. "PADCONFIG49_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xC4 15. "PADCONFIG49_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xC4 14. "PADCONFIG49_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xC4 11.--13. "PADCONFIG49_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC4 8. "PADCONFIG49_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xC4 7. "PADCONFIG49_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xC4 0.--3. "PADCONFIG49_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xC8 "CFG0_PADCONFIG50_PROXY,"
bitfld.long 0xC8 31. "PADCONFIG50_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xC8 30. "PADCONFIG50_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xC8 29. "PADCONFIG50_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xC8 28. "PADCONFIG50_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xC8 27. "PADCONFIG50_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xC8 26. "PADCONFIG50_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xC8 25. "PADCONFIG50_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xC8 24. "PADCONFIG50_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xC8 23. "PADCONFIG50_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xC8 22. "PADCONFIG50_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xC8 21. "PADCONFIG50_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xC8 19.--20. "PADCONFIG50_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xC8 18. "PADCONFIG50_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xC8 17. "PADCONFIG50_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xC8 16. "PADCONFIG50_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xC8 15. "PADCONFIG50_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xC8 14. "PADCONFIG50_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xC8 11.--13. "PADCONFIG50_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC8 8. "PADCONFIG50_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xC8 7. "PADCONFIG50_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xC8 0.--3. "PADCONFIG50_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xCC "CFG0_PADCONFIG51_PROXY,"
bitfld.long 0xCC 31. "PADCONFIG51_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xCC 30. "PADCONFIG51_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xCC 29. "PADCONFIG51_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xCC 28. "PADCONFIG51_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xCC 27. "PADCONFIG51_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xCC 26. "PADCONFIG51_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xCC 25. "PADCONFIG51_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xCC 24. "PADCONFIG51_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xCC 23. "PADCONFIG51_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xCC 22. "PADCONFIG51_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xCC 21. "PADCONFIG51_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xCC 19.--20. "PADCONFIG51_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xCC 18. "PADCONFIG51_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xCC 17. "PADCONFIG51_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xCC 16. "PADCONFIG51_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xCC 15. "PADCONFIG51_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xCC 14. "PADCONFIG51_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xCC 11.--13. "PADCONFIG51_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xCC 8. "PADCONFIG51_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xCC 7. "PADCONFIG51_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xCC 0.--3. "PADCONFIG51_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xD0 "CFG0_PADCONFIG52_PROXY,"
bitfld.long 0xD0 31. "PADCONFIG52_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xD0 30. "PADCONFIG52_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xD0 29. "PADCONFIG52_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xD0 28. "PADCONFIG52_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xD0 27. "PADCONFIG52_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xD0 26. "PADCONFIG52_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xD0 25. "PADCONFIG52_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xD0 24. "PADCONFIG52_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xD0 23. "PADCONFIG52_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xD0 22. "PADCONFIG52_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xD0 21. "PADCONFIG52_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xD0 19.--20. "PADCONFIG52_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xD0 18. "PADCONFIG52_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xD0 17. "PADCONFIG52_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xD0 16. "PADCONFIG52_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xD0 15. "PADCONFIG52_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xD0 14. "PADCONFIG52_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xD0 11.--13. "PADCONFIG52_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD0 8. "PADCONFIG52_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xD0 7. "PADCONFIG52_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xD0 0.--3. "PADCONFIG52_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xD4 "CFG0_PADCONFIG53_PROXY,"
bitfld.long 0xD4 31. "PADCONFIG53_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xD4 30. "PADCONFIG53_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xD4 29. "PADCONFIG53_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xD4 28. "PADCONFIG53_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xD4 27. "PADCONFIG53_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xD4 26. "PADCONFIG53_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xD4 25. "PADCONFIG53_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xD4 24. "PADCONFIG53_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xD4 23. "PADCONFIG53_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xD4 22. "PADCONFIG53_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xD4 21. "PADCONFIG53_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xD4 19.--20. "PADCONFIG53_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xD4 18. "PADCONFIG53_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xD4 17. "PADCONFIG53_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xD4 16. "PADCONFIG53_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xD4 15. "PADCONFIG53_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xD4 14. "PADCONFIG53_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xD4 11.--13. "PADCONFIG53_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD4 8. "PADCONFIG53_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xD4 7. "PADCONFIG53_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xD4 0.--3. "PADCONFIG53_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xD8 "CFG0_PADCONFIG54_PROXY,"
bitfld.long 0xD8 31. "PADCONFIG54_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xD8 30. "PADCONFIG54_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xD8 29. "PADCONFIG54_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xD8 28. "PADCONFIG54_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xD8 27. "PADCONFIG54_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xD8 26. "PADCONFIG54_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xD8 25. "PADCONFIG54_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xD8 24. "PADCONFIG54_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xD8 23. "PADCONFIG54_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xD8 22. "PADCONFIG54_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xD8 21. "PADCONFIG54_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xD8 19.--20. "PADCONFIG54_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xD8 18. "PADCONFIG54_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xD8 17. "PADCONFIG54_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xD8 16. "PADCONFIG54_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xD8 15. "PADCONFIG54_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xD8 14. "PADCONFIG54_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xD8 11.--13. "PADCONFIG54_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD8 8. "PADCONFIG54_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xD8 7. "PADCONFIG54_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xD8 0.--3. "PADCONFIG54_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xDC "CFG0_PADCONFIG55_PROXY,"
bitfld.long 0xDC 31. "PADCONFIG55_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xDC 30. "PADCONFIG55_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xDC 29. "PADCONFIG55_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xDC 28. "PADCONFIG55_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xDC 27. "PADCONFIG55_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xDC 26. "PADCONFIG55_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xDC 25. "PADCONFIG55_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xDC 24. "PADCONFIG55_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xDC 23. "PADCONFIG55_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xDC 22. "PADCONFIG55_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xDC 21. "PADCONFIG55_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xDC 19.--20. "PADCONFIG55_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xDC 18. "PADCONFIG55_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xDC 17. "PADCONFIG55_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xDC 16. "PADCONFIG55_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xDC 15. "PADCONFIG55_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xDC 14. "PADCONFIG55_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xDC 11.--13. "PADCONFIG55_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xDC 8. "PADCONFIG55_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xDC 7. "PADCONFIG55_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xDC 0.--3. "PADCONFIG55_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xE0 "CFG0_PADCONFIG56_PROXY,"
bitfld.long 0xE0 31. "PADCONFIG56_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xE0 30. "PADCONFIG56_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xE0 29. "PADCONFIG56_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xE0 28. "PADCONFIG56_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xE0 27. "PADCONFIG56_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xE0 26. "PADCONFIG56_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xE0 25. "PADCONFIG56_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xE0 24. "PADCONFIG56_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xE0 23. "PADCONFIG56_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xE0 22. "PADCONFIG56_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xE0 21. "PADCONFIG56_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xE0 19.--20. "PADCONFIG56_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xE0 18. "PADCONFIG56_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xE0 17. "PADCONFIG56_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xE0 16. "PADCONFIG56_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xE0 15. "PADCONFIG56_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xE0 14. "PADCONFIG56_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xE0 11.--13. "PADCONFIG56_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xE0 8. "PADCONFIG56_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xE0 7. "PADCONFIG56_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xE0 0.--3. "PADCONFIG56_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xE4 "CFG0_PADCONFIG57_PROXY,"
bitfld.long 0xE4 31. "PADCONFIG57_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xE4 30. "PADCONFIG57_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xE4 29. "PADCONFIG57_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xE4 28. "PADCONFIG57_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xE4 27. "PADCONFIG57_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xE4 26. "PADCONFIG57_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xE4 25. "PADCONFIG57_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xE4 24. "PADCONFIG57_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xE4 23. "PADCONFIG57_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xE4 22. "PADCONFIG57_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xE4 21. "PADCONFIG57_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xE4 19.--20. "PADCONFIG57_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xE4 18. "PADCONFIG57_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xE4 17. "PADCONFIG57_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xE4 16. "PADCONFIG57_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xE4 15. "PADCONFIG57_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xE4 14. "PADCONFIG57_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xE4 11.--13. "PADCONFIG57_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xE4 8. "PADCONFIG57_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xE4 7. "PADCONFIG57_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xE4 0.--3. "PADCONFIG57_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xE8 "CFG0_PADCONFIG58_PROXY,"
bitfld.long 0xE8 31. "PADCONFIG58_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xE8 30. "PADCONFIG58_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xE8 29. "PADCONFIG58_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xE8 28. "PADCONFIG58_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xE8 27. "PADCONFIG58_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xE8 26. "PADCONFIG58_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xE8 25. "PADCONFIG58_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xE8 24. "PADCONFIG58_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xE8 23. "PADCONFIG58_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xE8 22. "PADCONFIG58_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xE8 21. "PADCONFIG58_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xE8 19.--20. "PADCONFIG58_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xE8 18. "PADCONFIG58_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xE8 17. "PADCONFIG58_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xE8 16. "PADCONFIG58_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xE8 15. "PADCONFIG58_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xE8 14. "PADCONFIG58_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xE8 11.--13. "PADCONFIG58_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xE8 8. "PADCONFIG58_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xE8 7. "PADCONFIG58_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xE8 0.--3. "PADCONFIG58_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xEC "CFG0_PADCONFIG59_PROXY,"
bitfld.long 0xEC 31. "PADCONFIG59_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xEC 30. "PADCONFIG59_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xEC 29. "PADCONFIG59_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xEC 28. "PADCONFIG59_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xEC 27. "PADCONFIG59_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xEC 26. "PADCONFIG59_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xEC 25. "PADCONFIG59_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xEC 24. "PADCONFIG59_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xEC 23. "PADCONFIG59_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xEC 22. "PADCONFIG59_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xEC 21. "PADCONFIG59_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xEC 19.--20. "PADCONFIG59_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xEC 18. "PADCONFIG59_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xEC 17. "PADCONFIG59_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xEC 16. "PADCONFIG59_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xEC 15. "PADCONFIG59_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xEC 14. "PADCONFIG59_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xEC 11.--13. "PADCONFIG59_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xEC 8. "PADCONFIG59_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xEC 7. "PADCONFIG59_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xEC 0.--3. "PADCONFIG59_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xF0 "CFG0_PADCONFIG60_PROXY,"
bitfld.long 0xF0 31. "PADCONFIG60_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xF0 30. "PADCONFIG60_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xF0 29. "PADCONFIG60_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xF0 28. "PADCONFIG60_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xF0 27. "PADCONFIG60_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xF0 26. "PADCONFIG60_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xF0 25. "PADCONFIG60_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xF0 24. "PADCONFIG60_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xF0 23. "PADCONFIG60_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xF0 22. "PADCONFIG60_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xF0 21. "PADCONFIG60_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xF0 19.--20. "PADCONFIG60_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xF0 18. "PADCONFIG60_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xF0 17. "PADCONFIG60_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xF0 16. "PADCONFIG60_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xF0 15. "PADCONFIG60_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xF0 14. "PADCONFIG60_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xF0 11.--13. "PADCONFIG60_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xF0 8. "PADCONFIG60_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xF0 7. "PADCONFIG60_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xF0 0.--3. "PADCONFIG60_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xF4 "CFG0_PADCONFIG61_PROXY,"
bitfld.long 0xF4 31. "PADCONFIG61_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xF4 30. "PADCONFIG61_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xF4 29. "PADCONFIG61_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xF4 28. "PADCONFIG61_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xF4 27. "PADCONFIG61_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xF4 26. "PADCONFIG61_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xF4 25. "PADCONFIG61_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xF4 24. "PADCONFIG61_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xF4 23. "PADCONFIG61_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xF4 22. "PADCONFIG61_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xF4 21. "PADCONFIG61_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xF4 19.--20. "PADCONFIG61_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xF4 18. "PADCONFIG61_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xF4 17. "PADCONFIG61_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xF4 16. "PADCONFIG61_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xF4 15. "PADCONFIG61_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xF4 14. "PADCONFIG61_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xF4 11.--13. "PADCONFIG61_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xF4 8. "PADCONFIG61_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xF4 7. "PADCONFIG61_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xF4 0.--3. "PADCONFIG61_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xF8 "CFG0_PADCONFIG62_PROXY,"
bitfld.long 0xF8 31. "PADCONFIG62_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xF8 30. "PADCONFIG62_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xF8 29. "PADCONFIG62_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xF8 28. "PADCONFIG62_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xF8 27. "PADCONFIG62_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xF8 26. "PADCONFIG62_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xF8 25. "PADCONFIG62_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xF8 24. "PADCONFIG62_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xF8 23. "PADCONFIG62_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xF8 22. "PADCONFIG62_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xF8 21. "PADCONFIG62_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xF8 19.--20. "PADCONFIG62_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xF8 18. "PADCONFIG62_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xF8 17. "PADCONFIG62_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xF8 16. "PADCONFIG62_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xF8 15. "PADCONFIG62_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xF8 14. "PADCONFIG62_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xF8 11.--13. "PADCONFIG62_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xF8 8. "PADCONFIG62_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xF8 7. "PADCONFIG62_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xF8 0.--3. "PADCONFIG62_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xFC "CFG0_PADCONFIG63_PROXY,"
bitfld.long 0xFC 31. "PADCONFIG63_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xFC 30. "PADCONFIG63_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xFC 29. "PADCONFIG63_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xFC 28. "PADCONFIG63_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xFC 27. "PADCONFIG63_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xFC 26. "PADCONFIG63_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xFC 25. "PADCONFIG63_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xFC 24. "PADCONFIG63_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xFC 23. "PADCONFIG63_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xFC 22. "PADCONFIG63_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xFC 21. "PADCONFIG63_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xFC 19.--20. "PADCONFIG63_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xFC 18. "PADCONFIG63_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xFC 17. "PADCONFIG63_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xFC 16. "PADCONFIG63_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xFC 15. "PADCONFIG63_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xFC 14. "PADCONFIG63_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xFC 11.--13. "PADCONFIG63_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xFC 8. "PADCONFIG63_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xFC 7. "PADCONFIG63_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xFC 0.--3. "PADCONFIG63_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x100 "CFG0_PADCONFIG64_PROXY,"
bitfld.long 0x100 31. "PADCONFIG64_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x100 30. "PADCONFIG64_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x100 29. "PADCONFIG64_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x100 28. "PADCONFIG64_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x100 27. "PADCONFIG64_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x100 26. "PADCONFIG64_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x100 25. "PADCONFIG64_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x100 24. "PADCONFIG64_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x100 23. "PADCONFIG64_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x100 22. "PADCONFIG64_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x100 21. "PADCONFIG64_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x100 19.--20. "PADCONFIG64_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x100 18. "PADCONFIG64_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x100 17. "PADCONFIG64_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x100 16. "PADCONFIG64_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x100 15. "PADCONFIG64_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x100 14. "PADCONFIG64_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x100 11.--13. "PADCONFIG64_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x100 8. "PADCONFIG64_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x100 7. "PADCONFIG64_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x100 0.--3. "PADCONFIG64_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x104 "CFG0_PADCONFIG65_PROXY,"
bitfld.long 0x104 31. "PADCONFIG65_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x104 30. "PADCONFIG65_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x104 29. "PADCONFIG65_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x104 28. "PADCONFIG65_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x104 27. "PADCONFIG65_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x104 26. "PADCONFIG65_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x104 25. "PADCONFIG65_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x104 24. "PADCONFIG65_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x104 23. "PADCONFIG65_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x104 22. "PADCONFIG65_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x104 21. "PADCONFIG65_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x104 19.--20. "PADCONFIG65_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x104 18. "PADCONFIG65_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x104 17. "PADCONFIG65_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x104 16. "PADCONFIG65_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x104 15. "PADCONFIG65_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x104 14. "PADCONFIG65_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x104 11.--13. "PADCONFIG65_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 8. "PADCONFIG65_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x104 7. "PADCONFIG65_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x104 0.--3. "PADCONFIG65_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x108 "CFG0_PADCONFIG66_PROXY,"
bitfld.long 0x108 31. "PADCONFIG66_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x108 30. "PADCONFIG66_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x108 29. "PADCONFIG66_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x108 28. "PADCONFIG66_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x108 27. "PADCONFIG66_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x108 26. "PADCONFIG66_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x108 25. "PADCONFIG66_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x108 24. "PADCONFIG66_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x108 23. "PADCONFIG66_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x108 22. "PADCONFIG66_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x108 21. "PADCONFIG66_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x108 19.--20. "PADCONFIG66_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x108 18. "PADCONFIG66_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x108 17. "PADCONFIG66_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x108 16. "PADCONFIG66_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x108 15. "PADCONFIG66_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x108 14. "PADCONFIG66_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x108 11.--13. "PADCONFIG66_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x108 8. "PADCONFIG66_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x108 7. "PADCONFIG66_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x108 0.--3. "PADCONFIG66_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x10C "CFG0_PADCONFIG67_PROXY,"
bitfld.long 0x10C 31. "PADCONFIG67_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x10C 30. "PADCONFIG67_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x10C 29. "PADCONFIG67_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x10C 28. "PADCONFIG67_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x10C 27. "PADCONFIG67_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x10C 26. "PADCONFIG67_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x10C 25. "PADCONFIG67_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x10C 24. "PADCONFIG67_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x10C 23. "PADCONFIG67_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x10C 22. "PADCONFIG67_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x10C 21. "PADCONFIG67_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x10C 19.--20. "PADCONFIG67_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x10C 18. "PADCONFIG67_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x10C 17. "PADCONFIG67_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x10C 16. "PADCONFIG67_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x10C 15. "PADCONFIG67_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x10C 14. "PADCONFIG67_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x10C 11.--13. "PADCONFIG67_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10C 8. "PADCONFIG67_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x10C 7. "PADCONFIG67_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x10C 0.--3. "PADCONFIG67_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x110 "CFG0_PADCONFIG68_PROXY,"
bitfld.long 0x110 31. "PADCONFIG68_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x110 30. "PADCONFIG68_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x110 29. "PADCONFIG68_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x110 28. "PADCONFIG68_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x110 27. "PADCONFIG68_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x110 26. "PADCONFIG68_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x110 25. "PADCONFIG68_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x110 24. "PADCONFIG68_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x110 23. "PADCONFIG68_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x110 22. "PADCONFIG68_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x110 21. "PADCONFIG68_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x110 19.--20. "PADCONFIG68_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x110 18. "PADCONFIG68_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x110 17. "PADCONFIG68_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x110 16. "PADCONFIG68_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x110 15. "PADCONFIG68_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x110 14. "PADCONFIG68_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x110 11.--13. "PADCONFIG68_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x110 8. "PADCONFIG68_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x110 7. "PADCONFIG68_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x110 0.--3. "PADCONFIG68_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x114 "CFG0_PADCONFIG69_PROXY,"
bitfld.long 0x114 31. "PADCONFIG69_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x114 30. "PADCONFIG69_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x114 29. "PADCONFIG69_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x114 28. "PADCONFIG69_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x114 27. "PADCONFIG69_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x114 26. "PADCONFIG69_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x114 25. "PADCONFIG69_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x114 24. "PADCONFIG69_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x114 23. "PADCONFIG69_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x114 22. "PADCONFIG69_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x114 21. "PADCONFIG69_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x114 19.--20. "PADCONFIG69_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x114 18. "PADCONFIG69_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x114 17. "PADCONFIG69_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x114 16. "PADCONFIG69_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x114 15. "PADCONFIG69_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x114 14. "PADCONFIG69_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x114 11.--13. "PADCONFIG69_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x114 8. "PADCONFIG69_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x114 7. "PADCONFIG69_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x114 0.--3. "PADCONFIG69_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x118 "CFG0_PADCONFIG70_PROXY,"
bitfld.long 0x118 31. "PADCONFIG70_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x118 30. "PADCONFIG70_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x118 29. "PADCONFIG70_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x118 28. "PADCONFIG70_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x118 27. "PADCONFIG70_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x118 26. "PADCONFIG70_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x118 25. "PADCONFIG70_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x118 24. "PADCONFIG70_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x118 23. "PADCONFIG70_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x118 22. "PADCONFIG70_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x118 21. "PADCONFIG70_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x118 19.--20. "PADCONFIG70_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x118 18. "PADCONFIG70_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x118 17. "PADCONFIG70_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x118 16. "PADCONFIG70_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x118 15. "PADCONFIG70_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x118 14. "PADCONFIG70_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x118 11.--13. "PADCONFIG70_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x118 8. "PADCONFIG70_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x118 7. "PADCONFIG70_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x118 0.--3. "PADCONFIG70_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x11C "CFG0_PADCONFIG71_PROXY,"
bitfld.long 0x11C 31. "PADCONFIG71_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x11C 30. "PADCONFIG71_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x11C 29. "PADCONFIG71_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x11C 28. "PADCONFIG71_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x11C 27. "PADCONFIG71_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x11C 26. "PADCONFIG71_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x11C 25. "PADCONFIG71_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x11C 24. "PADCONFIG71_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x11C 23. "PADCONFIG71_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x11C 22. "PADCONFIG71_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x11C 21. "PADCONFIG71_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x11C 19.--20. "PADCONFIG71_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x11C 18. "PADCONFIG71_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x11C 17. "PADCONFIG71_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x11C 16. "PADCONFIG71_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x11C 15. "PADCONFIG71_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x11C 14. "PADCONFIG71_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x11C 11.--13. "PADCONFIG71_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x11C 8. "PADCONFIG71_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x11C 7. "PADCONFIG71_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x11C 0.--3. "PADCONFIG71_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x120 "CFG0_PADCONFIG72_PROXY,"
bitfld.long 0x120 31. "PADCONFIG72_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x120 30. "PADCONFIG72_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x120 29. "PADCONFIG72_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x120 28. "PADCONFIG72_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x120 27. "PADCONFIG72_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x120 26. "PADCONFIG72_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x120 25. "PADCONFIG72_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x120 24. "PADCONFIG72_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x120 23. "PADCONFIG72_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x120 22. "PADCONFIG72_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x120 21. "PADCONFIG72_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x120 19.--20. "PADCONFIG72_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x120 18. "PADCONFIG72_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x120 17. "PADCONFIG72_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x120 16. "PADCONFIG72_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x120 15. "PADCONFIG72_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x120 14. "PADCONFIG72_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x120 11.--13. "PADCONFIG72_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x120 8. "PADCONFIG72_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x120 7. "PADCONFIG72_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x120 0.--3. "PADCONFIG72_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x124 "CFG0_PADCONFIG73_PROXY,"
bitfld.long 0x124 31. "PADCONFIG73_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x124 30. "PADCONFIG73_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x124 29. "PADCONFIG73_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x124 28. "PADCONFIG73_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x124 27. "PADCONFIG73_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x124 26. "PADCONFIG73_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x124 25. "PADCONFIG73_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x124 24. "PADCONFIG73_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x124 23. "PADCONFIG73_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x124 22. "PADCONFIG73_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x124 21. "PADCONFIG73_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x124 19.--20. "PADCONFIG73_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x124 18. "PADCONFIG73_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x124 17. "PADCONFIG73_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x124 16. "PADCONFIG73_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x124 15. "PADCONFIG73_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x124 14. "PADCONFIG73_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x124 11.--13. "PADCONFIG73_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x124 8. "PADCONFIG73_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x124 7. "PADCONFIG73_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x124 0.--3. "PADCONFIG73_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x128 "CFG0_PADCONFIG74_PROXY,"
bitfld.long 0x128 31. "PADCONFIG74_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x128 30. "PADCONFIG74_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x128 29. "PADCONFIG74_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x128 28. "PADCONFIG74_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x128 27. "PADCONFIG74_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x128 26. "PADCONFIG74_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x128 25. "PADCONFIG74_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x128 24. "PADCONFIG74_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x128 23. "PADCONFIG74_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x128 22. "PADCONFIG74_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x128 21. "PADCONFIG74_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x128 19.--20. "PADCONFIG74_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x128 18. "PADCONFIG74_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x128 17. "PADCONFIG74_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x128 16. "PADCONFIG74_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x128 15. "PADCONFIG74_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x128 14. "PADCONFIG74_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x128 11.--13. "PADCONFIG74_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x128 8. "PADCONFIG74_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x128 7. "PADCONFIG74_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x128 0.--3. "PADCONFIG74_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x12C "CFG0_PADCONFIG75_PROXY,"
bitfld.long 0x12C 31. "PADCONFIG75_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x12C 30. "PADCONFIG75_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x12C 29. "PADCONFIG75_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x12C 28. "PADCONFIG75_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x12C 27. "PADCONFIG75_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x12C 26. "PADCONFIG75_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x12C 25. "PADCONFIG75_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x12C 24. "PADCONFIG75_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x12C 23. "PADCONFIG75_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x12C 22. "PADCONFIG75_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x12C 21. "PADCONFIG75_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x12C 19.--20. "PADCONFIG75_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x12C 18. "PADCONFIG75_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x12C 17. "PADCONFIG75_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x12C 16. "PADCONFIG75_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x12C 15. "PADCONFIG75_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x12C 14. "PADCONFIG75_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x12C 11.--13. "PADCONFIG75_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x12C 8. "PADCONFIG75_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x12C 7. "PADCONFIG75_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x12C 0.--3. "PADCONFIG75_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x130 "CFG0_PADCONFIG76_PROXY,"
bitfld.long 0x130 31. "PADCONFIG76_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x130 30. "PADCONFIG76_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x130 29. "PADCONFIG76_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x130 28. "PADCONFIG76_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x130 27. "PADCONFIG76_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x130 26. "PADCONFIG76_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x130 25. "PADCONFIG76_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x130 24. "PADCONFIG76_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x130 23. "PADCONFIG76_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x130 22. "PADCONFIG76_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x130 21. "PADCONFIG76_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x130 19.--20. "PADCONFIG76_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x130 18. "PADCONFIG76_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x130 17. "PADCONFIG76_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x130 16. "PADCONFIG76_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x130 15. "PADCONFIG76_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x130 14. "PADCONFIG76_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x130 11.--13. "PADCONFIG76_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x130 8. "PADCONFIG76_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x130 7. "PADCONFIG76_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x130 0.--3. "PADCONFIG76_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x134 "CFG0_PADCONFIG77_PROXY,"
bitfld.long 0x134 31. "PADCONFIG77_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x134 30. "PADCONFIG77_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x134 29. "PADCONFIG77_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x134 28. "PADCONFIG77_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x134 27. "PADCONFIG77_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x134 26. "PADCONFIG77_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x134 25. "PADCONFIG77_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x134 24. "PADCONFIG77_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x134 23. "PADCONFIG77_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x134 22. "PADCONFIG77_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x134 21. "PADCONFIG77_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x134 19.--20. "PADCONFIG77_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x134 18. "PADCONFIG77_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x134 17. "PADCONFIG77_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x134 16. "PADCONFIG77_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x134 15. "PADCONFIG77_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x134 14. "PADCONFIG77_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x134 11.--13. "PADCONFIG77_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x134 8. "PADCONFIG77_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x134 7. "PADCONFIG77_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x134 0.--3. "PADCONFIG77_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x138 "CFG0_PADCONFIG78_PROXY,"
bitfld.long 0x138 31. "PADCONFIG78_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x138 30. "PADCONFIG78_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x138 29. "PADCONFIG78_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x138 28. "PADCONFIG78_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x138 27. "PADCONFIG78_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x138 26. "PADCONFIG78_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x138 25. "PADCONFIG78_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x138 24. "PADCONFIG78_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x138 23. "PADCONFIG78_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x138 22. "PADCONFIG78_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x138 21. "PADCONFIG78_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x138 19.--20. "PADCONFIG78_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x138 18. "PADCONFIG78_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x138 17. "PADCONFIG78_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x138 16. "PADCONFIG78_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x138 15. "PADCONFIG78_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x138 14. "PADCONFIG78_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x138 11.--13. "PADCONFIG78_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x138 8. "PADCONFIG78_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x138 7. "PADCONFIG78_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x138 0.--3. "PADCONFIG78_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x13C "CFG0_PADCONFIG79_PROXY,"
bitfld.long 0x13C 31. "PADCONFIG79_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x13C 30. "PADCONFIG79_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x13C 29. "PADCONFIG79_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x13C 28. "PADCONFIG79_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x13C 27. "PADCONFIG79_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x13C 26. "PADCONFIG79_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x13C 25. "PADCONFIG79_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x13C 24. "PADCONFIG79_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x13C 23. "PADCONFIG79_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x13C 22. "PADCONFIG79_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x13C 21. "PADCONFIG79_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x13C 19.--20. "PADCONFIG79_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x13C 18. "PADCONFIG79_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x13C 17. "PADCONFIG79_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x13C 16. "PADCONFIG79_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x13C 15. "PADCONFIG79_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x13C 14. "PADCONFIG79_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x13C 11.--13. "PADCONFIG79_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x13C 8. "PADCONFIG79_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x13C 7. "PADCONFIG79_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x13C 0.--3. "PADCONFIG79_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x140 "CFG0_PADCONFIG80_PROXY,"
bitfld.long 0x140 31. "PADCONFIG80_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x140 30. "PADCONFIG80_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x140 29. "PADCONFIG80_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x140 28. "PADCONFIG80_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x140 27. "PADCONFIG80_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x140 26. "PADCONFIG80_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x140 25. "PADCONFIG80_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x140 24. "PADCONFIG80_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x140 23. "PADCONFIG80_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x140 22. "PADCONFIG80_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x140 21. "PADCONFIG80_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x140 19.--20. "PADCONFIG80_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x140 18. "PADCONFIG80_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x140 17. "PADCONFIG80_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x140 16. "PADCONFIG80_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x140 15. "PADCONFIG80_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x140 14. "PADCONFIG80_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x140 11.--13. "PADCONFIG80_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 8. "PADCONFIG80_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x140 7. "PADCONFIG80_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x140 0.--3. "PADCONFIG80_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x144 "CFG0_PADCONFIG81_PROXY,"
bitfld.long 0x144 31. "PADCONFIG81_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x144 30. "PADCONFIG81_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x144 29. "PADCONFIG81_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x144 28. "PADCONFIG81_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x144 27. "PADCONFIG81_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x144 26. "PADCONFIG81_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x144 25. "PADCONFIG81_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x144 24. "PADCONFIG81_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x144 23. "PADCONFIG81_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x144 22. "PADCONFIG81_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x144 21. "PADCONFIG81_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x144 19.--20. "PADCONFIG81_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x144 18. "PADCONFIG81_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x144 17. "PADCONFIG81_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x144 16. "PADCONFIG81_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x144 15. "PADCONFIG81_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x144 14. "PADCONFIG81_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x144 11.--13. "PADCONFIG81_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 8. "PADCONFIG81_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x144 7. "PADCONFIG81_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x144 0.--3. "PADCONFIG81_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x148 "CFG0_PADCONFIG82_PROXY,"
bitfld.long 0x148 31. "PADCONFIG82_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x148 30. "PADCONFIG82_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x148 29. "PADCONFIG82_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x148 28. "PADCONFIG82_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x148 27. "PADCONFIG82_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x148 26. "PADCONFIG82_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x148 25. "PADCONFIG82_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x148 24. "PADCONFIG82_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x148 23. "PADCONFIG82_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x148 22. "PADCONFIG82_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x148 21. "PADCONFIG82_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x148 19.--20. "PADCONFIG82_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x148 18. "PADCONFIG82_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x148 17. "PADCONFIG82_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x148 16. "PADCONFIG82_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x148 15. "PADCONFIG82_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x148 14. "PADCONFIG82_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x148 11.--13. "PADCONFIG82_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x148 8. "PADCONFIG82_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x148 7. "PADCONFIG82_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x148 0.--3. "PADCONFIG82_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x14C "CFG0_PADCONFIG83_PROXY,"
bitfld.long 0x14C 31. "PADCONFIG83_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x14C 30. "PADCONFIG83_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x14C 29. "PADCONFIG83_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x14C 28. "PADCONFIG83_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x14C 27. "PADCONFIG83_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x14C 26. "PADCONFIG83_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x14C 25. "PADCONFIG83_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x14C 24. "PADCONFIG83_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x14C 23. "PADCONFIG83_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x14C 22. "PADCONFIG83_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x14C 21. "PADCONFIG83_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x14C 19.--20. "PADCONFIG83_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x14C 18. "PADCONFIG83_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x14C 17. "PADCONFIG83_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x14C 16. "PADCONFIG83_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x14C 15. "PADCONFIG83_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x14C 14. "PADCONFIG83_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x14C 11.--13. "PADCONFIG83_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14C 8. "PADCONFIG83_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x14C 7. "PADCONFIG83_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x14C 0.--3. "PADCONFIG83_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x150 "CFG0_PADCONFIG84_PROXY,"
bitfld.long 0x150 31. "PADCONFIG84_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x150 30. "PADCONFIG84_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x150 29. "PADCONFIG84_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x150 28. "PADCONFIG84_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x150 27. "PADCONFIG84_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x150 26. "PADCONFIG84_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x150 25. "PADCONFIG84_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x150 24. "PADCONFIG84_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x150 23. "PADCONFIG84_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x150 22. "PADCONFIG84_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x150 21. "PADCONFIG84_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x150 19.--20. "PADCONFIG84_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x150 18. "PADCONFIG84_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x150 17. "PADCONFIG84_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x150 16. "PADCONFIG84_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x150 15. "PADCONFIG84_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x150 14. "PADCONFIG84_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x150 11.--13. "PADCONFIG84_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x150 8. "PADCONFIG84_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x150 7. "PADCONFIG84_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x150 0.--3. "PADCONFIG84_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x154 "CFG0_PADCONFIG85_PROXY,"
bitfld.long 0x154 31. "PADCONFIG85_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x154 30. "PADCONFIG85_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x154 29. "PADCONFIG85_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x154 28. "PADCONFIG85_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x154 27. "PADCONFIG85_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x154 26. "PADCONFIG85_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x154 25. "PADCONFIG85_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x154 24. "PADCONFIG85_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x154 23. "PADCONFIG85_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x154 22. "PADCONFIG85_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x154 21. "PADCONFIG85_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x154 19.--20. "PADCONFIG85_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x154 18. "PADCONFIG85_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x154 17. "PADCONFIG85_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x154 16. "PADCONFIG85_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x154 15. "PADCONFIG85_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x154 14. "PADCONFIG85_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x154 11.--13. "PADCONFIG85_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x154 8. "PADCONFIG85_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x154 7. "PADCONFIG85_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x154 0.--3. "PADCONFIG85_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x158 "CFG0_PADCONFIG86_PROXY,"
bitfld.long 0x158 31. "PADCONFIG86_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x158 30. "PADCONFIG86_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x158 29. "PADCONFIG86_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x158 28. "PADCONFIG86_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x158 27. "PADCONFIG86_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x158 26. "PADCONFIG86_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x158 25. "PADCONFIG86_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x158 24. "PADCONFIG86_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x158 23. "PADCONFIG86_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x158 22. "PADCONFIG86_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x158 21. "PADCONFIG86_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x158 19.--20. "PADCONFIG86_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x158 18. "PADCONFIG86_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x158 17. "PADCONFIG86_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x158 16. "PADCONFIG86_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x158 15. "PADCONFIG86_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x158 14. "PADCONFIG86_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x158 11.--13. "PADCONFIG86_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x158 8. "PADCONFIG86_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x158 7. "PADCONFIG86_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x158 0.--3. "PADCONFIG86_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x15C "CFG0_PADCONFIG87_PROXY,"
bitfld.long 0x15C 31. "PADCONFIG87_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x15C 30. "PADCONFIG87_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x15C 29. "PADCONFIG87_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x15C 28. "PADCONFIG87_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x15C 27. "PADCONFIG87_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x15C 26. "PADCONFIG87_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x15C 25. "PADCONFIG87_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x15C 24. "PADCONFIG87_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x15C 23. "PADCONFIG87_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x15C 22. "PADCONFIG87_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x15C 21. "PADCONFIG87_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x15C 19.--20. "PADCONFIG87_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x15C 18. "PADCONFIG87_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x15C 17. "PADCONFIG87_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x15C 16. "PADCONFIG87_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x15C 15. "PADCONFIG87_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x15C 14. "PADCONFIG87_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x15C 11.--13. "PADCONFIG87_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x15C 8. "PADCONFIG87_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x15C 7. "PADCONFIG87_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x15C 0.--3. "PADCONFIG87_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x160 "CFG0_PADCONFIG88_PROXY,"
bitfld.long 0x160 31. "PADCONFIG88_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x160 30. "PADCONFIG88_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x160 29. "PADCONFIG88_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x160 28. "PADCONFIG88_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x160 27. "PADCONFIG88_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x160 26. "PADCONFIG88_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x160 25. "PADCONFIG88_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x160 24. "PADCONFIG88_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x160 23. "PADCONFIG88_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x160 22. "PADCONFIG88_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x160 21. "PADCONFIG88_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x160 19.--20. "PADCONFIG88_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x160 18. "PADCONFIG88_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x160 17. "PADCONFIG88_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x160 16. "PADCONFIG88_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x160 15. "PADCONFIG88_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x160 14. "PADCONFIG88_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x160 11.--13. "PADCONFIG88_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x160 8. "PADCONFIG88_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x160 7. "PADCONFIG88_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x160 0.--3. "PADCONFIG88_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x164 "CFG0_PADCONFIG89_PROXY,"
bitfld.long 0x164 31. "PADCONFIG89_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x164 30. "PADCONFIG89_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x164 29. "PADCONFIG89_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x164 28. "PADCONFIG89_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x164 27. "PADCONFIG89_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x164 26. "PADCONFIG89_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x164 25. "PADCONFIG89_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x164 24. "PADCONFIG89_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x164 23. "PADCONFIG89_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x164 22. "PADCONFIG89_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x164 21. "PADCONFIG89_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x164 19.--20. "PADCONFIG89_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x164 18. "PADCONFIG89_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x164 17. "PADCONFIG89_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x164 16. "PADCONFIG89_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x164 15. "PADCONFIG89_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x164 14. "PADCONFIG89_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x164 11.--13. "PADCONFIG89_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x164 8. "PADCONFIG89_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x164 7. "PADCONFIG89_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x164 0.--3. "PADCONFIG89_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x168 "CFG0_PADCONFIG90_PROXY,"
bitfld.long 0x168 31. "PADCONFIG90_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x168 30. "PADCONFIG90_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x168 29. "PADCONFIG90_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x168 28. "PADCONFIG90_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x168 27. "PADCONFIG90_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x168 26. "PADCONFIG90_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x168 25. "PADCONFIG90_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x168 24. "PADCONFIG90_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x168 23. "PADCONFIG90_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x168 22. "PADCONFIG90_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x168 21. "PADCONFIG90_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x168 19.--20. "PADCONFIG90_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x168 18. "PADCONFIG90_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x168 17. "PADCONFIG90_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x168 16. "PADCONFIG90_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x168 15. "PADCONFIG90_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x168 14. "PADCONFIG90_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x168 11.--13. "PADCONFIG90_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x168 8. "PADCONFIG90_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x168 7. "PADCONFIG90_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x168 0.--3. "PADCONFIG90_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x16C "CFG0_PADCONFIG91_PROXY,"
bitfld.long 0x16C 31. "PADCONFIG91_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x16C 30. "PADCONFIG91_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x16C 29. "PADCONFIG91_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x16C 28. "PADCONFIG91_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x16C 27. "PADCONFIG91_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x16C 26. "PADCONFIG91_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x16C 25. "PADCONFIG91_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x16C 24. "PADCONFIG91_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x16C 23. "PADCONFIG91_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x16C 22. "PADCONFIG91_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x16C 21. "PADCONFIG91_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x16C 19.--20. "PADCONFIG91_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x16C 18. "PADCONFIG91_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x16C 17. "PADCONFIG91_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x16C 16. "PADCONFIG91_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x16C 15. "PADCONFIG91_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x16C 14. "PADCONFIG91_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x16C 11.--13. "PADCONFIG91_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x16C 8. "PADCONFIG91_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x16C 7. "PADCONFIG91_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x16C 0.--3. "PADCONFIG91_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x170 "CFG0_PADCONFIG92_PROXY,"
bitfld.long 0x170 31. "PADCONFIG92_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x170 30. "PADCONFIG92_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x170 29. "PADCONFIG92_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x170 28. "PADCONFIG92_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x170 27. "PADCONFIG92_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x170 26. "PADCONFIG92_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x170 25. "PADCONFIG92_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x170 24. "PADCONFIG92_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x170 23. "PADCONFIG92_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x170 22. "PADCONFIG92_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x170 21. "PADCONFIG92_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x170 19.--20. "PADCONFIG92_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x170 18. "PADCONFIG92_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x170 17. "PADCONFIG92_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x170 16. "PADCONFIG92_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x170 15. "PADCONFIG92_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x170 14. "PADCONFIG92_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x170 11.--13. "PADCONFIG92_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x170 8. "PADCONFIG92_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x170 7. "PADCONFIG92_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x170 0.--3. "PADCONFIG92_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x174 "CFG0_PADCONFIG93_PROXY,"
bitfld.long 0x174 31. "PADCONFIG93_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x174 30. "PADCONFIG93_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x174 29. "PADCONFIG93_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x174 28. "PADCONFIG93_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x174 27. "PADCONFIG93_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x174 26. "PADCONFIG93_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x174 25. "PADCONFIG93_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x174 24. "PADCONFIG93_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x174 23. "PADCONFIG93_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x174 22. "PADCONFIG93_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x174 21. "PADCONFIG93_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x174 19.--20. "PADCONFIG93_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x174 18. "PADCONFIG93_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x174 17. "PADCONFIG93_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x174 16. "PADCONFIG93_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x174 15. "PADCONFIG93_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x174 14. "PADCONFIG93_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x174 11.--13. "PADCONFIG93_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x174 8. "PADCONFIG93_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x174 7. "PADCONFIG93_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x174 0.--3. "PADCONFIG93_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x178 "CFG0_PADCONFIG94_PROXY,"
bitfld.long 0x178 31. "PADCONFIG94_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x178 30. "PADCONFIG94_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x178 29. "PADCONFIG94_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x178 28. "PADCONFIG94_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x178 27. "PADCONFIG94_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x178 26. "PADCONFIG94_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x178 25. "PADCONFIG94_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x178 24. "PADCONFIG94_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x178 23. "PADCONFIG94_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x178 22. "PADCONFIG94_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x178 21. "PADCONFIG94_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x178 19.--20. "PADCONFIG94_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x178 18. "PADCONFIG94_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x178 17. "PADCONFIG94_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x178 16. "PADCONFIG94_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x178 15. "PADCONFIG94_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x178 14. "PADCONFIG94_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x178 11.--13. "PADCONFIG94_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x178 8. "PADCONFIG94_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x178 7. "PADCONFIG94_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x178 0.--3. "PADCONFIG94_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x17C "CFG0_PADCONFIG95_PROXY,"
bitfld.long 0x17C 31. "PADCONFIG95_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x17C 30. "PADCONFIG95_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x17C 29. "PADCONFIG95_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x17C 28. "PADCONFIG95_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x17C 27. "PADCONFIG95_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x17C 26. "PADCONFIG95_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x17C 25. "PADCONFIG95_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x17C 24. "PADCONFIG95_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x17C 23. "PADCONFIG95_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x17C 22. "PADCONFIG95_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x17C 21. "PADCONFIG95_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x17C 19.--20. "PADCONFIG95_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x17C 18. "PADCONFIG95_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x17C 17. "PADCONFIG95_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x17C 16. "PADCONFIG95_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x17C 15. "PADCONFIG95_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x17C 14. "PADCONFIG95_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x17C 11.--13. "PADCONFIG95_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x17C 8. "PADCONFIG95_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x17C 7. "PADCONFIG95_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x17C 0.--3. "PADCONFIG95_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x180 "CFG0_PADCONFIG96_PROXY,"
bitfld.long 0x180 31. "PADCONFIG96_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x180 30. "PADCONFIG96_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x180 29. "PADCONFIG96_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x180 28. "PADCONFIG96_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x180 27. "PADCONFIG96_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x180 26. "PADCONFIG96_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x180 25. "PADCONFIG96_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x180 24. "PADCONFIG96_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x180 23. "PADCONFIG96_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x180 22. "PADCONFIG96_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x180 21. "PADCONFIG96_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x180 19.--20. "PADCONFIG96_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x180 18. "PADCONFIG96_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x180 17. "PADCONFIG96_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x180 16. "PADCONFIG96_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x180 15. "PADCONFIG96_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x180 14. "PADCONFIG96_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x180 11.--13. "PADCONFIG96_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x180 8. "PADCONFIG96_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x180 7. "PADCONFIG96_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x180 0.--3. "PADCONFIG96_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x184 "CFG0_PADCONFIG97_PROXY,"
bitfld.long 0x184 31. "PADCONFIG97_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x184 30. "PADCONFIG97_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x184 29. "PADCONFIG97_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x184 28. "PADCONFIG97_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x184 27. "PADCONFIG97_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x184 26. "PADCONFIG97_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x184 25. "PADCONFIG97_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x184 24. "PADCONFIG97_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x184 23. "PADCONFIG97_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x184 22. "PADCONFIG97_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x184 21. "PADCONFIG97_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x184 19.--20. "PADCONFIG97_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x184 18. "PADCONFIG97_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x184 17. "PADCONFIG97_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x184 16. "PADCONFIG97_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x184 15. "PADCONFIG97_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x184 14. "PADCONFIG97_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x184 11.--13. "PADCONFIG97_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x184 8. "PADCONFIG97_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x184 7. "PADCONFIG97_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x184 0.--3. "PADCONFIG97_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x188 "CFG0_PADCONFIG98_PROXY,"
bitfld.long 0x188 31. "PADCONFIG98_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x188 30. "PADCONFIG98_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x188 29. "PADCONFIG98_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x188 28. "PADCONFIG98_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x188 27. "PADCONFIG98_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x188 26. "PADCONFIG98_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x188 25. "PADCONFIG98_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x188 24. "PADCONFIG98_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x188 23. "PADCONFIG98_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x188 22. "PADCONFIG98_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x188 21. "PADCONFIG98_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x188 19.--20. "PADCONFIG98_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x188 18. "PADCONFIG98_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x188 17. "PADCONFIG98_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x188 16. "PADCONFIG98_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x188 15. "PADCONFIG98_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x188 14. "PADCONFIG98_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x188 11.--13. "PADCONFIG98_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x188 8. "PADCONFIG98_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x188 7. "PADCONFIG98_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x188 0.--3. "PADCONFIG98_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x18C "CFG0_PADCONFIG99_PROXY,"
bitfld.long 0x18C 31. "PADCONFIG99_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x18C 30. "PADCONFIG99_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x18C 29. "PADCONFIG99_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x18C 28. "PADCONFIG99_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x18C 27. "PADCONFIG99_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x18C 26. "PADCONFIG99_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x18C 25. "PADCONFIG99_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x18C 24. "PADCONFIG99_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x18C 23. "PADCONFIG99_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x18C 22. "PADCONFIG99_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x18C 21. "PADCONFIG99_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x18C 19.--20. "PADCONFIG99_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x18C 18. "PADCONFIG99_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x18C 17. "PADCONFIG99_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x18C 16. "PADCONFIG99_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x18C 15. "PADCONFIG99_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x18C 14. "PADCONFIG99_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x18C 11.--13. "PADCONFIG99_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18C 8. "PADCONFIG99_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x18C 7. "PADCONFIG99_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x18C 0.--3. "PADCONFIG99_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x190 "CFG0_PADCONFIG100_PROXY,"
bitfld.long 0x190 31. "PADCONFIG100_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x190 30. "PADCONFIG100_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x190 29. "PADCONFIG100_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x190 28. "PADCONFIG100_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x190 27. "PADCONFIG100_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x190 26. "PADCONFIG100_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x190 25. "PADCONFIG100_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x190 24. "PADCONFIG100_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x190 23. "PADCONFIG100_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x190 22. "PADCONFIG100_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x190 21. "PADCONFIG100_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x190 19.--20. "PADCONFIG100_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x190 18. "PADCONFIG100_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x190 17. "PADCONFIG100_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x190 16. "PADCONFIG100_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x190 15. "PADCONFIG100_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x190 14. "PADCONFIG100_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x190 11.--13. "PADCONFIG100_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x190 8. "PADCONFIG100_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x190 7. "PADCONFIG100_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x190 0.--3. "PADCONFIG100_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x194 "CFG0_PADCONFIG101_PROXY,"
bitfld.long 0x194 31. "PADCONFIG101_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x194 30. "PADCONFIG101_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x194 29. "PADCONFIG101_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x194 28. "PADCONFIG101_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x194 27. "PADCONFIG101_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x194 26. "PADCONFIG101_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x194 25. "PADCONFIG101_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x194 24. "PADCONFIG101_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x194 23. "PADCONFIG101_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x194 22. "PADCONFIG101_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x194 21. "PADCONFIG101_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x194 19.--20. "PADCONFIG101_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x194 18. "PADCONFIG101_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x194 17. "PADCONFIG101_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x194 16. "PADCONFIG101_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x194 15. "PADCONFIG101_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x194 14. "PADCONFIG101_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x194 11.--13. "PADCONFIG101_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x194 8. "PADCONFIG101_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x194 7. "PADCONFIG101_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x194 0.--3. "PADCONFIG101_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x198 "CFG0_PADCONFIG102_PROXY,"
bitfld.long 0x198 31. "PADCONFIG102_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x198 30. "PADCONFIG102_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x198 29. "PADCONFIG102_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x198 28. "PADCONFIG102_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x198 27. "PADCONFIG102_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x198 26. "PADCONFIG102_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x198 25. "PADCONFIG102_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x198 24. "PADCONFIG102_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x198 23. "PADCONFIG102_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x198 22. "PADCONFIG102_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x198 21. "PADCONFIG102_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x198 19.--20. "PADCONFIG102_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x198 18. "PADCONFIG102_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x198 17. "PADCONFIG102_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x198 16. "PADCONFIG102_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x198 15. "PADCONFIG102_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x198 14. "PADCONFIG102_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x198 11.--13. "PADCONFIG102_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x198 8. "PADCONFIG102_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x198 7. "PADCONFIG102_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x198 0.--3. "PADCONFIG102_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x19C "CFG0_PADCONFIG103_PROXY,"
bitfld.long 0x19C 31. "PADCONFIG103_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x19C 30. "PADCONFIG103_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x19C 29. "PADCONFIG103_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x19C 28. "PADCONFIG103_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x19C 27. "PADCONFIG103_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x19C 26. "PADCONFIG103_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x19C 25. "PADCONFIG103_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x19C 24. "PADCONFIG103_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x19C 23. "PADCONFIG103_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x19C 22. "PADCONFIG103_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x19C 21. "PADCONFIG103_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x19C 19.--20. "PADCONFIG103_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x19C 18. "PADCONFIG103_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x19C 17. "PADCONFIG103_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x19C 16. "PADCONFIG103_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x19C 15. "PADCONFIG103_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x19C 14. "PADCONFIG103_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x19C 11.--13. "PADCONFIG103_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x19C 8. "PADCONFIG103_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x19C 7. "PADCONFIG103_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x19C 0.--3. "PADCONFIG103_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1A0 "CFG0_PADCONFIG104_PROXY,"
bitfld.long 0x1A0 31. "PADCONFIG104_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1A0 30. "PADCONFIG104_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1A0 29. "PADCONFIG104_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1A0 28. "PADCONFIG104_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1A0 27. "PADCONFIG104_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1A0 26. "PADCONFIG104_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1A0 25. "PADCONFIG104_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1A0 24. "PADCONFIG104_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1A0 23. "PADCONFIG104_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1A0 22. "PADCONFIG104_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1A0 21. "PADCONFIG104_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1A0 19.--20. "PADCONFIG104_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1A0 18. "PADCONFIG104_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1A0 17. "PADCONFIG104_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1A0 16. "PADCONFIG104_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1A0 15. "PADCONFIG104_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1A0 14. "PADCONFIG104_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1A0 11.--13. "PADCONFIG104_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1A0 8. "PADCONFIG104_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1A0 7. "PADCONFIG104_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1A0 0.--3. "PADCONFIG104_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1A4 "CFG0_PADCONFIG105_PROXY,"
bitfld.long 0x1A4 31. "PADCONFIG105_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1A4 30. "PADCONFIG105_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1A4 29. "PADCONFIG105_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1A4 28. "PADCONFIG105_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1A4 27. "PADCONFIG105_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1A4 26. "PADCONFIG105_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1A4 25. "PADCONFIG105_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1A4 24. "PADCONFIG105_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1A4 23. "PADCONFIG105_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1A4 22. "PADCONFIG105_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1A4 21. "PADCONFIG105_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1A4 19.--20. "PADCONFIG105_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1A4 18. "PADCONFIG105_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1A4 17. "PADCONFIG105_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1A4 16. "PADCONFIG105_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1A4 15. "PADCONFIG105_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1A4 14. "PADCONFIG105_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1A4 11.--13. "PADCONFIG105_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1A4 8. "PADCONFIG105_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1A4 7. "PADCONFIG105_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1A4 0.--3. "PADCONFIG105_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1A8 "CFG0_PADCONFIG106_PROXY,"
bitfld.long 0x1A8 31. "PADCONFIG106_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1A8 30. "PADCONFIG106_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1A8 29. "PADCONFIG106_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1A8 28. "PADCONFIG106_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1A8 27. "PADCONFIG106_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1A8 26. "PADCONFIG106_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1A8 25. "PADCONFIG106_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1A8 24. "PADCONFIG106_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1A8 23. "PADCONFIG106_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1A8 22. "PADCONFIG106_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1A8 21. "PADCONFIG106_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1A8 19.--20. "PADCONFIG106_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1A8 18. "PADCONFIG106_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1A8 17. "PADCONFIG106_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1A8 16. "PADCONFIG106_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1A8 15. "PADCONFIG106_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1A8 14. "PADCONFIG106_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1A8 11.--13. "PADCONFIG106_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1A8 8. "PADCONFIG106_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1A8 7. "PADCONFIG106_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1A8 0.--3. "PADCONFIG106_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1AC "CFG0_PADCONFIG107_PROXY,"
bitfld.long 0x1AC 31. "PADCONFIG107_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1AC 30. "PADCONFIG107_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1AC 29. "PADCONFIG107_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1AC 28. "PADCONFIG107_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1AC 27. "PADCONFIG107_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1AC 26. "PADCONFIG107_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1AC 25. "PADCONFIG107_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1AC 24. "PADCONFIG107_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1AC 23. "PADCONFIG107_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1AC 22. "PADCONFIG107_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1AC 21. "PADCONFIG107_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1AC 19.--20. "PADCONFIG107_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1AC 18. "PADCONFIG107_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1AC 17. "PADCONFIG107_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1AC 16. "PADCONFIG107_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1AC 15. "PADCONFIG107_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1AC 14. "PADCONFIG107_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1AC 11.--13. "PADCONFIG107_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1AC 8. "PADCONFIG107_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1AC 7. "PADCONFIG107_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1AC 0.--3. "PADCONFIG107_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1B0 "CFG0_PADCONFIG108_PROXY,"
bitfld.long 0x1B0 31. "PADCONFIG108_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1B0 30. "PADCONFIG108_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1B0 29. "PADCONFIG108_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1B0 28. "PADCONFIG108_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1B0 27. "PADCONFIG108_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1B0 26. "PADCONFIG108_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1B0 25. "PADCONFIG108_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1B0 24. "PADCONFIG108_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1B0 23. "PADCONFIG108_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1B0 22. "PADCONFIG108_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1B0 21. "PADCONFIG108_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1B0 19.--20. "PADCONFIG108_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1B0 18. "PADCONFIG108_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1B0 17. "PADCONFIG108_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1B0 16. "PADCONFIG108_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1B0 15. "PADCONFIG108_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1B0 14. "PADCONFIG108_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1B0 11.--13. "PADCONFIG108_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1B0 8. "PADCONFIG108_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1B0 7. "PADCONFIG108_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1B0 0.--3. "PADCONFIG108_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1B4 "CFG0_PADCONFIG109_PROXY,"
bitfld.long 0x1B4 31. "PADCONFIG109_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1B4 30. "PADCONFIG109_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1B4 29. "PADCONFIG109_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1B4 28. "PADCONFIG109_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1B4 27. "PADCONFIG109_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1B4 26. "PADCONFIG109_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1B4 25. "PADCONFIG109_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1B4 24. "PADCONFIG109_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1B4 23. "PADCONFIG109_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1B4 22. "PADCONFIG109_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1B4 21. "PADCONFIG109_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1B4 19.--20. "PADCONFIG109_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1B4 18. "PADCONFIG109_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1B4 17. "PADCONFIG109_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1B4 16. "PADCONFIG109_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1B4 15. "PADCONFIG109_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1B4 14. "PADCONFIG109_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1B4 11.--13. "PADCONFIG109_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1B4 8. "PADCONFIG109_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1B4 7. "PADCONFIG109_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1B4 0.--3. "PADCONFIG109_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1B8 "CFG0_PADCONFIG110_PROXY,"
bitfld.long 0x1B8 31. "PADCONFIG110_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1B8 30. "PADCONFIG110_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1B8 29. "PADCONFIG110_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1B8 28. "PADCONFIG110_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1B8 27. "PADCONFIG110_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1B8 26. "PADCONFIG110_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1B8 25. "PADCONFIG110_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1B8 24. "PADCONFIG110_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1B8 23. "PADCONFIG110_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1B8 22. "PADCONFIG110_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1B8 21. "PADCONFIG110_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1B8 19.--20. "PADCONFIG110_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1B8 18. "PADCONFIG110_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1B8 17. "PADCONFIG110_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1B8 16. "PADCONFIG110_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1B8 15. "PADCONFIG110_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1B8 14. "PADCONFIG110_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1B8 11.--13. "PADCONFIG110_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1B8 8. "PADCONFIG110_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1B8 7. "PADCONFIG110_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1B8 0.--3. "PADCONFIG110_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1BC "CFG0_PADCONFIG111_PROXY,"
bitfld.long 0x1BC 31. "PADCONFIG111_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1BC 30. "PADCONFIG111_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1BC 29. "PADCONFIG111_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1BC 28. "PADCONFIG111_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1BC 27. "PADCONFIG111_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1BC 26. "PADCONFIG111_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1BC 25. "PADCONFIG111_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1BC 24. "PADCONFIG111_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1BC 23. "PADCONFIG111_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1BC 22. "PADCONFIG111_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1BC 21. "PADCONFIG111_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1BC 19.--20. "PADCONFIG111_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1BC 18. "PADCONFIG111_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1BC 17. "PADCONFIG111_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1BC 16. "PADCONFIG111_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1BC 15. "PADCONFIG111_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1BC 14. "PADCONFIG111_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1BC 11.--13. "PADCONFIG111_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1BC 8. "PADCONFIG111_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1BC 7. "PADCONFIG111_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1BC 0.--3. "PADCONFIG111_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C0 "CFG0_PADCONFIG112_PROXY,"
bitfld.long 0x1C0 31. "PADCONFIG112_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C0 30. "PADCONFIG112_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C0 29. "PADCONFIG112_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1C0 28. "PADCONFIG112_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1C0 27. "PADCONFIG112_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C0 26. "PADCONFIG112_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1C0 25. "PADCONFIG112_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C0 24. "PADCONFIG112_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1C0 23. "PADCONFIG112_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1C0 22. "PADCONFIG112_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1C0 21. "PADCONFIG112_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1C0 19.--20. "PADCONFIG112_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1C0 18. "PADCONFIG112_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1C0 17. "PADCONFIG112_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1C0 16. "PADCONFIG112_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C0 15. "PADCONFIG112_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1C0 14. "PADCONFIG112_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C0 11.--13. "PADCONFIG112_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C0 8. "PADCONFIG112_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1C0 7. "PADCONFIG112_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1C0 0.--3. "PADCONFIG112_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C4 "CFG0_PADCONFIG113_PROXY,"
bitfld.long 0x1C4 31. "PADCONFIG113_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C4 30. "PADCONFIG113_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C4 29. "PADCONFIG113_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1C4 28. "PADCONFIG113_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1C4 27. "PADCONFIG113_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C4 26. "PADCONFIG113_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1C4 25. "PADCONFIG113_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C4 24. "PADCONFIG113_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1C4 23. "PADCONFIG113_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1C4 22. "PADCONFIG113_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1C4 21. "PADCONFIG113_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1C4 19.--20. "PADCONFIG113_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1C4 18. "PADCONFIG113_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1C4 17. "PADCONFIG113_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1C4 16. "PADCONFIG113_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C4 15. "PADCONFIG113_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1C4 14. "PADCONFIG113_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C4 11.--13. "PADCONFIG113_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C4 8. "PADCONFIG113_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1C4 7. "PADCONFIG113_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1C4 0.--3. "PADCONFIG113_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C8 "CFG0_PADCONFIG114_PROXY,"
bitfld.long 0x1C8 31. "PADCONFIG114_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C8 30. "PADCONFIG114_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C8 29. "PADCONFIG114_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1C8 28. "PADCONFIG114_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1C8 27. "PADCONFIG114_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C8 26. "PADCONFIG114_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1C8 25. "PADCONFIG114_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C8 24. "PADCONFIG114_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1C8 23. "PADCONFIG114_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1C8 22. "PADCONFIG114_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1C8 21. "PADCONFIG114_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1C8 19.--20. "PADCONFIG114_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1C8 18. "PADCONFIG114_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1C8 17. "PADCONFIG114_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1C8 16. "PADCONFIG114_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C8 15. "PADCONFIG114_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1C8 14. "PADCONFIG114_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C8 11.--13. "PADCONFIG114_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C8 8. "PADCONFIG114_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1C8 7. "PADCONFIG114_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1C8 0.--3. "PADCONFIG114_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1CC "CFG0_PADCONFIG115_PROXY,"
bitfld.long 0x1CC 31. "PADCONFIG115_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1CC 30. "PADCONFIG115_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1CC 29. "PADCONFIG115_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1CC 28. "PADCONFIG115_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1CC 27. "PADCONFIG115_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1CC 26. "PADCONFIG115_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1CC 25. "PADCONFIG115_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1CC 24. "PADCONFIG115_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1CC 23. "PADCONFIG115_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1CC 22. "PADCONFIG115_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1CC 21. "PADCONFIG115_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1CC 19.--20. "PADCONFIG115_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1CC 18. "PADCONFIG115_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1CC 17. "PADCONFIG115_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1CC 16. "PADCONFIG115_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1CC 15. "PADCONFIG115_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1CC 14. "PADCONFIG115_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1CC 11.--13. "PADCONFIG115_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1CC 8. "PADCONFIG115_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1CC 7. "PADCONFIG115_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1CC 0.--3. "PADCONFIG115_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1D0 "CFG0_PADCONFIG116_PROXY,"
bitfld.long 0x1D0 31. "PADCONFIG116_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1D0 30. "PADCONFIG116_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1D0 29. "PADCONFIG116_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1D0 28. "PADCONFIG116_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x1D0 27. "PADCONFIG116_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1D0 26. "PADCONFIG116_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1D0 25. "PADCONFIG116_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x1D0 24. "PADCONFIG116_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1D0 23. "PADCONFIG116_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x1D0 22. "PADCONFIG116_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x1D0 21. "PADCONFIG116_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1D0 19.--20. "PADCONFIG116_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1D0 18. "PADCONFIG116_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1D0 17. "PADCONFIG116_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1D0 16. "PADCONFIG116_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1D0 15. "PADCONFIG116_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1D0 14. "PADCONFIG116_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1D0 11.--13. "PADCONFIG116_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1D0 8. "PADCONFIG116_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1D0 7. "PADCONFIG116_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1D0 0.--3. "PADCONFIG116_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1D4 "CFG0_PADCONFIG117_PROXY,"
bitfld.long 0x1D4 31. "PADCONFIG117_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1D4 30. "PADCONFIG117_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1D4 29. "PADCONFIG117_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1D4 28. "PADCONFIG117_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1D4 27. "PADCONFIG117_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1D4 26. "PADCONFIG117_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1D4 25. "PADCONFIG117_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1D4 24. "PADCONFIG117_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1D4 23. "PADCONFIG117_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1D4 22. "PADCONFIG117_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1D4 21. "PADCONFIG117_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1D4 19.--20. "PADCONFIG117_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1D4 18. "PADCONFIG117_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1D4 17. "PADCONFIG117_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1D4 16. "PADCONFIG117_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1D4 15. "PADCONFIG117_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1D4 14. "PADCONFIG117_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1D4 11.--13. "PADCONFIG117_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1D4 8. "PADCONFIG117_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1D4 7. "PADCONFIG117_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1D4 0.--3. "PADCONFIG117_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1D8 "CFG0_PADCONFIG118_PROXY,"
bitfld.long 0x1D8 31. "PADCONFIG118_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1D8 30. "PADCONFIG118_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1D8 29. "PADCONFIG118_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1D8 28. "PADCONFIG118_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1D8 27. "PADCONFIG118_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1D8 26. "PADCONFIG118_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1D8 25. "PADCONFIG118_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1D8 24. "PADCONFIG118_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1D8 23. "PADCONFIG118_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1D8 22. "PADCONFIG118_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1D8 21. "PADCONFIG118_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1D8 19.--20. "PADCONFIG118_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1D8 18. "PADCONFIG118_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1D8 17. "PADCONFIG118_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1D8 16. "PADCONFIG118_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1D8 15. "PADCONFIG118_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1D8 14. "PADCONFIG118_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1D8 11.--13. "PADCONFIG118_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1D8 8. "PADCONFIG118_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1D8 7. "PADCONFIG118_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1D8 0.--3. "PADCONFIG118_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1DC "CFG0_PADCONFIG119_PROXY,"
bitfld.long 0x1DC 31. "PADCONFIG119_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1DC 30. "PADCONFIG119_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1DC 29. "PADCONFIG119_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1DC 28. "PADCONFIG119_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1DC 27. "PADCONFIG119_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1DC 26. "PADCONFIG119_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1DC 25. "PADCONFIG119_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1DC 24. "PADCONFIG119_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1DC 23. "PADCONFIG119_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1DC 22. "PADCONFIG119_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1DC 21. "PADCONFIG119_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1DC 19.--20. "PADCONFIG119_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1DC 18. "PADCONFIG119_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1DC 17. "PADCONFIG119_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1DC 16. "PADCONFIG119_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1DC 15. "PADCONFIG119_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1DC 14. "PADCONFIG119_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1DC 11.--13. "PADCONFIG119_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1DC 8. "PADCONFIG119_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1DC 7. "PADCONFIG119_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1DC 0.--3. "PADCONFIG119_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1E0 "CFG0_PADCONFIG120_PROXY,"
bitfld.long 0x1E0 31. "PADCONFIG120_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1E0 30. "PADCONFIG120_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1E0 29. "PADCONFIG120_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1E0 28. "PADCONFIG120_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1E0 27. "PADCONFIG120_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1E0 26. "PADCONFIG120_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1E0 25. "PADCONFIG120_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1E0 24. "PADCONFIG120_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1E0 23. "PADCONFIG120_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1E0 22. "PADCONFIG120_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1E0 21. "PADCONFIG120_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1E0 19.--20. "PADCONFIG120_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1E0 18. "PADCONFIG120_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1E0 17. "PADCONFIG120_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1E0 16. "PADCONFIG120_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1E0 15. "PADCONFIG120_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1E0 14. "PADCONFIG120_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1E0 11.--13. "PADCONFIG120_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1E0 8. "PADCONFIG120_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1E0 7. "PADCONFIG120_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1E0 0.--3. "PADCONFIG120_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1E4 "CFG0_PADCONFIG121_PROXY,"
bitfld.long 0x1E4 31. "PADCONFIG121_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1E4 30. "PADCONFIG121_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1E4 29. "PADCONFIG121_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1E4 28. "PADCONFIG121_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1E4 27. "PADCONFIG121_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1E4 26. "PADCONFIG121_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1E4 25. "PADCONFIG121_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1E4 24. "PADCONFIG121_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1E4 23. "PADCONFIG121_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1E4 22. "PADCONFIG121_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1E4 21. "PADCONFIG121_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1E4 19.--20. "PADCONFIG121_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1E4 18. "PADCONFIG121_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1E4 17. "PADCONFIG121_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1E4 16. "PADCONFIG121_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1E4 15. "PADCONFIG121_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1E4 14. "PADCONFIG121_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1E4 11.--13. "PADCONFIG121_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1E4 8. "PADCONFIG121_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1E4 7. "PADCONFIG121_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1E4 0.--3. "PADCONFIG121_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1E8 "CFG0_PADCONFIG122_PROXY,"
bitfld.long 0x1E8 31. "PADCONFIG122_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1E8 30. "PADCONFIG122_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1E8 29. "PADCONFIG122_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1E8 28. "PADCONFIG122_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1E8 27. "PADCONFIG122_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1E8 26. "PADCONFIG122_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1E8 25. "PADCONFIG122_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1E8 24. "PADCONFIG122_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1E8 23. "PADCONFIG122_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1E8 22. "PADCONFIG122_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1E8 21. "PADCONFIG122_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1E8 19.--20. "PADCONFIG122_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1E8 18. "PADCONFIG122_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1E8 17. "PADCONFIG122_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1E8 16. "PADCONFIG122_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1E8 15. "PADCONFIG122_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1E8 14. "PADCONFIG122_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1E8 11.--13. "PADCONFIG122_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1E8 8. "PADCONFIG122_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1E8 7. "PADCONFIG122_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1E8 0.--3. "PADCONFIG122_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1EC "CFG0_PADCONFIG123_PROXY,"
bitfld.long 0x1EC 31. "PADCONFIG123_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1EC 30. "PADCONFIG123_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1EC 29. "PADCONFIG123_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1EC 28. "PADCONFIG123_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1EC 27. "PADCONFIG123_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1EC 26. "PADCONFIG123_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1EC 25. "PADCONFIG123_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1EC 24. "PADCONFIG123_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1EC 23. "PADCONFIG123_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1EC 22. "PADCONFIG123_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1EC 21. "PADCONFIG123_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1EC 19.--20. "PADCONFIG123_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1EC 18. "PADCONFIG123_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1EC 17. "PADCONFIG123_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1EC 16. "PADCONFIG123_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1EC 15. "PADCONFIG123_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1EC 14. "PADCONFIG123_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1EC 11.--13. "PADCONFIG123_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1EC 8. "PADCONFIG123_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1EC 7. "PADCONFIG123_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1EC 0.--3. "PADCONFIG123_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1F0 "CFG0_PADCONFIG124_PROXY,"
bitfld.long 0x1F0 31. "PADCONFIG124_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1F0 30. "PADCONFIG124_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1F0 29. "PADCONFIG124_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1F0 28. "PADCONFIG124_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1F0 27. "PADCONFIG124_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1F0 26. "PADCONFIG124_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1F0 25. "PADCONFIG124_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1F0 24. "PADCONFIG124_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1F0 23. "PADCONFIG124_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1F0 22. "PADCONFIG124_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x1F0 21. "PADCONFIG124_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1F0 19.--20. "PADCONFIG124_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1F0 18. "PADCONFIG124_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1F0 17. "PADCONFIG124_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1F0 16. "PADCONFIG124_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1F0 15. "PADCONFIG124_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1F0 14. "PADCONFIG124_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1F0 11.--13. "PADCONFIG124_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1F0 8. "PADCONFIG124_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1F0 7. "PADCONFIG124_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1F0 0.--3. "PADCONFIG124_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1F4 "CFG0_PADCONFIG125_PROXY,"
bitfld.long 0x1F4 31. "PADCONFIG125_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1F4 30. "PADCONFIG125_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1F4 29. "PADCONFIG125_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1F4 28. "PADCONFIG125_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1F4 27. "PADCONFIG125_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1F4 26. "PADCONFIG125_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1F4 25. "PADCONFIG125_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1F4 24. "PADCONFIG125_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1F4 23. "PADCONFIG125_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1F4 22. "PADCONFIG125_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1F4 21. "PADCONFIG125_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1F4 19.--20. "PADCONFIG125_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1F4 18. "PADCONFIG125_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1F4 17. "PADCONFIG125_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1F4 16. "PADCONFIG125_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1F4 15. "PADCONFIG125_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1F4 14. "PADCONFIG125_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1F4 11.--13. "PADCONFIG125_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1F4 8. "PADCONFIG125_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1F4 7. "PADCONFIG125_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1F4 0.--3. "PADCONFIG125_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1F8 "CFG0_PADCONFIG126_PROXY,"
bitfld.long 0x1F8 31. "PADCONFIG126_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1F8 30. "PADCONFIG126_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1F8 29. "PADCONFIG126_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1F8 28. "PADCONFIG126_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1F8 27. "PADCONFIG126_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1F8 26. "PADCONFIG126_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1F8 25. "PADCONFIG126_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1F8 24. "PADCONFIG126_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1F8 23. "PADCONFIG126_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1F8 22. "PADCONFIG126_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x1F8 21. "PADCONFIG126_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1F8 19.--20. "PADCONFIG126_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1F8 18. "PADCONFIG126_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1F8 17. "PADCONFIG126_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1F8 16. "PADCONFIG126_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1F8 15. "PADCONFIG126_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x1F8 14. "PADCONFIG126_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1F8 11.--13. "PADCONFIG126_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1F8 8. "PADCONFIG126_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1F8 7. "PADCONFIG126_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1F8 0.--3. "PADCONFIG126_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1FC "CFG0_PADCONFIG127_PROXY,"
bitfld.long 0x1FC 31. "PADCONFIG127_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1FC 30. "PADCONFIG127_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1FC 29. "PADCONFIG127_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1FC 28. "PADCONFIG127_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1FC 27. "PADCONFIG127_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1FC 26. "PADCONFIG127_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x1FC 25. "PADCONFIG127_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1FC 24. "PADCONFIG127_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1FC 23. "PADCONFIG127_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x1FC 22. "PADCONFIG127_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x1FC 21. "PADCONFIG127_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1FC 19.--20. "PADCONFIG127_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1FC 18. "PADCONFIG127_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1FC 17. "PADCONFIG127_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1FC 16. "PADCONFIG127_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1FC 15. "PADCONFIG127_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x1FC 14. "PADCONFIG127_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1FC 11.--13. "PADCONFIG127_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1FC 8. "PADCONFIG127_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x1FC 7. "PADCONFIG127_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x1FC 0.--3. "PADCONFIG127_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x200 "CFG0_PADCONFIG128_PROXY,"
bitfld.long 0x200 31. "PADCONFIG128_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x200 30. "PADCONFIG128_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x200 29. "PADCONFIG128_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x200 28. "PADCONFIG128_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x200 27. "PADCONFIG128_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x200 26. "PADCONFIG128_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x200 25. "PADCONFIG128_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x200 24. "PADCONFIG128_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x200 23. "PADCONFIG128_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x200 22. "PADCONFIG128_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x200 21. "PADCONFIG128_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x200 19.--20. "PADCONFIG128_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x200 18. "PADCONFIG128_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x200 17. "PADCONFIG128_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x200 16. "PADCONFIG128_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x200 15. "PADCONFIG128_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x200 14. "PADCONFIG128_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x200 11.--13. "PADCONFIG128_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x200 8. "PADCONFIG128_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x200 7. "PADCONFIG128_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x200 0.--3. "PADCONFIG128_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x204 "CFG0_PADCONFIG129_PROXY,"
bitfld.long 0x204 31. "PADCONFIG129_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x204 30. "PADCONFIG129_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x204 29. "PADCONFIG129_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x204 28. "PADCONFIG129_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x204 27. "PADCONFIG129_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x204 26. "PADCONFIG129_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x204 25. "PADCONFIG129_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x204 24. "PADCONFIG129_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x204 23. "PADCONFIG129_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x204 22. "PADCONFIG129_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x204 21. "PADCONFIG129_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x204 19.--20. "PADCONFIG129_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x204 18. "PADCONFIG129_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x204 17. "PADCONFIG129_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x204 16. "PADCONFIG129_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x204 15. "PADCONFIG129_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x204 14. "PADCONFIG129_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x204 11.--13. "PADCONFIG129_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x204 8. "PADCONFIG129_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x204 7. "PADCONFIG129_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x204 0.--3. "PADCONFIG129_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x208 "CFG0_PADCONFIG130_PROXY,"
bitfld.long 0x208 31. "PADCONFIG130_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x208 30. "PADCONFIG130_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x208 29. "PADCONFIG130_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x208 28. "PADCONFIG130_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x208 27. "PADCONFIG130_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x208 26. "PADCONFIG130_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x208 25. "PADCONFIG130_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x208 24. "PADCONFIG130_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x208 23. "PADCONFIG130_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x208 22. "PADCONFIG130_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x208 21. "PADCONFIG130_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x208 19.--20. "PADCONFIG130_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x208 18. "PADCONFIG130_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x208 17. "PADCONFIG130_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x208 16. "PADCONFIG130_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x208 15. "PADCONFIG130_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x208 14. "PADCONFIG130_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x208 11.--13. "PADCONFIG130_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x208 8. "PADCONFIG130_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x208 7. "PADCONFIG130_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x208 0.--3. "PADCONFIG130_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x20C "CFG0_PADCONFIG131_PROXY,"
bitfld.long 0x20C 31. "PADCONFIG131_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x20C 30. "PADCONFIG131_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x20C 29. "PADCONFIG131_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x20C 28. "PADCONFIG131_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x20C 27. "PADCONFIG131_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x20C 26. "PADCONFIG131_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x20C 25. "PADCONFIG131_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x20C 24. "PADCONFIG131_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x20C 23. "PADCONFIG131_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x20C 22. "PADCONFIG131_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x20C 21. "PADCONFIG131_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x20C 19.--20. "PADCONFIG131_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x20C 18. "PADCONFIG131_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x20C 17. "PADCONFIG131_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x20C 16. "PADCONFIG131_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x20C 15. "PADCONFIG131_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x20C 14. "PADCONFIG131_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x20C 11.--13. "PADCONFIG131_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20C 8. "PADCONFIG131_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x20C 7. "PADCONFIG131_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x20C 0.--3. "PADCONFIG131_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x210 "CFG0_PADCONFIG132_PROXY,"
bitfld.long 0x210 31. "PADCONFIG132_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x210 30. "PADCONFIG132_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x210 29. "PADCONFIG132_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x210 28. "PADCONFIG132_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x210 27. "PADCONFIG132_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x210 26. "PADCONFIG132_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x210 25. "PADCONFIG132_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x210 24. "PADCONFIG132_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x210 23. "PADCONFIG132_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x210 22. "PADCONFIG132_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x210 21. "PADCONFIG132_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x210 19.--20. "PADCONFIG132_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x210 18. "PADCONFIG132_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x210 17. "PADCONFIG132_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x210 16. "PADCONFIG132_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x210 15. "PADCONFIG132_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x210 14. "PADCONFIG132_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x210 11.--13. "PADCONFIG132_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x210 8. "PADCONFIG132_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x210 7. "PADCONFIG132_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x210 0.--3. "PADCONFIG132_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x214 "CFG0_PADCONFIG133_PROXY,"
bitfld.long 0x214 31. "PADCONFIG133_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x214 30. "PADCONFIG133_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x214 29. "PADCONFIG133_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x214 28. "PADCONFIG133_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x214 27. "PADCONFIG133_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x214 26. "PADCONFIG133_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x214 25. "PADCONFIG133_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x214 24. "PADCONFIG133_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x214 23. "PADCONFIG133_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x214 22. "PADCONFIG133_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x214 21. "PADCONFIG133_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x214 19.--20. "PADCONFIG133_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x214 18. "PADCONFIG133_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x214 17. "PADCONFIG133_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x214 16. "PADCONFIG133_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x214 15. "PADCONFIG133_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x214 14. "PADCONFIG133_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x214 11.--13. "PADCONFIG133_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x214 8. "PADCONFIG133_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x214 7. "PADCONFIG133_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x214 0.--3. "PADCONFIG133_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x218 "CFG0_PADCONFIG134_PROXY,"
bitfld.long 0x218 31. "PADCONFIG134_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x218 30. "PADCONFIG134_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x218 29. "PADCONFIG134_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x218 28. "PADCONFIG134_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x218 27. "PADCONFIG134_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x218 26. "PADCONFIG134_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x218 25. "PADCONFIG134_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x218 24. "PADCONFIG134_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x218 23. "PADCONFIG134_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x218 22. "PADCONFIG134_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x218 21. "PADCONFIG134_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x218 19.--20. "PADCONFIG134_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x218 18. "PADCONFIG134_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x218 17. "PADCONFIG134_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x218 16. "PADCONFIG134_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x218 15. "PADCONFIG134_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x218 14. "PADCONFIG134_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x218 11.--13. "PADCONFIG134_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x218 8. "PADCONFIG134_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x218 7. "PADCONFIG134_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x218 0.--3. "PADCONFIG134_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x21C "CFG0_PADCONFIG135_PROXY,"
bitfld.long 0x21C 31. "PADCONFIG135_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x21C 30. "PADCONFIG135_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x21C 29. "PADCONFIG135_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x21C 28. "PADCONFIG135_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x21C 27. "PADCONFIG135_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x21C 26. "PADCONFIG135_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x21C 25. "PADCONFIG135_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x21C 24. "PADCONFIG135_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x21C 23. "PADCONFIG135_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x21C 22. "PADCONFIG135_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x21C 21. "PADCONFIG135_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x21C 19.--20. "PADCONFIG135_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x21C 18. "PADCONFIG135_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x21C 17. "PADCONFIG135_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x21C 16. "PADCONFIG135_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x21C 15. "PADCONFIG135_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x21C 14. "PADCONFIG135_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x21C 11.--13. "PADCONFIG135_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x21C 8. "PADCONFIG135_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x21C 7. "PADCONFIG135_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x21C 0.--3. "PADCONFIG135_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x220 "CFG0_PADCONFIG136_PROXY,"
bitfld.long 0x220 31. "PADCONFIG136_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x220 30. "PADCONFIG136_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x220 29. "PADCONFIG136_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x220 28. "PADCONFIG136_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x220 27. "PADCONFIG136_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x220 26. "PADCONFIG136_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x220 25. "PADCONFIG136_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x220 24. "PADCONFIG136_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x220 23. "PADCONFIG136_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x220 22. "PADCONFIG136_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x220 21. "PADCONFIG136_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x220 19.--20. "PADCONFIG136_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x220 18. "PADCONFIG136_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x220 17. "PADCONFIG136_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x220 16. "PADCONFIG136_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x220 15. "PADCONFIG136_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x220 14. "PADCONFIG136_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x220 11.--13. "PADCONFIG136_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x220 8. "PADCONFIG136_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x220 7. "PADCONFIG136_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x220 0.--3. "PADCONFIG136_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x224 "CFG0_PADCONFIG137_PROXY,"
bitfld.long 0x224 31. "PADCONFIG137_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x224 30. "PADCONFIG137_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x224 29. "PADCONFIG137_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x224 28. "PADCONFIG137_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x224 27. "PADCONFIG137_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x224 26. "PADCONFIG137_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x224 25. "PADCONFIG137_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x224 24. "PADCONFIG137_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x224 23. "PADCONFIG137_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x224 22. "PADCONFIG137_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x224 21. "PADCONFIG137_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x224 19.--20. "PADCONFIG137_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x224 18. "PADCONFIG137_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x224 17. "PADCONFIG137_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x224 16. "PADCONFIG137_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x224 15. "PADCONFIG137_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x224 14. "PADCONFIG137_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x224 11.--13. "PADCONFIG137_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x224 8. "PADCONFIG137_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x224 7. "PADCONFIG137_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x224 0.--3. "PADCONFIG137_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x228 "CFG0_PADCONFIG138_PROXY,"
bitfld.long 0x228 31. "PADCONFIG138_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x228 30. "PADCONFIG138_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x228 29. "PADCONFIG138_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x228 28. "PADCONFIG138_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x228 27. "PADCONFIG138_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x228 26. "PADCONFIG138_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x228 25. "PADCONFIG138_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x228 24. "PADCONFIG138_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x228 23. "PADCONFIG138_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x228 22. "PADCONFIG138_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x228 21. "PADCONFIG138_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x228 19.--20. "PADCONFIG138_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x228 18. "PADCONFIG138_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x228 17. "PADCONFIG138_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x228 16. "PADCONFIG138_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x228 15. "PADCONFIG138_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x228 14. "PADCONFIG138_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x228 11.--13. "PADCONFIG138_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x228 8. "PADCONFIG138_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x228 7. "PADCONFIG138_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x228 0.--3. "PADCONFIG138_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x22C "CFG0_PADCONFIG139_PROXY,"
bitfld.long 0x22C 31. "PADCONFIG139_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x22C 30. "PADCONFIG139_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x22C 29. "PADCONFIG139_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x22C 28. "PADCONFIG139_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x22C 27. "PADCONFIG139_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x22C 26. "PADCONFIG139_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x22C 25. "PADCONFIG139_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x22C 24. "PADCONFIG139_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x22C 23. "PADCONFIG139_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x22C 22. "PADCONFIG139_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x22C 21. "PADCONFIG139_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x22C 19.--20. "PADCONFIG139_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x22C 18. "PADCONFIG139_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x22C 17. "PADCONFIG139_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x22C 16. "PADCONFIG139_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x22C 15. "PADCONFIG139_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x22C 14. "PADCONFIG139_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x22C 11.--13. "PADCONFIG139_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x22C 8. "PADCONFIG139_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x22C 7. "PADCONFIG139_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x22C 0.--3. "PADCONFIG139_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x230 "CFG0_PADCONFIG140_PROXY,"
bitfld.long 0x230 31. "PADCONFIG140_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x230 30. "PADCONFIG140_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x230 29. "PADCONFIG140_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x230 28. "PADCONFIG140_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x230 27. "PADCONFIG140_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x230 26. "PADCONFIG140_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x230 25. "PADCONFIG140_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x230 24. "PADCONFIG140_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x230 23. "PADCONFIG140_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x230 22. "PADCONFIG140_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x230 21. "PADCONFIG140_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x230 19.--20. "PADCONFIG140_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x230 18. "PADCONFIG140_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x230 17. "PADCONFIG140_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x230 16. "PADCONFIG140_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x230 15. "PADCONFIG140_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x230 14. "PADCONFIG140_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x230 11.--13. "PADCONFIG140_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x230 8. "PADCONFIG140_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x230 7. "PADCONFIG140_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x230 0.--3. "PADCONFIG140_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x234 "CFG0_PADCONFIG141_PROXY,"
bitfld.long 0x234 31. "PADCONFIG141_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x234 30. "PADCONFIG141_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x234 29. "PADCONFIG141_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x234 28. "PADCONFIG141_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x234 27. "PADCONFIG141_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x234 26. "PADCONFIG141_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x234 25. "PADCONFIG141_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x234 24. "PADCONFIG141_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x234 23. "PADCONFIG141_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x234 22. "PADCONFIG141_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x234 21. "PADCONFIG141_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x234 19.--20. "PADCONFIG141_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x234 18. "PADCONFIG141_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x234 17. "PADCONFIG141_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x234 16. "PADCONFIG141_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x234 15. "PADCONFIG141_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x234 14. "PADCONFIG141_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x234 11.--13. "PADCONFIG141_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x234 8. "PADCONFIG141_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x234 7. "PADCONFIG141_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x234 0.--3. "PADCONFIG141_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x238 "CFG0_PADCONFIG142_PROXY,"
bitfld.long 0x238 31. "PADCONFIG142_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x238 30. "PADCONFIG142_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x238 29. "PADCONFIG142_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x238 28. "PADCONFIG142_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x238 27. "PADCONFIG142_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x238 26. "PADCONFIG142_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x238 25. "PADCONFIG142_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x238 24. "PADCONFIG142_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x238 23. "PADCONFIG142_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x238 22. "PADCONFIG142_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x238 21. "PADCONFIG142_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x238 19.--20. "PADCONFIG142_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x238 18. "PADCONFIG142_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x238 17. "PADCONFIG142_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x238 16. "PADCONFIG142_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x238 15. "PADCONFIG142_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x238 14. "PADCONFIG142_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x238 11.--13. "PADCONFIG142_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x238 8. "PADCONFIG142_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x238 7. "PADCONFIG142_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x238 0.--3. "PADCONFIG142_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x23C "CFG0_PADCONFIG143_PROXY,"
bitfld.long 0x23C 31. "PADCONFIG143_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x23C 30. "PADCONFIG143_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x23C 29. "PADCONFIG143_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x23C 28. "PADCONFIG143_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x23C 27. "PADCONFIG143_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x23C 26. "PADCONFIG143_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x23C 25. "PADCONFIG143_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x23C 24. "PADCONFIG143_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x23C 23. "PADCONFIG143_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x23C 22. "PADCONFIG143_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x23C 21. "PADCONFIG143_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x23C 19.--20. "PADCONFIG143_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x23C 18. "PADCONFIG143_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x23C 17. "PADCONFIG143_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x23C 16. "PADCONFIG143_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x23C 15. "PADCONFIG143_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x23C 14. "PADCONFIG143_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x23C 11.--13. "PADCONFIG143_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x23C 8. "PADCONFIG143_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x23C 7. "PADCONFIG143_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x23C 0.--3. "PADCONFIG143_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x240 "CFG0_PADCONFIG144_PROXY,"
bitfld.long 0x240 31. "PADCONFIG144_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x240 30. "PADCONFIG144_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x240 29. "PADCONFIG144_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x240 28. "PADCONFIG144_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x240 27. "PADCONFIG144_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x240 26. "PADCONFIG144_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x240 25. "PADCONFIG144_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x240 24. "PADCONFIG144_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x240 23. "PADCONFIG144_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x240 22. "PADCONFIG144_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x240 21. "PADCONFIG144_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x240 19.--20. "PADCONFIG144_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x240 18. "PADCONFIG144_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x240 17. "PADCONFIG144_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x240 16. "PADCONFIG144_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x240 15. "PADCONFIG144_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x240 14. "PADCONFIG144_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x240 11.--13. "PADCONFIG144_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x240 8. "PADCONFIG144_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x240 7. "PADCONFIG144_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x240 0.--3. "PADCONFIG144_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x244 "CFG0_PADCONFIG145_PROXY,"
bitfld.long 0x244 31. "PADCONFIG145_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x244 30. "PADCONFIG145_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x244 29. "PADCONFIG145_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x244 28. "PADCONFIG145_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x244 27. "PADCONFIG145_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x244 26. "PADCONFIG145_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x244 25. "PADCONFIG145_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x244 24. "PADCONFIG145_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x244 23. "PADCONFIG145_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x244 22. "PADCONFIG145_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x244 21. "PADCONFIG145_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x244 19.--20. "PADCONFIG145_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x244 18. "PADCONFIG145_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x244 17. "PADCONFIG145_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x244 16. "PADCONFIG145_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x244 15. "PADCONFIG145_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x244 14. "PADCONFIG145_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x244 11.--13. "PADCONFIG145_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x244 8. "PADCONFIG145_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x244 7. "PADCONFIG145_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x244 0.--3. "PADCONFIG145_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x248 "CFG0_PADCONFIG146_PROXY,"
bitfld.long 0x248 31. "PADCONFIG146_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x248 30. "PADCONFIG146_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x248 29. "PADCONFIG146_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x248 28. "PADCONFIG146_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x248 27. "PADCONFIG146_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x248 26. "PADCONFIG146_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x248 25. "PADCONFIG146_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x248 24. "PADCONFIG146_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x248 23. "PADCONFIG146_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x248 22. "PADCONFIG146_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x248 21. "PADCONFIG146_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x248 19.--20. "PADCONFIG146_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x248 18. "PADCONFIG146_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x248 17. "PADCONFIG146_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x248 16. "PADCONFIG146_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x248 15. "PADCONFIG146_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x248 14. "PADCONFIG146_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x248 11.--13. "PADCONFIG146_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x248 8. "PADCONFIG146_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x248 7. "PADCONFIG146_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x248 0.--3. "PADCONFIG146_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x24C "CFG0_PADCONFIG147_PROXY,"
bitfld.long 0x24C 31. "PADCONFIG147_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x24C 30. "PADCONFIG147_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x24C 29. "PADCONFIG147_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x24C 28. "PADCONFIG147_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x24C 27. "PADCONFIG147_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x24C 26. "PADCONFIG147_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x24C 25. "PADCONFIG147_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x24C 24. "PADCONFIG147_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x24C 23. "PADCONFIG147_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x24C 22. "PADCONFIG147_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x24C 21. "PADCONFIG147_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x24C 19.--20. "PADCONFIG147_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x24C 18. "PADCONFIG147_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x24C 17. "PADCONFIG147_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x24C 16. "PADCONFIG147_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x24C 15. "PADCONFIG147_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x24C 14. "PADCONFIG147_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x24C 11.--13. "PADCONFIG147_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x24C 8. "PADCONFIG147_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x24C 7. "PADCONFIG147_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x24C 0.--3. "PADCONFIG147_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x250 "CFG0_PADCONFIG148_PROXY,"
bitfld.long 0x250 31. "PADCONFIG148_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x250 30. "PADCONFIG148_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x250 29. "PADCONFIG148_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x250 28. "PADCONFIG148_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x250 27. "PADCONFIG148_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x250 26. "PADCONFIG148_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x250 25. "PADCONFIG148_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x250 24. "PADCONFIG148_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x250 23. "PADCONFIG148_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x250 22. "PADCONFIG148_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x250 21. "PADCONFIG148_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x250 19.--20. "PADCONFIG148_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x250 18. "PADCONFIG148_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x250 17. "PADCONFIG148_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x250 16. "PADCONFIG148_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x250 15. "PADCONFIG148_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x250 14. "PADCONFIG148_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x250 11.--13. "PADCONFIG148_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x250 8. "PADCONFIG148_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x250 7. "PADCONFIG148_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x250 0.--3. "PADCONFIG148_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x254 "CFG0_PADCONFIG149_PROXY,"
bitfld.long 0x254 31. "PADCONFIG149_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x254 30. "PADCONFIG149_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x254 29. "PADCONFIG149_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x254 28. "PADCONFIG149_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x254 27. "PADCONFIG149_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x254 26. "PADCONFIG149_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x254 25. "PADCONFIG149_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x254 24. "PADCONFIG149_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x254 23. "PADCONFIG149_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x254 22. "PADCONFIG149_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x254 21. "PADCONFIG149_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x254 19.--20. "PADCONFIG149_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x254 18. "PADCONFIG149_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x254 17. "PADCONFIG149_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x254 16. "PADCONFIG149_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x254 15. "PADCONFIG149_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x254 14. "PADCONFIG149_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x254 11.--13. "PADCONFIG149_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x254 8. "PADCONFIG149_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x254 7. "PADCONFIG149_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x254 0.--3. "PADCONFIG149_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x258 "CFG0_PADCONFIG150_PROXY,"
bitfld.long 0x258 31. "PADCONFIG150_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x258 30. "PADCONFIG150_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x258 29. "PADCONFIG150_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x258 28. "PADCONFIG150_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x258 27. "PADCONFIG150_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x258 26. "PADCONFIG150_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x258 25. "PADCONFIG150_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x258 24. "PADCONFIG150_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x258 23. "PADCONFIG150_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x258 22. "PADCONFIG150_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x258 21. "PADCONFIG150_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x258 19.--20. "PADCONFIG150_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x258 18. "PADCONFIG150_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x258 17. "PADCONFIG150_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x258 16. "PADCONFIG150_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x258 15. "PADCONFIG150_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x258 14. "PADCONFIG150_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x258 11.--13. "PADCONFIG150_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x258 8. "PADCONFIG150_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x258 7. "PADCONFIG150_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x258 0.--3. "PADCONFIG150_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x25C "CFG0_PADCONFIG151_PROXY,"
bitfld.long 0x25C 31. "PADCONFIG151_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x25C 30. "PADCONFIG151_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x25C 29. "PADCONFIG151_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x25C 28. "PADCONFIG151_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x25C 27. "PADCONFIG151_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x25C 26. "PADCONFIG151_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x25C 25. "PADCONFIG151_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x25C 24. "PADCONFIG151_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x25C 23. "PADCONFIG151_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x25C 22. "PADCONFIG151_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x25C 21. "PADCONFIG151_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x25C 19.--20. "PADCONFIG151_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x25C 18. "PADCONFIG151_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x25C 17. "PADCONFIG151_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x25C 16. "PADCONFIG151_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x25C 15. "PADCONFIG151_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x25C 14. "PADCONFIG151_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x25C 11.--13. "PADCONFIG151_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x25C 8. "PADCONFIG151_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x25C 7. "PADCONFIG151_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x25C 0.--3. "PADCONFIG151_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x260 "CFG0_PADCONFIG152_PROXY,"
bitfld.long 0x260 31. "PADCONFIG152_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x260 30. "PADCONFIG152_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x260 29. "PADCONFIG152_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x260 28. "PADCONFIG152_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x260 27. "PADCONFIG152_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x260 26. "PADCONFIG152_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x260 25. "PADCONFIG152_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x260 24. "PADCONFIG152_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x260 23. "PADCONFIG152_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x260 22. "PADCONFIG152_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x260 21. "PADCONFIG152_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x260 19.--20. "PADCONFIG152_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x260 18. "PADCONFIG152_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x260 17. "PADCONFIG152_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x260 16. "PADCONFIG152_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x260 15. "PADCONFIG152_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x260 14. "PADCONFIG152_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x260 11.--13. "PADCONFIG152_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x260 8. "PADCONFIG152_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x260 7. "PADCONFIG152_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x260 0.--3. "PADCONFIG152_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x264 "CFG0_PADCONFIG153_PROXY,"
bitfld.long 0x264 31. "PADCONFIG153_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x264 30. "PADCONFIG153_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x264 29. "PADCONFIG153_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x264 28. "PADCONFIG153_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x264 27. "PADCONFIG153_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x264 26. "PADCONFIG153_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x264 25. "PADCONFIG153_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x264 24. "PADCONFIG153_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x264 23. "PADCONFIG153_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x264 22. "PADCONFIG153_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x264 21. "PADCONFIG153_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x264 19.--20. "PADCONFIG153_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x264 18. "PADCONFIG153_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x264 17. "PADCONFIG153_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x264 16. "PADCONFIG153_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x264 15. "PADCONFIG153_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x264 14. "PADCONFIG153_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x264 11.--13. "PADCONFIG153_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x264 8. "PADCONFIG153_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x264 7. "PADCONFIG153_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x264 0.--3. "PADCONFIG153_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x268 "CFG0_PADCONFIG154_PROXY,"
bitfld.long 0x268 31. "PADCONFIG154_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x268 30. "PADCONFIG154_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x268 29. "PADCONFIG154_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x268 28. "PADCONFIG154_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x268 27. "PADCONFIG154_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x268 26. "PADCONFIG154_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x268 25. "PADCONFIG154_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x268 24. "PADCONFIG154_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x268 23. "PADCONFIG154_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x268 22. "PADCONFIG154_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x268 21. "PADCONFIG154_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x268 19.--20. "PADCONFIG154_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x268 18. "PADCONFIG154_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x268 17. "PADCONFIG154_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x268 16. "PADCONFIG154_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x268 15. "PADCONFIG154_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x268 14. "PADCONFIG154_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x268 11.--13. "PADCONFIG154_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x268 8. "PADCONFIG154_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x268 7. "PADCONFIG154_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x268 0.--3. "PADCONFIG154_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x26C "CFG0_PADCONFIG155_PROXY,"
bitfld.long 0x26C 31. "PADCONFIG155_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x26C 30. "PADCONFIG155_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x26C 29. "PADCONFIG155_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x26C 28. "PADCONFIG155_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x26C 27. "PADCONFIG155_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x26C 26. "PADCONFIG155_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x26C 25. "PADCONFIG155_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x26C 24. "PADCONFIG155_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x26C 23. "PADCONFIG155_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x26C 22. "PADCONFIG155_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x26C 21. "PADCONFIG155_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x26C 19.--20. "PADCONFIG155_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x26C 18. "PADCONFIG155_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x26C 17. "PADCONFIG155_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x26C 16. "PADCONFIG155_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x26C 15. "PADCONFIG155_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x26C 14. "PADCONFIG155_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x26C 11.--13. "PADCONFIG155_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x26C 8. "PADCONFIG155_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x26C 7. "PADCONFIG155_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x26C 0.--3. "PADCONFIG155_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x270 "CFG0_PADCONFIG156_PROXY,"
bitfld.long 0x270 31. "PADCONFIG156_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x270 30. "PADCONFIG156_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x270 29. "PADCONFIG156_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x270 28. "PADCONFIG156_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x270 27. "PADCONFIG156_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x270 26. "PADCONFIG156_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x270 25. "PADCONFIG156_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x270 24. "PADCONFIG156_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x270 23. "PADCONFIG156_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x270 22. "PADCONFIG156_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x270 21. "PADCONFIG156_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x270 19.--20. "PADCONFIG156_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x270 18. "PADCONFIG156_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x270 17. "PADCONFIG156_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x270 16. "PADCONFIG156_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x270 15. "PADCONFIG156_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x270 14. "PADCONFIG156_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x270 11.--13. "PADCONFIG156_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x270 8. "PADCONFIG156_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x270 7. "PADCONFIG156_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x270 0.--3. "PADCONFIG156_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x274 "CFG0_PADCONFIG157_PROXY,"
bitfld.long 0x274 31. "PADCONFIG157_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x274 30. "PADCONFIG157_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x274 29. "PADCONFIG157_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x274 28. "PADCONFIG157_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x274 27. "PADCONFIG157_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x274 26. "PADCONFIG157_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x274 25. "PADCONFIG157_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x274 24. "PADCONFIG157_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x274 23. "PADCONFIG157_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x274 22. "PADCONFIG157_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x274 21. "PADCONFIG157_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x274 19.--20. "PADCONFIG157_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x274 18. "PADCONFIG157_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x274 17. "PADCONFIG157_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x274 16. "PADCONFIG157_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x274 15. "PADCONFIG157_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x274 14. "PADCONFIG157_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x274 11.--13. "PADCONFIG157_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x274 8. "PADCONFIG157_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x274 7. "PADCONFIG157_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x274 0.--3. "PADCONFIG157_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x278 "CFG0_PADCONFIG158_PROXY,"
bitfld.long 0x278 31. "PADCONFIG158_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x278 30. "PADCONFIG158_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x278 29. "PADCONFIG158_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x278 28. "PADCONFIG158_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x278 27. "PADCONFIG158_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x278 26. "PADCONFIG158_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x278 25. "PADCONFIG158_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x278 24. "PADCONFIG158_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x278 23. "PADCONFIG158_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x278 22. "PADCONFIG158_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x278 21. "PADCONFIG158_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x278 19.--20. "PADCONFIG158_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x278 18. "PADCONFIG158_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x278 17. "PADCONFIG158_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x278 16. "PADCONFIG158_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x278 15. "PADCONFIG158_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x278 14. "PADCONFIG158_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x278 11.--13. "PADCONFIG158_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x278 8. "PADCONFIG158_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x278 7. "PADCONFIG158_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x278 0.--3. "PADCONFIG158_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x27C "CFG0_PADCONFIG159_PROXY,"
bitfld.long 0x27C 31. "PADCONFIG159_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x27C 30. "PADCONFIG159_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x27C 29. "PADCONFIG159_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x27C 28. "PADCONFIG159_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x27C 27. "PADCONFIG159_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x27C 26. "PADCONFIG159_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x27C 25. "PADCONFIG159_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x27C 24. "PADCONFIG159_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x27C 23. "PADCONFIG159_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x27C 22. "PADCONFIG159_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x27C 21. "PADCONFIG159_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x27C 19.--20. "PADCONFIG159_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x27C 18. "PADCONFIG159_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x27C 17. "PADCONFIG159_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x27C 16. "PADCONFIG159_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x27C 15. "PADCONFIG159_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x27C 14. "PADCONFIG159_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x27C 11.--13. "PADCONFIG159_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x27C 8. "PADCONFIG159_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x27C 7. "PADCONFIG159_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x27C 0.--3. "PADCONFIG159_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x280 "CFG0_PADCONFIG160_PROXY,"
bitfld.long 0x280 31. "PADCONFIG160_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x280 30. "PADCONFIG160_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x280 29. "PADCONFIG160_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x280 28. "PADCONFIG160_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x280 27. "PADCONFIG160_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x280 26. "PADCONFIG160_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x280 25. "PADCONFIG160_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x280 24. "PADCONFIG160_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x280 23. "PADCONFIG160_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x280 22. "PADCONFIG160_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x280 21. "PADCONFIG160_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x280 19.--20. "PADCONFIG160_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x280 18. "PADCONFIG160_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x280 17. "PADCONFIG160_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x280 16. "PADCONFIG160_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x280 15. "PADCONFIG160_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x280 14. "PADCONFIG160_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x280 11.--13. "PADCONFIG160_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x280 8. "PADCONFIG160_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x280 7. "PADCONFIG160_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x280 0.--3. "PADCONFIG160_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x284 "CFG0_PADCONFIG161_PROXY,"
bitfld.long 0x284 31. "PADCONFIG161_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x284 30. "PADCONFIG161_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x284 29. "PADCONFIG161_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x284 28. "PADCONFIG161_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x284 27. "PADCONFIG161_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x284 26. "PADCONFIG161_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x284 25. "PADCONFIG161_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x284 24. "PADCONFIG161_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x284 23. "PADCONFIG161_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x284 22. "PADCONFIG161_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x284 21. "PADCONFIG161_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x284 19.--20. "PADCONFIG161_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x284 18. "PADCONFIG161_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x284 17. "PADCONFIG161_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x284 16. "PADCONFIG161_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x284 15. "PADCONFIG161_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x284 14. "PADCONFIG161_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x284 11.--13. "PADCONFIG161_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x284 8. "PADCONFIG161_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x284 7. "PADCONFIG161_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x284 0.--3. "PADCONFIG161_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x288 "CFG0_PADCONFIG162_PROXY,"
bitfld.long 0x288 31. "PADCONFIG162_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x288 30. "PADCONFIG162_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x288 29. "PADCONFIG162_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x288 28. "PADCONFIG162_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x288 27. "PADCONFIG162_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x288 26. "PADCONFIG162_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x288 25. "PADCONFIG162_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x288 24. "PADCONFIG162_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x288 23. "PADCONFIG162_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x288 22. "PADCONFIG162_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x288 21. "PADCONFIG162_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x288 19.--20. "PADCONFIG162_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x288 18. "PADCONFIG162_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x288 17. "PADCONFIG162_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x288 16. "PADCONFIG162_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x288 15. "PADCONFIG162_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x288 14. "PADCONFIG162_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x288 11.--13. "PADCONFIG162_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x288 8. "PADCONFIG162_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x288 7. "PADCONFIG162_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x288 0.--3. "PADCONFIG162_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x28C "CFG0_PADCONFIG163_PROXY,"
bitfld.long 0x28C 31. "PADCONFIG163_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x28C 30. "PADCONFIG163_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x28C 29. "PADCONFIG163_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x28C 28. "PADCONFIG163_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x28C 27. "PADCONFIG163_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x28C 26. "PADCONFIG163_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x28C 25. "PADCONFIG163_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x28C 24. "PADCONFIG163_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x28C 23. "PADCONFIG163_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x28C 22. "PADCONFIG163_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x28C 21. "PADCONFIG163_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x28C 19.--20. "PADCONFIG163_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x28C 18. "PADCONFIG163_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x28C 17. "PADCONFIG163_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x28C 16. "PADCONFIG163_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x28C 15. "PADCONFIG163_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x28C 14. "PADCONFIG163_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x28C 11.--13. "PADCONFIG163_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28C 8. "PADCONFIG163_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x28C 7. "PADCONFIG163_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x28C 0.--3. "PADCONFIG163_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x290 "CFG0_PADCONFIG164_PROXY,"
bitfld.long 0x290 31. "PADCONFIG164_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x290 30. "PADCONFIG164_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x290 29. "PADCONFIG164_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x290 28. "PADCONFIG164_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x290 27. "PADCONFIG164_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x290 26. "PADCONFIG164_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x290 25. "PADCONFIG164_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x290 24. "PADCONFIG164_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x290 23. "PADCONFIG164_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x290 22. "PADCONFIG164_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x290 21. "PADCONFIG164_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x290 19.--20. "PADCONFIG164_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x290 18. "PADCONFIG164_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x290 17. "PADCONFIG164_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x290 16. "PADCONFIG164_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x290 15. "PADCONFIG164_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x290 14. "PADCONFIG164_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x290 11.--13. "PADCONFIG164_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x290 8. "PADCONFIG164_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x290 7. "PADCONFIG164_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x290 0.--3. "PADCONFIG164_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x294 "CFG0_PADCONFIG165_PROXY,"
bitfld.long 0x294 31. "PADCONFIG165_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x294 30. "PADCONFIG165_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x294 29. "PADCONFIG165_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x294 28. "PADCONFIG165_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x294 27. "PADCONFIG165_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x294 26. "PADCONFIG165_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x294 25. "PADCONFIG165_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x294 24. "PADCONFIG165_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x294 23. "PADCONFIG165_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x294 22. "PADCONFIG165_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x294 21. "PADCONFIG165_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x294 19.--20. "PADCONFIG165_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x294 18. "PADCONFIG165_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x294 17. "PADCONFIG165_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x294 16. "PADCONFIG165_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x294 15. "PADCONFIG165_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x294 14. "PADCONFIG165_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x294 11.--13. "PADCONFIG165_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x294 8. "PADCONFIG165_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x294 7. "PADCONFIG165_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x294 0.--3. "PADCONFIG165_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x298 "CFG0_PADCONFIG166_PROXY,"
bitfld.long 0x298 31. "PADCONFIG166_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x298 30. "PADCONFIG166_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x298 29. "PADCONFIG166_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x298 28. "PADCONFIG166_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x298 27. "PADCONFIG166_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x298 26. "PADCONFIG166_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x298 25. "PADCONFIG166_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x298 24. "PADCONFIG166_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x298 23. "PADCONFIG166_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x298 22. "PADCONFIG166_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x298 21. "PADCONFIG166_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x298 19.--20. "PADCONFIG166_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x298 18. "PADCONFIG166_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x298 17. "PADCONFIG166_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x298 16. "PADCONFIG166_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x298 15. "PADCONFIG166_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x298 14. "PADCONFIG166_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x298 11.--13. "PADCONFIG166_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x298 8. "PADCONFIG166_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x298 7. "PADCONFIG166_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x298 0.--3. "PADCONFIG166_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x29C "CFG0_PADCONFIG167_PROXY,"
bitfld.long 0x29C 31. "PADCONFIG167_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x29C 30. "PADCONFIG167_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x29C 29. "PADCONFIG167_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x29C 28. "PADCONFIG167_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x29C 27. "PADCONFIG167_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x29C 26. "PADCONFIG167_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x29C 25. "PADCONFIG167_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x29C 24. "PADCONFIG167_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x29C 23. "PADCONFIG167_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x29C 22. "PADCONFIG167_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x29C 21. "PADCONFIG167_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x29C 19.--20. "PADCONFIG167_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x29C 18. "PADCONFIG167_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x29C 17. "PADCONFIG167_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x29C 16. "PADCONFIG167_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x29C 15. "PADCONFIG167_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x29C 14. "PADCONFIG167_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x29C 11.--13. "PADCONFIG167_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x29C 8. "PADCONFIG167_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x29C 7. "PADCONFIG167_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x29C 0.--3. "PADCONFIG167_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2A0 "CFG0_PADCONFIG168_PROXY,"
bitfld.long 0x2A0 31. "PADCONFIG168_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x2A0 30. "PADCONFIG168_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x2A0 29. "PADCONFIG168_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x2A0 28. "PADCONFIG168_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x2A0 27. "PADCONFIG168_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x2A0 26. "PADCONFIG168_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2A0 25. "PADCONFIG168_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x2A0 24. "PADCONFIG168_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x2A0 23. "PADCONFIG168_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x2A0 22. "PADCONFIG168_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x2A0 21. "PADCONFIG168_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x2A0 19.--20. "PADCONFIG168_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x2A0 18. "PADCONFIG168_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x2A0 17. "PADCONFIG168_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x2A0 16. "PADCONFIG168_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x2A0 15. "PADCONFIG168_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x2A0 14. "PADCONFIG168_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x2A0 11.--13. "PADCONFIG168_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2A0 8. "PADCONFIG168_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x2A0 7. "PADCONFIG168_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x2A0 0.--3. "PADCONFIG168_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2A4 "CFG0_PADCONFIG169_PROXY,"
bitfld.long 0x2A4 31. "PADCONFIG169_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x2A4 30. "PADCONFIG169_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x2A4 29. "PADCONFIG169_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x2A4 28. "PADCONFIG169_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x2A4 27. "PADCONFIG169_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x2A4 26. "PADCONFIG169_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2A4 25. "PADCONFIG169_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x2A4 24. "PADCONFIG169_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x2A4 23. "PADCONFIG169_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x2A4 22. "PADCONFIG169_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x2A4 21. "PADCONFIG169_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x2A4 19.--20. "PADCONFIG169_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x2A4 18. "PADCONFIG169_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x2A4 17. "PADCONFIG169_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x2A4 16. "PADCONFIG169_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x2A4 15. "PADCONFIG169_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x2A4 14. "PADCONFIG169_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x2A4 11.--13. "PADCONFIG169_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2A4 8. "PADCONFIG169_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x2A4 7. "PADCONFIG169_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x2A4 0.--3. "PADCONFIG169_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2A8 "CFG0_PADCONFIG170_PROXY,"
bitfld.long 0x2A8 31. "PADCONFIG170_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x2A8 30. "PADCONFIG170_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x2A8 29. "PADCONFIG170_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x2A8 28. "PADCONFIG170_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x2A8 27. "PADCONFIG170_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x2A8 26. "PADCONFIG170_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2A8 25. "PADCONFIG170_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x2A8 24. "PADCONFIG170_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x2A8 23. "PADCONFIG170_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x2A8 22. "PADCONFIG170_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x2A8 21. "PADCONFIG170_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x2A8 19.--20. "PADCONFIG170_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x2A8 18. "PADCONFIG170_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x2A8 17. "PADCONFIG170_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x2A8 16. "PADCONFIG170_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x2A8 15. "PADCONFIG170_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x2A8 14. "PADCONFIG170_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x2A8 11.--13. "PADCONFIG170_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2A8 8. "PADCONFIG170_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x2A8 7. "PADCONFIG170_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x2A8 0.--3. "PADCONFIG170_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
group.long 0x7008++0x07
line.long 0x00 "CFG0_LOCK1_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK1_KICK1_PROXY,"
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x7100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P1_R$1,"
repeat.end
tree.end
repeat 2. (list 1. 0. )(list ad:0x310000 ad:0x3F110000 )
tree "PBIST$1"
base $2
group.long 0x00++0x7F
line.long 0x00 "MEM_RF0L,"
line.long 0x04 "MEM_RF1L,"
line.long 0x08 "MEM_RF2L,"
line.long 0x0C "MEM_RF3L,"
line.long 0x10 "MEM_RF4L,"
line.long 0x14 "MEM_RF5L,"
line.long 0x18 "MEM_RF6L,"
line.long 0x1C "MEM_RF7L,"
line.long 0x20 "MEM_RF8L,"
line.long 0x24 "MEM_RF9L,"
line.long 0x28 "MEM_RF10L,"
line.long 0x2C "MEM_RF11L,"
line.long 0x30 "MEM_RF12L,"
line.long 0x34 "MEM_RF13L,"
line.long 0x38 "MEM_RF14L,"
line.long 0x3C "MEM_RF15L,"
line.long 0x40 "MEM_RF0U,"
line.long 0x44 "MEM_RF1U,"
line.long 0x48 "MEM_RF2U,"
line.long 0x4C "MEM_RF3U,"
line.long 0x50 "MEM_RF4U,"
line.long 0x54 "MEM_RF5U,"
line.long 0x58 "MEM_RF6U,"
line.long 0x5C "MEM_RF7U,"
line.long 0x60 "MEM_RF8U,"
line.long 0x64 "MEM_RF9U,"
line.long 0x68 "MEM_RF10U,"
line.long 0x6C "MEM_RF11U,"
line.long 0x70 "MEM_RF12U,"
line.long 0x74 "MEM_RF13U,"
line.long 0x78 "MEM_RF14U,"
line.long 0x7C "MEM_RF15U,"
group.long 0x100++0x27
line.long 0x00 "MEM_A0,"
hexmask.long.word 0x00 0.--15. 1. "A0,Variable Address Register 0 (A0)"
line.long 0x04 "MEM_A1,"
hexmask.long.word 0x04 0.--15. 1. "A1,Variable Address Register 1 (A1)"
line.long 0x08 "MEM_A2,"
hexmask.long.word 0x08 0.--15. 1. "A2,Variable Address Register 2 (A2)"
line.long 0x0C "MEM_A3,"
hexmask.long.word 0x0C 0.--15. 1. "A3,Variable Address Register 3 (A3)"
line.long 0x10 "MEM_L0,"
hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)"
line.long 0x14 "MEM_L1,"
hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)"
line.long 0x18 "MEM_L2,"
hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)"
line.long 0x1C "MEM_L3,"
hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)"
line.long 0x20 "MEM_D,"
hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)"
hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)"
line.long 0x24 "MEM_E,"
hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)"
hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)"
group.long 0x130++0x3F
line.long 0x00 "MEM_CA0,"
hexmask.long.word 0x00 0.--15. 1. "CA0,Constant Address Register 0 (CA0)"
line.long 0x04 "MEM_CA1,"
hexmask.long.word 0x04 0.--15. 1. "CA1,Constant Address Register 1 (CA1)"
line.long 0x08 "MEM_CA2,"
hexmask.long.word 0x08 0.--15. 1. "CA2,Constant Address Register 2 (CA2)"
line.long 0x0C "MEM_CA3,"
hexmask.long.word 0x0C 0.--15. 1. "CA3,Constant Address Register 3 (CA3)"
line.long 0x10 "MEM_CL0,"
hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)"
line.long 0x14 "MEM_CL1,"
hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)"
line.long 0x18 "MEM_CL2,"
hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)"
line.long 0x1C "MEM_CL3,"
hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)"
line.long 0x20 "MEM_I0,"
hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)"
line.long 0x24 "MEM_I1,"
hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)"
line.long 0x28 "MEM_I2,"
hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)"
line.long 0x2C "MEM_I3,"
hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)"
line.long 0x30 "MEM_RAMT,"
hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS"
hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS"
hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR"
bitfld.long 0x30 2.--5. "PLS,Pipeline Latency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3"
line.long 0x34 "MEM_DLR,"
hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)"
bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1"
bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1"
bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1"
bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1"
bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1"
newline
bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1"
bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1"
bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1"
bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1"
bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1"
bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1"
line.long 0x38 "MEM_CMS,"
bitfld.long 0x38 0.--3. "CMS,Clock Mux Select (CMS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "MEM_STR,"
bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1"
bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1"
bitfld.long 0x3C 2. "STOP,Stop" "0,1"
bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1"
bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1"
group.quad 0x170++0x07
line.quad 0x00 "MEM_SCR,"
hexmask.quad.byte 0x00 56.--63. 1. "SCR7,Address Scrambling Register 7"
hexmask.quad.byte 0x00 48.--55. 1. "SCR6,Address Scrambling Register 6"
hexmask.quad.byte 0x00 40.--47. 1. "SCR5,Address Scrambling Register 5"
hexmask.quad.byte 0x00 32.--39. 1. "SCR4,Address Scrambling Register 4"
hexmask.quad.byte 0x00 24.--31. 1. "SCR3,Address Scrambling Register 3"
hexmask.quad.byte 0x00 16.--23. 1. "SCR2,Address Scrambling Register 2"
newline
hexmask.quad.byte 0x00 8.--15. 1. "SCR1,Address Scrambling Register 1"
hexmask.quad.byte 0x00 0.--7. 1. "SCR0,Address Scrambling Register 0"
group.long 0x178++0x13
line.long 0x00 "MEM_CSR,"
hexmask.long.byte 0x00 24.--31. 1. "CSR3,Chip Select 3 (CSR3)"
hexmask.long.byte 0x00 16.--23. 1. "CSR2,Chip Select 2 (CSR2)"
hexmask.long.byte 0x00 8.--15. 1. "CSR1,Chip Select 1(CSR1)"
hexmask.long.byte 0x00 0.--7. 1. "CSR0,Chip Select 0 (CSR0)"
line.long 0x04 "MEM_FDLY,"
hexmask.long.byte 0x04 0.--7. 1. "FDLY,Fail Delay (FDLY)"
line.long 0x08 "MEM_PACT,"
bitfld.long 0x08 0. "PACT,PBIST Activate (PACT)" "0,1"
line.long 0x0C "MEM_PID,"
bitfld.long 0x0C 0.--4. "PID,PBIST ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "MEM_OVER,"
bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1"
bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1"
bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1"
bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1"
rgroup.quad 0x190++0x17
line.quad 0x00 "MEM_FSRF,"
bitfld.quad 0x00 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1"
bitfld.quad 0x00 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1"
line.quad 0x08 "MEM_FSRC,"
bitfld.quad 0x08 32.--35. "FSRC1,Fail Status Count - Port 1 (FSRC1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 0.--3. "FSRC0,Fail Status Count - Port 0 (FSRC0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.quad 0x10 "MEM_FSRA,"
hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)"
hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)"
rgroup.long 0x1A8++0x03
line.long 0x00 "MEM_FSRDL0,"
rgroup.long 0x1B0++0x17
line.long 0x00 "MEM_FSRDL1,"
line.long 0x04 "MEM_MARGIN_MODE,"
bitfld.long 0x04 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3"
bitfld.long 0x04 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3"
line.long 0x08 "MEM_WRENZ,"
bitfld.long 0x08 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3"
line.long 0x0C "MEM_PAGE_PGS,"
bitfld.long 0x0C 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3"
line.long 0x10 "MEM_ROM,"
bitfld.long 0x10 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3"
line.long 0x14 "MEM_ALGO,"
hexmask.long.byte 0x14 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)"
hexmask.long.byte 0x14 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)"
hexmask.long.byte 0x14 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)"
hexmask.long.byte 0x14 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)"
group.quad 0x1C8++0x07
line.quad 0x00 "MEM_RINFO,"
hexmask.quad.byte 0x00 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)"
hexmask.quad.byte 0x00 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)"
hexmask.quad.byte 0x00 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)"
hexmask.quad.byte 0x00 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)"
hexmask.quad.byte 0x00 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)"
hexmask.quad.byte 0x00 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)"
newline
hexmask.quad.byte 0x00 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)"
hexmask.quad.byte 0x00 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)"
tree.end
repeat.end
repeat 2. (list 0. 1. )(list ad:0xC00000 ad:0xC01000 )
tree "PDMA$1"
base $2
rgroup.long 0x00++0x03
line.long 0x00 "REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x04 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 3. "RPCF1_RAMECC_PEND,Interrupt Pending Status for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 2. "RPCF0_RAMECC_PEND,Interrupt Pending Status for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x04 1. "TPCF1_RAMECC_PEND,Interrupt Pending Status for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x04 0. "TPCF0_RAMECC_PEND,Interrupt Pending Status for tpcf0_ramecc_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 3. "RPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "TPCF1_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "TPCF0_RAMECC_ENABLE_SET,Interrupt Enable Set Register for tpcf0_ramecc_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 3. "RPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 2. "RPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for rpcf0_ramecc_pend" "0,1"
bitfld.long 0x00 1. "TPCF1_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf1_ramecc_pend" "0,1"
bitfld.long 0x00 0. "TPCF0_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for tpcf0_ramecc_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
repeat.end
tree "PLL0_CFG"
base ad:0x680000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_pll0_PID,"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
newline
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x08++0x03
line.long 0x00 "CFG_pll0_CFG,"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15"
newline
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved)" "SSM is not present,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table presence" "SSM Wave table is not present,SSM Wave table is present"
newline
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved)" "Fractional PLL,FractionalF PLL,De-Skew PLL,?..."
group.long 0x10++0x07
line.long 0x00 "CFG_pll0_LOCKKEY0,"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers"
newline
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CFG_pll0_LOCKKEY1,"
group.long 0x20++0x07
line.long 0x00 "CFG_pll0_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
newline
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL enable" "PLL is disabled,PLL is enabled"
newline
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable" "Output clocks are derived from the VCO clock,Output clocks are derived from the FREF.."
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator" "0,1"
newline
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK enable" "Post divide powered down,Post divide enabled"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator enable" "Delta-Sigma modulator is disabled (use integer..,Delta-Sigma modulator is enabled (use fractional.."
newline
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)" "Fractional NC DAC is disabled (for Test modes..,Fractional NC DAC is enabled (ignored in integer.."
line.long 0x04 "CFG_pll0_STAT,"
bitfld.long 0x04 0. "LOCK,PLL lock status" "PLL is not locked,PLL is locked"
group.long 0x30++0x0B
line.long 0x00 "CFG_pll0_FREQ_CTRL0,"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of" "0x010=Divide by 16,0x011=Divide by,0x140=Divide by,0xC80=Divide by 3200,0xFFF=Not supported"
line.long 0x04 "CFG_pll0_FREQ_CTRL1,"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395" "0x000001=.000000059605 (1/(2^24)),0x000002=.000000119209 (2/(2^24)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2^24))"
line.long 0x08 "CFG_pll0_DIV_CTRL,"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider" "Reserved (do not use),Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider" "Reserved /(do not use/),Divide by 1,Divide by,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 63"
group.long 0x40++0x07
line.long 0x00 "CFG_pll0_SS_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS modulator" "Spread spectrum modulation is enabled,SSMOD is bypassed"
newline
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address"
newline
bitfld.long 0x00 15. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance" "Center spread,Down spread"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved)" "Use 128 point triangle wave table,Use external wave table"
line.long 0x04 "CFG_pll0_SS_SPREAD,"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x60++0x07
line.long 0x00 "CFG_pll0_CAL_CTRL,"
bitfld.long 0x00 31. "CAL_EN,Calibration enable to actively adjust for input skew" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "FAST_CAL,Fast calibration enabled" "Normal operation,Used for initial calibration if initial value.."
newline
bitfld.long 0x00 16.--18. "CAL_CNT,Calibration loop programmable counter" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "CAL_BYP,Calibration bypass" "Use the calibration output to set the phase..,Use the cal_in input value to set the phase.."
newline
hexmask.long.word 0x00 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration"
line.long 0x04 "CFG_pll0_CAL_STAT,"
bitfld.long 0x04 31. "CAL_LOCK,Reserved for future use" "0,1"
newline
bitfld.long 0x04 16.--19. "LOCK_CNT,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0"
repeat 10. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 )
group.long ($2+0x80)++0x03
line.long 0x00 "CFG_pll0_HSDIV_CTRL$1,"
bitfld.long 0x00 31. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1 enable" "Synchronously disable CLKOUT1,Synchronously enable CLKOUT1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization logic" "Changes to DIV value synchronized to prevent..,Changes are asynchronous"
newline
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
repeat.end
rgroup.long 0x1000++0x03
line.long 0x00 "CFG_pll1_PID,"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
newline
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x1008++0x03
line.long 0x00 "CFG_pll1_CFG,"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15"
newline
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved)" "SSM is not present,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table presence" "SSM Wave table is not present,SSM Wave table is present"
newline
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved)" "Fractional PLL,FractionalF PLL,De-Skew PLL,?..."
group.long 0x1010++0x07
line.long 0x00 "CFG_pll1_LOCKKEY0,"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers"
newline
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CFG_pll1_LOCKKEY1,"
group.long 0x1020++0x07
line.long 0x00 "CFG_pll1_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
newline
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL enable" "PLL is disabled,PLL is enabled"
newline
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable" "Output clocks are derived from the VCO clock,Output clocks are derived from the FREF.."
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator" "0,1"
newline
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK enable" "Post divide powered down,Post divide enabled"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator enable" "Delta-Sigma modulator is disabled (use integer..,Delta-Sigma modulator is enabled (use fractional.."
newline
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)" "Fractional NC DAC is disabled (for Test modes..,Fractional NC DAC is enabled (ignored in integer.."
line.long 0x04 "CFG_pll1_STAT,"
bitfld.long 0x04 0. "LOCK,PLL lock status" "PLL is not locked,PLL is locked"
group.long 0x1030++0x0B
line.long 0x00 "CFG_pll1_FREQ_CTRL0,"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of" "0x010=Divide by 16,0x011=Divide by,0x140=Divide by,0xC80=Divide by 3200,0xFFF=Not supported"
line.long 0x04 "CFG_pll1_FREQ_CTRL1,"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395" "0x000001=.000000059605 (1/(2^24)),0x000002=.000000119209 (2/(2^24)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2^24))"
line.long 0x08 "CFG_pll1_DIV_CTRL,"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider" "Reserved (do not use),Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider" "Reserved /(do not use/),Divide by 1,Divide by,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 63"
group.long 0x1040++0x07
line.long 0x00 "CFG_pll1_SS_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS modulator" "Spread spectrum modulation is enabled,SSMOD is bypassed"
newline
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address"
newline
bitfld.long 0x00 15. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance" "Center spread,Down spread"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved)" "Use 128 point triangle wave table,Use external wave table"
line.long 0x04 "CFG_pll1_SS_SPREAD,"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1060++0x07
line.long 0x00 "CFG_pll1_CAL_CTRL,"
bitfld.long 0x00 31. "CAL_EN,Calibration enable to actively adjust for input skew" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "FAST_CAL,Fast calibration enabled" "Normal operation,Used for initial calibration if initial value.."
newline
bitfld.long 0x00 16.--18. "CAL_CNT,Calibration loop programmable counter" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "CAL_BYP,Calibration bypass" "Use the calibration output to set the phase..,Use the cal_in input value to set the phase.."
newline
hexmask.long.word 0x00 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration"
line.long 0x04 "CFG_pll1_CAL_STAT,"
bitfld.long 0x04 31. "CAL_LOCK,Reserved for future use" "0,1"
newline
bitfld.long 0x04 16.--19. "LOCK_CNT,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0"
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x1080)++0x03
line.long 0x00 "CFG_pll1_HSDIV_CTRL$1,"
bitfld.long 0x00 31. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1 enable" "Synchronously disable CLKOUT1,Synchronously enable CLKOUT1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization logic" "Changes to DIV value synchronized to prevent..,Changes are asynchronous"
newline
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
repeat.end
rgroup.long 0x2000++0x03
line.long 0x00 "CFG_pll2_PID,"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
newline
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x2008++0x03
line.long 0x00 "CFG_pll2_CFG,"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15"
newline
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved)" "SSM is not present,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table presence" "SSM Wave table is not present,SSM Wave table is present"
newline
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved)" "Fractional PLL,FractionalF PLL,De-Skew PLL,?..."
group.long 0x2010++0x07
line.long 0x00 "CFG_pll2_LOCKKEY0,"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers"
newline
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CFG_pll2_LOCKKEY1,"
group.long 0x2020++0x07
line.long 0x00 "CFG_pll2_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
newline
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL enable" "PLL is disabled,PLL is enabled"
newline
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable" "Output clocks are derived from the VCO clock,Output clocks are derived from the FREF.."
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator" "0,1"
newline
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK enable" "Post divide powered down,Post divide enabled"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator enable" "Delta-Sigma modulator is disabled (use integer..,Delta-Sigma modulator is enabled (use fractional.."
newline
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)" "Fractional NC DAC is disabled (for Test modes..,Fractional NC DAC is enabled (ignored in integer.."
line.long 0x04 "CFG_pll2_STAT,"
bitfld.long 0x04 0. "LOCK,PLL lock status" "PLL is not locked,PLL is locked"
group.long 0x2030++0x0B
line.long 0x00 "CFG_pll2_FREQ_CTRL0,"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of" "0x010=Divide by 16,0x011=Divide by,0x140=Divide by,0xC80=Divide by 3200,0xFFF=Not supported"
line.long 0x04 "CFG_pll2_FREQ_CTRL1,"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395" "0x000001=.000000059605 (1/(2^24)),0x000002=.000000119209 (2/(2^24)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2^24))"
line.long 0x08 "CFG_pll2_DIV_CTRL,"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider" "Reserved (do not use),Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider" "Reserved /(do not use/),Divide by 1,Divide by,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 63"
group.long 0x2040++0x07
line.long 0x00 "CFG_pll2_SS_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS modulator" "Spread spectrum modulation is enabled,SSMOD is bypassed"
newline
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address"
newline
bitfld.long 0x00 15. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance" "Center spread,Down spread"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved)" "Use 128 point triangle wave table,Use external wave table"
line.long 0x04 "CFG_pll2_SS_SPREAD,"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x2060++0x07
line.long 0x00 "CFG_pll2_CAL_CTRL,"
bitfld.long 0x00 31. "CAL_EN,Calibration enable to actively adjust for input skew" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "FAST_CAL,Fast calibration enabled" "Normal operation,Used for initial calibration if initial value.."
newline
bitfld.long 0x00 16.--18. "CAL_CNT,Calibration loop programmable counter" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "CAL_BYP,Calibration bypass" "Use the calibration output to set the phase..,Use the cal_in input value to set the phase.."
newline
hexmask.long.word 0x00 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration"
line.long 0x04 "CFG_pll2_CAL_STAT,"
bitfld.long 0x04 31. "CAL_LOCK,Reserved for future use" "0,1"
newline
bitfld.long 0x04 16.--19. "LOCK_CNT,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0"
repeat 10. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 )
group.long ($2+0x2080)++0x03
line.long 0x00 "CFG_pll2_HSDIV_CTRL$1,"
bitfld.long 0x00 31. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1 enable" "Synchronously disable CLKOUT1,Synchronously enable CLKOUT1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization logic" "Changes to DIV value synchronized to prevent..,Changes are asynchronous"
newline
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
repeat.end
rgroup.long 0x8000++0x03
line.long 0x00 "CFG_pll8_PID,"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
newline
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x8008++0x03
line.long 0x00 "CFG_pll8_CFG,"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15"
newline
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved)" "SSM is not present,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table presence" "SSM Wave table is not present,SSM Wave table is present"
newline
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved)" "Fractional PLL,FractionalF PLL,De-Skew PLL,?..."
group.long 0x8010++0x07
line.long 0x00 "CFG_pll8_LOCKKEY0,"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition8 registers"
newline
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CFG_pll8_LOCKKEY1,"
group.long 0x8020++0x07
line.long 0x00 "CFG_pll8_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
newline
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL enable" "PLL is disabled,PLL is enabled"
newline
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable" "Output clocks are derived from the VCO clock,Output clocks are derived from the FREF.."
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator" "0,1"
newline
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK enable" "Post divide powered down,Post divide enabled"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator enable" "Delta-Sigma modulator is disabled (use integer..,Delta-Sigma modulator is enabled (use fractional.."
newline
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)" "Fractional NC DAC is disabled (for Test modes..,Fractional NC DAC is enabled (ignored in integer.."
line.long 0x04 "CFG_pll8_STAT,"
bitfld.long 0x04 0. "LOCK,PLL lock status" "PLL is not locked,PLL is locked"
group.long 0x8030++0x0B
line.long 0x00 "CFG_pll8_FREQ_CTRL0,"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of" "0x010=Divide by 16,0x011=Divide by,0x140=Divide by,0xC80=Divide by 3200,0xFFF=Not supported"
line.long 0x04 "CFG_pll8_FREQ_CTRL1,"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395" "0x000001=.000000059605 (1/(2^24)),0x000002=.000000119209 (2/(2^24)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2^24))"
line.long 0x08 "CFG_pll8_DIV_CTRL,"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider" "Reserved (do not use),Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider" "Reserved /(do not use/),Divide by 1,Divide by,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 63"
group.long 0x8040++0x07
line.long 0x00 "CFG_pll8_SS_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS modulator" "Spread spectrum modulation is enabled,SSMOD is bypassed"
newline
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address"
newline
bitfld.long 0x00 15. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance" "Center spread,Down spread"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved)" "Use 128 point triangle wave table,Use external wave table"
line.long 0x04 "CFG_pll8_SS_SPREAD,"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x8060++0x07
line.long 0x00 "CFG_pll8_CAL_CTRL,"
bitfld.long 0x00 31. "CAL_EN,Calibration enable to actively adjust for input skew" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "FAST_CAL,Fast calibration enabled" "Normal operation,Used for initial calibration if initial value.."
newline
bitfld.long 0x00 16.--18. "CAL_CNT,Calibration loop programmable counter" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "CAL_BYP,Calibration bypass" "Use the calibration output to set the phase..,Use the cal_in input value to set the phase.."
newline
hexmask.long.word 0x00 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration"
line.long 0x04 "CFG_pll8_CAL_STAT,"
bitfld.long 0x04 31. "CAL_LOCK,Reserved for future use" "0,1"
newline
bitfld.long 0x04 16.--19. "LOCK_CNT,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0"
group.long 0x8080++0x03
line.long 0x00 "CFG_pll8_HSDIV_CTRL0,"
bitfld.long 0x00 31. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1 enable" "Synchronously disable CLKOUT1,Synchronously enable CLKOUT1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization logic" "Changes to DIV value synchronized to prevent..,Changes are asynchronous"
newline
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
rgroup.long 0xC000++0x03
line.long 0x00 "CFG_pll12_PID,"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
newline
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0xC008++0x03
line.long 0x00 "CFG_pll12_CFG,"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15"
newline
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved)" "SSM is not present,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table presence" "SSM Wave table is not present,SSM Wave table is present"
newline
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved)" "Fractional PLL,FractionalF PLL,De-Skew PLL,?..."
group.long 0xC010++0x07
line.long 0x00 "CFG_pll12_LOCKKEY0,"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition12 registers"
newline
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CFG_pll12_LOCKKEY1,"
group.long 0xC020++0x07
line.long 0x00 "CFG_pll12_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
newline
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL enable" "PLL is disabled,PLL is enabled"
newline
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable" "Output clocks are derived from the VCO clock,Output clocks are derived from the FREF.."
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator" "0,1"
newline
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK enable" "Post divide powered down,Post divide enabled"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator enable" "Delta-Sigma modulator is disabled (use integer..,Delta-Sigma modulator is enabled (use fractional.."
newline
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)" "Fractional NC DAC is disabled (for Test modes..,Fractional NC DAC is enabled (ignored in integer.."
line.long 0x04 "CFG_pll12_STAT,"
bitfld.long 0x04 0. "LOCK,PLL lock status" "PLL is not locked,PLL is locked"
group.long 0xC030++0x0B
line.long 0x00 "CFG_pll12_FREQ_CTRL0,"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of" "0x010=Divide by 16,0x011=Divide by,0x140=Divide by,0xC80=Divide by 3200,0xFFF=Not supported"
line.long 0x04 "CFG_pll12_FREQ_CTRL1,"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395" "0x000001=.000000059605 (1/(2^24)),0x000002=.000000119209 (2/(2^24)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2^24))"
line.long 0x08 "CFG_pll12_DIV_CTRL,"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider" "Reserved (do not use),Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider" "Reserved /(do not use/),Divide by 1,Divide by,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 63"
group.long 0xC040++0x07
line.long 0x00 "CFG_pll12_SS_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS modulator" "Spread spectrum modulation is enabled,SSMOD is bypassed"
newline
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address"
newline
bitfld.long 0x00 15. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance" "Center spread,Down spread"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved)" "Use 128 point triangle wave table,Use external wave table"
line.long 0x04 "CFG_pll12_SS_SPREAD,"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xC060++0x07
line.long 0x00 "CFG_pll12_CAL_CTRL,"
bitfld.long 0x00 31. "CAL_EN,Calibration enable to actively adjust for input skew" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "FAST_CAL,Fast calibration enabled" "Normal operation,Used for initial calibration if initial value.."
newline
bitfld.long 0x00 16.--18. "CAL_CNT,Calibration loop programmable counter" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "CAL_BYP,Calibration bypass" "Use the calibration output to set the phase..,Use the cal_in input value to set the phase.."
newline
hexmask.long.word 0x00 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration"
line.long 0x04 "CFG_pll12_CAL_STAT,"
bitfld.long 0x04 31. "CAL_LOCK,Reserved for future use" "0,1"
newline
bitfld.long 0x04 16.--19. "LOCK_CNT,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0"
group.long 0xC080++0x03
line.long 0x00 "CFG_pll12_HSDIV_CTRL0,"
bitfld.long 0x00 31. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1 enable" "Synchronously disable CLKOUT1,Synchronously enable CLKOUT1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization logic" "Changes to DIV value synchronized to prevent..,Changes are asynchronous"
newline
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
rgroup.long 0xF000++0x03
line.long 0x00 "CFG_pll15_PID,"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
newline
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0xF008++0x03
line.long 0x00 "CFG_pll15_CFG,"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15"
newline
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved)" "SSM is not present,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table presence" "SSM Wave table is not present,SSM Wave table is present"
newline
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved)" "Fractional PLL,FractionalF PLL,De-Skew PLL,?..."
group.long 0xF010++0x07
line.long 0x00 "CFG_pll15_LOCKKEY0,"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition15 registers"
newline
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CFG_pll15_LOCKKEY1,"
group.long 0xF020++0x07
line.long 0x00 "CFG_pll15_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
newline
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL enable" "PLL is disabled,PLL is enabled"
newline
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable" "Output clocks are derived from the VCO clock,Output clocks are derived from the FREF.."
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator" "0,1"
newline
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK enable" "Post divide powered down,Post divide enabled"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator enable" "Delta-Sigma modulator is disabled (use integer..,Delta-Sigma modulator is enabled (use fractional.."
newline
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)" "Fractional NC DAC is disabled (for Test modes..,Fractional NC DAC is enabled (ignored in integer.."
line.long 0x04 "CFG_pll15_STAT,"
bitfld.long 0x04 0. "LOCK,PLL lock status" "PLL is not locked,PLL is locked"
group.long 0xF030++0x0B
line.long 0x00 "CFG_pll15_FREQ_CTRL0,"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of" "0x010=Divide by 16,0x011=Divide by,0x140=Divide by,0xC80=Divide by 3200,0xFFF=Not supported"
line.long 0x04 "CFG_pll15_FREQ_CTRL1,"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395" "0x000001=.000000059605 (1/(2^24)),0x000002=.000000119209 (2/(2^24)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2^24))"
line.long 0x08 "CFG_pll15_DIV_CTRL,"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider" "Reserved (do not use),Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider" "Reserved /(do not use/),Divide by 1,Divide by,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 63"
group.long 0xF040++0x07
line.long 0x00 "CFG_pll15_SS_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS modulator" "Spread spectrum modulation is enabled,SSMOD is bypassed"
newline
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address"
newline
bitfld.long 0x00 15. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance" "Center spread,Down spread"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved)" "Use 128 point triangle wave table,Use external wave table"
line.long 0x04 "CFG_pll15_SS_SPREAD,"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xF060++0x07
line.long 0x00 "CFG_pll15_CAL_CTRL,"
bitfld.long 0x00 31. "CAL_EN,Calibration enable to actively adjust for input skew" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "FAST_CAL,Fast calibration enabled" "Normal operation,Used for initial calibration if initial value.."
newline
bitfld.long 0x00 16.--18. "CAL_CNT,Calibration loop programmable counter" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "CAL_BYP,Calibration bypass" "Use the calibration output to set the phase..,Use the cal_in input value to set the phase.."
newline
hexmask.long.word 0x00 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration"
line.long 0x04 "CFG_pll15_CAL_STAT,"
bitfld.long 0x04 31. "CAL_LOCK,Reserved for future use" "0,1"
newline
bitfld.long 0x04 16.--19. "LOCK_CNT,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xF080)++0x03
line.long 0x00 "CFG_pll15_HSDIV_CTRL$1,"
bitfld.long 0x00 31. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1 enable" "Synchronously disable CLKOUT1,Synchronously enable CLKOUT1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization logic" "Changes to DIV value synchronized to prevent..,Changes are asynchronous"
newline
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
repeat.end
rgroup.long 0x10000++0x03
line.long 0x00 "CFG_pll16_PID,"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
newline
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x10008++0x03
line.long 0x00 "CFG_pll16_CFG,"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15"
newline
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved)" "SSM is not present,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table presence" "SSM Wave table is not present,SSM Wave table is present"
newline
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved)" "Fractional PLL,FractionalF PLL,De-Skew PLL,?..."
group.long 0x10010++0x07
line.long 0x00 "CFG_pll16_LOCKKEY0,"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition16 registers"
newline
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CFG_pll16_LOCKKEY1,"
group.long 0x10020++0x07
line.long 0x00 "CFG_pll16_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
newline
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL enable" "PLL is disabled,PLL is enabled"
newline
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable" "Output clocks are derived from the VCO clock,Output clocks are derived from the FREF.."
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator" "0,1"
newline
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK enable" "Post divide powered down,Post divide enabled"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator enable" "Delta-Sigma modulator is disabled (use integer..,Delta-Sigma modulator is enabled (use fractional.."
newline
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)" "Fractional NC DAC is disabled (for Test modes..,Fractional NC DAC is enabled (ignored in integer.."
line.long 0x04 "CFG_pll16_STAT,"
bitfld.long 0x04 0. "LOCK,PLL lock status" "PLL is not locked,PLL is locked"
group.long 0x10030++0x0B
line.long 0x00 "CFG_pll16_FREQ_CTRL0,"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of" "0x010=Divide by 16,0x011=Divide by,0x140=Divide by,0xC80=Divide by 3200,0xFFF=Not supported"
line.long 0x04 "CFG_pll16_FREQ_CTRL1,"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395" "0x000001=.000000059605 (1/(2^24)),0x000002=.000000119209 (2/(2^24)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2^24))"
line.long 0x08 "CFG_pll16_DIV_CTRL,"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider" "Reserved (do not use),Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider" "Reserved /(do not use/),Divide by 1,Divide by,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 63"
group.long 0x10040++0x07
line.long 0x00 "CFG_pll16_SS_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS modulator" "Spread spectrum modulation is enabled,SSMOD is bypassed"
newline
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address"
newline
bitfld.long 0x00 15. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance" "Center spread,Down spread"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved)" "Use 128 point triangle wave table,Use external wave table"
line.long 0x04 "CFG_pll16_SS_SPREAD,"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x10060++0x07
line.long 0x00 "CFG_pll16_CAL_CTRL,"
bitfld.long 0x00 31. "CAL_EN,Calibration enable to actively adjust for input skew" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "FAST_CAL,Fast calibration enabled" "Normal operation,Used for initial calibration if initial value.."
newline
bitfld.long 0x00 16.--18. "CAL_CNT,Calibration loop programmable counter" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "CAL_BYP,Calibration bypass" "Use the calibration output to set the phase..,Use the cal_in input value to set the phase.."
newline
hexmask.long.word 0x00 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration"
line.long 0x04 "CFG_pll16_CAL_STAT,"
bitfld.long 0x04 31. "CAL_LOCK,Reserved for future use" "0,1"
newline
bitfld.long 0x04 16.--19. "LOCK_CNT,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0"
group.long 0x10080++0x03
line.long 0x00 "CFG_pll16_HSDIV_CTRL0,"
bitfld.long 0x00 31. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1 enable" "Synchronously disable CLKOUT1,Synchronously enable CLKOUT1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization logic" "Changes to DIV value synchronized to prevent..,Changes are asynchronous"
newline
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
rgroup.long 0x11000++0x03
line.long 0x00 "CFG_pll17_PID,"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
newline
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x11008++0x03
line.long 0x00 "CFG_pll17_CFG,"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15"
newline
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved)" "SSM is not present,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table presence" "SSM Wave table is not present,SSM Wave table is present"
newline
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved)" "Fractional PLL,FractionalF PLL,De-Skew PLL,?..."
group.long 0x11010++0x07
line.long 0x00 "CFG_pll17_LOCKKEY0,"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition17 registers"
newline
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CFG_pll17_LOCKKEY1,"
group.long 0x11020++0x07
line.long 0x00 "CFG_pll17_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
newline
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL enable" "PLL is disabled,PLL is enabled"
newline
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable" "Output clocks are derived from the VCO clock,Output clocks are derived from the FREF.."
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator" "0,1"
newline
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK enable" "Post divide powered down,Post divide enabled"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator enable" "Delta-Sigma modulator is disabled (use integer..,Delta-Sigma modulator is enabled (use fractional.."
newline
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)" "Fractional NC DAC is disabled (for Test modes..,Fractional NC DAC is enabled (ignored in integer.."
line.long 0x04 "CFG_pll17_STAT,"
bitfld.long 0x04 0. "LOCK,PLL lock status" "PLL is not locked,PLL is locked"
group.long 0x11030++0x0B
line.long 0x00 "CFG_pll17_FREQ_CTRL0,"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of" "0x010=Divide by 16,0x011=Divide by,0x140=Divide by,0xC80=Divide by 3200,0xFFF=Not supported"
line.long 0x04 "CFG_pll17_FREQ_CTRL1,"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395" "0x000001=.000000059605 (1/(2^24)),0x000002=.000000119209 (2/(2^24)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2^24))"
line.long 0x08 "CFG_pll17_DIV_CTRL,"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider" "Reserved (do not use),Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider" "Reserved /(do not use/),Divide by 1,Divide by,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 63"
group.long 0x11040++0x07
line.long 0x00 "CFG_pll17_SS_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS modulator" "Spread spectrum modulation is enabled,SSMOD is bypassed"
newline
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address"
newline
bitfld.long 0x00 15. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance" "Center spread,Down spread"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved)" "Use 128 point triangle wave table,Use external wave table"
line.long 0x04 "CFG_pll17_SS_SPREAD,"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x11060++0x07
line.long 0x00 "CFG_pll17_CAL_CTRL,"
bitfld.long 0x00 31. "CAL_EN,Calibration enable to actively adjust for input skew" "Disabled,Enabled"
newline
bitfld.long 0x00 20. "FAST_CAL,Fast calibration enabled" "Normal operation,Used for initial calibration if initial value.."
newline
bitfld.long 0x00 16.--18. "CAL_CNT,Calibration loop programmable counter" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 15. "CAL_BYP,Calibration bypass" "Use the calibration output to set the phase..,Use the cal_in input value to set the phase.."
newline
hexmask.long.word 0x00 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration"
line.long 0x04 "CFG_pll17_CAL_STAT,"
bitfld.long 0x04 31. "CAL_LOCK,Reserved for future use" "0,1"
newline
bitfld.long 0x04 16.--19. "LOCK_CNT,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0"
group.long 0x11080++0x03
line.long 0x00 "CFG_pll17_HSDIV_CTRL0,"
bitfld.long 0x00 31. "RESET,SSM reset" "0,1"
newline
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1 enable" "Synchronously disable CLKOUT1,Synchronously enable CLKOUT1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization logic" "Changes to DIV value synchronized to prevent..,Changes are asynchronous"
newline
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
tree.end
tree "PSC0"
base ad:0x400000
rgroup.long 0x00++0x03
line.long 0x00 "VBUS_PID,The peripheral identification register is a constant register that contains the ID and ID revision number for that module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x10++0x0B
line.long 0x00 "VBUS_GBLCTL,This register contains global control to PSC"
hexmask.long.byte 0x00 8.--15. 1. "IO_ANA_CTL,General purpose IO/Analog PowerDown control"
line.long 0x04 "VBUS_GBLSTAT,This register shows the PSC global status"
hexmask.long.word 0x04 16.--27. 1. "EF_SMRFLEX,Smart reflex class0 bits"
bitfld.long 0x04 0. "OVRIDE,PSC Override Status" "0,1"
line.long 0x08 "VBUS_INTEVAL,This register has no storage"
bitfld.long 0x08 19. "GOSET,GOSTAT Interrupt Set" "0,1"
bitfld.long 0x08 18. "EPCSET,External Power Control Interrupt Set" "0,1"
bitfld.long 0x08 17. "ERRSET,Combined Interrupt Set" "0,1"
bitfld.long 0x08 2. "EPCEV,External Power Control Interrupt Set" "0,1"
bitfld.long 0x08 1. "ERREV,Re_evaluate Error Interrupt" "0,1"
bitfld.long 0x08 0. "ALLEV,Re_evaluate combined PSC interrupt" "0,1"
rgroup.long 0x40++0x03
line.long 0x00 "VBUS_MERRPR,This register records pending error conditions for all modules"
group.long 0x50++0x03
line.long 0x00 "VBUS_MERRCR,This register has no storage"
rgroup.long 0x60++0x03
line.long 0x00 "VBUS_PERRPR,This register records pending error conditions for each power domain"
group.long 0x68++0x03
line.long 0x00 "VBUS_PERRCR,This register has no storage"
rgroup.long 0x70++0x03
line.long 0x00 "VBUS_EPCPR,This register records pending external power control conditions"
group.long 0x78++0x03
line.long 0x00 "VBUS_EPCCR,This register has no storage"
rgroup.long 0x100++0x0B
line.long 0x00 "VBUS_RAILSTAT,This register is a read-only and shows the current rail requestor whose request is being granted and the current value of the counter associated with this requestor"
bitfld.long 0x00 24.--28. "RAILNUM,Indicates Current Rail Requestor being processed by GPSC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--7. 1. "RAILCNT,Indicates the current rail counter value"
line.long 0x04 "VBUS_RAILCTL,This register is user programmable"
hexmask.long.byte 0x04 8.--15. 1. "RAILCTR1,Rail Counter Value 1"
hexmask.long.byte 0x04 0.--7. 1. "RAILCTR0,Rail Counter Value 0"
line.long 0x08 "VBUS_RAILSEL,User can use this register to select the counter value (RAILCTL) for each power domain"
group.long 0x120++0x03
line.long 0x00 "VBUS_PTCMD,This is a pseudo-command register with no actual storage"
rgroup.long 0x128++0x03
line.long 0x00 "VBUS_PTSTAT,This is a status register"
rgroup.long 0x200++0x03
line.long 0x00 "VBUS_PDSTAT,This is a status register"
bitfld.long 0x00 11. "EMUIHB,Emulation Alters Domain State" "0,1"
bitfld.long 0x00 10. "PWRBAD,Power Bad error" "0,1"
bitfld.long 0x00 9. "PORDONE,POR Done Input Status" "0,1"
bitfld.long 0x00 8. "PORZ,PORz output actual status" "0,1"
bitfld.long 0x00 0.--4. "STATE,Current Power Domain State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x300++0x03
line.long 0x00 "VBUS_PDCTL,This is a control register"
bitfld.long 0x00 31. "FORCE,Force Bit" "0,1"
bitfld.long 0x00 29. "PWRSW,Power shorting Switch Control" "0,1"
bitfld.long 0x00 28. "ISO,Isolation Cell control" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "WAKECNT,RAM wake count delay value"
bitfld.long 0x00 12.--14. "PDMODE,Power Down mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "EMUIHBIE,Emulation alters domain state" "0,1"
bitfld.long 0x00 8. "EPCGOOD,External Power Control Power Good Indication" "0,1"
bitfld.long 0x00 0. "NEXT,User_Desired Next Power Domain State" "0,1"
rgroup.long 0x400++0x03
line.long 0x00 "VBUS_PDCFG,This is a status register"
bitfld.long 0x00 3. "ICEPICK,Icepick support" "0,1"
bitfld.long 0x00 1. "MEMSLPKWK,Memory sleep-wake domain" "0,1"
bitfld.long 0x00 0. "ALWAYSON,Always on power domain" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "VBUS_MDCFG,This is a constant register showing some PSC settings for easy debug"
bitfld.long 0x00 16.--20. "PWRDOM,Indicates which power domain this module belongs to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 15. "AUTOONLY," "0,1"
bitfld.long 0x00 14. "RESETISO," "0,1"
bitfld.long 0x00 13. "NEXTLOCK," "0,1"
bitfld.long 0x00 12. "ASYNC,Async Lpsc" "0,1"
bitfld.long 0x00 11. "ICEPICK,IcePick support" "0,1"
bitfld.long 0x00 10. "PERMDIS,Permanently disable" "0,1"
bitfld.long 0x00 9. "PLLHANDSHAKE,RTL parameter PLL_HANDSHAKE" "0,1"
newline
bitfld.long 0x00 6.--8. "NUMSCRDISBALE,Number of PWR_SCR_DISABLE interfaces required on LPSC" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--5. "NUMCLKEN,Number of PWR_CLK_EN interfaces required on LPSC" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "NUMCLK,Number of PWR_CLKSTOP interfaces required on LPSC" "0,1,2,3,4,5,6,7"
rgroup.long 0x800++0x03
line.long 0x00 "VBUS_MDSTAT,This register shows the status of each module"
bitfld.long 0x00 17. "EMUIHB,Emulation Alters Module State" "0,1"
bitfld.long 0x00 16. "EMURST,Emulation Alters Reset" "0,1"
bitfld.long 0x00 12. "MCKOUT,Actual modclk output to module" "0,1"
bitfld.long 0x00 11. "MRSTDONE,Module reset initialization done status" "0,1"
bitfld.long 0x00 10. "MRSTZ,Module reset actual status" "0,1"
bitfld.long 0x00 9. "LRSTDONE,Module local reset initialization done status" "0,1"
bitfld.long 0x00 8. "LRSTZ,Module local reset actual status" "0,1"
bitfld.long 0x00 0.--5. "STATE,These bits indicate the current module state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA00++0x03
line.long 0x00 "VBUS_MDCTL,This register provides specific control for the individual module"
bitfld.long 0x00 31. "FORCE,Force Bit" "0,1"
bitfld.long 0x00 12. "RESETISO,Reset Isolation" "0,1"
bitfld.long 0x00 11. "BLKCHIP1RST,Block Chip_1_Reset" "0,1"
bitfld.long 0x00 10. "EMUIHBIE,Emulation Alters Module State" "0,1"
bitfld.long 0x00 9. "EMURSTIE,Emulation Alter Reset Interrupt Enable" "0,1"
bitfld.long 0x00 8. "LRSTZ,Module local reset control" "0,1"
bitfld.long 0x00 0.--4. "NEXT,Module Next State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "PSC0_ECC_AGGR_0_REGS"
base ad:0x700400
rgroup.long 0x00++0x03
line.long 0x00 "REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "TABLE_PEND,Interrupt Pending Status for table_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "TABLE_ENABLE_SET,Interrupt Enable Set Register for table_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "TABLE_ENABLE_CLR,Interrupt Enable Clear Register for table_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "TABLE_PEND,Interrupt Pending Status for table_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "TABLE_ENABLE_SET,Interrupt Enable Set Register for table_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "TABLE_ENABLE_CLR,Interrupt Enable Clear Register for table_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "PSC0_FW_0_FW"
base ad:0x45020000
group.long 0x00++0x0F
line.long 0x00 "FW_REGS_dst_fwch_region_0_ch_0_control,The FW Region 0 Channel 0 Control Register defines the control fields for the slave slv0.slv region 0 channel 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_dst_fwch_region_0_ch_0_permission_0,The FW Region 0 Channel 0 Permission 0 Register defines the permissions for the slave slv0.slv region 0 channel 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_dst_fwch_region_0_ch_0_permission_1,The FW Region 0 Channel 0 Permission 1 Register defines the permissions for the slave slv0.slv region 0 channel 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_dst_fwch_region_0_ch_0_permission_2,The FW Region 0 Channel 0 Permission 2 Register defines the permissions for the slave slv0.slv region 0 channel 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x20++0x0F
line.long 0x00 "FW_REGS_dst_fwch_region_1_ch_0_control,The FW Region 1 Channel 0 Control Register defines the control fields for the slave slv0.slv region 1 channel 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_dst_fwch_region_1_ch_0_permission_0,The FW Region 1 Channel 0 Permission 0 Register defines the permissions for the slave slv0.slv region 1 channel 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_dst_fwch_region_1_ch_0_permission_1,The FW Region 1 Channel 0 Permission 1 Register defines the permissions for the slave slv0.slv region 1 channel 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_dst_fwch_region_1_ch_0_permission_2,The FW Region 1 Channel 0 Permission 2 Register defines the permissions for the slave slv0.slv region 1 channel 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x40++0x0F
line.long 0x00 "FW_REGS_dst_fwch_region_2_ch_0_control,The FW Region 2 Channel 0 Control Register defines the control fields for the slave slv0.slv region 2 channel 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_dst_fwch_region_2_ch_0_permission_0,The FW Region 2 Channel 0 Permission 0 Register defines the permissions for the slave slv0.slv region 2 channel 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_dst_fwch_region_2_ch_0_permission_1,The FW Region 2 Channel 0 Permission 1 Register defines the permissions for the slave slv0.slv region 2 channel 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_dst_fwch_region_2_ch_0_permission_2,The FW Region 2 Channel 0 Permission 2 Register defines the permissions for the slave slv0.slv region 2 channel 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x60++0x0F
line.long 0x00 "FW_REGS_dst_fwch_region_3_ch_0_control,The FW Region 3 Channel 0 Control Register defines the control fields for the slave slv0.slv region 3 channel 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_dst_fwch_region_3_ch_0_permission_0,The FW Region 3 Channel 0 Permission 0 Register defines the permissions for the slave slv0.slv region 3 channel 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_dst_fwch_region_3_ch_0_permission_1,The FW Region 3 Channel 0 Permission 1 Register defines the permissions for the slave slv0.slv region 3 channel 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_dst_fwch_region_3_ch_0_permission_2,The FW Region 3 Channel 0 Permission 2 Register defines the permissions for the slave slv0.slv region 3 channel 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
group.long 0x80++0x0F
line.long 0x00 "FW_REGS_dst_fwch_region_4_ch_0_control,The FW Region 4 Channel 0 Control Register defines the control fields for the slave slv0.slv region 4 channel 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_dst_fwch_region_4_ch_0_permission_0,The FW Region 4 Channel 0 Permission 0 Register defines the permissions for the slave slv0.slv region 4 channel 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_dst_fwch_region_4_ch_0_permission_1,The FW Region 4 Channel 0 Permission 1 Register defines the permissions for the slave slv0.slv region 4 channel 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_dst_fwch_region_4_ch_0_permission_2,The FW Region 4 Channel 0 Permission 2 Register defines the permissions for the slave slv0.slv region 4 channel 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
tree.end
tree "PSC0_FW_0_GLB"
base ad:0x45B09000
rgroup.long 0x00++0x07
line.long 0x00 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "PSRAMECC0_ECC_AGGR"
base ad:0x700000
rgroup.long 0x00++0x03
line.long 0x00 "REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "PSRAMECC0_RAM"
base ad:0x00
group.long 0x00++0x03
line.long 0x00 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "PSRAMECC_16K0_ECC_AGGR"
base ad:0x3F001000
rgroup.long 0x00++0x03
line.long 0x00 "REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 0. "SRAM_PEND,Interrupt Pending Status for sram_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_SET,Interrupt Enable Set Register for sram_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 0. "SRAM_ENABLE_CLR,Interrupt Enable Clear Register for sram_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "PSRAMECC_16K0_RAM"
base ad:0x70000000
group.long 0x00++0x03
line.long 0x00 "RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "RTI0_CFG"
base ad:0xE000000
group.long 0x00++0x1B
line.long 0x00 "CFG_GCTRL,"
bitfld.long 0x00 16.--19. "NTUSEL,These bits determine which NTU input signal is used as external timebase" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
bitfld.long 0x00 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting" "stop counters in debug mode,continue counting in debug mode"
newline
bitfld.long 0x00 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1)" "stop counters,start counters"
bitfld.long 0x00 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters"
line.long 0x04 "CFG_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "CFG_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
bitfld.long 0x08 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "CFG_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "CFG_FRC0,"
line.long 0x14 "CFG_UC0,"
line.long 0x18 "CFG_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "CFG_CAFRC0,"
line.long 0x04 "CFG_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "CFG_FRC1,"
line.long 0x04 "CFG_UC1,"
line.long 0x08 "CFG_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "CFG_CAFRC1,"
line.long 0x04 "CFG_CAUC1,"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x08 0x10 0x18 )
group.long ($2+0x50)++0x03
line.long 0x00 "CFG_COMP$1,"
repeat.end
group.long 0x54++0x03
line.long 0x00 "CFG_UDCP0,"
group.long 0x5C++0x03
line.long 0x00 "CFG_UDCP1,"
group.long 0x64++0x03
line.long 0x00 "CFG_UDCP2,"
group.long 0x6C++0x0B
line.long 0x00 "CFG_UDCP3,"
line.long 0x04 "CFG_TBLCOMP,"
line.long 0x08 "CFG_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "CFG_SETINT,"
bitfld.long 0x00 18. "SETOVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 17. "SETOVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 11. "SETDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 3. "SETINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 2. "SETINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 1. "SETINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 0. "SETINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "CFG_CLEARINT,"
bitfld.long 0x04 18. "CLEAROVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 17. "CLEAROVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 16. "CLEARTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 11. "CLEARDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 3. "CLEARINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 2. "CLEARINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 1. "CLEARINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 0. "CLEARINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "CFG_INTFLAG,"
bitfld.long 0x08 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 3. "INT3,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "CFG_DWDCTRL,"
line.long 0x04 "CFG_DWDPRLD,"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value"
line.long 0x08 "CFG_WDSTATUS,"
bitfld.long 0x08 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 1. "DWDST,status flag and is maintained for compatibility reasons" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 0. "AWDST,User and priviledge mode (read)" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "CFG_WDKEY,"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate"
line.long 0x10 "CFG_DWDCNTR,"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF"
line.long 0x14 "CFG_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,User and privilege mode (read) privileged mode (write)" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "CFG_WWDSIZECTRL,"
line.long 0x1C "CFG_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "CFG_COMP0CLR,"
line.long 0x24 "CFG_COMP1CLR,"
line.long 0x28 "CFG_COMP2CLR,"
line.long 0x2C "CFG_COMP3CLR,"
tree.end
tree "RTI15_CFG"
base ad:0xE0F0000
group.long 0x00++0x1B
line.long 0x00 "CFG_GCTRL,"
bitfld.long 0x00 16.--19. "NTUSEL,These bits determine which NTU input signal is used as external timebase" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
bitfld.long 0x00 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting" "stop counters in debug mode,continue counting in debug mode"
newline
bitfld.long 0x00 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1)" "stop counters,start counters"
bitfld.long 0x00 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters"
line.long 0x04 "CFG_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "CFG_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
bitfld.long 0x08 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "CFG_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "CFG_FRC0,"
line.long 0x14 "CFG_UC0,"
line.long 0x18 "CFG_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "CFG_CAFRC0,"
line.long 0x04 "CFG_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "CFG_FRC1,"
line.long 0x04 "CFG_UC1,"
line.long 0x08 "CFG_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "CFG_CAFRC1,"
line.long 0x04 "CFG_CAUC1,"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x08 0x10 0x18 )
group.long ($2+0x50)++0x03
line.long 0x00 "CFG_COMP$1,"
repeat.end
group.long 0x54++0x03
line.long 0x00 "CFG_UDCP0,"
group.long 0x5C++0x03
line.long 0x00 "CFG_UDCP1,"
group.long 0x64++0x03
line.long 0x00 "CFG_UDCP2,"
group.long 0x6C++0x0B
line.long 0x00 "CFG_UDCP3,"
line.long 0x04 "CFG_TBLCOMP,"
line.long 0x08 "CFG_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "CFG_SETINT,"
bitfld.long 0x00 18. "SETOVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 17. "SETOVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 11. "SETDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 3. "SETINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 2. "SETINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 1. "SETINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 0. "SETINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "CFG_CLEARINT,"
bitfld.long 0x04 18. "CLEAROVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 17. "CLEAROVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 16. "CLEARTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 11. "CLEARDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 3. "CLEARINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 2. "CLEARINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 1. "CLEARINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 0. "CLEARINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "CFG_INTFLAG,"
bitfld.long 0x08 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 3. "INT3,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "CFG_DWDCTRL,"
line.long 0x04 "CFG_DWDPRLD,"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value"
line.long 0x08 "CFG_WDSTATUS,"
bitfld.long 0x08 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 1. "DWDST,status flag and is maintained for compatibility reasons" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 0. "AWDST,User and priviledge mode (read)" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "CFG_WDKEY,"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate"
line.long 0x10 "CFG_DWDCNTR,"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF"
line.long 0x14 "CFG_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,User and privilege mode (read) privileged mode (write)" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "CFG_WWDSIZECTRL,"
line.long 0x1C "CFG_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "CFG_COMP0CLR,"
line.long 0x24 "CFG_COMP1CLR,"
line.long 0x28 "CFG_COMP2CLR,"
line.long 0x2C "CFG_COMP3CLR,"
tree.end
tree "RTI1_CFG"
base ad:0xE010000
group.long 0x00++0x1B
line.long 0x00 "CFG_GCTRL,"
bitfld.long 0x00 16.--19. "NTUSEL,These bits determine which NTU input signal is used as external timebase" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
bitfld.long 0x00 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting" "stop counters in debug mode,continue counting in debug mode"
newline
bitfld.long 0x00 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1)" "stop counters,start counters"
bitfld.long 0x00 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters"
line.long 0x04 "CFG_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "CFG_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
bitfld.long 0x08 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "CFG_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "CFG_FRC0,"
line.long 0x14 "CFG_UC0,"
line.long 0x18 "CFG_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "CFG_CAFRC0,"
line.long 0x04 "CFG_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "CFG_FRC1,"
line.long 0x04 "CFG_UC1,"
line.long 0x08 "CFG_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "CFG_CAFRC1,"
line.long 0x04 "CFG_CAUC1,"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x08 0x10 0x18 )
group.long ($2+0x50)++0x03
line.long 0x00 "CFG_COMP$1,"
repeat.end
group.long 0x54++0x03
line.long 0x00 "CFG_UDCP0,"
group.long 0x5C++0x03
line.long 0x00 "CFG_UDCP1,"
group.long 0x64++0x03
line.long 0x00 "CFG_UDCP2,"
group.long 0x6C++0x0B
line.long 0x00 "CFG_UDCP3,"
line.long 0x04 "CFG_TBLCOMP,"
line.long 0x08 "CFG_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "CFG_SETINT,"
bitfld.long 0x00 18. "SETOVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 17. "SETOVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 11. "SETDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 3. "SETINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 2. "SETINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 1. "SETINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 0. "SETINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "CFG_CLEARINT,"
bitfld.long 0x04 18. "CLEAROVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 17. "CLEAROVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 16. "CLEARTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 11. "CLEARDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 3. "CLEARINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 2. "CLEARINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 1. "CLEARINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 0. "CLEARINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "CFG_INTFLAG,"
bitfld.long 0x08 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 3. "INT3,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "CFG_DWDCTRL,"
line.long 0x04 "CFG_DWDPRLD,"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value"
line.long 0x08 "CFG_WDSTATUS,"
bitfld.long 0x08 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 1. "DWDST,status flag and is maintained for compatibility reasons" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 0. "AWDST,User and priviledge mode (read)" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "CFG_WDKEY,"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate"
line.long 0x10 "CFG_DWDCNTR,"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF"
line.long 0x14 "CFG_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,User and privilege mode (read) privileged mode (write)" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "CFG_WWDSIZECTRL,"
line.long 0x1C "CFG_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "CFG_COMP0CLR,"
line.long 0x24 "CFG_COMP1CLR,"
line.long 0x28 "CFG_COMP2CLR,"
line.long 0x2C "CFG_COMP3CLR,"
tree.end
tree "RTI2_CFG"
base ad:0xE020000
group.long 0x00++0x1B
line.long 0x00 "CFG_GCTRL,"
bitfld.long 0x00 16.--19. "NTUSEL,These bits determine which NTU input signal is used as external timebase" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
bitfld.long 0x00 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting" "stop counters in debug mode,continue counting in debug mode"
newline
bitfld.long 0x00 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1)" "stop counters,start counters"
bitfld.long 0x00 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters"
line.long 0x04 "CFG_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "CFG_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
bitfld.long 0x08 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "CFG_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "CFG_FRC0,"
line.long 0x14 "CFG_UC0,"
line.long 0x18 "CFG_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "CFG_CAFRC0,"
line.long 0x04 "CFG_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "CFG_FRC1,"
line.long 0x04 "CFG_UC1,"
line.long 0x08 "CFG_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "CFG_CAFRC1,"
line.long 0x04 "CFG_CAUC1,"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x08 0x10 0x18 )
group.long ($2+0x50)++0x03
line.long 0x00 "CFG_COMP$1,"
repeat.end
group.long 0x54++0x03
line.long 0x00 "CFG_UDCP0,"
group.long 0x5C++0x03
line.long 0x00 "CFG_UDCP1,"
group.long 0x64++0x03
line.long 0x00 "CFG_UDCP2,"
group.long 0x6C++0x0B
line.long 0x00 "CFG_UDCP3,"
line.long 0x04 "CFG_TBLCOMP,"
line.long 0x08 "CFG_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "CFG_SETINT,"
bitfld.long 0x00 18. "SETOVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 17. "SETOVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 11. "SETDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 3. "SETINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 2. "SETINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 1. "SETINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 0. "SETINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "CFG_CLEARINT,"
bitfld.long 0x04 18. "CLEAROVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 17. "CLEAROVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 16. "CLEARTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 11. "CLEARDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 3. "CLEARINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 2. "CLEARINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 1. "CLEARINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 0. "CLEARINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "CFG_INTFLAG,"
bitfld.long 0x08 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 3. "INT3,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "CFG_DWDCTRL,"
line.long 0x04 "CFG_DWDPRLD,"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value"
line.long 0x08 "CFG_WDSTATUS,"
bitfld.long 0x08 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 1. "DWDST,status flag and is maintained for compatibility reasons" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 0. "AWDST,User and priviledge mode (read)" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "CFG_WDKEY,"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate"
line.long 0x10 "CFG_DWDCNTR,"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF"
line.long 0x14 "CFG_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,User and privilege mode (read) privileged mode (write)" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "CFG_WWDSIZECTRL,"
line.long 0x1C "CFG_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "CFG_COMP0CLR,"
line.long 0x24 "CFG_COMP1CLR,"
line.long 0x28 "CFG_COMP2CLR,"
line.long 0x2C "CFG_COMP3CLR,"
tree.end
tree "RTI3_CFG"
base ad:0xE030000
group.long 0x00++0x1B
line.long 0x00 "CFG_GCTRL,"
bitfld.long 0x00 16.--19. "NTUSEL,These bits determine which NTU input signal is used as external timebase" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
bitfld.long 0x00 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting" "stop counters in debug mode,continue counting in debug mode"
newline
bitfld.long 0x00 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1)" "stop counters,start counters"
bitfld.long 0x00 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters"
line.long 0x04 "CFG_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "CFG_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
bitfld.long 0x08 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "CFG_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "CFG_FRC0,"
line.long 0x14 "CFG_UC0,"
line.long 0x18 "CFG_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "CFG_CAFRC0,"
line.long 0x04 "CFG_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "CFG_FRC1,"
line.long 0x04 "CFG_UC1,"
line.long 0x08 "CFG_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "CFG_CAFRC1,"
line.long 0x04 "CFG_CAUC1,"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x08 0x10 0x18 )
group.long ($2+0x50)++0x03
line.long 0x00 "CFG_COMP$1,"
repeat.end
group.long 0x54++0x03
line.long 0x00 "CFG_UDCP0,"
group.long 0x5C++0x03
line.long 0x00 "CFG_UDCP1,"
group.long 0x64++0x03
line.long 0x00 "CFG_UDCP2,"
group.long 0x6C++0x0B
line.long 0x00 "CFG_UDCP3,"
line.long 0x04 "CFG_TBLCOMP,"
line.long 0x08 "CFG_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "CFG_SETINT,"
bitfld.long 0x00 18. "SETOVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 17. "SETOVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 11. "SETDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 3. "SETINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 2. "SETINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 1. "SETINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 0. "SETINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "CFG_CLEARINT,"
bitfld.long 0x04 18. "CLEAROVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 17. "CLEAROVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 16. "CLEARTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 11. "CLEARDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 3. "CLEARINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 2. "CLEARINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 1. "CLEARINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 0. "CLEARINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "CFG_INTFLAG,"
bitfld.long 0x08 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 3. "INT3,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "CFG_DWDCTRL,"
line.long 0x04 "CFG_DWDPRLD,"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value"
line.long 0x08 "CFG_WDSTATUS,"
bitfld.long 0x08 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 1. "DWDST,status flag and is maintained for compatibility reasons" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 0. "AWDST,User and priviledge mode (read)" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "CFG_WDKEY,"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate"
line.long 0x10 "CFG_DWDCNTR,"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF"
line.long 0x14 "CFG_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,User and privilege mode (read) privileged mode (write)" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "CFG_WWDSIZECTRL,"
line.long 0x1C "CFG_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "CFG_COMP0CLR,"
line.long 0x24 "CFG_COMP1CLR,"
line.long 0x28 "CFG_COMP2CLR,"
line.long 0x2C "CFG_COMP3CLR,"
tree.end
tree "SPINLOCK0"
base ad:0x2A000000
rgroup.long 0x00++0x03
line.long 0x00 "REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU identifier" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module family"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_REV,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Special version number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR_REV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x07
line.long 0x00 "REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock"
bitfld.long 0x00 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware" "0,1"
line.long 0x04 "REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module"
hexmask.long.byte 0x04 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32"
bitfld.long 0x04 7. "IN_USE7,In-Use flag 7 covering lock registers" "All lock registers 224 - 255 are in the Not..,At least one of the lock registers 224 - 255 are.."
newline
bitfld.long 0x04 6. "IN_USE6,In-Use flag 6 covering lock registers" "All lock registers 192 - 223 are in the Not..,At least one of the lock registers 192 - 223 are.."
bitfld.long 0x04 5. "IN_USE5,In-Use flag 5 covering lock registers" "All lock registers 160 - 191 are in the Not..,At least one of the lock registers 160 - 191 are.."
newline
bitfld.long 0x04 4. "IN_USE4,In-Use flag 4 covering lock registers" "All lock registers 128 - 159 are in the Not..,At least one of the lock registers 128 - 159 are.."
bitfld.long 0x04 3. "IN_USE3,In-Use flag 3 covering lock registers" "All lock registers 96 - 127 are in the Not Taken..,At least one of the lock registers 96 - 127 are.."
newline
bitfld.long 0x04 2. "IN_USE2,In-Use flag 2 covering lock registers" "All lock registers 64 - 95 are in the Not Taken..,At least one of the lock registers 64 - 95 are.."
bitfld.long 0x04 1. "IN_USE1,In-Use flag 1 covering lock registers" "All lock registers 32 - 63 are in the Not Taken..,At least one of the lock registers 32 - 63 are.."
newline
bitfld.long 0x04 0. "IN_USE0,In-Use flag 0 covering lock registers" "All lock registers 0 - 31 are in the Not Taken..,At least one of the lock registers 0 - 31 are in.."
group.long 0x800++0x03
line.long 0x00 "REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'"
bitfld.long 0x00 0. "TAKEN,Lock Status" "Free the lock by setting..,No effect"
tree.end
tree "STM0_CTI_CSCTI"
base ad:0x73D201000
group.long 0x00++0x03
line.long 0x00 "CTI__CFG__CSCTI_CFG_CTICONTROL,The CTI Control Register enables the CTI"
bitfld.long 0x00 0. "GLBEN,Enables or disables the ECT" "0,1"
group.long 0x10++0x17
line.long 0x00 "CTI__CFG__CSCTI_CFG_CTIINTACK,The CTI Interrupt Acknowledge Register is write-only"
hexmask.long.byte 0x00 0.--7. 1. "INTACK,Acknowledges the corresponding ctitrigout output"
line.long 0x04 "CTI__CFG__CSCTI_CFG_CTIAPPSET,The CTI Application Trigger Set Register is read/"
bitfld.long 0x04 0.--3. "APPSET,Setting a bit HIGH generates a channel event for the selected channel" "no effect,generate channel event,?..."
line.long 0x08 "CTI__CFG__CSCTI_CFG_CTIAPPCLEAR,The CTI Interrupt Acknowledge Register is write-only"
bitfld.long 0x08 0.--3. "APPCLEAR,Clears corresponding bits in the CTIAPPSET register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CTI__CFG__CSCTI_CFG_CTIAPPPULSE,The CTI Application Pulse Register is write-only"
bitfld.long 0x0C 0.--3. "APPULSE,Setting a bit HIGH generates a channel event pulse for the selected channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CTI__CFG__CSCTI_CFG_CTIINEN0,The CTI Trigger 0 to Channel Enable Register enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI"
bitfld.long 0x10 0.--3. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "CTI__CFG__CSCTI_CFG_CTIINEN1,The CTI Trigger 1 to Channel Enable Register enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI"
bitfld.long 0x14 0.--3. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 6. (list 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x28)++0x03
line.long 0x00 "CTI__CFG__CSCTI_CFG_CTIINEN$1,The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger. ctitrigin. to the CTI"
bitfld.long 0x00 0.--3. "TRIGINEN,Enables a cross trigger event to the corresponding channel when an ctitrigin is activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
group.long 0xA0++0x1F
line.long 0x00 "CTI__CFG__CSCTI_CFG_CTIOUTEN0,The CTI Channel to Trigger 0 Enable Registers define which channels can generate a ctitrigout[0] output"
bitfld.long 0x00 0.--3. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[1] output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CTI__CFG__CSCTI_CFG_CTIOUTEN1,The CTI Channel to Trigger 1 Enable Registers define which channels can generate a ctitrigout[1] output"
bitfld.long 0x04 0.--3. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[1] output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CTI__CFG__CSCTI_CFG_CTIOUTEN2,The CTI Channel to Trigger 2 Enable Registers define which channels can generate a ctitrigout[2] output"
bitfld.long 0x08 0.--3. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[2] output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CTI__CFG__CSCTI_CFG_CTIOUTEN3,The CTI Channel to Trigger 3 Enable Registers define which channels can generate a ctitrigout[3] output"
bitfld.long 0x0C 0.--3. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[3] output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CTI__CFG__CSCTI_CFG_CTIOUTEN4,The CTI Channel to Trigger 4 Enable Registers define which channels can generate a ctitrigout[4] output"
bitfld.long 0x10 0.--3. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[4] output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "CTI__CFG__CSCTI_CFG_CTIOUTEN5,The CTI Channel to Trigger 5 Enable Registers define which channels can generate a ctitrigout[5] output"
bitfld.long 0x14 0.--3. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[5] output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "CTI__CFG__CSCTI_CFG_CTIOUTEN6,The CTI Channel to Trigger 6 Enable Registers define which channels can generate a ctitrigout[6] output"
bitfld.long 0x18 0.--3. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[6] output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "CTI__CFG__CSCTI_CFG_CTIOUTEN7,The CTI Channel to Trigger 7 Enable Registers define which channels can generate a ctitrigout[7] output"
bitfld.long 0x1C 0.--3. "TRIGOUTEN,Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[7] output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x130++0x17
line.long 0x00 "CTI__CFG__CSCTI_CFG_CTITRIGINSTATUS,The CTI Trigger In Status Register provides the status of the ctitrigin inputs"
abitfld.long 0x00 0.--7. "TRIGINSTATUS,Shows the status of the ctitrigin inputs" "0x00=ctitrigin is inactive,0x01=ctitrigin is active"
line.long 0x04 "CTI__CFG__CSCTI_CFG_CTITRIGOUTSTATUS,The CTI Trigger Out Status Register provides the status of the ctitrigout outputs"
abitfld.long 0x04 0.--7. "TRIGOUTSTATUS,Shows the status of the ctitrigout outputs" "0x00=ctitrigout is inactive,0x01=ctitrigout is active"
line.long 0x08 "CTI__CFG__CSCTI_CFG_CTICHINSTATUS,The CTI Channel In Status Register provides the status of the ctichin inputs"
bitfld.long 0x08 0.--3. "CTICHINSTATUS,Shows the status of the ctichin inputs" "ctichin is inactive,ctichin is active,?..."
line.long 0x0C "CTI__CFG__CSCTI_CFG_CTICHOUTSTATUS,The CTI Channel Out Status Register provides the status of the CTI ctichout outputs"
bitfld.long 0x0C 0.--3. "CTICHOUTSTATUS,Shows the status of the ctichout outputs" "ctichout is inactive,ctichout is active,?..."
line.long 0x10 "CTI__CFG__CSCTI_CFG_CTIGATE,The Gate Enable Register prevents the channels from propagating through the CTM to other CTIs"
bitfld.long 0x10 3. "CTIGATEEN3,Enable CTICHOUT3" "0,1"
bitfld.long 0x10 2. "CTIGATEEN2,Enable CTICHOUT2" "0,1"
bitfld.long 0x10 1. "CTIGATEEN1,Enable CTICHOUT1" "0,1"
bitfld.long 0x10 0. "CTIGATEEN0,Enable CTICHOUT0" "0,1"
line.long 0x14 "CTI__CFG__CSCTI_CFG_ASICCTL,Implementation-defined ASIC control. value written to the register is output on asicctl[7 : 0]"
hexmask.long.byte 0x14 0.--7. 1. "ASICCTL,Implementation-defined ASIC control value written to the register is output on asicctl[7 : 0]"
group.long 0xEDC++0x1F
line.long 0x00 "CTI__CFG__CSCTI_CFG_ITCHINACK,This register is a write-only register"
bitfld.long 0x00 0.--3. "CTCHINACK,Set the value of the CTCHINACK outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CTI__CFG__CSCTI_CFG_ITTRIGINACK,This register is a write-only register"
hexmask.long.byte 0x04 0.--7. 1. "CTTRIGINACK,Set the value of the CTTRIGINACK outputs"
line.long 0x08 "CTI__CFG__CSCTI_CFG_ITCHOUT,This register is a write-only register"
bitfld.long 0x08 0.--3. "CTCHOUT,Set the value of the CTCHOUT outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CTI__CFG__CSCTI_CFG_ITTRIGOUT,This register is a write-only register"
hexmask.long.byte 0x0C 0.--7. 1. "CTTRIGOUT,Set the value of the CTTRIGOUT outputs"
line.long 0x10 "CTI__CFG__CSCTI_CFG_ITCHOUTACK,This register is a read-only register"
bitfld.long 0x10 0.--3. "CTCHOUTACK,Read the values of the CTCHOUTACK inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "CTI__CFG__CSCTI_CFG_ITTRIGOUTACK,This register is a read-only register"
hexmask.long.byte 0x14 0.--7. 1. "CTTRIGOUTACK,Read the value of the CTTRIGOUTACK inputs"
line.long 0x18 "CTI__CFG__CSCTI_CFG_ITCHIN,This register is a read-only register"
bitfld.long 0x18 0.--3. "CTCHIN,Read the value of the CTCHIN inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "CTI__CFG__CSCTI_CFG_ITTRIGIN,This register is a read-only register"
hexmask.long.byte 0x1C 0.--7. 1. "CTTRIGIN,Read the values of the CTTRIGIN inputs"
group.long 0xF00++0x03
line.long 0x00 "CTI__CFG__CSCTI_CFG_ITCTRL,This register is used to enable topology detection"
bitfld.long 0x00 0. "INTEGRATION_MODE,Allows the component to switch from functional mode to integration mode or back" "0,1"
group.long 0xFA0++0x07
line.long 0x00 "CTI__CFG__CSCTI_CFG_CLAIMSET,This is used in conjunction with Claim Tag Clear Register. CLAIMCLR"
bitfld.long 0x00 0.--3. "CLAIMSET,This claim tag bit is implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CTI__CFG__CSCTI_CFG_CLAIMCLR,This register is used in conjunction with Claim Tag Set Register. CLAIMSET"
bitfld.long 0x04 0.--3. "CLAIMCLR,The value present reflects the current setting of the Claim Tag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFB0++0x0B
line.long 0x00 "CTI__CFG__CSCTI_CFG_LAR,This is used to enable write access to device registers"
line.long 0x04 "CTI__CFG__CSCTI_CFG_LSR,This indicates the status of the Lock control mechanism"
bitfld.long 0x04 2. "LOCKTYPE,Indicates if the Lock Access Register (0xFB0) is implemented as 8-bit or 32-bit" "0,1"
bitfld.long 0x04 1. "LOCKGRANT,Returns the current status of the Lock" "0,1"
bitfld.long 0x04 0. "LOCKEXIST,Indicates that a lock control mechanism exists for this device" "0,1"
line.long 0x08 "CTI__CFG__CSCTI_CFG_AUTHSTATUS,Reports what functionality is currently permitted by the authentication interface"
bitfld.long 0x08 6.--7. "SNID,Indicates the security level for secure non-invasive debug" "0,1,2,3"
bitfld.long 0x08 4.--5. "SID,Indicates the security level for secure invasive debug" "0,1,2,3"
bitfld.long 0x08 2.--3. "NSNID,Indicates the security level for non-secure non-invasive debug" "0,1,2,3"
bitfld.long 0x08 0.--1. "NSID,Indicates the security level for non-secure invasive debug" "0,1,2,3"
rgroup.long 0xFC8++0x0B
line.long 0x00 "CTI__CFG__CSCTI_CFG_DEVID,This register indicates the capabilities of the CTI"
bitfld.long 0x00 16.--19. "NUMCH,Number of ECT channels available" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "NUMTRIG,Number of ECT triggers available"
bitfld.long 0x00 0.--4. "EXTMUXNUM,Indicates the number of multiplexing available on Trigger Inputs and Trigger Outputs using asicctl" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CTI__CFG__CSCTI_CFG_DEVTYPE,It provides a debugger with information about the component when the Part Number field is not recognized"
bitfld.long 0x04 4.--7. "SUB_TYPE,Sub-classification within the major category" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "MAJOR_TYPE,Major classification grouping for this debug/trace component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CTI__CFG__CSCTI_CFG_PERIPHID4,Part of the set of Peripheral Identification registers"
bitfld.long 0x08 4.--7. "SIZE,This is a 4-bit value that indicates the total contiguous size of the memory window used by this component in powers of 2 from the standard 4KB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--3. "DES_2,JEDEC continuation code indicating the designer of the component (along with the identity code)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFE0++0x1F
line.long 0x00 "CTI__CFG__CSCTI_CFG_PERIPHID0,Part of the set of Peripheral Identification registers"
hexmask.long.byte 0x00 0.--7. 1. "PART_0,Bits [7 : 0] of the component's part number"
line.long 0x04 "CTI__CFG__CSCTI_CFG_PERIPHID1,Part of the set of Peripheral Identification registers"
bitfld.long 0x04 4.--7. "DES_0,Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "PART_1,Bits [11 : 8] of the component's part number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CTI__CFG__CSCTI_CFG_PERIPHID2,Part of the set of Peripheral Identification registers"
bitfld.long 0x08 4.--7. "REVISION,The Revision field is an incremental value starting at 0x0 for the first design of this component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3. "JEDEC,Always set" "0,1"
bitfld.long 0x08 0.--2. "DES_1,Bits" "0,1,2,3,4,5,6,7"
line.long 0x0C "CTI__CFG__CSCTI_CFG_PERIPHID3,Part of the set of Peripheral Identification registers"
bitfld.long 0x0C 4.--7. "REVAND,This field indicates minor errata fixes specific to this design for example metal fixes after implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "CMOD,Where the component is reusable IP this value indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CTI__CFG__CSCTI_CFG_COMPID0,Reserved Reserved Reserved A component identification register. that indicates that the identification registers are present"
hexmask.long.byte 0x10 0.--7. 1. "PRMBL_0,Contains bits [7 : 0] of the component identification"
line.long 0x14 "CTI__CFG__CSCTI_CFG_COMPID1,A component identification register. that indicates that the identification registers are present"
bitfld.long 0x14 4.--7. "CLASS,Class of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--3. "PRMBL_1,Contains bits [11 : 8] of the component identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "CTI__CFG__CSCTI_CFG_COMPID2,A component identification register. that indicates that the identification registers are present"
hexmask.long.byte 0x18 0.--7. 1. "PRMBL_2,Contains bits [23 : 16] of the component identification"
line.long 0x1C "CTI__CFG__CSCTI_CFG_COMPID3,A component identification register. that indicates that the identification registers are present"
hexmask.long.byte 0x1C 0.--7. 1. "PRMBL_3,Contains bits [31 : 24] of the component identification"
tree.end
tree "STM0_CXSTM"
base ad:0x73D200000
group.long 0xC04++0x0F
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDMASTARTR,This write-only register is used to start a DMA transfer.<p/>A write of one when the DMA peripheral request interface is idle starts a DMA transfer"
bitfld.long 0x00 0. "START," "0,1"
line.long 0x04 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDMASTOPR,This write-only register is used to stop a DMA transfer.<p/>A write of one stops an active DMA transfer"
bitfld.long 0x04 0. "STOP," "0,1"
line.long 0x08 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDMASTATR,This read-only register is used to determine the status of the DMA peripheral request interface"
bitfld.long 0x08 0. "STATUS," "0,1"
line.long 0x0C "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDMACTLR,Controls the DMA transfer request mechanism"
bitfld.long 0x0C 2.--3. "SENS," "0,1,2,3"
rgroup.long 0xCFC++0x07
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDMAIDR,This read-only register indicates the DMA features of the STM"
bitfld.long 0x00 8.--11. "VENDSPEC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "CLASSREV," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "CLASS," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEER,This read/write register is used to enable hardware events to generate trace.<p/>The register defined one bit per hardware event"
group.long 0xD20++0x03
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHETER,This register is used to enable trigger generation on hardware events"
group.long 0xD60++0x0B
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEBSR,This register is used to select the Hardware Event bank"
bitfld.long 0x00 0. "HEBS," "0,1"
line.long 0x04 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEMCR,This register is used to control the primary functions of Hardware Event tracing"
bitfld.long 0x04 7. "ATBTRIGEN," "0,1"
bitfld.long 0x04 6. "TRIGCLEAR," "0,1"
rbitfld.long 0x04 5. "TRIGSTATUS," "0,1"
bitfld.long 0x04 4. "TRIGCTL," "0,1"
rbitfld.long 0x04 2. "ERRDETECT," "0,1"
newline
bitfld.long 0x04 1. "COMPEN," "0,1"
bitfld.long 0x04 0. "EN," "0,1"
line.long 0x08 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEEXTMUXR,This register is used to control hardware event multiplexors external to the STM"
hexmask.long.byte 0x08 0.--7. 1. "EXTMUX,"
rgroup.long 0xDF4++0x0F
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEMASTR,Indicates the STPv2 master number of hardware event trace"
hexmask.long.word 0x00 0.--15. 1. "MASTER,"
line.long 0x04 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEFEAT1R,Indicates the features of the STM"
bitfld.long 0x04 28.--30. "HEEXTMUXSIZE," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 15.--23. 1. "NUMHE,"
bitfld.long 0x04 4.--5. "HECOMP," "0,1,2,3"
bitfld.long 0x04 3. "HEMASTR," "0,1"
bitfld.long 0x04 2. "HEERR," "0,1"
newline
bitfld.long 0x04 0. "HETER," "0,1"
line.long 0x08 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMHEIDR,Indicates the features of hardware event tracing in the STM"
bitfld.long 0x08 8.--11. "VENDSPEC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 4.--7. "CLASSREV," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--3. "CLASS," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPER,This read/write only register is used to enable the stimulus registers to generate trace.<p/>The register defines one bit per stimulus register"
group.long 0xE20++0x03
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPTER,This register is used to enable trigger generation on writes to enabled stimulus port registers"
group.long 0xE60++0x13
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPSCR,This register allows a debugger to program which stimulus ports the STMSPER and STMSPTER apply to"
hexmask.long.word 0x00 20.--31. 1. "PORTSEL,"
bitfld.long 0x00 0.--1. "PORTCTL," "0,1,2,3"
line.long 0x04 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPMSCR,This register allows a debugger to program which masters the STMSPSCR applies to"
hexmask.long.byte 0x04 15.--22. 1. "MASTSEL,"
bitfld.long 0x04 0. "MASTCTL," "0,1"
line.long 0x08 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPOVERRIDER,This register allows a debugger to override various features of the STM"
hexmask.long.tbyte 0x08 15.--31. 1. "PORTSEL,"
bitfld.long 0x08 2. "OVERTS," "0,1"
bitfld.long 0x08 0.--1. "OVERCTL," "0,1,2,3"
line.long 0x0C "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPMOVERRIDER,This register allows a debugger to choose which masters the STMSPOVERRIDERR applies to"
hexmask.long.byte 0x0C 15.--22. 1. "MASTSEL,"
bitfld.long 0x0C 0. "MASTCTL," "0,1"
line.long 0x10 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSPTRIGCSR,This register is used to control the STM triggers caused by STMSPTER"
bitfld.long 0x10 4. "ATBTRIGEN_DIR," "0,1"
bitfld.long 0x10 3. "ATBTRIGEN_TE," "0,1"
bitfld.long 0x10 2. "TRIGCLEAR," "0,1"
rbitfld.long 0x10 1. "TRIGSTATUS," "0,1"
bitfld.long 0x10 0. "TRIGCTL," "0,1"
group.long 0xE80++0x07
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMTCSR,Controls the STM settings"
rbitfld.long 0x00 23. "BUSY," "0,1"
hexmask.long.byte 0x00 16.--22. 1. "TRACEID,"
bitfld.long 0x00 5. "COMPEN," "0,1"
rbitfld.long 0x00 2. "SYNCEN," "0,1"
bitfld.long 0x00 1. "TSEN," "0,1"
newline
bitfld.long 0x00 0. "EN," "0,1"
line.long 0x04 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMTSSTIMR,This write-only register is used to force the next packet caused by a stimulus port write to have a timestamp output"
bitfld.long 0x04 0. "FORCETS," "0,1"
group.long 0xE8C++0x0B
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMTSFREQR,This read-write register is used to indicate the frequency of the timestamp counter"
line.long 0x04 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMSYNCR,This register controls the interval between synchronization packets. in terms of the number of bytes of trace generated.<p/>This register only provides a hint of the desired synchronization frequency.."
bitfld.long 0x04 12. "MODE," "0,1"
hexmask.long.word 0x04 3.--11. 1. "COUNT,"
line.long 0x08 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMAUXCR,Used for IMPLEMENTATION DEFINED STM controls"
bitfld.long 0x08 7. "QHWEVOVERRIDE," "0,1"
bitfld.long 0x08 2. "PRIORINVDIS," "0,1"
bitfld.long 0x08 1. "ASYNCPE," "0,1"
bitfld.long 0x08 0. "FIFOAF," "0,1"
rgroup.long 0xEA0++0x0B
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMFEAT1R,Indicates the features of the STM"
bitfld.long 0x00 22.--23. "SWOEN," "0,1,2,3"
bitfld.long 0x00 20.--21. "SYNCEN," "0,1,2,3"
bitfld.long 0x00 18.--19. "HWTEN," "0,1,2,3"
bitfld.long 0x00 16.--17. "TSPRESCALE," "0,1,2,3"
bitfld.long 0x00 14.--15. "TRIGCTL," "0,1,2,3"
newline
bitfld.long 0x00 10.--13. "TRACEBUS," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--9. "SYNC," "0,1,2,3"
bitfld.long 0x00 7. "FORCETS," "0,1"
bitfld.long 0x00 6. "TSFREQ," "0,1"
bitfld.long 0x00 4.--5. "TS," "0,1,2,3"
newline
bitfld.long 0x00 0.--3. "PROT," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMFEAT2R,Indicates the features of the STM"
bitfld.long 0x04 16.--17. "SPTYPE," "0,1,2,3"
bitfld.long 0x04 12.--15. "DSIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 9.--10. "SPTRTYPE," "0,1,2,3"
bitfld.long 0x04 7.--8. "PRIVMASK," "0,1,2,3"
bitfld.long 0x04 6. "SPOVERRIDE," "0,1"
newline
bitfld.long 0x04 4.--5. "SPCOMP," "0,1,2,3"
bitfld.long 0x04 2. "SPER," "0,1"
bitfld.long 0x04 0.--1. "SPTER," "0,1,2,3"
line.long 0x08 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMFEAT3R,Indicates the features of the STM"
hexmask.long.byte 0x08 0.--6. 1. "NUMMAST,"
group.long 0xEE8++0x13
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITTRIGGER,Integration Test for Cross-Trigger Outputs Register"
bitfld.long 0x00 3. "ASYNCOUT_W," "0,1"
bitfld.long 0x00 2. "TRIGOUTHETE_W," "0,1"
bitfld.long 0x00 1. "TRIGOUTSW_W," "0,1"
bitfld.long 0x00 0. "TRIGOUTSPTE_W," "0,1"
line.long 0x04 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITATBDATA0,Controls the value of the ATDATAM output in integration mode"
bitfld.long 0x04 8. "ATDATAM63_W," "0,1"
bitfld.long 0x04 7. "ATDATAM55_W," "0,1"
bitfld.long 0x04 6. "ATDATAM47_W," "0,1"
bitfld.long 0x04 5. "ATDATAM39_W," "0,1"
bitfld.long 0x04 4. "ATDATAM31_W," "0,1"
newline
bitfld.long 0x04 3. "ATDATAM23_W," "0,1"
bitfld.long 0x04 2. "ATDATAM15_W," "0,1"
bitfld.long 0x04 1. "ATDATAM7_W," "0,1"
bitfld.long 0x04 0. "ATDATAM0_W," "0,1"
line.long 0x08 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITATBCTR2,Returns the value of the ATREADYM and AFVALIDM inputs in integration mode"
bitfld.long 0x08 1. "AFVALIDM_R," "0,1"
bitfld.long 0x08 0. "ATREADYM_R," "0,1"
line.long 0x0C "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITATBID,Controls the value of the ATIDM output in integration mode"
hexmask.long.byte 0x0C 0.--6. 1. "ATIDM_W,"
line.long 0x10 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITATBCTR0,Controls the value of the ATVALIDM. AFREADYM. and ATBYTESM outputs in integration mode"
bitfld.long 0x10 8.--10. "ATBYTESM_W," "0,1,2,3,4,5,6,7"
bitfld.long 0x10 1. "AFREADYM_W," "0,1"
bitfld.long 0x10 0. "ATVALIDM_W," "0,1"
group.long 0xF00++0x03
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMITCTRL,Used to enable topology detection"
bitfld.long 0x00 0. "IME," "0,1"
rgroup.long 0xFA0++0x07
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCLAIMSET,This is used in conjunction with Claim Tag Clear Register. STMCLAIMCLR"
bitfld.long 0x00 0.--3. "SET," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCLAIMCLR,This register is used in conjunction with Claim Tag Set Register. STMCLAIMSET"
bitfld.long 0x04 0.--3. "CLR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFB0++0x0F
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMLAR,Enables write access to device registers"
line.long 0x04 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMLSR,Indicates the status of the lock control mechanism"
bitfld.long 0x04 2. "NTT," "0,1"
bitfld.long 0x04 1. "SLK," "0,1"
bitfld.long 0x04 0. "SLI," "0,1"
line.long 0x08 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMAUTHSTATUS,Reports the required security level and current status of the authentication interface"
bitfld.long 0x08 6.--7. "SNID," "0,1,2,3"
bitfld.long 0x08 4.--5. "SID," "0,1,2,3"
bitfld.long 0x08 2.--3. "NSNID," "0,1,2,3"
bitfld.long 0x08 0.--1. "NSID," "0,1,2,3"
line.long 0x0C "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDEVARCH,Indicates the architect and architecture of the STM"
hexmask.long.word 0x0C 21.--31. 1. "ARCHITECT,"
bitfld.long 0x0C 20. "PRESENT," "0,1"
bitfld.long 0x0C 16.--19. "REVISION," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x0C 0.--14. 1. "ARCHID,"
rgroup.long 0xFC8++0x0B
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDEVID,Indicates the capabilities of the CoreSight STM"
hexmask.long.tbyte 0x00 0.--16. 1. "NUMSP,"
line.long 0x04 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMDEVTYPE,Provides a debugger with information about the component when the part number is not recognized"
bitfld.long 0x04 4.--7. "SUB," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "MAJOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR4,Part of the set of Peripheral Identification registers"
bitfld.long 0x08 4.--7. "SIZE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 0.--3. "DES_2," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 3. (list 5. 6. 7. )(list 0x00 0x04 0x08 )
hgroup.long ($2+0xFD4)++0x03
hide.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR$1,Reserved"
repeat.end
rgroup.long 0xFE0++0x0F
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR0,Part of the set of Peripheral Identification registers"
hexmask.long.byte 0x00 0.--7. 1. "PART_0,"
line.long 0x04 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR1,Part of the set of Peripheral Identification registers"
bitfld.long 0x04 4.--7. "DES_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. "PART_1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR2,Part of the set of Peripheral Identification registers"
bitfld.long 0x08 4.--7. "REVISION," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 3. "JEDEC," "0,1"
bitfld.long 0x08 0.--2. "DES_1," "0,1,2,3,4,5,6,7"
line.long 0x0C "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMPIDR3,Part of the set of Peripheral Identification registers"
bitfld.long 0x0C 4.--7. "REVAND," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "CMOD," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 3. (list 0. 2. 3. )(list 0x00 0x08 0x0C )
rgroup.long ($2+0xFF0)++0x03
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCIDR$1,A component identification register. that indicates that the identification registers are present"
hexmask.long.byte 0x00 0.--7. 1. "PRMBL_0,"
repeat.end
rgroup.long 0xFF4++0x03
line.long 0x00 "VBUSP2APB_WRAP__CXSTM_CFG__STM_REGS_STMCIDR1,A component identification register. that indicates that the identification registers are present"
bitfld.long 0x00 4.--7. "CLASS," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PRMBL_1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "STM0_STIMULUS"
base ad:0x42000000
tree.end
tree "TIMER0_CFG"
base ad:0x2400000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER1_CFG"
base ad:0x2410000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER2_CFG"
base ad:0x2420000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER3_CFG"
base ad:0x2430000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER4_CFG"
base ad:0x2440000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER5_CFG"
base ad:0x2450000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER6_CFG"
base ad:0x2460000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMER7_CFG"
base ad:0x2470000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "TIMESYNC_EVENT_ROUTER0_INTR_ROUTER_CFG"
base ad:0xA40000
rgroup.long 0x00++0x07
line.long 0x00 "INTR_ROUTER_CFG_PID,Identification register"
bitfld.long 0x00 30.--31. "SCHEME,scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,function"
bitfld.long 0x00 11.--15. "RTLVER,rtl version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom id" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINREV,minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register"
bitfld.long 0x04 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1"
bitfld.long 0x04 0.--4. "MUX_CNTL,Mux control for interrupt N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list ad:0x2800000 ad:0x2810000 ad:0x2820000 ad:0x2830000 ad:0x2840000 ad:0x2850000 ad:0x2860000 )
tree "UART$1"
base $2
group.long 0x00++0x03
line.long 0x00 "MEM_DLL,Divisor Latches Low Register"
hexmask.long.byte 0x00 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value"
rgroup.long 0x00++0x03
line.long 0x00 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "RHR,Receive holding register"
group.long 0x00++0x07
line.long 0x00 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER"
line.long 0x04 "MEM_DLH,Divisor Latches High Register"
hexmask.long.byte 0x04 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value"
group.long 0x04++0x03
line.long 0x00 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt"
bitfld.long 0x00 6.--7. "NOT_USED2," "0,1,2,3"
newline
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x00 4. "NOT_USED1," "0,1"
newline
bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x03
line.long 0x00 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt"
bitfld.long 0x00 7. "EOF_IT," "0,1"
newline
bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x00 4. "STS_FIFO_TRIG_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x00 2. "LAST_RX_BYTE_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x07
line.long 0x00 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 7. "CTS_IT," "0,1"
newline
bitfld.long 0x00 6. "RTS_IT," "0,1"
newline
bitfld.long 0x00 5. "XOFF_IT," "0,1"
newline
bitfld.long 0x00 4. "SLEEP_MODE," "0,1"
newline
bitfld.long 0x00 3. "MODEM_STS_IT," "0,1"
newline
bitfld.long 0x00 2. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
line.long 0x04 "MEM_EFR,Enhanced Feature Register"
bitfld.long 0x04 7. "AUTO_CTS_EN,Auto-CTS enable bit" "Normal operation,Auto-CTS flow control is enabled i.e"
newline
bitfld.long 0x04 6. "AUTO_RTS_EN,Auto-RTS enable bit" "Normal operation,Auto- RTS flow control is enabled i.e"
newline
bitfld.long 0x04 5. "SPECIAL_CHAR_DETECT," "0,1"
newline
bitfld.long 0x04 4. "ENHANCED_EN,Enhanced functions write enable bit" "Disables writing to IER bits 4-7 FCR bits 4-5..,Enables writing to IER bits 4-7 FCR bits 4-5 and.."
newline
bitfld.long 0x04 0.--3. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "MEM_FCR,Notes: Bits 4 and 5 can only be written to when EFR[4] = 1 Bits 0 to 3 can be changed only when the baud clock is not running (DLL and DLH set to 0) See Table 31 for FCR[5:4] setting restriction when SCR[6]=1 See Table 32 for FCR[7:6] setting.."
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] =" "8 characters,16 characters,56 characters,60 characters If SCR[7] = 0 and.."
newline
bitfld.long 0x00 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] =" "8 spaces,16 spaces,32 spaces,56 spaces If SCR[6] = 0.."
newline
bitfld.long 0x00 3. "DMA_MODE,This register is considered if SCR[0] = 0" "0,1"
newline
bitfld.long 0x00 2. "TX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x00 1. "RX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x00 0. "FIFO_EN," "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner"
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner"
bitfld.long 0x00 7. "EOF_IT," "0,1"
newline
bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x00 4. "STS_FIFO_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x00 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x0B
line.long 0x00 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
newline
bitfld.long 0x00 1.--5. "IT_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0. "IT_PENDING," "0,1"
line.long 0x04 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception.Note: As soon as LCR[6] is set to 1. the TX line is forced to 0 and remains in this state as long as LCR[6] = 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "DIV_EN," "0,1"
newline
bitfld.long 0x04 6. "BREAK_EN,Break control bit" "0,1"
newline
bitfld.long 0x04 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]" "0,1"
newline
bitfld.long 0x04 4. "PARITY_TYPE1," "0,1"
newline
bitfld.long 0x04 3. "PARITY_EN," "0,1"
newline
bitfld.long 0x04 2. "NB_STOP,Specifies the number of stop bits" "0,1"
newline
bitfld.long 0x04 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3"
line.long 0x08 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x08 7. "RESERVED," "0,1"
newline
bitfld.long 0x08 6. "TCR_TLR," "0,1"
newline
bitfld.long 0x08 5. "XON_EN," "0,1"
newline
bitfld.long 0x08 4. "LOOPBACK_EN," "0,1"
newline
bitfld.long 0x08 3. "CD_STS_CH," "0,1"
newline
bitfld.long 0x08 2. "RI_STS_CH," "0,1"
newline
bitfld.long 0x08 1. "RTS,In loop back controls MSR[4]" "0,1"
newline
bitfld.long 0x08 0. "DTR," "0,1"
group.long 0x10++0x07
line.long 0x00 "MEM_XON1_ADDR1,XON1/ADDR1 Register"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes"
line.long 0x04 "MEM_LSR_CIR,"
bitfld.long 0x04 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x04 6. "RESERVED," "0,1"
newline
bitfld.long 0x04 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR)" "0,1"
newline
bitfld.long 0x04 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "MEM_LSR_IRDA,"
bitfld.long 0x00 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x00 6. "STS_FIFO_FULL," "0,1"
newline
bitfld.long 0x00 5. "RX_LAST_BYTE," "0,1"
newline
bitfld.long 0x00 4. "FRAME_TOO_LONG," "0,1"
newline
bitfld.long 0x00 3. "ABORT," "0,1"
newline
bitfld.long 0x00 2. "CRC," "0,1"
newline
bitfld.long 0x00 1. "STS_FIFO_E," "0,1"
newline
bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "MEM_LSR_UART,"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 7. "RX_FIFO_STS," "0,1"
newline
bitfld.long 0x00 6. "TX_SR_E," "0,1"
newline
bitfld.long 0x00 5. "TX_FIFO_E," "0,1"
newline
bitfld.long 0x00 4. "RX_BI," "0,1"
newline
bitfld.long 0x00 3. "RX_FE," "0,1"
newline
bitfld.long 0x00 2. "RX_PE," "0,1"
newline
bitfld.long 0x00 1. "RX_OE," "0,1"
newline
bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x07
line.long 0x00 "MEM_XON2_ADDR2,XON2/ADDR2 Register"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes"
line.long 0x04 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "NCD_STS,This bit is the complement of the DCD* input" "0,1"
newline
bitfld.long 0x04 6. "NRI_STS,This bit is the complement of the RI* input" "0,1"
newline
bitfld.long 0x04 5. "NDSR_STS,This bit is the complement of the DSR* input" "0,1"
newline
bitfld.long 0x04 4. "NCTS_STS,This bit is the complement of the CTS* input" "0,1"
newline
bitfld.long 0x04 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed" "0,1"
newline
bitfld.long 0x04 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high" "0,1"
newline
bitfld.long 0x04 1. "DSR_STS," "0,1"
newline
bitfld.long 0x04 0. "CTS_STS," "0,1"
group.long 0x18++0x03
line.long 0x00 "MEM_TCR,Transmission Control Register"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x07
line.long 0x00 "MEM_XOFF1,XOFF1 Register"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes"
line.long 0x04 "MEM_SPR,This read/write register does not control the module in anyway"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x04 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x03
line.long 0x00 "MEM_TLR,Trigger Level Register"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x0F
line.long 0x00 "MEM_XOFF2,XOFF2 Register"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes"
line.long 0x04 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR)"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "FRAME_END_MODE,IrDA mode only" "0,1"
newline
bitfld.long 0x04 6. "SIP_MODE,MIR/FIR modes only" "0,1"
newline
bitfld.long 0x04 5. "SCT,Store and control the transmission" "0,1"
newline
bitfld.long 0x04 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1"
newline
bitfld.long 0x04 3. "IR_SLEEP," "0,1"
newline
bitfld.long 0x04 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7"
line.long 0x08 "MEM_MDR2,IR-IrDA and IR-CIR modes only.MDR2[0] describes the status of the interrupt in IIR[5]"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x08 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1"
newline
bitfld.long 0x08 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block" "0,1"
newline
bitfld.long 0x08 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition" "0,1,2,3"
newline
bitfld.long 0x08 3. "UART_PULSE,UART mode only" "0,1"
newline
bitfld.long 0x08 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode" "0,1,2,3"
newline
rbitfld.long 0x08 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is" "0,1"
line.long 0x0C "MEM_SFLSR,IrDA modes only.Reading this register effectively reads frame status information from the status FIFO (this register doesn't physically exist)"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0C 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 4. "OE_ERROR," "0,1"
newline
bitfld.long 0x0C 3. "FRAME_TOO_LONG_ERROR," "0,1"
newline
bitfld.long 0x0C 2. "ABORT_DETECT," "0,1"
newline
bitfld.long 0x0C 1. "CRC_ERROR," "0,1"
newline
bitfld.long 0x0C 0. "RESERVED0," "0,1"
group.long 0x28++0x07
line.long 0x00 "MEM_TXFLL,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes)"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
line.long 0x04 "MEM_RESUME,IR-IrDA and IR-CIR modes only.This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x04 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x07
line.long 0x00 "MEM_TXFLH,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes)"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "TXFLH,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "MEM_RXFLL,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x04 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x07
line.long 0x00 "MEM_SFREGL,IrDA modes only.The frame lengths of received frames are written into the status FIFO"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "SFREGL,LSB part of the frame length"
line.long 0x04 "MEM_RXFLH,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x04 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--3. "RXFLH,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x34++0x07
line.long 0x00 "MEM_SFREGH,IrDA modes only.The frame lengths of received frames are written into the status FIFO"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "SFREGH,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MEM_BLR,IrDA modes only.Note that BLR[6] is used to select whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR Mode"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "STS_FIFO_RESET,Status FIFO reset" "0,1"
newline
bitfld.long 0x04 6. "XBOF_TYPE,SIR xBOF select" "0,1"
newline
rbitfld.long 0x04 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x38++0x13
line.long 0x00 "MEM_UASR,UART Autobauding Status Register"
bitfld.long 0x00 6.--7. "PARITY_TYPE," "?,Parity space,Even Parity,Odd Parity"
newline
bitfld.long 0x00 5. "BIT_BY_CHAR," "0,1"
newline
bitfld.long 0x00 0.--4. "SPEED,Used to report the speed identified" "No speed identified,115200 bauds,57600 bauds,38400 bauds,28800 bauds,19200 bauds,14400 bauds,9600 bauds,4800 bauds,2400 bauds,1200 bauds,?..."
line.long 0x04 "MEM_ACREG,IR-IrDA and IR-CIR modes only"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "PULSE_TYPE,SIR pulse width select" "0,1"
newline
bitfld.long 0x04 6. "SD_MOD,Primary output used to configure transceivers" "0,1"
newline
bitfld.long 0x04 5. "DIS_IR_RX," "0,1"
newline
bitfld.long 0x04 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt" "0,1"
newline
bitfld.long 0x04 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission" "0,1"
newline
bitfld.long 0x04 2. "SCTX_EN,Store and controlled TX start" "0,1"
newline
bitfld.long 0x04 1. "ABORT_EN,Frame Abort" "0,1"
newline
bitfld.long 0x04 0. "EOT_EN,EOT [end of transmission] bit" "0,1"
line.long 0x08 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x08 7. "RX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x08 6. "TX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x08 5. "DSR_IT," "0,1"
newline
bitfld.long 0x08 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1"
newline
bitfld.long 0x08 3. "TX_EMPTY_CTL_IT," "0,1"
newline
bitfld.long 0x08 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3"
newline
bitfld.long 0x08 0. "DMA_MODE_CTL," "0,1"
line.long 0x0C "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0C 3.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 2. "DMA_COUNTER_RST," "0,1"
newline
rbitfld.long 0x0C 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1"
newline
rbitfld.long 0x0C 0. "TX_FIFO_FULL," "0,1"
line.long 0x10 "MEM_EBLR,IR-IrDA and IR-CIR modes only.In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,"
newline
abitfld.long 0x10 0.--7. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification" "0x00=feature disabled,0x01=generate RX_STOP interrupt after receiving..,0xFF=generate RX_STOP interrupt after receiving.."
rgroup.long 0x50++0x57
line.long 0x00 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module"
bitfld.long 0x00 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function revision number of module"
newline
bitfld.long 0x00 11.--15. "RTL,Rtl revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x04 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3"
newline
bitfld.long 0x04 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1"
newline
bitfld.long 0x04 1. "SOFTRESET,Software reset" "0,1"
newline
bitfld.long 0x04 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
line.long 0x08 "MEM_SYSS,"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x08 1.--7. 1. "RESERVED,"
newline
bitfld.long 0x08 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x0C "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0C 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
newline
bitfld.long 0x0C 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0C 5. "EVENT_5_RHR_INTERRUPT," "0,1"
newline
bitfld.long 0x0C 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 1. "EVENT_1_DSR_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x10 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x10 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]"
line.long 0x14 "MEM_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x14 0.--7. 1. "RXFIFO_LVL,"
line.long 0x18 "MEM_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x18 0.--7. 1. "TXFIFO_LVL,"
line.long 0x1C "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x1C 3.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 2. "RHR_IT_DIS," "0,1"
newline
bitfld.long 0x1C 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt" "0,1"
newline
bitfld.long 0x1C 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt" "0,1"
line.long 0x20 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x20 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x20 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1"
newline
bitfld.long 0x20 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1"
line.long 0x24 "MEM_FREQ_SEL,Sample per bit value selector"
hexmask.long.byte 0x24 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used"
line.long 0x28 "MEM_ABAUD_1ST_CHAR,Unused"
line.long 0x2C "MEM_BAUD_2ND_CHAR,Unused"
line.long 0x30 "MEM_MDR3,Mode definition register 3"
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED2,"
newline
bitfld.long 0x30 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
newline
bitfld.long 0x30 3. "DIR_POL,RS-485 External Transceiver Direction Polarity" "TX,TX"
newline
bitfld.long 0x30 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1"
newline
bitfld.long 0x30 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x30 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1"
line.long 0x34 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level.MDR3[2] SET_TX_DMA_THRESHOLD must be one and must be value + tx_trigger_level <= 64 (TX FIFO size).If not. 64-tx_trigger_level will be used w/o modifying the value of this register"
bitfld.long 0x34 0.--5. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "MEM_MDR4,Mode definition register 4"
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x38 7. "RESERVED," "0,1"
newline
bitfld.long 0x38 6. "MODE9,9-bit character length" "0,1"
newline
bitfld.long 0x38 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7"
line.long 0x3C "MEM_EFR2,Enhanced Features Register 2"
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0x3C 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
newline
bitfld.long 0x3C 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
newline
bitfld.long 0x3C 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
newline
bitfld.long 0x3C 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
newline
bitfld.long 0x3C 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
newline
bitfld.long 0x3C 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1"
newline
bitfld.long 0x3C 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1"
newline
bitfld.long 0x3C 0. "ENDIAN,Endianness" "0,1"
line.long 0x40 "MEM_ECR,Enhanced Control register"
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x40 6.--7. "RESERVED," "0,1,2,3"
newline
bitfld.long 0x40 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
newline
bitfld.long 0x40 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x40 3. "RX_EN,Enables/Disables the receiver" "0,1"
newline
bitfld.long 0x40 2. "TX_RST,Writing '1' resets the transmitter" "0,1"
newline
bitfld.long 0x40 1. "RX_RST,Writing '1' resets the receiver" "0,1"
newline
bitfld.long 0x40 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1"
line.long 0x44 "MEM_TIMEGUARD,Timeguard"
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x44 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices"
line.long 0x48 "MEM_TIMEOUTL,Timeout lower byte"
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x48 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0"
line.long 0x4C "MEM_TIMEOUTH,Timeout higher byte"
hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0"
line.long 0x50 "MEM_SCCR,Smartcard (ISO7816) mode Control Register"
hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0x50 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error" "0,1"
newline
bitfld.long 0x50 6. "INACK,Inhibit NACK when receiving even if an error is received" "0,1"
newline
rbitfld.long 0x50 3.--5. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x50 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge" "0,1,2,3,4,5,6,7"
line.long 0x54 "MEM_ERHR,Extended Receive Holding Register"
hexmask.long.tbyte 0x54 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x54 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR"
group.long 0xA4++0x0F
line.long 0x00 "MEM_ETHR,Extended Transmit Holding Register"
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x00 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR"
line.long 0x04 "MEM_MAR,Multidrop Address Register"
hexmask.long.byte 0x04 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x08 "MEM_MMR,Multidrop Mask Register"
hexmask.long.byte 0x08 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0x0C "MEM_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0x0C 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
repeat.end
tree "WKUP_CBASS0_ERR"
base ad:0x2B400000
rgroup.long 0x00++0x07
line.long 0x00 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "WKUP_CBASS0_FW"
base ad:0x45008000
group.long 0x00++0x7F
line.long 0x00 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall"
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall"
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall"
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 0 firewall"
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall"
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall"
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall"
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 1 firewall"
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall"
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall"
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall"
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 2 firewall"
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall"
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall"
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall"
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_Ipulsar_ul_wkup_0_cpu0_slv_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave Ipulsar_ul_wkup_0.cpu0_slv region 3 firewall"
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
group.long 0x400++0x1FF
line.long 0x00 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv.."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv.."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv.."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv.."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x80 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 4 firewall"
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region" "0,1"
bitfld.long 0x80 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 4 firewall"
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x88 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 4 firewall"
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x8C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 4 firewall"
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x90 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv.."
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x94 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x98 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x9C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xA0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 5 firewall"
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xA0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 5 firewall"
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xA8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 5 firewall"
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xAC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 5 firewall"
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xB0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv.."
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xB4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xB8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xBC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xC0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 6 firewall"
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xC0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 6 firewall"
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xC8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 6 firewall"
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xCC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 6 firewall"
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xD0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv.."
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xD4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xD8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xDC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xE0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 7 firewall"
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xE0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 7 firewall"
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xE8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 7 firewall"
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xEC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 7 firewall"
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xF0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv.."
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xF4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xF8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xFC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x100 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_8_control,The FW Region 8 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 8 firewall"
bitfld.long 0x100 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x100 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x100 4. "LOCK,Lock region" "0,1"
bitfld.long 0x100 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x104 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_8_permission_0,The FW Region 8 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 8 firewall"
hexmask.long.byte 0x104 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x104 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x104 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x104 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x104 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x104 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x104 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x104 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x104 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x104 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x104 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x104 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x104 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x104 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x104 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x104 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x104 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x108 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_8_permission_1,The FW Region 8 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 8 firewall"
hexmask.long.byte 0x108 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x108 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x108 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x108 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x108 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x108 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x108 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x108 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x108 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x108 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x108 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x108 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x108 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x108 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x108 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x108 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x108 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_8_permission_2,The FW Region 8 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 8 firewall"
hexmask.long.byte 0x10C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x10C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x10C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x10C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x10C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x10C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x10C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x10C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x10C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x10C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x10C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x10C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x10C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x10C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x10C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x10C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x10C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x110 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_8_start_address_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv.."
hexmask.long.tbyte 0x110 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x110 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x114 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_8_start_address_h,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x114 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x118 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_8_end_address_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x118 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x118 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x11C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_8_end_address_h,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x11C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x120 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_9_control,The FW Region 9 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 9 firewall"
bitfld.long 0x120 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x120 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x120 4. "LOCK,Lock region" "0,1"
bitfld.long 0x120 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x124 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_9_permission_0,The FW Region 9 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 9 firewall"
hexmask.long.byte 0x124 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x124 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x124 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x124 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x124 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x124 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x124 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x124 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x124 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x124 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x124 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x124 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x124 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x124 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x124 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x124 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x124 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x128 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_9_permission_1,The FW Region 9 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 9 firewall"
hexmask.long.byte 0x128 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x128 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x128 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x128 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x128 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x128 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x128 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x128 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x128 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x128 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x128 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x128 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x128 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x128 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x128 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x128 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x128 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x12C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_9_permission_2,The FW Region 9 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 9 firewall"
hexmask.long.byte 0x12C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x12C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x12C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x12C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x12C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x12C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x12C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x12C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x12C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x12C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x12C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x12C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x12C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x12C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x12C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x12C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x12C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x130 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_9_start_address_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv.."
hexmask.long.tbyte 0x130 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x130 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x134 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_9_start_address_h,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x134 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x138 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_9_end_address_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x138 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x138 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x13C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_9_end_address_h,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x13C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x140 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_10_control,The FW Region 10 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 10 firewall"
bitfld.long 0x140 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x140 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x140 4. "LOCK,Lock region" "0,1"
bitfld.long 0x140 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x144 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_10_permission_0,The FW Region 10 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 10 firewall"
hexmask.long.byte 0x144 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x144 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x144 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x144 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x144 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x144 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x144 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x144 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x144 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x144 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x144 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x144 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x144 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x144 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x144 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x144 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x144 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x148 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_10_permission_1,The FW Region 10 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 10 firewall"
hexmask.long.byte 0x148 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x148 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x148 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x148 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x148 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x148 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x148 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x148 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x148 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x148 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x148 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x148 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x148 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x148 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x148 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x148 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x148 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x14C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_10_permission_2,The FW Region 10 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 10 firewall"
hexmask.long.byte 0x14C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x14C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x14C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x14C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x14C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x14C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x14C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x14C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x14C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x14C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x14C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x14C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x14C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x14C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x14C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x14C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x14C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x150 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_10_start_address_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave.."
hexmask.long.tbyte 0x150 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x150 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x154 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_10_start_address_h,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x154 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x158 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_10_end_address_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x158 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x158 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x15C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_10_end_address_h,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x15C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x160 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_11_control,The FW Region 11 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 11 firewall"
bitfld.long 0x160 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x160 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x160 4. "LOCK,Lock region" "0,1"
bitfld.long 0x160 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_11_permission_0,The FW Region 11 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 11 firewall"
hexmask.long.byte 0x164 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x164 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x164 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x164 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x164 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x164 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x164 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x164 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x164 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x164 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x164 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x164 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x164 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x164 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x164 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x164 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x164 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x168 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_11_permission_1,The FW Region 11 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 11 firewall"
hexmask.long.byte 0x168 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x168 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x168 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x168 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x168 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x168 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x168 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x168 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x168 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x168 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x168 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x168 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x168 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x168 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x168 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x168 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x168 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x16C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_11_permission_2,The FW Region 11 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 11 firewall"
hexmask.long.byte 0x16C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x16C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x16C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x16C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x16C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x16C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x16C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x16C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x16C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x16C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x16C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x16C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x16C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x16C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x16C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x16C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x16C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x170 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_11_start_address_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave.."
hexmask.long.tbyte 0x170 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x170 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x174 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_11_start_address_h,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x174 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x178 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_11_end_address_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x178 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x178 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x17C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_11_end_address_h,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x17C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x180 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_12_control,The FW Region 12 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 12 firewall"
bitfld.long 0x180 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x180 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x180 4. "LOCK,Lock region" "0,1"
bitfld.long 0x180 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_12_permission_0,The FW Region 12 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 12 firewall"
hexmask.long.byte 0x184 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x184 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x184 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x184 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x184 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x184 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x184 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x184 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x184 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x184 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x184 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x184 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x184 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x184 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x184 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x184 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x184 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x188 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_12_permission_1,The FW Region 12 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 12 firewall"
hexmask.long.byte 0x188 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x188 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x188 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x188 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x188 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x188 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x188 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x188 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x188 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x188 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x188 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x188 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x188 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x188 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x188 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x188 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x188 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x18C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_12_permission_2,The FW Region 12 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 12 firewall"
hexmask.long.byte 0x18C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x18C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x18C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x18C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x18C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x18C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x18C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x18C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x18C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x18C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x18C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x18C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x18C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x18C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x18C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x18C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x18C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x190 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_12_start_address_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave.."
hexmask.long.tbyte 0x190 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x190 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x194 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_12_start_address_h,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x194 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x198 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_12_end_address_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x198 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x198 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x19C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_12_end_address_h,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x19C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x1A0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_13_control,The FW Region 13 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 13 firewall"
bitfld.long 0x1A0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x1A0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x1A0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x1A0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_13_permission_0,The FW Region 13 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 13 firewall"
hexmask.long.byte 0x1A4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1A4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1A4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1A4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1A4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1A8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_13_permission_1,The FW Region 13 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 13 firewall"
hexmask.long.byte 0x1A8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1A8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1A8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1A8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1A8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1AC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_13_permission_2,The FW Region 13 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 13 firewall"
hexmask.long.byte 0x1AC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1AC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1AC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1AC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1AC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1AC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1B0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_13_start_address_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave.."
hexmask.long.tbyte 0x1B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x1B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x1B4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_13_start_address_h,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x1B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x1B8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_13_end_address_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x1B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x1B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1BC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_13_end_address_h,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x1BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x1C0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_14_control,The FW Region 14 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 14 firewall"
bitfld.long 0x1C0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x1C0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x1C0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x1C0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_14_permission_0,The FW Region 14 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 14 firewall"
hexmask.long.byte 0x1C4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1C4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1C4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1C4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1C4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1C8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_14_permission_1,The FW Region 14 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 14 firewall"
hexmask.long.byte 0x1C8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1C8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1C8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1C8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1C8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1CC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_14_permission_2,The FW Region 14 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 14 firewall"
hexmask.long.byte 0x1CC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1CC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1CC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1CC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1CC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1CC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1D0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_14_start_address_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave.."
hexmask.long.tbyte 0x1D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x1D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x1D4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_14_start_address_h,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x1D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x1D8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_14_end_address_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x1D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x1D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1DC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_14_end_address_h,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x1DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x1E0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_15_control,The FW Region 15 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 15 firewall"
bitfld.long 0x1E0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x1E0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x1E0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x1E0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_15_permission_0,The FW Region 15 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 15 firewall"
hexmask.long.byte 0x1E4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1E4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1E4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1E4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1E4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1E8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_15_permission_1,The FW Region 15 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 15 firewall"
hexmask.long.byte 0x1E8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1E8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1E8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1E8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1E8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1EC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_15_permission_2,The FW Region 15 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0.slv region 15 firewall"
hexmask.long.byte 0x1EC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1EC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1EC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1EC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1EC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1EC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1F0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_15_start_address_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave.."
hexmask.long.tbyte 0x1F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x1F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x1F4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_15_start_address_h,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x1F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x1F8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_15_end_address_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x1F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x1F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1FC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_main_infra_cbass_data_l0_fw_region_15_end_address_h,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x1FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
group.long 0x800++0xFF
line.long 0x00 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall"
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall"
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall"
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 0 firewall"
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall"
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall"
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall"
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 1 firewall"
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall"
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall"
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall"
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 2 firewall"
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall"
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall"
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall"
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 3 firewall"
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x80 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall"
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region" "0,1"
bitfld.long 0x80 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall"
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x88 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall"
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x8C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall"
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x90 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall"
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x94 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall"
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x98 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall"
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x9C "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 4 firewall"
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xA0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall"
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xA0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall"
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xA8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall"
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xAC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall"
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xB0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall"
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xB4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall"
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xB8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall"
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xBC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 5 firewall"
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xC0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall"
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xC0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall"
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xC8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall"
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xCC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall"
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xD0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall"
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xD4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall"
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xD8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall"
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xDC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 6 firewall"
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xE0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall"
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xE0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall"
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xE8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall"
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xEC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall"
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xF0 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall"
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xF4 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall"
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xF8 "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall"
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xFC "FW_REGS_br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave br_SCRM_DM_clk1_to_SCRP_32b_DM_clk4_l0 region 7 firewall"
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
group.long 0xC00++0x1FF
line.long 0x00 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_0_control,The FW Region 0 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 0 firewall"
bitfld.long 0x00 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x00 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_0_permission_0,The FW Region 0 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 0 firewall"
hexmask.long.byte 0x04 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x04 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x04 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x04 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x04 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x04 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x04 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x04 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x04 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x04 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x04 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x04 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x04 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x04 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x08 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_0_permission_1,The FW Region 0 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 0 firewall"
hexmask.long.byte 0x08 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x08 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x08 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x08 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x08 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x08 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x08 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x08 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x08 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x08 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x08 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x08 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x08 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x08 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x0C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_0_permission_2,The FW Region 0 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 0 firewall"
hexmask.long.byte 0x0C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x0C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x0C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x0C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x0C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x0C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x0C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x0C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x0C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x0C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x0C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x0C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x0C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_0_start_address_l,The FW Region 0 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0x10 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x10 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x14 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_0_start_address_h,The FW Region 0 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.word 0x14 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x18 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_0_end_address_l,The FW Region 0 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x18 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x18 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_0_end_address_h,The FW Region 0 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x1C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x20 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_1_control,The FW Region 1 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 1 firewall"
bitfld.long 0x20 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x20 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x20 4. "LOCK,Lock region" "0,1"
bitfld.long 0x20 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_1_permission_0,The FW Region 1 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 1 firewall"
hexmask.long.byte 0x24 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x24 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x24 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x24 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x24 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x24 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x24 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x24 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x24 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x24 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x24 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x24 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x24 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x24 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x28 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_1_permission_1,The FW Region 1 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 1 firewall"
hexmask.long.byte 0x28 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x28 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x28 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x28 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x28 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x28 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x28 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x28 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x28 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x28 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x28 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x28 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x28 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x28 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x2C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_1_permission_2,The FW Region 1 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 1 firewall"
hexmask.long.byte 0x2C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x2C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x2C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x2C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x2C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x2C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x2C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x2C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x2C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x2C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x2C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x2C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x2C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x30 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_1_start_address_l,The FW Region 1 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0x30 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x30 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x34 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_1_start_address_h,The FW Region 1 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.word 0x34 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x38 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_1_end_address_l,The FW Region 1 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x38 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x38 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x3C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_1_end_address_h,The FW Region 1 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x3C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x40 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_2_control,The FW Region 2 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 2 firewall"
bitfld.long 0x40 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x40 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x40 4. "LOCK,Lock region" "0,1"
bitfld.long 0x40 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_2_permission_0,The FW Region 2 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 2 firewall"
hexmask.long.byte 0x44 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x44 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x44 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x44 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x44 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x44 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x44 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x44 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x44 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x44 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x44 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x44 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x44 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x44 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x48 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_2_permission_1,The FW Region 2 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 2 firewall"
hexmask.long.byte 0x48 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x48 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x48 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x48 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x48 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x48 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x48 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x48 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x48 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x48 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x48 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x48 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x48 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x48 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x4C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_2_permission_2,The FW Region 2 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 2 firewall"
hexmask.long.byte 0x4C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x4C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x4C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x4C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x4C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x4C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x4C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x4C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x4C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x4C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x4C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x4C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x4C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x50 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_2_start_address_l,The FW Region 2 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0x50 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x50 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x54 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_2_start_address_h,The FW Region 2 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.word 0x54 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x58 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_2_end_address_l,The FW Region 2 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x58 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x58 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x5C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_2_end_address_h,The FW Region 2 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x5C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x60 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_3_control,The FW Region 3 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 3 firewall"
bitfld.long 0x60 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x60 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x60 4. "LOCK,Lock region" "0,1"
bitfld.long 0x60 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_3_permission_0,The FW Region 3 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 3 firewall"
hexmask.long.byte 0x64 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x64 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x64 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x64 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x64 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x64 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x64 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x64 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x64 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x64 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x64 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x64 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x64 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x64 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x68 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_3_permission_1,The FW Region 3 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 3 firewall"
hexmask.long.byte 0x68 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x68 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x68 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x68 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x68 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x68 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x68 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x68 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x68 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x68 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x68 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x68 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x68 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x68 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x6C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_3_permission_2,The FW Region 3 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 3 firewall"
hexmask.long.byte 0x6C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x6C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x6C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x6C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x6C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x6C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x6C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x6C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x6C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x6C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x6C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x6C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x6C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x70 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_3_start_address_l,The FW Region 3 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0x70 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x70 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x74 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_3_start_address_h,The FW Region 3 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.word 0x74 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x78 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_3_end_address_l,The FW Region 3 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x78 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x78 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x7C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_3_end_address_h,The FW Region 3 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x7C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x80 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_4_control,The FW Region 4 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 4 firewall"
bitfld.long 0x80 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x80 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x80 4. "LOCK,Lock region" "0,1"
bitfld.long 0x80 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_4_permission_0,The FW Region 4 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 4 firewall"
hexmask.long.byte 0x84 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x84 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x84 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x84 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x84 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x84 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x84 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x84 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x84 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x84 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x84 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x84 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x84 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x84 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x88 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_4_permission_1,The FW Region 4 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 4 firewall"
hexmask.long.byte 0x88 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x88 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x88 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x88 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x88 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x88 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x88 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x88 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x88 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x88 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x88 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x88 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x88 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x88 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x8C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_4_permission_2,The FW Region 4 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 4 firewall"
hexmask.long.byte 0x8C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x8C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x8C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x8C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x8C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x8C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x8C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x8C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x8C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x8C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x8C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x8C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x8C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x90 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_4_start_address_l,The FW Region 4 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0x90 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x90 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x94 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_4_start_address_h,The FW Region 4 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.word 0x94 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x98 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_4_end_address_l,The FW Region 4 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x98 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x98 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x9C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_4_end_address_h,The FW Region 4 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x9C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xA0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_5_control,The FW Region 5 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 5 firewall"
bitfld.long 0xA0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xA0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xA0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xA0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_5_permission_0,The FW Region 5 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 5 firewall"
hexmask.long.byte 0xA4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xA8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_5_permission_1,The FW Region 5 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 5 firewall"
hexmask.long.byte 0xA8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xA8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xA8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xA8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xA8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xA8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xA8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xA8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xA8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xA8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xA8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xA8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xA8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xAC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_5_permission_2,The FW Region 5 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 5 firewall"
hexmask.long.byte 0xAC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xAC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xAC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xAC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xAC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xAC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xAC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xAC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xAC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xAC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xAC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xAC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xAC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xB0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_5_start_address_l,The FW Region 5 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0xB0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xB0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xB4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_5_start_address_h,The FW Region 5 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.word 0xB4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xB8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_5_end_address_l,The FW Region 5 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0xB8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xB8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xBC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_5_end_address_h,The FW Region 5 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0xBC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xC0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_6_control,The FW Region 6 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 6 firewall"
bitfld.long 0xC0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xC0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xC0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xC0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_6_permission_0,The FW Region 6 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 6 firewall"
hexmask.long.byte 0xC4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xC8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_6_permission_1,The FW Region 6 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 6 firewall"
hexmask.long.byte 0xC8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xC8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xC8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xC8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xC8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xC8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xC8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xC8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xC8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xC8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xC8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xC8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xC8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xCC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_6_permission_2,The FW Region 6 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 6 firewall"
hexmask.long.byte 0xCC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xCC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xCC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xCC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xCC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xCC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xCC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xCC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xCC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xCC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xCC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xCC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xCC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xD0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_6_start_address_l,The FW Region 6 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0xD0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xD0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xD4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_6_start_address_h,The FW Region 6 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.word 0xD4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xD8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_6_end_address_l,The FW Region 6 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0xD8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xD8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xDC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_6_end_address_h,The FW Region 6 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0xDC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0xE0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_7_control,The FW Region 7 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 7 firewall"
bitfld.long 0xE0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0xE0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0xE0 4. "LOCK,Lock region" "0,1"
bitfld.long 0xE0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_7_permission_0,The FW Region 7 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 7 firewall"
hexmask.long.byte 0xE4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xE8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_7_permission_1,The FW Region 7 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 7 firewall"
hexmask.long.byte 0xE8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xE8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xE8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xE8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xE8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xE8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xE8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xE8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xE8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xE8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xE8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xE8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xE8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xEC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_7_permission_2,The FW Region 7 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 7 firewall"
hexmask.long.byte 0xEC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0xEC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0xEC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0xEC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0xEC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0xEC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0xEC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0xEC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0xEC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0xEC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0xEC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0xEC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0xEC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0xF0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_7_start_address_l,The FW Region 7 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0xF0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0xF0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0xF4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_7_start_address_h,The FW Region 7 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.word 0xF4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0xF8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_7_end_address_l,The FW Region 7 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0xF8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0xF8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0xFC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_7_end_address_h,The FW Region 7 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0xFC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x100 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_8_control,The FW Region 8 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 8 firewall"
bitfld.long 0x100 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x100 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x100 4. "LOCK,Lock region" "0,1"
bitfld.long 0x100 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x104 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_8_permission_0,The FW Region 8 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 8 firewall"
hexmask.long.byte 0x104 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x104 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x104 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x104 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x104 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x104 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x104 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x104 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x104 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x104 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x104 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x104 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x104 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x104 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x104 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x104 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x104 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x108 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_8_permission_1,The FW Region 8 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 8 firewall"
hexmask.long.byte 0x108 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x108 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x108 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x108 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x108 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x108 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x108 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x108 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x108 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x108 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x108 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x108 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x108 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x108 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x108 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x108 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x108 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x10C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_8_permission_2,The FW Region 8 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 8 firewall"
hexmask.long.byte 0x10C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x10C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x10C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x10C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x10C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x10C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x10C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x10C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x10C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x10C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x10C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x10C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x10C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x10C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x10C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x10C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x10C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x110 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_8_start_address_l,The FW Region 8 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0x110 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x110 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x114 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_8_start_address_h,The FW Region 8 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.word 0x114 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x118 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_8_end_address_l,The FW Region 8 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x118 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x118 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x11C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_8_end_address_h,The FW Region 8 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x11C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x120 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_9_control,The FW Region 9 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 9 firewall"
bitfld.long 0x120 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x120 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x120 4. "LOCK,Lock region" "0,1"
bitfld.long 0x120 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x124 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_9_permission_0,The FW Region 9 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 9 firewall"
hexmask.long.byte 0x124 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x124 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x124 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x124 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x124 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x124 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x124 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x124 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x124 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x124 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x124 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x124 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x124 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x124 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x124 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x124 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x124 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x128 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_9_permission_1,The FW Region 9 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 9 firewall"
hexmask.long.byte 0x128 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x128 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x128 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x128 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x128 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x128 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x128 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x128 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x128 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x128 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x128 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x128 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x128 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x128 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x128 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x128 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x128 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x12C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_9_permission_2,The FW Region 9 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 9 firewall"
hexmask.long.byte 0x12C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x12C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x12C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x12C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x12C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x12C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x12C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x12C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x12C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x12C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x12C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x12C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x12C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x12C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x12C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x12C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x12C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x130 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_9_start_address_l,The FW Region 9 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0x130 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x130 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x134 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_9_start_address_h,The FW Region 9 Start Address High Register defines the start address bits 47 to 32 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.word 0x134 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x138 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_9_end_address_l,The FW Region 9 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x138 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x138 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x13C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_9_end_address_h,The FW Region 9 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x13C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x140 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_10_control,The FW Region 10 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 10 firewall"
bitfld.long 0x140 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x140 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x140 4. "LOCK,Lock region" "0,1"
bitfld.long 0x140 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x144 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_10_permission_0,The FW Region 10 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 10 firewall"
hexmask.long.byte 0x144 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x144 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x144 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x144 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x144 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x144 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x144 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x144 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x144 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x144 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x144 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x144 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x144 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x144 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x144 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x144 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x144 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x148 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_10_permission_1,The FW Region 10 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 10 firewall"
hexmask.long.byte 0x148 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x148 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x148 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x148 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x148 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x148 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x148 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x148 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x148 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x148 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x148 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x148 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x148 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x148 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x148 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x148 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x148 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x14C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_10_permission_2,The FW Region 10 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 10 firewall"
hexmask.long.byte 0x14C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x14C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x14C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x14C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x14C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x14C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x14C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x14C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x14C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x14C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x14C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x14C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x14C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x14C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x14C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x14C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x14C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x150 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_10_start_address_l,The FW Region 10 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0x150 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x150 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x154 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_10_start_address_h,The FW Region 10 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x154 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x158 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_10_end_address_l,The FW Region 10 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x158 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x158 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x15C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_10_end_address_h,The FW Region 10 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x15C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x160 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_11_control,The FW Region 11 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 11 firewall"
bitfld.long 0x160 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x160 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x160 4. "LOCK,Lock region" "0,1"
bitfld.long 0x160 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_11_permission_0,The FW Region 11 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 11 firewall"
hexmask.long.byte 0x164 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x164 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x164 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x164 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x164 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x164 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x164 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x164 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x164 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x164 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x164 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x164 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x164 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x164 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x164 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x164 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x164 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x168 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_11_permission_1,The FW Region 11 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 11 firewall"
hexmask.long.byte 0x168 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x168 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x168 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x168 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x168 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x168 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x168 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x168 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x168 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x168 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x168 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x168 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x168 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x168 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x168 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x168 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x168 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x16C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_11_permission_2,The FW Region 11 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 11 firewall"
hexmask.long.byte 0x16C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x16C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x16C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x16C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x16C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x16C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x16C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x16C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x16C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x16C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x16C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x16C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x16C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x16C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x16C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x16C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x16C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x170 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_11_start_address_l,The FW Region 11 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0x170 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x170 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x174 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_11_start_address_h,The FW Region 11 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x174 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x178 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_11_end_address_l,The FW Region 11 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x178 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x178 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x17C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_11_end_address_h,The FW Region 11 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x17C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x180 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_12_control,The FW Region 12 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 12 firewall"
bitfld.long 0x180 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x180 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x180 4. "LOCK,Lock region" "0,1"
bitfld.long 0x180 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_12_permission_0,The FW Region 12 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 12 firewall"
hexmask.long.byte 0x184 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x184 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x184 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x184 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x184 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x184 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x184 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x184 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x184 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x184 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x184 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x184 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x184 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x184 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x184 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x184 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x184 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x188 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_12_permission_1,The FW Region 12 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 12 firewall"
hexmask.long.byte 0x188 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x188 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x188 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x188 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x188 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x188 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x188 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x188 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x188 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x188 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x188 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x188 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x188 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x188 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x188 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x188 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x188 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x18C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_12_permission_2,The FW Region 12 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 12 firewall"
hexmask.long.byte 0x18C 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x18C 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x18C 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x18C 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x18C 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x18C 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x18C 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x18C 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x18C 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x18C 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x18C 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x18C 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x18C 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x18C 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x18C 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x18C 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x18C 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x190 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_12_start_address_l,The FW Region 12 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0x190 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x190 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x194 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_12_start_address_h,The FW Region 12 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x194 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x198 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_12_end_address_l,The FW Region 12 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x198 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x198 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x19C "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_12_end_address_h,The FW Region 12 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x19C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x1A0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_13_control,The FW Region 13 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 13 firewall"
bitfld.long 0x1A0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x1A0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x1A0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x1A0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_13_permission_0,The FW Region 13 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 13 firewall"
hexmask.long.byte 0x1A4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1A4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1A4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1A4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1A4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1A4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1A4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1A4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1A4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1A4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1A4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1A8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_13_permission_1,The FW Region 13 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 13 firewall"
hexmask.long.byte 0x1A8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1A8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1A8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1A8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1A8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1A8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1A8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1A8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1A8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1A8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1A8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1A8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1A8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1A8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1AC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_13_permission_2,The FW Region 13 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 13 firewall"
hexmask.long.byte 0x1AC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1AC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1AC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1AC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1AC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1AC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1AC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1AC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1AC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1AC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1AC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1AC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1AC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1AC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1AC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1AC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1AC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1B0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_13_start_address_l,The FW Region 13 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0x1B0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x1B0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x1B4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_13_start_address_h,The FW Region 13 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x1B4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x1B8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_13_end_address_l,The FW Region 13 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x1B8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x1B8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1BC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_13_end_address_h,The FW Region 13 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x1BC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x1C0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_14_control,The FW Region 14 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 14 firewall"
bitfld.long 0x1C0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x1C0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x1C0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x1C0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_14_permission_0,The FW Region 14 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 14 firewall"
hexmask.long.byte 0x1C4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1C4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1C4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1C4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1C4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1C4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1C4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1C4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1C4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1C4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1C4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1C8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_14_permission_1,The FW Region 14 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 14 firewall"
hexmask.long.byte 0x1C8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1C8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1C8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1C8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1C8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1C8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1C8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1C8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1C8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1C8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1C8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1C8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1C8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1C8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1CC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_14_permission_2,The FW Region 14 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 14 firewall"
hexmask.long.byte 0x1CC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1CC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1CC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1CC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1CC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1CC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1CC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1CC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1CC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1CC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1CC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1CC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1CC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1CC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1CC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1CC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1CC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1D0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_14_start_address_l,The FW Region 14 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0x1D0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x1D0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x1D4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_14_start_address_h,The FW Region 14 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x1D4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x1D8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_14_end_address_l,The FW Region 14 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x1D8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x1D8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1DC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_14_end_address_h,The FW Region 14 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x1DC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
line.long 0x1E0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_15_control,The FW Region 15 Control Register defines the control fields for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 15 firewall"
bitfld.long 0x1E0 9. "CACHE_MODE,Cache mode for region" "0,1"
bitfld.long 0x1E0 8. "BACKGROUND,Background enable for region" "0,1"
newline
bitfld.long 0x1E0 4. "LOCK,Lock region" "0,1"
bitfld.long 0x1E0 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_15_permission_0,The FW Region 15 Permission 0 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 15 firewall"
hexmask.long.byte 0x1E4 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1E4 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1E4 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1E4 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1E4 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1E4 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E4 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E4 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E4 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1E4 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1E4 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1E4 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1E4 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1E4 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E4 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E4 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E4 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1E8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_15_permission_1,The FW Region 15 Permission 1 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 15 firewall"
hexmask.long.byte 0x1E8 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1E8 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1E8 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1E8 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1E8 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1E8 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E8 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E8 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E8 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1E8 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1E8 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1E8 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1E8 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1E8 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1E8 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1E8 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1E8 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1EC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_15_permission_2,The FW Region 15 Permission 2 Register defines the permissions for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv region 15 firewall"
hexmask.long.byte 0x1EC 16.--23. 1. "PRIV_ID,Allowed privid"
bitfld.long 0x1EC 15. "NONSEC_USER_DEBUG,Non-secure user debug allowed" "0,1"
newline
bitfld.long 0x1EC 14. "NONSEC_USER_CACHEABLE,Non-secure user cacheable allowed" "0,1"
bitfld.long 0x1EC 13. "NONSEC_USER_READ,Non-secure user read allowed" "0,1"
newline
bitfld.long 0x1EC 12. "NONSEC_USER_WRITE,Non-secure user write allowed" "0,1"
bitfld.long 0x1EC 11. "NONSEC_SUPV_DEBUG,Non-secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1EC 10. "NONSEC_SUPV_CACHEABLE,Non-secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1EC 9. "NONSEC_SUPV_READ,Non-secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1EC 8. "NONSEC_SUPV_WRITE,Non-secure supervisor write allowed" "0,1"
bitfld.long 0x1EC 7. "SEC_USER_DEBUG,Secure user debug allowed" "0,1"
newline
bitfld.long 0x1EC 6. "SEC_USER_CACHEABLE,Secure user cacheable allowed" "0,1"
bitfld.long 0x1EC 5. "SEC_USER_READ,Secure user read allowed" "0,1"
newline
bitfld.long 0x1EC 4. "SEC_USER_WRITE,Secure user write allowed" "0,1"
bitfld.long 0x1EC 3. "SEC_SUPV_DEBUG,Secure supervisor debug allowed" "0,1"
newline
bitfld.long 0x1EC 2. "SEC_SUPV_CACHEABLE,Secure supervisor cacheable allowed" "0,1"
bitfld.long 0x1EC 1. "SEC_SUPV_READ,Secure supervisor read allowed" "0,1"
newline
bitfld.long 0x1EC 0. "SEC_SUPV_WRITE,Secure supervisor write allowed" "0,1"
line.long 0x1F0 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_15_start_address_l,The FW Region 15 Start Address Low Register defines the start address bits 31 to 0 for the slave export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0.slv.."
hexmask.long.tbyte 0x1F0 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x1F0 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 are forced to 0 as address must be 4KB aligned"
line.long 0x1F4 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_15_start_address_h,The FW Region 15 Start Address High Register defines the start address bits 47 to 32 for the slave.."
hexmask.long.word 0x1F4 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x1F8 "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_15_end_address_l,The FW Region 15 End Address Low Register defines the end address bits 31 to 0 to include for the slave.."
hexmask.long.tbyte 0x1F8 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x1F8 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to 1s as address must be 4KB aligned minus 1"
line.long 0x1FC "FW_REGS_export_am62_wkup_dm_cbass_to_am62_wkup_safe_cbass_data_l0_fw_region_15_end_address_h,The FW Region 15 End Address High Register defines the end address bits 47 to 32 to include for the slave.."
hexmask.long.word 0x1FC 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32 to include in the match"
tree.end
tree "WKUP_CBASS0_GLB"
base ad:0x45B03000
rgroup.long 0x00++0x07
line.long 0x00 "GLB_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "GLB_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x20++0x1B
line.long 0x00 "GLB_REGS_exception_logging_control,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_PEND,Disables logging pending when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "GLB_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "GLB_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "GLB_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "GLB_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x14 "GLB_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
newline
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "GLB_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x40++0x07
line.long 0x00 "GLB_REGS_exception_pend_set,The Exception Logging Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "GLB_REGS_exception_pend_clear,The Exception Logging Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
tree.end
tree "WKUP_CBASS0_ISC"
base ad:0x45814000
group.long 0x00++0x03
line.long 0x00 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_rmst region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
newline
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x13
line.long 0x00 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_rmst region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x13
line.long 0x00 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 1 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 1 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 1 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 1 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_rmst region 2 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50++0x13
line.long 0x00 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 2 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 2 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 2 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 2 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_rmst region 3 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x70++0x13
line.long 0x00 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 3 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 3 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 3 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_rmst region 3 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_rmst region 4 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
newline
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x400++0x03
line.long 0x00 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_wmst region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
newline
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x410++0x13
line.long 0x00 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_wmst region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x430++0x13
line.long 0x00 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 1 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 1 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 1 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 1 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_wmst region 2 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x450++0x13
line.long 0x00 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 2 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 2 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 2 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 2 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_wmst region 3 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x470++0x13
line.long 0x00 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 3 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 3 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 3 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_wmst region 3 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_wmst region 4 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
newline
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x800++0x03
line.long 0x00 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_0_control,The ISC Region 0 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_pmst region 0 ISC"
bitfld.long 0x00 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x00 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x00 21. "PASS,No privID replacement pass through value" "0,1"
newline
bitfld.long 0x00 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x00 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x00 6. "DEF,Default region indication" "0,1"
bitfld.long 0x00 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x00 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x00 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x810++0x13
line.long 0x00 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_0_start_address_l,The ISC Region 0 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 0 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_0_start_address_h,The ISC Region 0 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 0 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_0_end_address_l,The ISC Region 0 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 0 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_0_end_address_h,The ISC Region 0 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 0 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_1_control,The ISC Region 1 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_pmst region 1 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x830++0x13
line.long 0x00 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_1_start_address_l,The ISC Region 1 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 1 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_1_start_address_h,The ISC Region 1 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 1 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_1_end_address_l,The ISC Region 1 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 1 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_1_end_address_h,The ISC Region 1 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 1 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_2_control,The ISC Region 2 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_pmst region 2 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x850++0x13
line.long 0x00 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_2_start_address_l,The ISC Region 2 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 2 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_2_start_address_h,The ISC Region 2 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 2 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_2_end_address_l,The ISC Region 2 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 2 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_2_end_address_h,The ISC Region 2 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 2 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_3_control,The ISC Region 3 Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_pmst region 3 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement pass through value" "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
bitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
newline
bitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x870++0x13
line.long 0x00 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_3_start_address_l,The ISC Region 3 Start Address Low Register defines the start address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 3 ISC"
hexmask.long.tbyte 0x00 12.--31. 1. "START_ADDRESS_L,Start address bits 31 to 12"
hexmask.long.word 0x00 0.--11. 1. "START_ADDRESS_LSB,Start address bits 11 to 0 must be 0 as address must be 4KB aligned in address mode"
line.long 0x04 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_3_start_address_h,The ISC Region 3 Start Address High Register defines the start address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 3 ISC"
hexmask.long.word 0x04 0.--15. 1. "START_ADDRESS_H,Start address bits 47 to 32"
line.long 0x08 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_3_end_address_l,The ISC Region 3 End Address Low Register defines the end included address bits 31 to 0 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 3 ISC"
hexmask.long.tbyte 0x08 12.--31. 1. "END_ADDRESS_L,End address bits 31 to 12 to include in the match"
hexmask.long.word 0x08 0.--11. 1. "END_ADDRESS_LSB,End address bits 11 to 0 are forced to Fs as address must be 4KB aligned"
line.long 0x0C "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_3_end_address_h,The ISC Region 3 End Address High Register defines the end address bits 47 to 32 for the master Ipulsar_ul_wkup_0.cpu0_pmst region 3 ISC"
hexmask.long.word 0x0C 0.--15. 1. "END_ADDRESS_H,End address bits 47 to 32"
line.long 0x10 "ISC_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_isc_region_def_control,The ISC Default Region Control Register defines the control fields for the master Ipulsar_ul_wkup_0.cpu0_pmst region 4 ISC"
bitfld.long 0x10 26.--27. "NOPRIV,Clear output priv attribute" "0,1,2,3"
bitfld.long 0x10 24.--25. "PRIV,Set outgoing priv attribute" "0,1,2,3"
bitfld.long 0x10 21. "PASS,No privID replacement" "0,1"
newline
bitfld.long 0x10 20. "NONSEC,Make outgoing non-secure" "0,1"
bitfld.long 0x10 16.--19. "SEC,Make outgoing secure" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x10 8.--15. 1. "PRIV_ID,Priv ID value to use if pass is 0"
newline
rbitfld.long 0x10 6. "DEF,Default region indication" "0,1"
rbitfld.long 0x10 5. "CH_MODE,Enable channel mode to match region to a chanid value" "0,1"
bitfld.long 0x10 4. "LOCK,Lock region" "0,1"
newline
rbitfld.long 0x10 0.--3. "ENABLE,Enable region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "WKUP_CBASS0_QOS"
base ad:0x45D14000
group.long 0x100++0x03
line.long 0x00 "QOS_REGS_Ipulsar_ul_wkup_0_cpu0_rmst_map0,The Map Register defines the fields for the master Ipulsar_ul_wkup_0.cpu0_rmst per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x500++0x03
line.long 0x00 "QOS_REGS_Ipulsar_ul_wkup_0_cpu0_wmst_map0,The Map Register defines the fields for the master Ipulsar_ul_wkup_0.cpu0_wmst per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
group.long 0x900++0x03
line.long 0x00 "QOS_REGS_Ipulsar_ul_wkup_0_cpu0_pmst_map0,The Map Register defines the fields for the master Ipulsar_ul_wkup_0.cpu0_pmst per channel"
bitfld.long 0x00 12.--14. "EPRIORITY,epriority signal for channel N" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "ASEL,asel signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "ORDERID,orderid signal for channel N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "QOS,qos signal for channel N" "0,1,2,3,4,5,6,7"
tree.end
tree "WKUP_CTRL_MMR1_CFG0"
base ad:0x4500000
rgroup.long 0x00++0x03
line.long 0x00 "CFG0_PID,"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16,"
newline
bitfld.long 0x00 11.--15. "PID_MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "PID_CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x08++0x03
line.long 0x00 "CFG0_MMR_CFG1,"
bitfld.long 0x00 31. "MMR_CFG1_PROXY_EN,Proxy addressing activated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions"
group.long 0x100++0x03
line.long 0x00 "CFG0_IPC_SET0,"
abitfld.long 0x00 4.--31. "IPC_SET0_IPC_SRC_SET,Read returns current value Write" "0x0000000=No effect,0x0000001=Sets both SRC_SETx and.."
newline
bitfld.long 0x00 0. "IPC_SET0_IPC_SET,Read returns 0 Write" "No effect,Sets both the IPC_SET and.."
group.long 0x180++0x03
line.long 0x00 "CFG0_IPC_CLR0,"
abitfld.long 0x00 4.--31. "IPC_CLR0_IPC_SRC_CLR,Read returns current value Write" "0x0000000=No effect,0x0000001=Clears both SRC_CLRx and.."
newline
bitfld.long 0x00 0. "IPC_CLR0_IPC_CLR,Read returns current value Write" "No effect,Clears both IPC_CLR and.."
rgroup.long 0x270++0x03
line.long 0x00 "CFG0_CBA_ERR_STAT,"
bitfld.long 0x00 24. "CBA_ERR_STAT_WKUP_SAFE_CBA_ERR,Access Error from Wkup Safe CBASS" "0,1"
newline
bitfld.long 0x00 20. "CBA_ERR_STAT_MCU_CBA_ERR,Access Error from MCU CBASS" "0,1"
rgroup.long 0x280++0x03
line.long 0x00 "CFG0_ACCESS_ERR_STAT,"
bitfld.long 0x00 9. "ACCESS_ERR_STAT_ACCESS_ERR_IN9,Access Error Detected in MCU PadCfg MMR" "0,1"
newline
bitfld.long 0x00 8. "ACCESS_ERR_STAT_ACCESS_ERR_IN8,Access Error Detected in MCU Ctrl MMR" "0,1"
newline
bitfld.long 0x00 4. "ACCESS_ERR_STAT_ACCESS_ERR_IN4,Access Error Detected in MAIN PadCfg MMR" "0,1"
newline
bitfld.long 0x00 3. "ACCESS_ERR_STAT_ACCESS_ERR_IN3,Access Error Detected in MAIN Ctrl MMR" "0,1"
newline
bitfld.long 0x00 0. "ACCESS_ERR_STAT_ACCESS_ERR_IN0,Access Error Detected in WKUP Ctrl MMR" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "CFG0_LOCK0_KICK0,"
line.long 0x04 "CFG0_LOCK0_KICK1,"
line.long 0x08 "CFG0_intr_raw_status,"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "CFG0_intr_enabled_status_clear,"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "CFG0_intr_enable,"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "CFG0_intr_enable_clear,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "CFG0_eoi,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value"
line.long 0x1C "CFG0_fault_address,"
line.long 0x20 "CFG0_fault_type_status,"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "CFG0_fault_attr_status,"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "CFG0_fault_clear,"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
rgroup.long 0x1100++0x17
line.long 0x00 "CFG0_CLAIMREG_P0_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P0_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P0_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P0_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P0_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P0_R5_READONLY,"
rgroup.long 0x2000++0x03
line.long 0x00 "CFG0_PID_PROXY,"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16_PROXY,"
newline
bitfld.long 0x00 11.--15. "PID_MISC_PROXY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR_PROXY," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "PID_CUSTOM_PROXY," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR_PROXY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x2008++0x03
line.long 0x00 "CFG0_MMR_CFG1_PROXY,"
bitfld.long 0x00 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing activated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions"
group.long 0x2100++0x03
line.long 0x00 "CFG0_IPC_SET0_PROXY,"
abitfld.long 0x00 4.--31. "IPC_SET0_IPC_SRC_SET_PROXY,Read returns current value Write" "0x0000000=No effect,0x0000001=Sets both SRC_SETx and.."
newline
bitfld.long 0x00 0. "IPC_SET0_IPC_SET_PROXY,Read returns 0 Write" "No effect,Sets both the IPC_SET and.."
group.long 0x2180++0x03
line.long 0x00 "CFG0_IPC_CLR0_PROXY,"
abitfld.long 0x00 4.--31. "IPC_CLR0_IPC_SRC_CLR_PROXY,Read returns current value Write" "0x0000000=No effect,0x0000001=Clears both SRC_CLRx and.."
newline
bitfld.long 0x00 0. "IPC_CLR0_IPC_CLR_PROXY,Read returns current value Write" "No effect,Clears both IPC_CLR and.."
rgroup.long 0x2270++0x03
line.long 0x00 "CFG0_CBA_ERR_STAT_PROXY,"
bitfld.long 0x00 24. "CBA_ERR_STAT_WKUP_SAFE_CBA_ERR_PROXY,Access Error from Wkup Safe CBASS" "0,1"
newline
bitfld.long 0x00 20. "CBA_ERR_STAT_MCU_CBA_ERR_PROXY,Access Error from MCU CBASS" "0,1"
rgroup.long 0x2280++0x03
line.long 0x00 "CFG0_ACCESS_ERR_STAT_PROXY,"
bitfld.long 0x00 9. "ACCESS_ERR_STAT_ACCESS_ERR_IN9_PROXY,Access Error Detected in MCU PadCfg MMR" "0,1"
newline
bitfld.long 0x00 8. "ACCESS_ERR_STAT_ACCESS_ERR_IN8_PROXY,Access Error Detected in MCU Ctrl MMR" "0,1"
newline
bitfld.long 0x00 4. "ACCESS_ERR_STAT_ACCESS_ERR_IN4_PROXY,Access Error Detected in MAIN PadCfg MMR" "0,1"
newline
bitfld.long 0x00 3. "ACCESS_ERR_STAT_ACCESS_ERR_IN3_PROXY,Access Error Detected in MAIN Ctrl MMR" "0,1"
newline
bitfld.long 0x00 0. "ACCESS_ERR_STAT_ACCESS_ERR_IN0_PROXY,Access Error Detected in WKUP Ctrl MMR" "0,1"
group.long 0x3008++0x2B
line.long 0x00 "CFG0_LOCK0_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK0_KICK1_PROXY,"
line.long 0x08 "CFG0_intr_raw_status_PROXY,"
bitfld.long 0x08 3. "PROXY_ERR_PROXY,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR_PROXY,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR_PROXY,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR_PROXY,Protection violation error" "0,1"
line.long 0x0C "CFG0_intr_enabled_status_clear_PROXY,"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR_PROXY,Protection violation error" "0,1"
line.long 0x10 "CFG0_intr_enable_PROXY,"
bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable" "0,1"
line.long 0x14 "CFG0_intr_enable_clear_PROXY,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear" "0,1"
line.long 0x18 "CFG0_eoi_PROXY,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value"
line.long 0x1C "CFG0_fault_address_PROXY,"
line.long 0x20 "CFG0_fault_type_status_PROXY,"
bitfld.long 0x20 6. "FAULT_NS_PROXY,Non-secure access" "0,1"
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bitfld.long 0x20 0.--5. "FAULT_TYPE_PROXY,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "CFG0_fault_attr_status_PROXY,"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID_PROXY,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID"
line.long 0x28 "CFG0_fault_clear_PROXY,"
bitfld.long 0x28 0. "FAULT_CLR_PROXY,Fault clear" "0,1"
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x3100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P0_R$1,"
repeat.end
group.long 0x4020++0x03
line.long 0x00 "CFG0_MCU_GPIO_CTRL,"
bitfld.long 0x00 0. "MCU_GPIO_CTRL_WAKEN,Activates MCU_GPIO wakeup event operation by controling the MCU_GPIO LPSC clockstop_ack behavior" "No MCU_GPIO wakeup support,MCU_GPIO wakeup activated"
group.long 0x4084++0x17
line.long 0x00 "CFG0_DBOUNCE_CFG1,"
bitfld.long 0x00 0.--5. "DBOUNCE_CFG1_DB_CFG,Configures the debounce period used for I/Os with debounce_sel1 activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG0_DBOUNCE_CFG2,"
bitfld.long 0x04 0.--5. "DBOUNCE_CFG2_DB_CFG,Configures the debounce period used for I/Os with debounce_sel2 activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CFG0_DBOUNCE_CFG3,"
bitfld.long 0x08 0.--5. "DBOUNCE_CFG3_DB_CFG,Configures the debounce period used for I/Os with debounce_sel3 activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "CFG0_DBOUNCE_CFG4,"
bitfld.long 0x0C 0.--5. "DBOUNCE_CFG4_DB_CFG,Configures the debounce period used for I/Os with debounce_sel4 activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "CFG0_DBOUNCE_CFG5,"
bitfld.long 0x10 0.--5. "DBOUNCE_CFG5_DB_CFG,Configures the debounce period used for I/Os with debounce_sel5 activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "CFG0_DBOUNCE_CFG6,"
bitfld.long 0x14 0.--5. "DBOUNCE_CFG6_DB_CFG,Configures the debounce period used for I/Os with debounce_sel6 activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x40A0++0x03
line.long 0x00 "CFG0_TEMP_DIODE_TRIM,"
hexmask.long.word 0x00 0.--13. 1. "TEMP_DIODE_TRIM_TRIM,Sets the diode non-ideality factor (n) starting from 100th place decimal and going down"
rgroup.long 0x40B0++0x03
line.long 0x00 "CFG0_IO_VOLTAGE_STAT,"
bitfld.long 0x00 17. "IO_VOLTAGE_STAT_GPMC,Indicates the voltage for the GPMC I/O group (VDDSHV3)" "I/O group is set for 3.3V,I/O group is set for 1.8V"
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bitfld.long 0x00 16. "IO_VOLTAGE_STAT_GEMAC,Indicates the voltage for the GEMAC I/O group (VDDSHV2)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
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bitfld.long 0x00 11. "IO_VOLTAGE_STAT_MMC2,Indicates the voltage for the MMC2 I/O group (VDDSHV6)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
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bitfld.long 0x00 10. "IO_VOLTAGE_STAT_MMC1,Indicates the voltage for the MMC1 I/O group (VDDSHV5)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
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bitfld.long 0x00 9. "IO_VOLTAGE_STAT_MMC0,Indicates the voltage for the MMC0 I/O group (VDDSHV4)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
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bitfld.long 0x00 8. "IO_VOLTAGE_STAT_GENERAL,Indicates the voltage for the General I/O group (VDDSHV0)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
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bitfld.long 0x00 2. "IO_VOLTAGE_STAT_CANUART,Indicates the voltage for the CANUART I/O group (VDDSHV_WKUP)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
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bitfld.long 0x00 1. "IO_VOLTAGE_STAT_FLASH,Indicates the voltage for the Flash I/O group (VDDSHV1)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
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bitfld.long 0x00 0. "IO_VOLTAGE_STAT_WKUP_MCU,Indicates the voltage for the WKUP_MCU I/O group (VDDSHV_MCU)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
group.long 0x4204++0x03
line.long 0x00 "CFG0_MCU_TIMER1_CTRL,"
bitfld.long 0x00 8. "MCU_TIMER1_CTRL_CASCADE_EN,Activates cascading of TIMER1 to TIMER0" "0,1"
group.long 0x420C++0x03
line.long 0x00 "CFG0_MCU_TIMER3_CTRL,"
bitfld.long 0x00 8. "MCU_TIMER3_CTRL_CASCADE_EN,Activates cascading of TIMER3 to TIMER2" "0,1"
group.long 0x42E0++0x03
line.long 0x00 "CFG0_MCU_I2C0_CTRL,"
bitfld.long 0x00 0. "MCU_I2C0_CTRL_HS_MCS_EN,HS Mode controller current source activate" "0,1"
group.long 0x4600++0x07
line.long 0x00 "CFG0_MAIN_MTOG_CTRL,"
bitfld.long 0x00 31. "MAIN_MTOG_CTRL_IDLE_STAT,Idle Status: When high indicates MTOG0 is idle Field values (others are reserved)" "Gasket is Not Idle,Gasket is Idle"
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abitfld.long 0x00 16.--23. "MAIN_MTOG_CTRL_FORCE_TIMEOUT,Force Timout This is a fault tolerant bitfield" "0x00=Other Values Have No Effect,0x95=This is a fault tolerant bitfield"
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bitfld.long 0x00 15. "MAIN_MTOG_CTRL_TIMEOUT_EN,Timeout Activate" "Deactivate the gasket,Activate Gasket Functions"
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bitfld.long 0x00 0.--2. "MAIN_MTOG_CTRL_TIMEOUT_VAL,Gasket Timeout Value Selects the number of clock cycles before the interface is considered to have timed out" "0,1,2,3,4,5,6,7"
line.long 0x04 "CFG0_WKUP_MTOG_CTRL,"
bitfld.long 0x04 31. "WKUP_MTOG_CTRL_IDLE_STAT,Idle Status Field values (others are reserved)" "Gasket is Not Idle,Gasket is Idle"
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abitfld.long 0x04 16.--23. "WKUP_MTOG_CTRL_FORCE_TIMEOUT,Force Timout This is a fault tolerant bitfield" "0x00=Other Values Have No Effect,0x95=This is a fault tolerant bitfield"
newline
bitfld.long 0x04 15. "WKUP_MTOG_CTRL_TIMEOUT_EN,Timeout Activate" "Deactivate the gasket,Activate Gasket Functions"
newline
bitfld.long 0x04 0.--2. "WKUP_MTOG_CTRL_TIMEOUT_VAL,Gasket Timeout Value Selects the number of clock cycles before the interface is considered to have timed out" "0,1,2,3,4,5,6,7"
rgroup.long 0x4610++0x03
line.long 0x00 "CFG0_TOG_STAT,"
bitfld.long 0x00 15.--16. "TOG_STAT_SLV_TOG_STAT,Error Status of target Timeout Gaskets slv_tog_statundefined - Error status of mcu2central timeout gasket slv_tog_statundefined - Error status of mcu2dm timeout gasket" "0,1,2,3"
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bitfld.long 0x00 0.--1. "TOG_STAT_MST_TOG_STAT,Error Status of Controller Timeout Gaskets mst_tog_statundefined - Error status of central2mcu timeout gasket mst_tog_statundefined - Error status of dm2ws timeout gasket" "0,1,2,3"
group.long 0x5008++0x07
line.long 0x00 "CFG0_LOCK1_KICK0,"
line.long 0x04 "CFG0_LOCK1_KICK1,"
rgroup.long 0x5100++0x33
line.long 0x00 "CFG0_CLAIMREG_P1_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P1_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P1_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P1_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P1_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P1_R5_READONLY,"
line.long 0x18 "CFG0_CLAIMREG_P1_R6_READONLY,"
line.long 0x1C "CFG0_CLAIMREG_P1_R7_READONLY,"
line.long 0x20 "CFG0_CLAIMREG_P1_R8_READONLY,"
line.long 0x24 "CFG0_CLAIMREG_P1_R9_READONLY,"
line.long 0x28 "CFG0_CLAIMREG_P1_R10_READONLY,"
line.long 0x2C "CFG0_CLAIMREG_P1_R11_READONLY,"
line.long 0x30 "CFG0_CLAIMREG_P1_R12_READONLY,"
group.long 0x6020++0x03
line.long 0x00 "CFG0_MCU_GPIO_CTRL_PROXY,"
bitfld.long 0x00 0. "MCU_GPIO_CTRL_WAKEN_PROXY,Activates MCU_GPIO wakeup event operation by controling the MCU_GPIO LPSC clockstop_ack behavior" "No MCU_GPIO wakeup support,MCU_GPIO wakeup activated"
group.long 0x6084++0x17
line.long 0x00 "CFG0_DBOUNCE_CFG1_PROXY,"
bitfld.long 0x00 0.--5. "DBOUNCE_CFG1_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel1 activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG0_DBOUNCE_CFG2_PROXY,"
bitfld.long 0x04 0.--5. "DBOUNCE_CFG2_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel2 activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CFG0_DBOUNCE_CFG3_PROXY,"
bitfld.long 0x08 0.--5. "DBOUNCE_CFG3_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel3 activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "CFG0_DBOUNCE_CFG4_PROXY,"
bitfld.long 0x0C 0.--5. "DBOUNCE_CFG4_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel4 activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "CFG0_DBOUNCE_CFG5_PROXY,"
bitfld.long 0x10 0.--5. "DBOUNCE_CFG5_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel5 activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "CFG0_DBOUNCE_CFG6_PROXY,"
bitfld.long 0x14 0.--5. "DBOUNCE_CFG6_DB_CFG_PROXY,Configures the debounce period used for I/Os with debounce_sel6 activated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x60A0++0x03
line.long 0x00 "CFG0_TEMP_DIODE_TRIM_PROXY,"
hexmask.long.word 0x00 0.--13. 1. "TEMP_DIODE_TRIM_TRIM_PROXY,Sets the diode non-ideality factor (n) starting from 100th place decimal and going down"
rgroup.long 0x60B0++0x03
line.long 0x00 "CFG0_IO_VOLTAGE_STAT_PROXY,"
bitfld.long 0x00 17. "IO_VOLTAGE_STAT_GPMC_PROXY,Indicates the voltage for the GPMC I/O group (VDDSHV3)" "I/O group is set for 3.3V,I/O group is set for 1.8V"
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bitfld.long 0x00 16. "IO_VOLTAGE_STAT_GEMAC_PROXY,Indicates the voltage for the GEMAC I/O group (VDDSHV2)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
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bitfld.long 0x00 11. "IO_VOLTAGE_STAT_MMC2_PROXY,Indicates the voltage for the MMC2 I/O group (VDDSHV6)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
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bitfld.long 0x00 10. "IO_VOLTAGE_STAT_MMC1_PROXY,Indicates the voltage for the MMC1 I/O group (VDDSHV5)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
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bitfld.long 0x00 9. "IO_VOLTAGE_STAT_MMC0_PROXY,Indicates the voltage for the MMC0 I/O group (VDDSHV4)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
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bitfld.long 0x00 8. "IO_VOLTAGE_STAT_GENERAL_PROXY,Indicates the voltage for the General I/O group (VDDSHV0)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
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bitfld.long 0x00 2. "IO_VOLTAGE_STAT_CANUART_PROXY,Indicates the voltage for the CANUART I/O group (VDDSHV_WKUP)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
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bitfld.long 0x00 1. "IO_VOLTAGE_STAT_FLASH_PROXY,Indicates the voltage for the Flash I/O group (VDDSHV1)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
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bitfld.long 0x00 0. "IO_VOLTAGE_STAT_WKUP_MCU_PROXY,Indicates the voltage for the WKUP_MCU I/O group (VDDSHV_MCU)" "I/O group is set for 1.8V,I/O group is set for 3.3V"
group.long 0x6204++0x03
line.long 0x00 "CFG0_MCU_TIMER1_CTRL_PROXY,"
bitfld.long 0x00 8. "MCU_TIMER1_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER1 to TIMER0" "0,1"
group.long 0x620C++0x03
line.long 0x00 "CFG0_MCU_TIMER3_CTRL_PROXY,"
bitfld.long 0x00 8. "MCU_TIMER3_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER3 to TIMER2" "0,1"
group.long 0x62E0++0x03
line.long 0x00 "CFG0_MCU_I2C0_CTRL_PROXY,"
bitfld.long 0x00 0. "MCU_I2C0_CTRL_HS_MCS_EN_PROXY,HS Mode controller current source activate" "0,1"
group.long 0x6600++0x07
line.long 0x00 "CFG0_MAIN_MTOG_CTRL_PROXY,"
bitfld.long 0x00 31. "MAIN_MTOG_CTRL_IDLE_STAT_PROXY,Idle Status: When high indicates MTOG0 is idle Field values (others are reserved)" "Gasket is Not Idle,Gasket is Idle"
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abitfld.long 0x00 16.--23. "MAIN_MTOG_CTRL_FORCE_TIMEOUT_PROXY,Force Timout This is a fault tolerant bitfield" "0x00=Other Values Have No Effect,0x95=This is a fault tolerant bitfield"
newline
bitfld.long 0x00 15. "MAIN_MTOG_CTRL_TIMEOUT_EN_PROXY,Timeout Activate" "Deactivate the gasket,Activate Gasket Functions"
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bitfld.long 0x00 0.--2. "MAIN_MTOG_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout Value Selects the number of clock cycles before the interface is considered to have timed out" "0,1,2,3,4,5,6,7"
line.long 0x04 "CFG0_WKUP_MTOG_CTRL_PROXY,"
bitfld.long 0x04 31. "WKUP_MTOG_CTRL_IDLE_STAT_PROXY,Idle Status Field values (others are reserved)" "Gasket is Not Idle,Gasket is Idle"
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abitfld.long 0x04 16.--23. "WKUP_MTOG_CTRL_FORCE_TIMEOUT_PROXY,Force Timout This is a fault tolerant bitfield" "0x00=Other Values Have No Effect,0x95=This is a fault tolerant bitfield"
newline
bitfld.long 0x04 15. "WKUP_MTOG_CTRL_TIMEOUT_EN_PROXY,Timeout Activate" "Deactivate the gasket,Activate Gasket Functions"
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bitfld.long 0x04 0.--2. "WKUP_MTOG_CTRL_TIMEOUT_VAL_PROXY,Gasket Timeout Value Selects the number of clock cycles before the interface is considered to have timed out" "0,1,2,3,4,5,6,7"
rgroup.long 0x6610++0x03
line.long 0x00 "CFG0_TOG_STAT_PROXY,"
bitfld.long 0x00 15.--16. "TOG_STAT_SLV_TOG_STAT_PROXY,Error Status of target Timeout Gaskets slv_tog_statundefined - Error status of mcu2central timeout gasket slv_tog_statundefined - Error status of mcu2dm timeout gasket" "0,1,2,3"
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bitfld.long 0x00 0.--1. "TOG_STAT_MST_TOG_STAT_PROXY,Error Status of Controller Timeout Gaskets mst_tog_statundefined - Error status of central2mcu timeout gasket mst_tog_statundefined - Error status of dm2ws timeout gasket" "0,1,2,3"
group.long 0x7008++0x07
line.long 0x00 "CFG0_LOCK1_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK1_KICK1_PROXY,"
repeat 13. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 )
group.long ($2+0x7100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P1_R$1,"
repeat.end
group.long 0x8000++0x03
line.long 0x00 "CFG0_MCU_OBSCLK_CTRL,"
bitfld.long 0x00 24. "MCU_OBSCLK_CTRL_OUT_MUX_SEL,MCU_OBSCLK pin output mux selection" "The output of the MCU_OBSCLK output divider is..,HFOSC0_CLK is output on the pin"
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bitfld.long 0x00 16. "MCU_OBSCLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the OBSCLK divider value" "0,1"
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bitfld.long 0x00 8.--11. "MCU_OBSCLK_CTRL_CLK_DIV,MCU_OBSCLK pin clock selection output divider Output clock is divided by clk_div+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "MCU_OBSCLK_CTRL_CLK_SEL,MCU_OBSCLK pin clock selection Field values (others are reserved)" "CLK_12M_RC,'0',MCU_PLL0_HSDIV0_CLKOUT,MCU_PLL0_HSDIV4_CLKOUT,MCU_PLLCTRL_OBSCLK,CLK_32K,HFOSC0_CLKOUT,HFOSC0_CLKOUT_32K,MCU_SYSCLK0,DEVICE_CLKOUT_32K,?..."
group.long 0x8010++0x03
line.long 0x00 "CFG0_HFOSC0_CTRL,"
bitfld.long 0x00 7. "HFOSC0_CTRL_PD_C,Oscillator powerdown control" "0,1"
newline
bitfld.long 0x00 4. "HFOSC0_CTRL_BP_C,Reserved - Must Write '0'" "0,1"
group.long 0x8018++0x03
line.long 0x00 "CFG0_HFOSC0_TRIM,"
bitfld.long 0x00 31. "HFOSC0_TRIM_TRIM_EN,Apply MMR values to OSC trim inputs instead of tie-offs" "0,1"
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bitfld.long 0x00 20.--21. "HFOSC0_TRIM_HYST,Sets comparator hysterisis" "0,1,2,3"
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bitfld.long 0x00 16.--18. "HFOSC0_TRIM_I_MULT,AGC AMP current multiplication gain" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--13. "HFOSC0_TRIM_R_REF,Sets the AMP AGC bias current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 4.--7. "HFOSC0_TRIM_I_IBIAS_COMP,Sets the COMP bias current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "HFOSC0_TRIM_R_IBIAS_REF,Sets the base IBIAS reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x8020++0x07
line.long 0x00 "CFG0_HFOSC0_STAT,"
bitfld.long 0x00 0. "HFOSC0_STAT_DS_ON_WFI_STAT,Allows MCU to monitor the DM attempting a Deep Sleep" "0,1"
line.long 0x04 "CFG0_RC12M_OSC_TRIM,"
bitfld.long 0x04 6. "RC12M_OSC_TRIM_TRIMOSC_COARSE_DIR,Coarse adjustment direction" "Coarse adjustment decreases frequency,Coarse adjustment increases frequency"
newline
bitfld.long 0x04 3.--5. "RC12M_OSC_TRIM_TRIMOSC_COARSE,Coarse adjustment" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0.--2. "RC12M_OSC_TRIM_TRIMOSC_FINE,Fine adjustment" "0,1,2,3,4,5,6,7"
group.long 0x8030++0x03
line.long 0x00 "CFG0_HFOSC0_CLKOUT_32K_CTRL,"
bitfld.long 0x00 31. "HFOSC0_CLKOUT_32K_CTRL_RESET,Asynchronous Divider Reset" "Divider out of reset HFOSC0_CLKOUT_32K running,Divider is Reset HFOSC0_CLKOUT32K reset"
newline
bitfld.long 0x00 15. "HFOSC0_CLKOUT_32K_CTRL_CLKOUT_EN,HFOSC0_CLKOUT_32K activate" "Synchronously Deactivate HFOSC0_CLKOUT_32KHz,Synchronously Activate HFOSC0_CKLKOUT_32KHz"
newline
bitfld.long 0x00 8. "HFOSC0_CLKOUT_32K_CTRL_SYNC_DIS,HFOSC0_CLKOUT_32K Synchronize Deactivate" "Divider Updates are shadowed and take effect on..,Divider Updates are immediate and hazardous Do.."
newline
hexmask.long.byte 0x00 0.--6. 1. "HFOSC0_CLKOUT_32K_CTRL_HSDIV,HFOSC0_CLKOUT_32K divider: HFOSC0_CLKKOUT_32K Frequency = HFOSC0 Frequency / [8 * (hsdiv + 1)] Ex"
group.long 0x8038++0x0F
line.long 0x00 "CFG0_LFXOSC_CTRL,"
bitfld.long 0x00 7. "LFXOSC_CTRL_PD_C,Oscillator powerdown control" "0,1"
newline
bitfld.long 0x00 4. "LFXOSC_CTRL_BP_C,Oscillator bypass control" "0,1"
line.long 0x04 "CFG0_LFXOSC_TRIM,"
bitfld.long 0x04 20.--21. "LFXOSC_TRIM_HYST,Sets comparator hysterisis Field values (others are reserved)" "Hysteresis deactivated,Type 1 hysteresis activated (Default),Type 2 hysteresis activated,Both types 1 & 2 hysteresis activated"
newline
bitfld.long 0x04 16.--18. "LFXOSC_TRIM_I_MULT,AGC AMP current multiplication gain Field values (others are reserved)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 8.--13. "LFXOSC_TRIM_R_REF,Sets the AMP AGC bias current Field values (others are reserved)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 4.--7. "LFXOSC_TRIM_I_IBIAS_COMP,Sets the COMP bias current Field values (others are reserved)" "Base IBIAS ref x2,Base IBIAS ref x3,Base IBIAS ref x4,Base IBIAS ref x5,Base IBIAS ref x6,Base IBIAS ref x7,Base IBIAS ref x8,Base IBIAS ref x9,Base IBIAS ref x10,Base IBIAS ref x11,Base IBIAS ref x12,Base IBIAS ref x13,Base IBIAS ref x14,Base IBIAS ref x15,Base IBIAS ref x16,Base IBIAS ref x17"
newline
bitfld.long 0x04 0.--3. "LFXOSC_TRIM_R_IBIAS_REF,Sets the base IBIAS reference Field values (others are reserved)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CFG0_MCU_M4FSS_CLKSEL,"
bitfld.long 0x08 0. "MCU_M4FSS_CLKSEL_M4FSS_CLKSEL,Selects the Clock Divider for M4FSS" "MCU_SYSCLK0,MCU_SYSCLK0 / 2"
line.long 0x0C "CFG0_MCU_M4FSS_SYSTICK,"
rbitfld.long 0x0C 25. "MCU_M4FSS_SYSTICK_NOREF,No External Reference Clock for SysTick is available" "0,1"
newline
bitfld.long 0x0C 24. "MCU_M4FSS_SYSTICK_SKEW,Indicates whether or not the M4FSS free running clock divided by TENMS produces a 100Hz tick exactly Field values (others are reserved)" "Divider produces exactly a 100 Hz SysTick,The SysTick Frequency is not exactly 100 Hz"
newline
hexmask.long.tbyte 0x0C 0.--23. 1. "MCU_M4FSS_SYSTICK_TENMS,Integer Divider Value that produces a 100Hz SysTick from the M4FSS Clock Frequency"
group.long 0x8050++0x03
line.long 0x00 "CFG0_MCU_PLL_CLKSEL,"
bitfld.long 0x00 31. "MCU_PLL_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a mcu_reset_z for MCU PLL[2:0]" "0,1"
newline
bitfld.long 0x00 23. "MCU_PLL_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset" "Exit bypass mode (based on MCU..,Maintain bypass mode"
newline
bitfld.long 0x00 8. "MCU_PLL_CLKSEL_CLKLOSS_SWTCH_EN,When set activates automatic switching of MCU PLL[2:0] clock source to CLK_12M_RC if HFOSC0 clock loss is detected" "0,1"
group.long 0x8058++0x03
line.long 0x00 "CFG0_DEVICE_CLKOUT_32K_CTRL,"
bitfld.long 0x00 0.--1. "DEVICE_CLKOUT_32K_CTRL_CLK_32K_RC_SEL,Selects the source of the device level 32KHz Clock Field values (others are reserved)" "CLK_32K_RC,HFOSC0_CLKOUT_32K,Reserved - (implementation: CLK_32K_RC),LFOSC0_CLKOUT"
group.long 0x8060++0x13
line.long 0x00 "CFG0_MCU_TIMER0_CLKSEL,"
bitfld.long 0x00 0.--2. "MCU_TIMER0_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,MCU_SYSCLK0 / 2,CLK_12M_RC,MCU_PLL0_HSDIV3_CLKOUT,MCU_EXT_REFCLK0,DEVICE_CLKOUT_32K,CPSW_GENF0,CLK_32K_RC"
line.long 0x04 "CFG0_MCU_TIMER1_CLKSEL,"
bitfld.long 0x04 0.--2. "MCU_TIMER1_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,MCU_SYSCLK0 / 2,CLK_12M_RC,MCU_PLL0_HSDIV3_CLKOUT,MCU_EXT_REFCLK0,DEVICE_CLKOUT_32K,CPSW_GENF0,CLK_32K_RC"
line.long 0x08 "CFG0_MCU_TIMER2_CLKSEL,"
bitfld.long 0x08 0.--2. "MCU_TIMER2_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,MCU_SYSCLK0 / 2,CLK_12M_RC,MCU_PLL0_HSDIV3_CLKOUT,MCU_EXT_REFCLK0,DEVICE_CLKOUT_32K,CPSW_GENF0,CLK_32K_RC"
line.long 0x0C "CFG0_MCU_TIMER3_CLKSEL,"
bitfld.long 0x0C 0.--2. "MCU_TIMER3_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,MCU_SYSCLK0 / 2,CLK_12M_RC,MCU_PLL0_HSDIV3_CLKOUT,MCU_EXT_REFCLK0,DEVICE_CLKOUT_32K,CPSW_GENF0,CLK_32K_RC"
line.long 0x10 "CFG0_MCU_GPIO_CLKSEL,"
bitfld.long 0x10 0.--1. "MCU_GPIO_CLKSEL_CLK_SEL,MCU_GPIO clock selection" "MCU_SYSCLK0 / 4,LFSOSC_CLKOUT,CLK_32K,CLK_12M_RC"
group.long 0x8080++0x07
line.long 0x00 "CFG0_MCU_MCAN0_CLKSEL,"
bitfld.long 0x00 0.--1. "MCU_MCAN0_CLKSEL_CLK_SEL,Selects the clock source for MCAN0 Field values (others are reserved)" "MCU_PLL0_HSDIV4_CLKOUT,MCU_EXT_REFCLK0,HFOSC0_CLKOUT,HFOSC0_CLKOUT"
line.long 0x04 "CFG0_MCU_MCAN1_CLKSEL,"
bitfld.long 0x04 0.--1. "MCU_MCAN1_CLKSEL_CLK_SEL,Selects the clock source for MCAN1 Field values (others are reserved)" "MCU_PLL0_HSDIV4_CLKOUT,MCU_EXT_REFCLK0,HFOSC0_CLKOUT,HFOSC0_CLKOUT"
group.long 0x80A0++0x07
line.long 0x00 "CFG0_MCU_SPI0_CLKSEL,"
bitfld.long 0x00 16. "MCU_SPI0_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
line.long 0x04 "CFG0_MCU_SPI1_CLKSEL,"
bitfld.long 0x04 16. "MCU_SPI1_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
group.long 0x80B0++0x03
line.long 0x00 "CFG0_MCU_WWD0_CLKSEL,"
bitfld.long 0x00 31. "MCU_WWD0_CLKSEL_WRTLOCK,When set locks WWD0_CLKSEL from further writes until the next module reset" "0,1"
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bitfld.long 0x00 0.--1. "MCU_WWD0_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K_RC"
group.long 0x9008++0x07
line.long 0x00 "CFG0_LOCK2_KICK0,"
line.long 0x04 "CFG0_LOCK2_KICK1,"
rgroup.long 0x9100++0x07
line.long 0x00 "CFG0_CLAIMREG_P2_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P2_R1_READONLY,"
group.long 0xA000++0x03
line.long 0x00 "CFG0_MCU_OBSCLK_CTRL_PROXY,"
bitfld.long 0x00 24. "MCU_OBSCLK_CTRL_OUT_MUX_SEL_PROXY,MCU_OBSCLK pin output mux selection" "The output of the MCU_OBSCLK output divider is..,HFOSC0_CLK is output on the pin"
newline
bitfld.long 0x00 16. "MCU_OBSCLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the OBSCLK divider value" "0,1"
newline
bitfld.long 0x00 8.--11. "MCU_OBSCLK_CTRL_CLK_DIV_PROXY,MCU_OBSCLK pin clock selection output divider Output clock is divided by clk_div+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "MCU_OBSCLK_CTRL_CLK_SEL_PROXY,MCU_OBSCLK pin clock selection Field values (others are reserved)" "CLK_12M_RC,'0',MCU_PLL0_HSDIV0_CLKOUT,MCU_PLL0_HSDIV4_CLKOUT,MCU_PLLCTRL_OBSCLK,CLK_32K,HFOSC0_CLKOUT,HFOSC0_CLKOUT_32K,MCU_SYSCLK0,DEVICE_CLKOUT_32K,?..."
group.long 0xA010++0x03
line.long 0x00 "CFG0_HFOSC0_CTRL_PROXY,"
bitfld.long 0x00 7. "HFOSC0_CTRL_PD_C_PROXY,Oscillator powerdown control" "0,1"
newline
bitfld.long 0x00 4. "HFOSC0_CTRL_BP_C_PROXY,Reserved - Must Write '0'" "0,1"
group.long 0xA018++0x03
line.long 0x00 "CFG0_HFOSC0_TRIM_PROXY,"
bitfld.long 0x00 31. "HFOSC0_TRIM_TRIM_EN_PROXY,Apply MMR values to OSC trim inputs instead of tie-offs" "0,1"
newline
bitfld.long 0x00 20.--21. "HFOSC0_TRIM_HYST_PROXY,Sets comparator hysterisis" "0,1,2,3"
newline
bitfld.long 0x00 16.--18. "HFOSC0_TRIM_I_MULT_PROXY,AGC AMP current multiplication gain" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--13. "HFOSC0_TRIM_R_REF_PROXY,Sets the AMP AGC bias current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 4.--7. "HFOSC0_TRIM_I_IBIAS_COMP_PROXY,Sets the COMP bias current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "HFOSC0_TRIM_R_IBIAS_REF_PROXY,Sets the base IBIAS reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xA020++0x07
line.long 0x00 "CFG0_HFOSC0_STAT_PROXY,"
bitfld.long 0x00 0. "HFOSC0_STAT_DS_ON_WFI_STAT_PROXY,Allows MCU to monitor the DM attempting a Deep Sleep" "0,1"
line.long 0x04 "CFG0_RC12M_OSC_TRIM_PROXY,"
bitfld.long 0x04 6. "RC12M_OSC_TRIM_TRIMOSC_COARSE_DIR_PROXY,Coarse adjustment direction" "Coarse adjustment decreases frequency,Coarse adjustment increases frequency"
newline
bitfld.long 0x04 3.--5. "RC12M_OSC_TRIM_TRIMOSC_COARSE_PROXY,Coarse adjustment" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0.--2. "RC12M_OSC_TRIM_TRIMOSC_FINE_PROXY,Fine adjustment" "0,1,2,3,4,5,6,7"
group.long 0xA030++0x03
line.long 0x00 "CFG0_HFOSC0_CLKOUT_32K_CTRL_PROXY,"
bitfld.long 0x00 31. "HFOSC0_CLKOUT_32K_CTRL_RESET_PROXY,Asynchronous Divider Reset" "Divider out of reset HFOSC0_CLKOUT_32K running,Divider is Reset HFOSC0_CLKOUT32K reset"
newline
bitfld.long 0x00 15. "HFOSC0_CLKOUT_32K_CTRL_CLKOUT_EN_PROXY,HFOSC0_CLKOUT_32K activate" "Synchronously Deactivate HFOSC0_CLKOUT_32KHz,Synchronously Activate HFOSC0_CKLKOUT_32KHz"
newline
bitfld.long 0x00 8. "HFOSC0_CLKOUT_32K_CTRL_SYNC_DIS_PROXY,HFOSC0_CLKOUT_32K Synchronize Deactivate" "Divider Updates are shadowed and take effect on..,Divider Updates are immediate and hazardous Do.."
newline
hexmask.long.byte 0x00 0.--6. 1. "HFOSC0_CLKOUT_32K_CTRL_HSDIV_PROXY,HFOSC0_CLKOUT_32K divider: HFOSC0_CLKKOUT_32K Frequency = HFOSC0 Frequency / [8 * (hsdiv + 1)] Ex"
group.long 0xA038++0x0F
line.long 0x00 "CFG0_LFXOSC_CTRL_PROXY,"
bitfld.long 0x00 7. "LFXOSC_CTRL_PD_C_PROXY,Oscillator powerdown control" "0,1"
newline
bitfld.long 0x00 4. "LFXOSC_CTRL_BP_C_PROXY,Oscillator bypass control" "0,1"
line.long 0x04 "CFG0_LFXOSC_TRIM_PROXY,"
bitfld.long 0x04 20.--21. "LFXOSC_TRIM_HYST_PROXY,Sets comparator hysterisis Field values (others are reserved)" "Hysteresis deactivated,Type 1 hysteresis activated (Default),Type 2 hysteresis activated,Both types 1 & 2 hysteresis activated"
newline
bitfld.long 0x04 16.--18. "LFXOSC_TRIM_I_MULT_PROXY,AGC AMP current multiplication gain Field values (others are reserved)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 8.--13. "LFXOSC_TRIM_R_REF_PROXY,Sets the AMP AGC bias current Field values (others are reserved)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 4.--7. "LFXOSC_TRIM_I_IBIAS_COMP_PROXY,Sets the COMP bias current Field values (others are reserved)" "Base IBIAS ref x2,Base IBIAS ref x3,Base IBIAS ref x4,Base IBIAS ref x5,Base IBIAS ref x6,Base IBIAS ref x7,Base IBIAS ref x8,Base IBIAS ref x9,Base IBIAS ref x10,Base IBIAS ref x11,Base IBIAS ref x12,Base IBIAS ref x13,Base IBIAS ref x14,Base IBIAS ref x15,Base IBIAS ref x16,Base IBIAS ref x17"
newline
bitfld.long 0x04 0.--3. "LFXOSC_TRIM_R_IBIAS_REF_PROXY,Sets the base IBIAS reference Field values (others are reserved)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CFG0_MCU_M4FSS_CLKSEL_PROXY,"
bitfld.long 0x08 0. "MCU_M4FSS_CLKSEL_M4FSS_CLKSEL_PROXY,Selects the Clock Divider for M4FSS" "MCU_SYSCLK0,MCU_SYSCLK0 / 2"
line.long 0x0C "CFG0_MCU_M4FSS_SYSTICK_PROXY,"
rbitfld.long 0x0C 25. "MCU_M4FSS_SYSTICK_NOREF_PROXY,No External Reference Clock for SysTick is available" "0,1"
newline
bitfld.long 0x0C 24. "MCU_M4FSS_SYSTICK_SKEW_PROXY,Indicates whether or not the M4FSS free running clock divided by TENMS produces a 100Hz tick exactly Field values (others are reserved)" "Divider produces exactly a 100 Hz SysTick,The SysTick Frequency is not exactly 100 Hz"
newline
hexmask.long.tbyte 0x0C 0.--23. 1. "MCU_M4FSS_SYSTICK_TENMS_PROXY,Integer Divider Value that produces a 100Hz SysTick from the M4FSS Clock Frequency"
group.long 0xA050++0x03
line.long 0x00 "CFG0_MCU_PLL_CLKSEL_PROXY,"
bitfld.long 0x00 31. "MCU_PLL_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a mcu_reset_z for MCU PLL[2:0]" "0,1"
newline
bitfld.long 0x00 23. "MCU_PLL_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset" "Exit bypass mode (based on MCU..,Maintain bypass mode"
newline
bitfld.long 0x00 8. "MCU_PLL_CLKSEL_CLKLOSS_SWTCH_EN_PROXY,When set activates automatic switching of MCU PLL[2:0] clock source to CLK_12M_RC if HFOSC0 clock loss is detected" "0,1"
group.long 0xA058++0x03
line.long 0x00 "CFG0_DEVICE_CLKOUT_32K_CTRL_PROXY,"
bitfld.long 0x00 0.--1. "DEVICE_CLKOUT_32K_CTRL_CLK_32K_RC_SEL_PROXY,Selects the source of the device level 32KHz Clock Field values (others are reserved)" "CLK_32K_RC,HFOSC0_CLKOUT_32K,Reserved - (implementation: CLK_32K_RC),LFOSC0_CLKOUT"
group.long 0xA060++0x13
line.long 0x00 "CFG0_MCU_TIMER0_CLKSEL_PROXY,"
bitfld.long 0x00 0.--2. "MCU_TIMER0_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,MCU_SYSCLK0 / 2,CLK_12M_RC,MCU_PLL0_HSDIV3_CLKOUT,MCU_EXT_REFCLK0,DEVICE_CLKOUT_32K,CPSW_GENF0,CLK_32K_RC"
line.long 0x04 "CFG0_MCU_TIMER1_CLKSEL_PROXY,"
bitfld.long 0x04 0.--2. "MCU_TIMER1_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,MCU_SYSCLK0 / 2,CLK_12M_RC,MCU_PLL0_HSDIV3_CLKOUT,MCU_EXT_REFCLK0,DEVICE_CLKOUT_32K,CPSW_GENF0,CLK_32K_RC"
line.long 0x08 "CFG0_MCU_TIMER2_CLKSEL_PROXY,"
bitfld.long 0x08 0.--2. "MCU_TIMER2_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,MCU_SYSCLK0 / 2,CLK_12M_RC,MCU_PLL0_HSDIV3_CLKOUT,MCU_EXT_REFCLK0,DEVICE_CLKOUT_32K,CPSW_GENF0,CLK_32K_RC"
line.long 0x0C "CFG0_MCU_TIMER3_CLKSEL_PROXY,"
bitfld.long 0x0C 0.--2. "MCU_TIMER3_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,MCU_SYSCLK0 / 2,CLK_12M_RC,MCU_PLL0_HSDIV3_CLKOUT,MCU_EXT_REFCLK0,DEVICE_CLKOUT_32K,CPSW_GENF0,CLK_32K_RC"
line.long 0x10 "CFG0_MCU_GPIO_CLKSEL_PROXY,"
bitfld.long 0x10 0.--1. "MCU_GPIO_CLKSEL_CLK_SEL_PROXY,MCU_GPIO clock selection" "MCU_SYSCLK0 / 4,LFSOSC_CLKOUT,CLK_32K,CLK_12M_RC"
group.long 0xA080++0x07
line.long 0x00 "CFG0_MCU_MCAN0_CLKSEL_PROXY,"
bitfld.long 0x00 0.--1. "MCU_MCAN0_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MCAN0 Field values (others are reserved)" "MCU_PLL0_HSDIV4_CLKOUT,MCU_EXT_REFCLK0,HFOSC0_CLKOUT,HFOSC0_CLKOUT"
line.long 0x04 "CFG0_MCU_MCAN1_CLKSEL_PROXY,"
bitfld.long 0x04 0.--1. "MCU_MCAN1_CLKSEL_CLK_SEL_PROXY,Selects the clock source for MCAN1 Field values (others are reserved)" "MCU_PLL0_HSDIV4_CLKOUT,MCU_EXT_REFCLK0,HFOSC0_CLKOUT,HFOSC0_CLKOUT"
group.long 0xA0A0++0x07
line.long 0x00 "CFG0_MCU_SPI0_CLKSEL_PROXY,"
bitfld.long 0x00 16. "MCU_SPI0_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
line.long 0x04 "CFG0_MCU_SPI1_CLKSEL_PROXY,"
bitfld.long 0x04 16. "MCU_SPI1_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
group.long 0xA0B0++0x03
line.long 0x00 "CFG0_MCU_WWD0_CLKSEL_PROXY,"
bitfld.long 0x00 31. "MCU_WWD0_CLKSEL_WRTLOCK_PROXY,When set locks WWD0_CLKSEL from further writes until the next module reset" "0,1"
newline
bitfld.long 0x00 0.--1. "MCU_WWD0_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K_RC"
group.long 0xB008++0x07
line.long 0x00 "CFG0_LOCK2_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK2_KICK1_PROXY,"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xB100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P2_R$1,"
repeat.end
group.long 0xC020++0x1F
line.long 0x00 "CFG0_MCU_M4FSS0_LBIST_CTRL,"
bitfld.long 0x00 31. "MCU_M4FSS0_LBIST_CTRL_BIST_RESET,This bitfield is not used" "0,1"
newline
bitfld.long 0x00 24.--27. "MCU_M4FSS0_LBIST_CTRL_BIST_RUN,This bitfield is not used" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--20. "MCU_M4FSS0_LBIST_CTRL_SUBCHIP_ID,Specifies which sub-chip is to be tested" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 12.--15. "MCU_M4FSS0_LBIST_CTRL_RUNBIST_MODE,Runbist mode activate if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--9. "MCU_M4FSS0_LBIST_CTRL_DC_DEF,Clock delay after scan_activate switching" "0,1,2,3"
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bitfld.long 0x00 7. "MCU_M4FSS0_LBIST_CTRL_LOAD_DIV,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1"
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bitfld.long 0x00 0.--4. "MCU_M4FSS0_LBIST_CTRL_DIVIDE_RATIO,LBIST clock divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CFG0_MCU_M4FSS0_LBIST_PATCOUNT,"
hexmask.long.word 0x04 16.--29. 1. "MCU_M4FSS0_LBIST_PATCOUNT_STATIC_PC_DEF,Number of stuck-at patterns to run"
newline
bitfld.long 0x04 8.--11. "MCU_M4FSS0_LBIST_PATCOUNT_SET_PC_DEF,Number of set patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 4.--7. "MCU_M4FSS0_LBIST_PATCOUNT_RESET_PC_DEF,Number of reset patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--3. "MCU_M4FSS0_LBIST_PATCOUNT_SCAN_PC_DEF,Number of chain test patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CFG0_MCU_M4FSS0_LBIST_SEED0,"
line.long 0x0C "CFG0_MCU_M4FSS0_LBIST_SEED1,"
hexmask.long.tbyte 0x0C 0.--20. 1. "MCU_M4FSS0_LBIST_SEED1_PRPG_DEF,Initial seed for PRPG (bits 52:32)"
line.long 0x10 "CFG0_MCU_M4FSS0_LBIST_SPARE0,"
hexmask.long 0x10 2.--31. 1. "MCU_M4FSS0_LBIST_SPARE0_SPARE0,LBIST spare bits"
newline
bitfld.long 0x10 1. "MCU_M4FSS0_LBIST_SPARE0_PBIST_SELFTEST_EN,PBIST isolation control" "0,1"
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bitfld.long 0x10 0. "MCU_M4FSS0_LBIST_SPARE0_LBIST_SELFTEST_EN,LBIST isolation control" "0,1"
line.long 0x14 "CFG0_MCU_M4FSS0_LBIST_SPARE1,"
line.long 0x18 "CFG0_MCU_M4FSS0_LBIST_STAT,"
rbitfld.long 0x18 31. "MCU_M4FSS0_LBIST_STAT_BIST_DONE,LBIST is done" "0,1"
newline
rbitfld.long 0x18 15. "MCU_M4FSS0_LBIST_STAT_BIST_RUNNING,LBIST is running" "0,1"
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bitfld.long 0x18 8.--9. "MCU_M4FSS0_LBIST_STAT_OUT_MUX_CTL,Selects source of LBIST output" "LBIST IP PID value,LBIST CTRL ID value 1x - MISR value,?..."
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hexmask.long.byte 0x18 0.--7. 1. "MCU_M4FSS0_LBIST_STAT_MISR_MUX_CTL,Selects block of 32 MISR bits to"
line.long 0x1C "CFG0_MCU_M4FSS0_LBIST_MISR,"
group.long 0xD008++0x07
line.long 0x00 "CFG0_LOCK3_KICK0,"
line.long 0x04 "CFG0_LOCK3_KICK1,"
rgroup.long 0xD100++0x03
line.long 0x00 "CFG0_CLAIMREG_P3_R0_READONLY,"
group.long 0xE020++0x1F
line.long 0x00 "CFG0_MCU_M4FSS0_LBIST_CTRL_PROXY,"
bitfld.long 0x00 31. "MCU_M4FSS0_LBIST_CTRL_BIST_RESET_PROXY,This bitfield is not used" "0,1"
newline
bitfld.long 0x00 24.--27. "MCU_M4FSS0_LBIST_CTRL_BIST_RUN_PROXY,This bitfield is not used" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--20. "MCU_M4FSS0_LBIST_CTRL_SUBCHIP_ID_PROXY,Specifies which sub-chip is to be tested" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 12.--15. "MCU_M4FSS0_LBIST_CTRL_RUNBIST_MODE_PROXY,Runbist mode activate if all bits are 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--9. "MCU_M4FSS0_LBIST_CTRL_DC_DEF_PROXY,Clock delay after scan_activate switching" "0,1,2,3"
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bitfld.long 0x00 7. "MCU_M4FSS0_LBIST_CTRL_LOAD_DIV_PROXY,Loads LBIST clock divide ratio on transition from 0 to 1" "0,1"
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bitfld.long 0x00 0.--4. "MCU_M4FSS0_LBIST_CTRL_DIVIDE_RATIO_PROXY,LBIST clock divide ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CFG0_MCU_M4FSS0_LBIST_PATCOUNT_PROXY,"
hexmask.long.word 0x04 16.--29. 1. "MCU_M4FSS0_LBIST_PATCOUNT_STATIC_PC_DEF_PROXY,Number of stuck-at patterns to run"
newline
bitfld.long 0x04 8.--11. "MCU_M4FSS0_LBIST_PATCOUNT_SET_PC_DEF_PROXY,Number of set patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 4.--7. "MCU_M4FSS0_LBIST_PATCOUNT_RESET_PC_DEF_PROXY,Number of reset patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--3. "MCU_M4FSS0_LBIST_PATCOUNT_SCAN_PC_DEF_PROXY,Number of chain test patterns to run" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CFG0_MCU_M4FSS0_LBIST_SEED0_PROXY,"
line.long 0x0C "CFG0_MCU_M4FSS0_LBIST_SEED1_PROXY,"
hexmask.long.tbyte 0x0C 0.--20. 1. "MCU_M4FSS0_LBIST_SEED1_PRPG_DEF_PROXY,Initial seed for PRPG (bits 52:32)"
line.long 0x10 "CFG0_MCU_M4FSS0_LBIST_SPARE0_PROXY,"
hexmask.long 0x10 2.--31. 1. "MCU_M4FSS0_LBIST_SPARE0_SPARE0_PROXY,LBIST spare bits"
newline
bitfld.long 0x10 1. "MCU_M4FSS0_LBIST_SPARE0_PBIST_SELFTEST_EN_PROXY,PBIST isolation control" "0,1"
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bitfld.long 0x10 0. "MCU_M4FSS0_LBIST_SPARE0_LBIST_SELFTEST_EN_PROXY,LBIST isolation control" "0,1"
line.long 0x14 "CFG0_MCU_M4FSS0_LBIST_SPARE1_PROXY,"
line.long 0x18 "CFG0_MCU_M4FSS0_LBIST_STAT_PROXY,"
rbitfld.long 0x18 31. "MCU_M4FSS0_LBIST_STAT_BIST_DONE_PROXY,LBIST is done" "0,1"
newline
rbitfld.long 0x18 15. "MCU_M4FSS0_LBIST_STAT_BIST_RUNNING_PROXY,LBIST is running" "0,1"
newline
bitfld.long 0x18 8.--9. "MCU_M4FSS0_LBIST_STAT_OUT_MUX_CTL_PROXY,Selects source of LBIST output" "LBIST IP PID value,LBIST CTRL ID value 1x - MISR value,?..."
newline
hexmask.long.byte 0x18 0.--7. 1. "MCU_M4FSS0_LBIST_STAT_MISR_MUX_CTL_PROXY,Selects block of 32 MISR bits to"
line.long 0x1C "CFG0_MCU_M4FSS0_LBIST_MISR_PROXY,"
group.long 0xF008++0x07
line.long 0x00 "CFG0_LOCK3_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK3_KICK1_PROXY,"
group.long 0xF100++0x03
line.long 0x00 "CFG0_CLAIMREG_P3_R0,"
group.long 0x10874++0x03
line.long 0x00 "CFG0_OLDI_PD_CTRL_TEST_REG,"
rbitfld.long 0x00 31. "OLDI_PD_CTRL_TEST_REG_BGOK,Status of the Bandgap" "0,1"
newline
bitfld.long 0x00 8. "OLDI_PD_CTRL_TEST_REG_PD_BG,When Set forces the LVDS Bandgap into Power Down" "0,1"
newline
bitfld.long 0x00 1. "OLDI_PD_CTRL_TEST_REG_PD_OLDI1,When Set overrides the biase_en of all OLDI1 LVDS IO to force power down" "0,1"
newline
bitfld.long 0x00 0. "OLDI_PD_CTRL_TEST_REG_PD_OLDI0,When Set overrides the biase_en of all OLDI0 LVDS IO to force power down" "0,1"
group.long 0x10890++0x03
line.long 0x00 "CFG0_PBIST_EN_TEST_REG,"
bitfld.long 0x00 6. "PBIST_EN_TEST_REG_DSS0_PBIST_EN,PBIST Activate" "0,1"
newline
bitfld.long 0x00 4. "PBIST_EN_TEST_REG_USB1_PBIST_EN,PBIST Activate" "0,1"
newline
bitfld.long 0x00 3. "PBIST_EN_TEST_REG_USB0_PBIST_EN,PBIST Activate" "0,1"
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bitfld.long 0x00 2. "PBIST_EN_TEST_REG_EMMC2_PBIST_EN,PBIST Activate" "0,1"
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bitfld.long 0x00 1. "PBIST_EN_TEST_REG_EMMC1_PBIST_EN,PBIST Activate" "0,1"
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bitfld.long 0x00 0. "PBIST_EN_TEST_REG_EMMC0_PBIST_EN,PBIST Activate" "0,1"
group.long 0x11008++0x07
line.long 0x00 "CFG0_LOCK4_KICK0,"
line.long 0x04 "CFG0_LOCK4_KICK1,"
rgroup.long 0x11100++0x4F
line.long 0x00 "CFG0_CLAIMREG_P4_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P4_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P4_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P4_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P4_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P4_R5_READONLY,"
line.long 0x18 "CFG0_CLAIMREG_P4_R6_READONLY,"
line.long 0x1C "CFG0_CLAIMREG_P4_R7_READONLY,"
line.long 0x20 "CFG0_CLAIMREG_P4_R8_READONLY,"
line.long 0x24 "CFG0_CLAIMREG_P4_R9_READONLY,"
line.long 0x28 "CFG0_CLAIMREG_P4_R10_READONLY,"
line.long 0x2C "CFG0_CLAIMREG_P4_R11_READONLY,"
line.long 0x30 "CFG0_CLAIMREG_P4_R12_READONLY,"
line.long 0x34 "CFG0_CLAIMREG_P4_R13_READONLY,"
line.long 0x38 "CFG0_CLAIMREG_P4_R14_READONLY,"
line.long 0x3C "CFG0_CLAIMREG_P4_R15_READONLY,"
line.long 0x40 "CFG0_CLAIMREG_P4_R16_READONLY,"
line.long 0x44 "CFG0_CLAIMREG_P4_R17_READONLY,"
line.long 0x48 "CFG0_CLAIMREG_P4_R18_READONLY,"
line.long 0x4C "CFG0_CLAIMREG_P4_R19_READONLY,"
group.long 0x12874++0x03
line.long 0x00 "CFG0_OLDI_PD_CTRL_TEST_REG_PROXY,"
rbitfld.long 0x00 31. "OLDI_PD_CTRL_TEST_REG_BGOK_PROXY,Status of the Bandgap" "0,1"
newline
bitfld.long 0x00 8. "OLDI_PD_CTRL_TEST_REG_PD_BG_PROXY,When Set forces the LVDS Bandgap into Power Down" "0,1"
newline
bitfld.long 0x00 1. "OLDI_PD_CTRL_TEST_REG_PD_OLDI1_PROXY,When Set overrides the biase_en of all OLDI1 LVDS IO to force power down" "0,1"
newline
bitfld.long 0x00 0. "OLDI_PD_CTRL_TEST_REG_PD_OLDI0_PROXY,When Set overrides the biase_en of all OLDI0 LVDS IO to force power down" "0,1"
group.long 0x12890++0x03
line.long 0x00 "CFG0_PBIST_EN_TEST_REG_PROXY,"
bitfld.long 0x00 6. "PBIST_EN_TEST_REG_DSS0_PBIST_EN_PROXY,PBIST Activate" "0,1"
newline
bitfld.long 0x00 4. "PBIST_EN_TEST_REG_USB1_PBIST_EN_PROXY,PBIST Activate" "0,1"
newline
bitfld.long 0x00 3. "PBIST_EN_TEST_REG_USB0_PBIST_EN_PROXY,PBIST Activate" "0,1"
newline
bitfld.long 0x00 2. "PBIST_EN_TEST_REG_EMMC2_PBIST_EN_PROXY,PBIST Activate" "0,1"
newline
bitfld.long 0x00 1. "PBIST_EN_TEST_REG_EMMC1_PBIST_EN_PROXY,PBIST Activate" "0,1"
newline
bitfld.long 0x00 0. "PBIST_EN_TEST_REG_EMMC0_PBIST_EN_PROXY,PBIST Activate" "0,1"
group.long 0x13008++0x07
line.long 0x00 "CFG0_LOCK4_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK4_KICK1_PROXY,"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x13100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P4_R$1,"
repeat.end
repeat 4. (list 16. 17. 18. 19. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x13140)++0x03
line.long 0x00 "CFG0_CLAIMREG_P4_R$1,"
repeat.end
group.long 0x18000++0x07
line.long 0x00 "CFG0_POR_CTRL,"
bitfld.long 0x00 29. "POR_CTRL_OVRD_SET5,Reserved override set" "0,1"
newline
bitfld.long 0x00 28. "POR_CTRL_OVRD_SET4,POKLVB override set" "0,1"
newline
bitfld.long 0x00 27. "POR_CTRL_OVRD_SET3,POKLVA override set" "0,1"
newline
bitfld.long 0x00 26. "POR_CTRL_OVRD_SET2,POKHV override set" "0,1"
newline
bitfld.long 0x00 25. "POR_CTRL_OVRD_SET1,BGOK override set" "0,1"
newline
bitfld.long 0x00 24. "POR_CTRL_OVRD_SET0,PORHV override set" "0,1"
newline
bitfld.long 0x00 21. "POR_CTRL_OVRD5,Reserved override activate" "0,1"
newline
bitfld.long 0x00 20. "POR_CTRL_OVRD4,POKLVB override activate" "0,1"
newline
bitfld.long 0x00 19. "POR_CTRL_OVRD3,POKLVA override activate" "0,1"
newline
bitfld.long 0x00 18. "POR_CTRL_OVRD2,POKHV override activate" "0,1"
newline
bitfld.long 0x00 17. "POR_CTRL_OVRD1,BGOK override activate" "0,1"
newline
bitfld.long 0x00 16. "POR_CTRL_OVRD0,PORHV override activate" "0,1"
newline
bitfld.long 0x00 7. "POR_CTRL_TRIM_SEL,POR Trim Select" "Trim selections for Bandgap and POKs come from..,Trim selections for Bandgap and POKs come from.."
newline
bitfld.long 0x00 4. "POR_CTRL_MASK_HHV,Mask HHV/SOC_PORz outputs when applying new trim values" "0,1"
line.long 0x04 "CFG0_POR_STAT,"
bitfld.long 0x04 8. "POR_STAT_BGOK,Bandgap OK status" "0,1"
newline
bitfld.long 0x04 4. "POR_STAT_SOC_POR,POR module status" "Module is in functional mode,Module is in reset mode"
group.long 0x18100++0x03
line.long 0x00 "CFG0_POR_BANDGAP_CTRL,"
bitfld.long 0x00 16.--19. "POR_BANDGAP_CTRL_BGAPI,Bandgap output current trim bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 8.--15. 1. "POR_BANDGAP_CTRL_BGAPV,Bandgap output voltage magnitude trim bits"
newline
hexmask.long.byte 0x00 0.--7. 1. "POR_BANDGAP_CTRL_BGAPC,Bandgap slope trim bits"
group.long 0x18110++0x17
line.long 0x00 "CFG0_POK_VDDA_MCU_UV_CTRL,"
bitfld.long 0x00 31. "POK_VDDA_MCU_UV_CTRL_HYST_EN,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x00 7. "POK_VDDA_MCU_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x00 0.--6. 1. "POK_VDDA_MCU_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x04 "CFG0_POK_VDDA_MCU_OV_CTRL,"
bitfld.long 0x04 31. "POK_VDDA_MCU_OV_CTRL_HYST_EN,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x04 7. "POK_VDDA_MCU_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x04 0.--6. 1. "POK_VDDA_MCU_OV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x08 "CFG0_POK_VDD_CORE_UV_CTRL,"
bitfld.long 0x08 31. "POK_VDD_CORE_UV_CTRL_HYST_EN,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x08 7. "POK_VDD_CORE_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x08 0.--6. 1. "POK_VDD_CORE_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x0C "CFG0_POK_VDD_CORE_OV_CTRL,"
bitfld.long 0x0C 31. "POK_VDD_CORE_OV_CTRL_HYST_EN,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x0C 7. "POK_VDD_CORE_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x0C 0.--6. 1. "POK_VDD_CORE_OV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x10 "CFG0_POK_VDDR_CORE_UV_CTRL,"
bitfld.long 0x10 31. "POK_VDDR_CORE_UV_CTRL_HYST_EN,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x10 7. "POK_VDDR_CORE_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x10 0.--6. 1. "POK_VDDR_CORE_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x14 "CFG0_POK_VDDR_CORE_OV_CTRL,"
bitfld.long 0x14 31. "POK_VDDR_CORE_OV_CTRL_HYST_EN,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x14 7. "POK_VDDR_CORE_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x14 0.--6. 1. "POK_VDDR_CORE_OV_CTRL_POK_TRIM,POK Trim Bits"
group.long 0x18138++0x1F
line.long 0x00 "CFG0_POK_VMON_CAP_MCU_GENERAL_UV_CTRL,"
bitfld.long 0x00 31. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_HYST_EN,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x00 7. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x00 0.--6. 1. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x04 "CFG0_POK_VMON_CAP_MCU_GENERAL_OV_CTRL,"
bitfld.long 0x04 31. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_HYST_EN,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x04 7. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x04 0.--6. 1. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x08 "CFG0_POK_VDDSHV_MAIN_1P8_UV_CTRL,"
bitfld.long 0x08 31. "POK_VDDSHV_MAIN_1P8_UV_CTRL_HYST_EN,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x08 7. "POK_VDDSHV_MAIN_1P8_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x08 0.--6. 1. "POK_VDDSHV_MAIN_1P8_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x0C "CFG0_POK_VDDSHV_MAIN_1P8_OV_CTRL,"
bitfld.long 0x0C 31. "POK_VDDSHV_MAIN_1P8_OV_CTRL_HYST_EN,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x0C 7. "POK_VDDSHV_MAIN_1P8_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x0C 0.--6. 1. "POK_VDDSHV_MAIN_1P8_OV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x10 "CFG0_POK_VDDSHV_MAIN_3P3_UV_CTRL,"
bitfld.long 0x10 31. "POK_VDDSHV_MAIN_3P3_UV_CTRL_HYST_EN,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x10 7. "POK_VDDSHV_MAIN_3P3_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
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hexmask.long.byte 0x10 0.--6. 1. "POK_VDDSHV_MAIN_3P3_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x14 "CFG0_POK_VDDSHV_MAIN_3P3_OV_CTRL,"
bitfld.long 0x14 31. "POK_VDDSHV_MAIN_3P3_OV_CTRL_HYST_EN,Activate POK hysteresis" "0,1"
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bitfld.long 0x14 7. "POK_VDDSHV_MAIN_3P3_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x14 0.--6. 1. "POK_VDDSHV_MAIN_3P3_OV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x18 "CFG0_POK_VDDS_DDRIO_UV_CTRL,"
bitfld.long 0x18 31. "POK_VDDS_DDRIO_UV_CTRL_HYST_EN,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x18 7. "POK_VDDS_DDRIO_UV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x18 0.--6. 1. "POK_VDDS_DDRIO_UV_CTRL_POK_TRIM,POK Trim Bits"
line.long 0x1C "CFG0_POK_VDDS_DDRIO_OV_CTRL,"
bitfld.long 0x1C 31. "POK_VDDS_DDRIO_OV_CTRL_HYST_EN,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x1C 7. "POK_VDDS_DDRIO_OV_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
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hexmask.long.byte 0x1C 0.--6. 1. "POK_VDDS_DDRIO_OV_CTRL_POK_TRIM,POK Trim Bits"
group.long 0x18160++0x03
line.long 0x00 "CFG0_POK_VDDA_PMIC_IN_CTRL,"
bitfld.long 0x00 31. "POK_VDDA_PMIC_IN_CTRL_HYST_EN,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x00 15. "POK_VDDA_PMIC_IN_CTRL_OVER_VOLT_DET,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
group.long 0x18170++0x13
line.long 0x00 "CFG0_RST_CTRL,"
bitfld.long 0x00 22. "RST_CTRL_DM_WDT_RST_EN_Z,Deactivate Reset from DM WDT propogating to MCU domain" "Activated,Deactivated"
newline
bitfld.long 0x00 18. "RST_CTRL_MCU_RESET_ISO_DONE_Z,MCU can set this bit to block warm reset in the main domain which is useful when the MCU may be accessing main domain resources (peripherals memory..)" "Reset of Main Domain is not Blocked by MCU Domain,Reset of Main Domain is Blocked by MCU Domain"
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bitfld.long 0x00 17. "RST_CTRL_MCU_ESM_ERROR_RST_EN_Z,Deactivate Reset of MCU by ESM" "Activated,Deactivated"
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bitfld.long 0x00 16. "RST_CTRL_SMS_COLD_RESET_EN_Z,Deactivate Reset of MCU by SMS" "Activated,Deactivated"
newline
bitfld.long 0x00 8.--11. "RST_CTRL_SW_MCU_WARMRST,This is a fault tolerant bitfield" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "RST_CTRL_SW_MAIN_POR,This is a fault tolerant bitfield" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "RST_CTRL_SW_MAIN_WARMRST,This is a fault tolerant bitfield" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CFG0_RST_STAT,"
bitfld.long 0x04 0. "RST_STAT_MAIN_RESETSTATZ,Status of Main Domain Reset" "Reset Asserted,Reset Deasserted"
line.long 0x08 "CFG0_RST_SRC,"
bitfld.long 0x08 31. "RST_SRC_SAFETY_ERROR,Reset Caused by MCU ESM Error" "0,1"
newline
bitfld.long 0x08 30. "RST_SRC_MAIN_ESM_ERROR,Reset Caused by Main ESM Error" "0,1"
newline
bitfld.long 0x08 25. "RST_SRC_SW_MAIN_POR_FROM_MAIN,Software Main Power On Reset From MAIN CTRL MMR" "0,1"
newline
bitfld.long 0x08 24. "RST_SRC_SW_MAIN_POR_FROM_MCU,Software Main Power On Reset From MCU CTRL MMR" "0,1"
newline
bitfld.long 0x08 23. "RST_SRC_DS_MAIN_PORZ,Reset of Main/Wkup Domains while in Deep Sleep as a result of an MCU Warm Reset" "0,1"
newline
bitfld.long 0x08 22. "RST_SRC_DM_WDT_RST,Watchdog Initiated Reset" "0,1"
newline
bitfld.long 0x08 21. "RST_SRC_SW_MAIN_WARMRST_FROM_MAIN,Software Main Warm Reset from MAIN CTRL MMR" "0,1"
newline
bitfld.long 0x08 20. "RST_SRC_SW_MAIN_WARMRST_FROM_MCU,Software Main Warm Reset From MCU CTRL MMR" "0,1"
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bitfld.long 0x08 16. "RST_SRC_SW_MCU_WARMRST,Software Warm Reset" "0,1"
newline
bitfld.long 0x08 13. "RST_SRC_WARM_OUT_RST,SMS Warm Reset" "0,1"
newline
bitfld.long 0x08 12. "RST_SRC_COLD_OUT_RST,SMS Cold Reset" "0,1"
newline
bitfld.long 0x08 8. "RST_SRC_DEBUG_RST,Debug Subsystem Initiated Reset" "0,1"
newline
bitfld.long 0x08 4. "RST_SRC_THERMAL_RST,Thermal Reset" "0,1"
newline
bitfld.long 0x08 2. "RST_SRC_MAIN_RESET_REQ,Main Reset Pin" "0,1"
newline
bitfld.long 0x08 0. "RST_SRC_MCU_RESET_PIN,Rest Caused by MCU Reset Pin" "0,1"
line.long 0x0C "CFG0_RST_MAGIC_WORD,"
line.long 0x10 "CFG0_ISO_CTRL,"
bitfld.long 0x10 1. "ISO_CTRL_MCU_DBG_ISO_EN,Isolates the MCU domain from Debug Field values (others are reserved)" "M4FSS is not debug isolated,M4FSS is isolated from debug if RST_MAGIC_WORD.."
newline
bitfld.long 0x10 0. "ISO_CTRL_MCU_RST_ISO_EN,Isolates the MCU domain from Warm Reset initiated by Main Field values (others are reserved)" "M4FSS is not reset isolated,M4FSS is isolated from main warm reset if.."
group.long 0x18190++0x03
line.long 0x00 "CFG0_VDD_CORE_GLDTC_CTRL,"
bitfld.long 0x00 31. "VDD_CORE_GLDTC_CTRL_PWDB,Power down - active low" "Deactivate all functions,Activate glitch detectors"
newline
bitfld.long 0x00 30. "VDD_CORE_GLDTC_CTRL_RSTB,Reset - active low" "Reset glitch detector flags,Glitch detection flags are activated"
newline
bitfld.long 0x00 16.--18. "VDD_CORE_GLDTC_CTRL_LP_FILTER_SEL,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--13. "VDD_CORE_GLDTC_CTRL_THRESH_HI_SEL,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "VDD_CORE_GLDTC_CTRL_THRESH_LO_SEL,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x181B0++0x03
line.long 0x00 "CFG0_VDD_CORE_GLDTC_STAT,"
bitfld.long 0x00 8. "VDD_CORE_GLDTC_STAT_THRESH_HI_FLAG,High voltage flag" "No high voltage detected,Voltage above the high voltage threshold was.."
newline
bitfld.long 0x00 0. "VDD_CORE_GLDTC_STAT_THRESH_LOW_FLAG,Low voltage flag" "No low voltage detected,Voltage below the low voltage threshold was.."
group.long 0x18200++0x03
line.long 0x00 "CFG0_PRG_PP_0_CTRL,"
bitfld.long 0x00 16.--17. "PRG_PP_0_CTRL_DEGLITCH_SEL,Deglitch period for PRG_PP0 POKs" "0,1,2,3"
newline
bitfld.long 0x00 15. "PRG_PP_0_CTRL_POK_EN_SEL,Select POK activate source" "POK activates come from hardware tie-offs,POK activates come from PRG_PP0_CTRL register"
newline
bitfld.long 0x00 4. "PRG_PP_0_CTRL_POK_VDDA_PMIC_IN_UV_EN,Activate VDDA_PMIC_IN undervoltage POK detection" "POK detection deactivated,POK detection activated"
newline
bitfld.long 0x00 3. "PRG_PP_0_CTRL_POK_VDD_MCU_OV_EN,Activate VDD_MCU overvoltage POK detection" "POK detection deactivated,POK detection activated"
newline
bitfld.long 0x00 2. "PRG_PP_0_CTRL_POK_VDD_MCU_UV_EN,Activate VDD_MCU undervoltage POK detection" "POK detection deactivated,POK detection activated"
newline
bitfld.long 0x00 1. "PRG_PP_0_CTRL_POK_VDDA_MCU_OV_EN,Activate 1.8V VDDA_MCU overvoltage POK detection" "POK detection deactivated,POK detection activated"
newline
bitfld.long 0x00 0. "PRG_PP_0_CTRL_POK_VDDA_MCU_UV_EN,Activate 1.8V VDDA_MCU undervoltage POK detection" "POK detection deactivated,POK detection activated"
group.long 0x18208++0x03
line.long 0x00 "CFG0_PRG_PP_1_CTRL,"
bitfld.long 0x00 19. "PRG_PP_1_CTRL_POK_PP_EN,POK ping-pong activate" "No pingpong operation,Pingpong operation activated"
newline
bitfld.long 0x00 16.--17. "PRG_PP_1_CTRL_DEGLITCH_SEL,Deglitch period for PRG_PP1 POKs" "0,1,2,3"
newline
bitfld.long 0x00 15. "PRG_PP_1_CTRL_POK_EN_SEL,Select POK activate source" "POK activates come from hardware tie-offs,POK activates come from PRG_PP1_CTRL register"
newline
bitfld.long 0x00 14. "PRG_PP_1_CTRL_POK_VDDS_DDRIO_OV_SEL,POK_VDDS_DDRIO mode" "Undervoltage (pok_pp_en = 0) Ping-Pong..,Overvoltage (pok_pp_en = x)"
newline
bitfld.long 0x00 13. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_OV_SEL,POK_VDDSHV_MAIN_3P3 mode" "Undervoltage (pok_pp_en = 0) Ping-Pong..,Overvoltage (pok_pp_en = x)"
newline
bitfld.long 0x00 12. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_OV_SEL,POK_VDDSHV_MAIN_1P8 mode" "Undervoltage (pok_pp_en = 0) Ping-Pong..,Overvoltage (pok_pp_en = x)"
newline
bitfld.long 0x00 11. "PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_OV_SEL,POK_VMON_CAP_MCU_GENERAL mode" "Undervoltage (pok_pp_en = 0) Ping-Pong..,Overvoltage (pok_pp_en = x)"
newline
bitfld.long 0x00 8. "PRG_PP_1_CTRL_POK_VDDR_CORE_OV_SEL,POK_VDDR_CORE Mode" "Undervoltage (pok_pp_en = 0) Ping-Pong..,Overvoltage (pok_pp_en = x)"
newline
bitfld.long 0x00 6. "PRG_PP_1_CTRL_POK_VDDS_DDRIO_EN,Activate POK_VDDS_DDRIO (if pok_en_sel =" "POK Detection Deactivated,POK Detection Activated"
newline
bitfld.long 0x00 5. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_EN,Activate POK_VDDSHV_MAIN_3P3 (if pok_en_sel =" "POK Detection Deactivated,POK Detection Activated"
newline
bitfld.long 0x00 4. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_EN,Activate POK_VDDSHV_MAIN_1P8 (if pok_en_sel =" "POK Detection Deactivated,POK Detection Activated"
newline
bitfld.long 0x00 3. "PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_EN,Activate POK_VMON_CAP_MCU_GENERAL (if pok_en_sel =" "POK Detection Deactivated,POK Detection Activated"
newline
bitfld.long 0x00 0. "PRG_PP_1_CTRL_POK_VDDR_CORE_EN,Activate POK_VDDR_CORE (if pok_en_sel =" "POK Detection Deactivated,POK Detection Activated"
group.long 0x18280++0x03
line.long 0x00 "CFG0_CLKGATE_CTRL,"
bitfld.long 0x00 2. "CLKGATE_CTRL_MCUSS_NOGATE,MCU Subsystem clock gate deactivate" "Clocks are gated on idle for power savings,Clocks are not gated on idle power saving.."
newline
bitfld.long 0x00 1. "CLKGATE_CTRL_MCU_CBA_NOGATE,MCU domain Data bus (mcu_cbass) clock gate deactivate" "Clocks are gated on idle for power savings,Clocks are not gated on idle power saving.."
newline
bitfld.long 0x00 0. "CLKGATE_CTRL_WKUP_SAFE_CBA_NOGATE,WKUP domain Infrastructure bus (wkup_safe_cbass) clock gate deactivate" "Clocks are gated on idle for power savings,Clocks are not gated on idle power saving.."
group.long 0x18300++0x03
line.long 0x00 "CFG0_LVDS_BANDGAP_CTRL,"
hexmask.long.byte 0x00 0.--7. 1. "LVDS_BANDGAP_CTRL_BGAPC,Bandgap Flip and Center Trim Setting"
group.long 0x19008++0x07
line.long 0x00 "CFG0_LOCK6_KICK0,"
line.long 0x04 "CFG0_LOCK6_KICK1,"
rgroup.long 0x19100++0x1B
line.long 0x00 "CFG0_CLAIMREG_P6_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P6_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P6_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P6_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P6_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P6_R5_READONLY,"
line.long 0x18 "CFG0_CLAIMREG_P6_R6_READONLY,"
group.long 0x1A000++0x07
line.long 0x00 "CFG0_POR_CTRL_PROXY,"
bitfld.long 0x00 29. "POR_CTRL_OVRD_SET5_PROXY,Reserved override set" "0,1"
newline
bitfld.long 0x00 28. "POR_CTRL_OVRD_SET4_PROXY,POKLVB override set" "0,1"
newline
bitfld.long 0x00 27. "POR_CTRL_OVRD_SET3_PROXY,POKLVA override set" "0,1"
newline
bitfld.long 0x00 26. "POR_CTRL_OVRD_SET2_PROXY,POKHV override set" "0,1"
newline
bitfld.long 0x00 25. "POR_CTRL_OVRD_SET1_PROXY,BGOK override set" "0,1"
newline
bitfld.long 0x00 24. "POR_CTRL_OVRD_SET0_PROXY,PORHV override set" "0,1"
newline
bitfld.long 0x00 21. "POR_CTRL_OVRD5_PROXY,Reserved override activate" "0,1"
newline
bitfld.long 0x00 20. "POR_CTRL_OVRD4_PROXY,POKLVB override activate" "0,1"
newline
bitfld.long 0x00 19. "POR_CTRL_OVRD3_PROXY,POKLVA override activate" "0,1"
newline
bitfld.long 0x00 18. "POR_CTRL_OVRD2_PROXY,POKHV override activate" "0,1"
newline
bitfld.long 0x00 17. "POR_CTRL_OVRD1_PROXY,BGOK override activate" "0,1"
newline
bitfld.long 0x00 16. "POR_CTRL_OVRD0_PROXY,PORHV override activate" "0,1"
newline
bitfld.long 0x00 7. "POR_CTRL_TRIM_SEL_PROXY,POR Trim Select" "Trim selections for Bandgap and POKs come from..,Trim selections for Bandgap and POKs come from.."
newline
bitfld.long 0x00 4. "POR_CTRL_MASK_HHV_PROXY,Mask HHV/SOC_PORz outputs when applying new trim values" "0,1"
line.long 0x04 "CFG0_POR_STAT_PROXY,"
bitfld.long 0x04 8. "POR_STAT_BGOK_PROXY,Bandgap OK status" "0,1"
newline
bitfld.long 0x04 4. "POR_STAT_SOC_POR_PROXY,POR module status" "Module is in functional mode,Module is in reset mode"
group.long 0x1A100++0x03
line.long 0x00 "CFG0_POR_BANDGAP_CTRL_PROXY,"
bitfld.long 0x00 16.--19. "POR_BANDGAP_CTRL_BGAPI_PROXY,Bandgap output current trim bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 8.--15. 1. "POR_BANDGAP_CTRL_BGAPV_PROXY,Bandgap output voltage magnitude trim bits"
newline
hexmask.long.byte 0x00 0.--7. 1. "POR_BANDGAP_CTRL_BGAPC_PROXY,Bandgap slope trim bits"
group.long 0x1A110++0x17
line.long 0x00 "CFG0_POK_VDDA_MCU_UV_CTRL_PROXY,"
bitfld.long 0x00 31. "POK_VDDA_MCU_UV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x00 7. "POK_VDDA_MCU_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x00 0.--6. 1. "POK_VDDA_MCU_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x04 "CFG0_POK_VDDA_MCU_OV_CTRL_PROXY,"
bitfld.long 0x04 31. "POK_VDDA_MCU_OV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x04 7. "POK_VDDA_MCU_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x04 0.--6. 1. "POK_VDDA_MCU_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x08 "CFG0_POK_VDD_CORE_UV_CTRL_PROXY,"
bitfld.long 0x08 31. "POK_VDD_CORE_UV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x08 7. "POK_VDD_CORE_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x08 0.--6. 1. "POK_VDD_CORE_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x0C "CFG0_POK_VDD_CORE_OV_CTRL_PROXY,"
bitfld.long 0x0C 31. "POK_VDD_CORE_OV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x0C 7. "POK_VDD_CORE_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x0C 0.--6. 1. "POK_VDD_CORE_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x10 "CFG0_POK_VDDR_CORE_UV_CTRL_PROXY,"
bitfld.long 0x10 31. "POK_VDDR_CORE_UV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x10 7. "POK_VDDR_CORE_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x10 0.--6. 1. "POK_VDDR_CORE_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x14 "CFG0_POK_VDDR_CORE_OV_CTRL_PROXY,"
bitfld.long 0x14 31. "POK_VDDR_CORE_OV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x14 7. "POK_VDDR_CORE_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x14 0.--6. 1. "POK_VDDR_CORE_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
group.long 0x1A138++0x1F
line.long 0x00 "CFG0_POK_VMON_CAP_MCU_GENERAL_UV_CTRL_PROXY,"
bitfld.long 0x00 31. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x00 7. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x00 0.--6. 1. "POK_VMON_CAP_MCU_GENERAL_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x04 "CFG0_POK_VMON_CAP_MCU_GENERAL_OV_CTRL_PROXY,"
bitfld.long 0x04 31. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x04 7. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x04 0.--6. 1. "POK_VMON_CAP_MCU_GENERAL_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x08 "CFG0_POK_VDDSHV_MAIN_1P8_UV_CTRL_PROXY,"
bitfld.long 0x08 31. "POK_VDDSHV_MAIN_1P8_UV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x08 7. "POK_VDDSHV_MAIN_1P8_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x08 0.--6. 1. "POK_VDDSHV_MAIN_1P8_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x0C "CFG0_POK_VDDSHV_MAIN_1P8_OV_CTRL_PROXY,"
bitfld.long 0x0C 31. "POK_VDDSHV_MAIN_1P8_OV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x0C 7. "POK_VDDSHV_MAIN_1P8_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x0C 0.--6. 1. "POK_VDDSHV_MAIN_1P8_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x10 "CFG0_POK_VDDSHV_MAIN_3P3_UV_CTRL_PROXY,"
bitfld.long 0x10 31. "POK_VDDSHV_MAIN_3P3_UV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x10 7. "POK_VDDSHV_MAIN_3P3_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x10 0.--6. 1. "POK_VDDSHV_MAIN_3P3_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x14 "CFG0_POK_VDDSHV_MAIN_3P3_OV_CTRL_PROXY,"
bitfld.long 0x14 31. "POK_VDDSHV_MAIN_3P3_OV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x14 7. "POK_VDDSHV_MAIN_3P3_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x14 0.--6. 1. "POK_VDDSHV_MAIN_3P3_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x18 "CFG0_POK_VDDS_DDRIO_UV_CTRL_PROXY,"
bitfld.long 0x18 31. "POK_VDDS_DDRIO_UV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x18 7. "POK_VDDS_DDRIO_UV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x18 0.--6. 1. "POK_VDDS_DDRIO_UV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
line.long 0x1C "CFG0_POK_VDDS_DDRIO_OV_CTRL_PROXY,"
bitfld.long 0x1C 31. "POK_VDDS_DDRIO_OV_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x1C 7. "POK_VDDS_DDRIO_OV_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
newline
hexmask.long.byte 0x1C 0.--6. 1. "POK_VDDS_DDRIO_OV_CTRL_POK_TRIM_PROXY,POK Trim Bits"
group.long 0x1A160++0x03
line.long 0x00 "CFG0_POK_VDDA_PMIC_IN_CTRL_PROXY,"
bitfld.long 0x00 31. "POK_VDDA_PMIC_IN_CTRL_HYST_EN_PROXY,Activate POK hysteresis" "0,1"
newline
bitfld.long 0x00 15. "POK_VDDA_PMIC_IN_CTRL_OVER_VOLT_DET_PROXY,Over / under voltage detection mode" "Under voltage detection,Over voltage detection"
group.long 0x1A170++0x13
line.long 0x00 "CFG0_RST_CTRL_PROXY,"
bitfld.long 0x00 22. "RST_CTRL_DM_WDT_RST_EN_Z_PROXY,Deactivate Reset from DM WDT propogating to MCU domain" "Activated,Deactivated"
newline
bitfld.long 0x00 18. "RST_CTRL_MCU_RESET_ISO_DONE_Z_PROXY,MCU can set this bit to block warm reset in the main domain which is useful when the MCU may be accessing main domain resources (peripherals memory..)" "Reset of Main Domain is not Blocked by MCU Domain,Reset of Main Domain is Blocked by MCU Domain"
newline
bitfld.long 0x00 17. "RST_CTRL_MCU_ESM_ERROR_RST_EN_Z_PROXY,Deactivate Reset of MCU by ESM" "Activated,Deactivated"
newline
bitfld.long 0x00 16. "RST_CTRL_SMS_COLD_RESET_EN_Z_PROXY,Deactivate Reset of MCU by SMS" "Activated,Deactivated"
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bitfld.long 0x00 8.--11. "RST_CTRL_SW_MCU_WARMRST_PROXY,This is a fault tolerant bitfield" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "RST_CTRL_SW_MAIN_POR_PROXY,This is a fault tolerant bitfield" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "RST_CTRL_SW_MAIN_WARMRST_PROXY,This is a fault tolerant bitfield" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CFG0_RST_STAT_PROXY,"
bitfld.long 0x04 0. "RST_STAT_MAIN_RESETSTATZ_PROXY,Status of Main Domain Reset" "Reset Asserted,Reset Deasserted"
line.long 0x08 "CFG0_RST_SRC_PROXY,"
bitfld.long 0x08 31. "RST_SRC_SAFETY_ERROR_PROXY,Reset Caused by MCU ESM Error" "0,1"
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bitfld.long 0x08 30. "RST_SRC_MAIN_ESM_ERROR_PROXY,Reset Caused by Main ESM Error" "0,1"
newline
bitfld.long 0x08 25. "RST_SRC_SW_MAIN_POR_FROM_MAIN_PROXY,Software Main Power On Reset From MAIN CTRL MMR" "0,1"
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bitfld.long 0x08 24. "RST_SRC_SW_MAIN_POR_FROM_MCU_PROXY,Software Main Power On Reset From MCU CTRL MMR" "0,1"
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bitfld.long 0x08 23. "RST_SRC_DS_MAIN_PORZ_PROXY,Reset of Main/Wkup Domains while in Deep Sleep as a result of an MCU Warm Reset" "0,1"
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bitfld.long 0x08 22. "RST_SRC_DM_WDT_RST_PROXY,Watchdog Initiated Reset" "0,1"
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bitfld.long 0x08 21. "RST_SRC_SW_MAIN_WARMRST_FROM_MAIN_PROXY,Software Main Warm Reset from MAIN CTRL MMR" "0,1"
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bitfld.long 0x08 20. "RST_SRC_SW_MAIN_WARMRST_FROM_MCU_PROXY,Software Main Warm Reset From MCU CTRL MMR" "0,1"
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bitfld.long 0x08 16. "RST_SRC_SW_MCU_WARMRST_PROXY,Software Warm Reset" "0,1"
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bitfld.long 0x08 13. "RST_SRC_WARM_OUT_RST_PROXY,SMS Warm Reset" "0,1"
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bitfld.long 0x08 12. "RST_SRC_COLD_OUT_RST_PROXY,SMS Cold Reset" "0,1"
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bitfld.long 0x08 8. "RST_SRC_DEBUG_RST_PROXY,Debug Subsystem Initiated Reset" "0,1"
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bitfld.long 0x08 4. "RST_SRC_THERMAL_RST_PROXY,Thermal Reset" "0,1"
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bitfld.long 0x08 2. "RST_SRC_MAIN_RESET_REQ_PROXY,Main Reset Pin" "0,1"
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bitfld.long 0x08 0. "RST_SRC_MCU_RESET_PIN_PROXY,Rest Caused by MCU Reset Pin" "0,1"
line.long 0x0C "CFG0_RST_MAGIC_WORD_PROXY,"
line.long 0x10 "CFG0_ISO_CTRL_PROXY,"
bitfld.long 0x10 1. "ISO_CTRL_MCU_DBG_ISO_EN_PROXY,Isolates the MCU domain from Debug Field values (others are reserved)" "M4FSS is not debug isolated,M4FSS is isolated from debug if RST_MAGIC_WORD.."
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bitfld.long 0x10 0. "ISO_CTRL_MCU_RST_ISO_EN_PROXY,Isolates the MCU domain from Warm Reset initiated by Main Field values (others are reserved)" "M4FSS is not reset isolated,M4FSS is isolated from main warm reset if.."
group.long 0x1A190++0x03
line.long 0x00 "CFG0_VDD_CORE_GLDTC_CTRL_PROXY,"
bitfld.long 0x00 31. "VDD_CORE_GLDTC_CTRL_PWDB_PROXY,Power down - active low" "Deactivate all functions,Activate glitch detectors"
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bitfld.long 0x00 30. "VDD_CORE_GLDTC_CTRL_RSTB_PROXY,Reset - active low" "Reset glitch detector flags,Glitch detection flags are activated"
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bitfld.long 0x00 16.--18. "VDD_CORE_GLDTC_CTRL_LP_FILTER_SEL_PROXY,Selects the glitch detect low-pass filter bandwidth Field values (others are reserved)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--13. "VDD_CORE_GLDTC_CTRL_THRESH_HI_SEL_PROXY,Selects the high voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 0.--5. "VDD_CORE_GLDTC_CTRL_THRESH_LO_SEL_PROXY,Selects the low voltage glitch threshold as a percentage of the monitored voltage Field values (others are reserved)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x1A1B0++0x03
line.long 0x00 "CFG0_VDD_CORE_GLDTC_STAT_PROXY,"
bitfld.long 0x00 8. "VDD_CORE_GLDTC_STAT_THRESH_HI_FLAG_PROXY,High voltage flag" "No high voltage detected,Voltage above the high voltage threshold was.."
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bitfld.long 0x00 0. "VDD_CORE_GLDTC_STAT_THRESH_LOW_FLAG_PROXY,Low voltage flag" "No low voltage detected,Voltage below the low voltage threshold was.."
group.long 0x1A200++0x03
line.long 0x00 "CFG0_PRG_PP_0_CTRL_PROXY,"
bitfld.long 0x00 16.--17. "PRG_PP_0_CTRL_DEGLITCH_SEL_PROXY,Deglitch period for PRG_PP0 POKs" "0,1,2,3"
newline
bitfld.long 0x00 15. "PRG_PP_0_CTRL_POK_EN_SEL_PROXY,Select POK activate source" "POK activates come from hardware tie-offs,POK activates come from PRG_PP0_CTRL register"
newline
bitfld.long 0x00 4. "PRG_PP_0_CTRL_POK_VDDA_PMIC_IN_UV_EN_PROXY,Activate VDDA_PMIC_IN undervoltage POK detection" "POK detection deactivated,POK detection activated"
newline
bitfld.long 0x00 3. "PRG_PP_0_CTRL_POK_VDD_MCU_OV_EN_PROXY,Activate VDD_MCU overvoltage POK detection" "POK detection deactivated,POK detection activated"
newline
bitfld.long 0x00 2. "PRG_PP_0_CTRL_POK_VDD_MCU_UV_EN_PROXY,Activate VDD_MCU undervoltage POK detection" "POK detection deactivated,POK detection activated"
newline
bitfld.long 0x00 1. "PRG_PP_0_CTRL_POK_VDDA_MCU_OV_EN_PROXY,Activate 1.8V VDDA_MCU overvoltage POK detection" "POK detection deactivated,POK detection activated"
newline
bitfld.long 0x00 0. "PRG_PP_0_CTRL_POK_VDDA_MCU_UV_EN_PROXY,Activate 1.8V VDDA_MCU undervoltage POK detection" "POK detection deactivated,POK detection activated"
group.long 0x1A208++0x03
line.long 0x00 "CFG0_PRG_PP_1_CTRL_PROXY,"
bitfld.long 0x00 19. "PRG_PP_1_CTRL_POK_PP_EN_PROXY,POK ping-pong activate" "No pingpong operation,Pingpong operation activated"
newline
bitfld.long 0x00 16.--17. "PRG_PP_1_CTRL_DEGLITCH_SEL_PROXY,Deglitch period for PRG_PP1 POKs" "0,1,2,3"
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bitfld.long 0x00 15. "PRG_PP_1_CTRL_POK_EN_SEL_PROXY,Select POK activate source" "POK activates come from hardware tie-offs,POK activates come from PRG_PP1_CTRL register"
newline
bitfld.long 0x00 14. "PRG_PP_1_CTRL_POK_VDDS_DDRIO_OV_SEL_PROXY,POK_VDDS_DDRIO mode" "Undervoltage (pok_pp_en = 0) Ping-Pong..,Overvoltage (pok_pp_en = x)"
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bitfld.long 0x00 13. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_OV_SEL_PROXY,POK_VDDSHV_MAIN_3P3 mode" "Undervoltage (pok_pp_en = 0) Ping-Pong..,Overvoltage (pok_pp_en = x)"
newline
bitfld.long 0x00 12. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_OV_SEL_PROXY,POK_VDDSHV_MAIN_1P8 mode" "Undervoltage (pok_pp_en = 0) Ping-Pong..,Overvoltage (pok_pp_en = x)"
newline
bitfld.long 0x00 11. "PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_OV_SEL_PROXY,POK_VMON_CAP_MCU_GENERAL mode" "Undervoltage (pok_pp_en = 0) Ping-Pong..,Overvoltage (pok_pp_en = x)"
newline
bitfld.long 0x00 8. "PRG_PP_1_CTRL_POK_VDDR_CORE_OV_SEL_PROXY,POK_VDDR_CORE Mode" "Undervoltage (pok_pp_en = 0) Ping-Pong..,Overvoltage (pok_pp_en = x)"
newline
bitfld.long 0x00 6. "PRG_PP_1_CTRL_POK_VDDS_DDRIO_EN_PROXY,Activate POK_VDDS_DDRIO (if pok_en_sel =" "POK Detection Deactivated,POK Detection Activated"
newline
bitfld.long 0x00 5. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_3P3_EN_PROXY,Activate POK_VDDSHV_MAIN_3P3 (if pok_en_sel =" "POK Detection Deactivated,POK Detection Activated"
newline
bitfld.long 0x00 4. "PRG_PP_1_CTRL_POK_VDDSHV_MAIN_1P8_EN_PROXY,Activate POK_VDDSHV_MAIN_1P8 (if pok_en_sel =" "POK Detection Deactivated,POK Detection Activated"
newline
bitfld.long 0x00 3. "PRG_PP_1_CTRL_POK_VMON_CAP_MCU_GENERAL_EN_PROXY,Activate POK_VMON_CAP_MCU_GENERAL (if pok_en_sel =" "POK Detection Deactivated,POK Detection Activated"
newline
bitfld.long 0x00 0. "PRG_PP_1_CTRL_POK_VDDR_CORE_EN_PROXY,Activate POK_VDDR_CORE (if pok_en_sel =" "POK Detection Deactivated,POK Detection Activated"
group.long 0x1A280++0x03
line.long 0x00 "CFG0_CLKGATE_CTRL_PROXY,"
bitfld.long 0x00 2. "CLKGATE_CTRL_MCUSS_NOGATE_PROXY,MCU Subsystem clock gate deactivate" "Clocks are gated on idle for power savings,Clocks are not gated on idle power saving.."
newline
bitfld.long 0x00 1. "CLKGATE_CTRL_MCU_CBA_NOGATE_PROXY,MCU domain Data bus (mcu_cbass) clock gate deactivate" "Clocks are gated on idle for power savings,Clocks are not gated on idle power saving.."
newline
bitfld.long 0x00 0. "CLKGATE_CTRL_WKUP_SAFE_CBA_NOGATE_PROXY,WKUP domain Infrastructure bus (wkup_safe_cbass) clock gate deactivate" "Clocks are gated on idle for power savings,Clocks are not gated on idle power saving.."
group.long 0x1A300++0x03
line.long 0x00 "CFG0_LVDS_BANDGAP_CTRL_PROXY,"
hexmask.long.byte 0x00 0.--7. 1. "LVDS_BANDGAP_CTRL_BGAPC_PROXY,Bandgap Flip and Center Trim Setting"
group.long 0x1B008++0x07
line.long 0x00 "CFG0_LOCK6_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK6_KICK1_PROXY,"
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x1B100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P6_R$1,"
repeat.end
tree.end
tree "WKUP_ESM0_CFG"
base ad:0x4100000
rgroup.long 0x00++0x33
line.long 0x00 "CFG_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_INFO,The Info Register gives the configuration Inforrmation of this ESM"
bitfld.long 0x04 31. "LAST_RESET,Indicates the Source of the last Reset" "0,1"
hexmask.long.byte 0x04 8.--15. 1. "PULSE_GROUPS,Number of Pulse Error Groups"
hexmask.long.byte 0x04 0.--7. 1. "GROUPS,Total number of Error Groups"
line.long 0x08 "CFG_EN,The Global Enable Register has the master interrupt mask"
bitfld.long 0x08 0.--3. "KEY,Global Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CFG_SFT_RST,The Global Soft Reset Register controls the global clear for raw status and enables"
bitfld.long 0x0C 0.--3. "KEY,Global Soft Reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CFG_ERR_RAW,Raw Status/Set Register for Configuration Errors"
bitfld.long 0x10 0.--2. "STS,This is the raw status for config errors" "0,1,2,3,4,5,6,7"
line.long 0x14 "CFG_ERR_STS,Config Error Enable and Clear Register"
bitfld.long 0x14 0.--2. "MSK,This is the masked status/clear for config errors" "0,1,2,3,4,5,6,7"
line.long 0x18 "CFG_ERR_EN_SET,Config Error Enable Set Register"
bitfld.long 0x18 0.--2. "MSK,This is the mask enable set for config errors" "0,1,2,3,4,5,6,7"
line.long 0x1C "CFG_ERR_EN_CLR,Config Error Interrupt Enabled Clear register"
bitfld.long 0x1C 0.--2. "MSK,This is the mask enable clear for config errors" "0,1,2,3,4,5,6,7"
line.long 0x20 "CFG_LOW_PRI,Shows which is the highest priority outstanding low priority interrupt"
hexmask.long.word 0x20 16.--31. 1. "PLS,This is the highest priority outstanding low priority pulse interrupt"
hexmask.long.word 0x20 0.--15. 1. "LVL,This is the highest priority outstanding low priority level interrupt"
line.long 0x24 "CFG_HI_PRI,Shows which is the highest priority outstanding high priority interrupt"
hexmask.long.word 0x24 16.--31. 1. "PLS,This is the highest priority outstanding high priority pulse interrupt"
hexmask.long.word 0x24 0.--15. 1. "LVL,This is the highest priority outstanding high priority level interrupt"
line.long 0x28 "CFG_LOW,Shows which groups have oustanding low priority interrupts"
line.long 0x2C "CFG_HI,Shows which groups have oustanding high priority interrupts"
line.long 0x30 "CFG_EOI,End of Interrupt Register"
hexmask.long.word 0x30 0.--10. 1. "KEY,This is the interrupt being serviced"
group.long 0x40++0x1F
line.long 0x00 "CFG_PIN_CTRL,This register controls the error_pin_n output"
bitfld.long 0x00 4.--7. "PWM_EN,PWM enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "KEY,Pin Control Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CFG_PIN_STS,This register reflects the status of the error_pin_n output"
bitfld.long 0x04 0. "VAL,Value of the error_pin_n" "0,1"
line.long 0x08 "CFG_PIN_CNTR,This register shows the current value of the error pin counter"
hexmask.long.tbyte 0x08 0.--23. 1. "COUNT,Current Counter Value"
line.long 0x0C "CFG_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error Counter"
hexmask.long.tbyte 0x0C 0.--23. 1. "COUNT,Counter Pre-Load Value"
line.long 0x10 "CFG_PWMH_PIN_CNTR,This register shows the current value of the error pin PWM high counter"
hexmask.long.tbyte 0x10 0.--23. 1. "COUNT,Current Counter Value"
line.long 0x14 "CFG_PWMH_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM High Counter"
hexmask.long.tbyte 0x14 0.--23. 1. "COUNT,Counter Pre-Load Value"
line.long 0x18 "CFG_PWML_PIN_CNTR,This register shows the current value of the error pin PWM low counter"
hexmask.long.tbyte 0x18 0.--23. 1. "COUNT,Current Counter Value"
line.long 0x1C "CFG_PWML_PIN_CNTR_PRE,This register contains the value that is loaded in to the Error PWM Low Counter"
hexmask.long.tbyte 0x1C 0.--23. 1. "COUNT,Counter Pre-Load Value"
tree.end
tree "WKUP_I2C0_CFG"
base ad:0x2B200000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x04 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x04 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x00 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
newline
bitfld.long 0x00 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Autoidle bit" "0,1"
group.long 0x20++0x2F
line.long 0x00 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
line.long 0x04 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x08 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x08 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x08 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x08 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x08 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x08 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x08 8. "BF,Bus Free IRQ enabled status" "0,1"
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bitfld.long 0x08 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x08 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x08 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x08 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x08 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x0C "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector"
bitfld.long 0x0C 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0C 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0C 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0C 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x0C 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0C 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0C 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0C 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x0C 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0C 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0C 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0C 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x0C 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0C 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0C 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector"
bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1"
newline
bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x14 "CFG_I2C_WE,I2C wakeup enable vector (legacy)"
bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x18 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set"
bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set"
bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x20 "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear"
bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear"
bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x28 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable"
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x2C "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable"
bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x07
line.long 0x00 "CFG_I2C_IE,I2C interrupt enable vector (legacy)"
bitfld.long 0x00 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x00 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x00 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x00 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x00 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x00 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x00 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x00 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x00 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x00 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x00 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x00 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x00 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x00 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x00 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x04 "CFG_I2C_STAT,I2C interrupt status vector (legacy)"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
rgroup.long 0x90++0x0F
line.long 0x00 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x00 0. "RDONE,Reset done bit" "0,1"
line.long 0x04 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x04 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x04 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
bitfld.long 0x04 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
newline
bitfld.long 0x04 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
bitfld.long 0x04 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x08 0.--15. 1. "DCOUNT,Data count"
line.long 0x0C "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x0C 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x33
line.long 0x00 "CFG_I2C_CON,I2C configuration register"
bitfld.long 0x00 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x00 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x00 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x00 10. "MST,Master/slave mode" "0,1"
newline
bitfld.long 0x00 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x00 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x00 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x00 6. "XOA1,Expand Own address 1" "0,1"
newline
bitfld.long 0x00 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x00 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x00 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x00 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x04 "CFG_I2C_OA,Own address register"
bitfld.long 0x04 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "OA,Own address"
line.long 0x08 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x08 0.--9. 1. "SA,Slave address"
line.long 0x0C "CFG_I2C_PSC,I2C Clock Prescaler Register"
abitfld.long 0x0C 0.--7. "PSC,Fast/Standard mode prescale sampling clock divider value" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
newline
rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
newline
bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
newline
bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
line.long 0x1C "CFG_I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x1C 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
bitfld.long 0x1C 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1C 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x20 0.--9. 1. "OA1,Own address 1"
line.long 0x24 "CFG_I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x24 0.--9. 1. "OA2,Own address 2"
line.long 0x28 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x28 0.--9. 1. "OA3,Own address 3"
line.long 0x2C "CFG_I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x2C 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x2C 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x2C 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x2C 0. "OA0_ACT,Own Address 0 active" "0,1"
line.long 0x30 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x30 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x30 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x30 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x30 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree "WKUP_MCU_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG"
base ad:0x4210000
rgroup.long 0x00++0x07
line.long 0x00 "INTR_ROUTER_CFG_PID,Identification register"
bitfld.long 0x00 30.--31. "SCHEME,scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,function"
bitfld.long 0x00 11.--15. "RTLVER,rtl version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom id" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINREV,minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "INTR_ROUTER_CFG_INTR_MUXCNTL,Interrupt mux control register"
bitfld.long 0x04 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1"
bitfld.long 0x04 0.--4. "MUX_CNTL,Mux control for interrupt N" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "WKUP_PADCFG_CTRL0_CFG0"
base ad:0x4080000
rgroup.long 0x00++0x0B
line.long 0x00 "CFG0_PID,"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16,"
newline
bitfld.long 0x00 11.--15. "PID_MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "PID_CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG0_MMR_CFG0,"
hexmask.long.word 0x04 16.--31. 1. "MMR_CFG0_CFG_REV,Major configuration release"
newline
hexmask.long.word 0x04 0.--15. 1. "MMR_CFG0_SPEC_REV,Minor spec-only revision"
line.long 0x08 "CFG0_MMR_CFG1,"
bitfld.long 0x08 31. "MMR_CFG1_PROXY_EN,Proxy addressing enabled" "0,1"
newline
hexmask.long.byte 0x08 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions"
group.long 0x1008++0x2B
line.long 0x00 "CFG0_LOCK0_KICK0,"
line.long 0x04 "CFG0_LOCK0_KICK1,"
line.long 0x08 "CFG0_intr_raw_status,"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "CFG0_intr_enabled_status_clear,"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "CFG0_intr_enable,"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "CFG0_intr_enable_clear,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "CFG0_eoi,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value"
line.long 0x1C "CFG0_fault_address,"
line.long 0x20 "CFG0_fault_type_status,"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "CFG0_fault_attr_status,"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "CFG0_fault_clear,"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
rgroup.long 0x1100++0x03
line.long 0x00 "CFG0_CLAIMREG_P0_R0_READONLY,"
rgroup.long 0x2000++0x0B
line.long 0x00 "CFG0_PID_PROXY,"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16_PROXY,"
newline
bitfld.long 0x00 11.--15. "PID_MISC_PROXY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR_PROXY," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "PID_CUSTOM_PROXY," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR_PROXY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG0_MMR_CFG0_PROXY,"
hexmask.long.word 0x04 16.--31. 1. "MMR_CFG0_CFG_REV_PROXY,Major configuration release"
newline
hexmask.long.word 0x04 0.--15. 1. "MMR_CFG0_SPEC_REV_PROXY,Minor spec-only revision"
line.long 0x08 "CFG0_MMR_CFG1_PROXY,"
bitfld.long 0x08 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing enabled" "0,1"
newline
hexmask.long.byte 0x08 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions"
group.long 0x3008++0x2B
line.long 0x00 "CFG0_LOCK0_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK0_KICK1_PROXY,"
line.long 0x08 "CFG0_intr_raw_status_PROXY,"
bitfld.long 0x08 3. "PROXY_ERR_PROXY,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR_PROXY,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR_PROXY,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR_PROXY,Protection violation error" "0,1"
line.long 0x0C "CFG0_intr_enabled_status_clear_PROXY,"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR_PROXY,Protection violation error" "0,1"
line.long 0x10 "CFG0_intr_enable_PROXY,"
bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable" "0,1"
line.long 0x14 "CFG0_intr_enable_clear_PROXY,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear" "0,1"
line.long 0x18 "CFG0_eoi_PROXY,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value"
line.long 0x1C "CFG0_fault_address_PROXY,"
line.long 0x20 "CFG0_fault_type_status_PROXY,"
bitfld.long 0x20 6. "FAULT_NS_PROXY,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE_PROXY,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "CFG0_fault_attr_status_PROXY,"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID_PROXY,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID"
line.long 0x28 "CFG0_fault_clear_PROXY,"
bitfld.long 0x28 0. "FAULT_CLR_PROXY,Fault clear" "0,1"
group.long 0x3100++0x03
line.long 0x00 "CFG0_CLAIMREG_P0_R0,"
group.long 0x4000++0x87
line.long 0x00 "CFG0_PADCONFIG0,"
bitfld.long 0x00 31. "PADCONFIG0_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x00 30. "PADCONFIG0_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x00 29. "PADCONFIG0_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x00 28. "PADCONFIG0_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x00 27. "PADCONFIG0_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x00 26. "PADCONFIG0_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x00 25. "PADCONFIG0_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x00 24. "PADCONFIG0_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x00 23. "PADCONFIG0_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x00 22. "PADCONFIG0_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x00 21. "PADCONFIG0_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x00 19.--20. "PADCONFIG0_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "PADCONFIG0_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x00 17. "PADCONFIG0_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x00 16. "PADCONFIG0_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x00 15. "PADCONFIG0_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x00 14. "PADCONFIG0_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x00 11.--13. "PADCONFIG0_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8. "PADCONFIG0_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x00 7. "PADCONFIG0_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--3. "PADCONFIG0_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x04 "CFG0_PADCONFIG1,"
bitfld.long 0x04 31. "PADCONFIG1_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x04 30. "PADCONFIG1_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x04 29. "PADCONFIG1_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x04 28. "PADCONFIG1_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x04 27. "PADCONFIG1_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x04 26. "PADCONFIG1_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x04 25. "PADCONFIG1_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x04 24. "PADCONFIG1_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x04 23. "PADCONFIG1_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x04 22. "PADCONFIG1_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x04 21. "PADCONFIG1_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x04 19.--20. "PADCONFIG1_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x04 18. "PADCONFIG1_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x04 17. "PADCONFIG1_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x04 16. "PADCONFIG1_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x04 15. "PADCONFIG1_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x04 14. "PADCONFIG1_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x04 11.--13. "PADCONFIG1_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 8. "PADCONFIG1_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x04 7. "PADCONFIG1_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x04 0.--3. "PADCONFIG1_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x08 "CFG0_PADCONFIG2,"
bitfld.long 0x08 31. "PADCONFIG2_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x08 30. "PADCONFIG2_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x08 29. "PADCONFIG2_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x08 28. "PADCONFIG2_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x08 27. "PADCONFIG2_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x08 26. "PADCONFIG2_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x08 25. "PADCONFIG2_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x08 24. "PADCONFIG2_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x08 23. "PADCONFIG2_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x08 22. "PADCONFIG2_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x08 21. "PADCONFIG2_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x08 19.--20. "PADCONFIG2_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x08 18. "PADCONFIG2_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x08 17. "PADCONFIG2_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x08 16. "PADCONFIG2_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x08 15. "PADCONFIG2_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x08 14. "PADCONFIG2_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x08 11.--13. "PADCONFIG2_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 8. "PADCONFIG2_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x08 7. "PADCONFIG2_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x08 0.--3. "PADCONFIG2_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x0C "CFG0_PADCONFIG3,"
bitfld.long 0x0C 31. "PADCONFIG3_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x0C 30. "PADCONFIG3_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x0C 29. "PADCONFIG3_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x0C 28. "PADCONFIG3_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x0C 27. "PADCONFIG3_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x0C 26. "PADCONFIG3_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x0C 25. "PADCONFIG3_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x0C 24. "PADCONFIG3_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x0C 23. "PADCONFIG3_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x0C 22. "PADCONFIG3_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x0C 21. "PADCONFIG3_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x0C 19.--20. "PADCONFIG3_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x0C 18. "PADCONFIG3_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x0C 17. "PADCONFIG3_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x0C 16. "PADCONFIG3_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x0C 15. "PADCONFIG3_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x0C 14. "PADCONFIG3_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x0C 11.--13. "PADCONFIG3_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 8. "PADCONFIG3_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x0C 7. "PADCONFIG3_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x0C 0.--3. "PADCONFIG3_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x10 "CFG0_PADCONFIG4,"
bitfld.long 0x10 31. "PADCONFIG4_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x10 30. "PADCONFIG4_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x10 29. "PADCONFIG4_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x10 28. "PADCONFIG4_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x10 27. "PADCONFIG4_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x10 26. "PADCONFIG4_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x10 25. "PADCONFIG4_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x10 24. "PADCONFIG4_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x10 23. "PADCONFIG4_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x10 22. "PADCONFIG4_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x10 21. "PADCONFIG4_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x10 15. "PADCONFIG4_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x10 14. "PADCONFIG4_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 8. "PADCONFIG4_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x10 7. "PADCONFIG4_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x10 0.--3. "PADCONFIG4_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x14 "CFG0_PADCONFIG5,"
bitfld.long 0x14 31. "PADCONFIG5_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x14 30. "PADCONFIG5_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x14 29. "PADCONFIG5_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x14 28. "PADCONFIG5_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x14 27. "PADCONFIG5_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x14 26. "PADCONFIG5_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x14 25. "PADCONFIG5_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x14 24. "PADCONFIG5_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x14 23. "PADCONFIG5_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x14 22. "PADCONFIG5_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x14 21. "PADCONFIG5_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x14 15. "PADCONFIG5_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x14 14. "PADCONFIG5_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 8. "PADCONFIG5_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x14 7. "PADCONFIG5_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x14 0.--3. "PADCONFIG5_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x18 "CFG0_PADCONFIG6,"
bitfld.long 0x18 31. "PADCONFIG6_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x18 30. "PADCONFIG6_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x18 29. "PADCONFIG6_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x18 28. "PADCONFIG6_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x18 27. "PADCONFIG6_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x18 26. "PADCONFIG6_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x18 25. "PADCONFIG6_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x18 24. "PADCONFIG6_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x18 23. "PADCONFIG6_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x18 22. "PADCONFIG6_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x18 21. "PADCONFIG6_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x18 15. "PADCONFIG6_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x18 14. "PADCONFIG6_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 8. "PADCONFIG6_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x18 7. "PADCONFIG6_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x18 0.--3. "PADCONFIG6_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C "CFG0_PADCONFIG7,"
bitfld.long 0x1C 31. "PADCONFIG7_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C 30. "PADCONFIG7_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C 29. "PADCONFIG7_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1C 28. "PADCONFIG7_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1C 27. "PADCONFIG7_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C 26. "PADCONFIG7_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1C 25. "PADCONFIG7_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C 24. "PADCONFIG7_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1C 23. "PADCONFIG7_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1C 22. "PADCONFIG7_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C 15. "PADCONFIG7_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1C 14. "PADCONFIG7_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 8. "PADCONFIG7_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1C 7. "PADCONFIG7_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1C 0.--3. "PADCONFIG7_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x20 "CFG0_PADCONFIG8,"
bitfld.long 0x20 31. "PADCONFIG8_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x20 30. "PADCONFIG8_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x20 29. "PADCONFIG8_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x20 28. "PADCONFIG8_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x20 27. "PADCONFIG8_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x20 26. "PADCONFIG8_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x20 25. "PADCONFIG8_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x20 24. "PADCONFIG8_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x20 23. "PADCONFIG8_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x20 22. "PADCONFIG8_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x20 21. "PADCONFIG8_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x20 15. "PADCONFIG8_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x20 14. "PADCONFIG8_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 8. "PADCONFIG8_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x20 7. "PADCONFIG8_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x20 0.--3. "PADCONFIG8_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x24 "CFG0_PADCONFIG9,"
bitfld.long 0x24 31. "PADCONFIG9_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x24 30. "PADCONFIG9_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x24 29. "PADCONFIG9_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x24 28. "PADCONFIG9_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x24 27. "PADCONFIG9_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x24 26. "PADCONFIG9_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x24 25. "PADCONFIG9_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x24 24. "PADCONFIG9_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x24 23. "PADCONFIG9_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x24 22. "PADCONFIG9_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x24 21. "PADCONFIG9_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x24 15. "PADCONFIG9_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x24 14. "PADCONFIG9_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 8. "PADCONFIG9_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x24 7. "PADCONFIG9_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x24 0.--3. "PADCONFIG9_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x28 "CFG0_PADCONFIG10,"
bitfld.long 0x28 31. "PADCONFIG10_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x28 30. "PADCONFIG10_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x28 29. "PADCONFIG10_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x28 28. "PADCONFIG10_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x28 27. "PADCONFIG10_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x28 26. "PADCONFIG10_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x28 25. "PADCONFIG10_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x28 24. "PADCONFIG10_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x28 23. "PADCONFIG10_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x28 22. "PADCONFIG10_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x28 21. "PADCONFIG10_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x28 15. "PADCONFIG10_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x28 14. "PADCONFIG10_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 8. "PADCONFIG10_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x28 7. "PADCONFIG10_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x28 0.--3. "PADCONFIG10_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2C "CFG0_PADCONFIG11,"
bitfld.long 0x2C 31. "PADCONFIG11_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x2C 30. "PADCONFIG11_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x2C 29. "PADCONFIG11_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x2C 28. "PADCONFIG11_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x2C 27. "PADCONFIG11_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x2C 26. "PADCONFIG11_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x2C 25. "PADCONFIG11_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x2C 24. "PADCONFIG11_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x2C 23. "PADCONFIG11_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x2C 22. "PADCONFIG11_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x2C 15. "PADCONFIG11_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x2C 14. "PADCONFIG11_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x2C 8. "PADCONFIG11_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x2C 7. "PADCONFIG11_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x2C 0.--3. "PADCONFIG11_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x30 "CFG0_PADCONFIG12,"
bitfld.long 0x30 31. "PADCONFIG12_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x30 30. "PADCONFIG12_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x30 29. "PADCONFIG12_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x30 28. "PADCONFIG12_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x30 27. "PADCONFIG12_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x30 26. "PADCONFIG12_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x30 25. "PADCONFIG12_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x30 24. "PADCONFIG12_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x30 23. "PADCONFIG12_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x30 22. "PADCONFIG12_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x30 21. "PADCONFIG12_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x30 15. "PADCONFIG12_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x30 14. "PADCONFIG12_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x30 8. "PADCONFIG12_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x30 7. "PADCONFIG12_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x30 0.--3. "PADCONFIG12_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x34 "CFG0_PADCONFIG13,"
bitfld.long 0x34 31. "PADCONFIG13_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x34 30. "PADCONFIG13_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x34 29. "PADCONFIG13_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x34 28. "PADCONFIG13_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x34 27. "PADCONFIG13_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x34 26. "PADCONFIG13_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x34 25. "PADCONFIG13_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x34 24. "PADCONFIG13_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x34 23. "PADCONFIG13_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x34 22. "PADCONFIG13_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x34 21. "PADCONFIG13_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x34 15. "PADCONFIG13_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x34 14. "PADCONFIG13_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x34 8. "PADCONFIG13_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x34 7. "PADCONFIG13_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x34 0.--3. "PADCONFIG13_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x38 "CFG0_PADCONFIG14,"
bitfld.long 0x38 31. "PADCONFIG14_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x38 30. "PADCONFIG14_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x38 29. "PADCONFIG14_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x38 28. "PADCONFIG14_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x38 27. "PADCONFIG14_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x38 26. "PADCONFIG14_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x38 25. "PADCONFIG14_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x38 24. "PADCONFIG14_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x38 23. "PADCONFIG14_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x38 22. "PADCONFIG14_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x38 21. "PADCONFIG14_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x38 15. "PADCONFIG14_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x38 14. "PADCONFIG14_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x38 8. "PADCONFIG14_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x38 7. "PADCONFIG14_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x38 0.--3. "PADCONFIG14_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x3C "CFG0_PADCONFIG15,"
bitfld.long 0x3C 31. "PADCONFIG15_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x3C 30. "PADCONFIG15_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x3C 29. "PADCONFIG15_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x3C 28. "PADCONFIG15_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x3C 27. "PADCONFIG15_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x3C 26. "PADCONFIG15_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x3C 25. "PADCONFIG15_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x3C 24. "PADCONFIG15_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x3C 23. "PADCONFIG15_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x3C 22. "PADCONFIG15_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x3C 15. "PADCONFIG15_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x3C 14. "PADCONFIG15_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x3C 8. "PADCONFIG15_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x3C 7. "PADCONFIG15_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x3C 0.--3. "PADCONFIG15_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x40 "CFG0_PADCONFIG16,"
bitfld.long 0x40 31. "PADCONFIG16_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x40 30. "PADCONFIG16_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x40 29. "PADCONFIG16_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x40 28. "PADCONFIG16_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x40 27. "PADCONFIG16_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x40 26. "PADCONFIG16_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x40 25. "PADCONFIG16_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x40 24. "PADCONFIG16_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x40 23. "PADCONFIG16_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x40 22. "PADCONFIG16_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x40 21. "PADCONFIG16_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x40 15. "PADCONFIG16_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x40 14. "PADCONFIG16_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x40 8. "PADCONFIG16_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x40 7. "PADCONFIG16_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x40 0.--3. "PADCONFIG16_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x44 "CFG0_PADCONFIG17,"
bitfld.long 0x44 31. "PADCONFIG17_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x44 30. "PADCONFIG17_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x44 29. "PADCONFIG17_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x44 28. "PADCONFIG17_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x44 27. "PADCONFIG17_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x44 26. "PADCONFIG17_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x44 25. "PADCONFIG17_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x44 24. "PADCONFIG17_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x44 23. "PADCONFIG17_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x44 22. "PADCONFIG17_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x44 21. "PADCONFIG17_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x44 15. "PADCONFIG17_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x44 14. "PADCONFIG17_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x44 8. "PADCONFIG17_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x44 7. "PADCONFIG17_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x44 0.--3. "PADCONFIG17_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x48 "CFG0_PADCONFIG18,"
bitfld.long 0x48 31. "PADCONFIG18_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x48 30. "PADCONFIG18_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x48 29. "PADCONFIG18_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x48 28. "PADCONFIG18_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x48 27. "PADCONFIG18_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x48 26. "PADCONFIG18_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x48 25. "PADCONFIG18_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x48 24. "PADCONFIG18_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x48 23. "PADCONFIG18_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x48 22. "PADCONFIG18_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x48 21. "PADCONFIG18_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x48 15. "PADCONFIG18_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x48 14. "PADCONFIG18_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x48 8. "PADCONFIG18_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x48 7. "PADCONFIG18_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x48 0.--3. "PADCONFIG18_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x4C "CFG0_PADCONFIG19,"
bitfld.long 0x4C 31. "PADCONFIG19_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x4C 30. "PADCONFIG19_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x4C 29. "PADCONFIG19_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x4C 28. "PADCONFIG19_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x4C 27. "PADCONFIG19_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x4C 26. "PADCONFIG19_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x4C 25. "PADCONFIG19_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x4C 24. "PADCONFIG19_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x4C 23. "PADCONFIG19_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x4C 22. "PADCONFIG19_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x4C 15. "PADCONFIG19_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x4C 14. "PADCONFIG19_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4C 8. "PADCONFIG19_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x4C 7. "PADCONFIG19_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x4C 0.--3. "PADCONFIG19_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x50 "CFG0_PADCONFIG20,"
bitfld.long 0x50 31. "PADCONFIG20_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x50 30. "PADCONFIG20_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x50 29. "PADCONFIG20_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x50 28. "PADCONFIG20_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x50 27. "PADCONFIG20_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x50 26. "PADCONFIG20_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x50 25. "PADCONFIG20_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x50 24. "PADCONFIG20_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x50 23. "PADCONFIG20_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x50 22. "PADCONFIG20_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x50 21. "PADCONFIG20_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x50 15. "PADCONFIG20_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x50 14. "PADCONFIG20_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x50 8. "PADCONFIG20_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x50 7. "PADCONFIG20_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x50 0.--3. "PADCONFIG20_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x54 "CFG0_PADCONFIG21,"
bitfld.long 0x54 31. "PADCONFIG21_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x54 30. "PADCONFIG21_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x54 29. "PADCONFIG21_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x54 28. "PADCONFIG21_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x54 27. "PADCONFIG21_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x54 26. "PADCONFIG21_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x54 25. "PADCONFIG21_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x54 24. "PADCONFIG21_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x54 23. "PADCONFIG21_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x54 22. "PADCONFIG21_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x54 21. "PADCONFIG21_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x54 15. "PADCONFIG21_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x54 14. "PADCONFIG21_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x54 8. "PADCONFIG21_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x54 7. "PADCONFIG21_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x54 0.--3. "PADCONFIG21_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x58 "CFG0_PADCONFIG22,"
bitfld.long 0x58 31. "PADCONFIG22_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x58 30. "PADCONFIG22_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x58 29. "PADCONFIG22_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x58 28. "PADCONFIG22_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x58 27. "PADCONFIG22_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x58 26. "PADCONFIG22_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x58 25. "PADCONFIG22_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x58 24. "PADCONFIG22_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x58 23. "PADCONFIG22_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x58 22. "PADCONFIG22_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x58 21. "PADCONFIG22_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x58 15. "PADCONFIG22_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x58 14. "PADCONFIG22_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x58 8. "PADCONFIG22_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x58 7. "PADCONFIG22_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x58 0.--3. "PADCONFIG22_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x5C "CFG0_PADCONFIG23,"
bitfld.long 0x5C 31. "PADCONFIG23_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x5C 30. "PADCONFIG23_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x5C 29. "PADCONFIG23_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x5C 28. "PADCONFIG23_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x5C 27. "PADCONFIG23_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x5C 26. "PADCONFIG23_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x5C 25. "PADCONFIG23_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x5C 24. "PADCONFIG23_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x5C 23. "PADCONFIG23_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x5C 22. "PADCONFIG23_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x5C 15. "PADCONFIG23_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x5C 14. "PADCONFIG23_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x5C 8. "PADCONFIG23_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x5C 7. "PADCONFIG23_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x5C 0.--3. "PADCONFIG23_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x60 "CFG0_PADCONFIG24,"
bitfld.long 0x60 31. "PADCONFIG24_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x60 30. "PADCONFIG24_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x60 29. "PADCONFIG24_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x60 28. "PADCONFIG24_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x60 27. "PADCONFIG24_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x60 26. "PADCONFIG24_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x60 25. "PADCONFIG24_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x60 24. "PADCONFIG24_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x60 23. "PADCONFIG24_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x60 22. "PADCONFIG24_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x60 21. "PADCONFIG24_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x60 15. "PADCONFIG24_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x60 14. "PADCONFIG24_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x60 8. "PADCONFIG24_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x60 7. "PADCONFIG24_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x60 0.--3. "PADCONFIG24_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x64 "CFG0_PADCONFIG25,"
bitfld.long 0x64 31. "PADCONFIG25_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x64 30. "PADCONFIG25_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x64 29. "PADCONFIG25_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x64 28. "PADCONFIG25_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x64 27. "PADCONFIG25_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x64 26. "PADCONFIG25_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x64 25. "PADCONFIG25_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x64 24. "PADCONFIG25_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x64 23. "PADCONFIG25_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x64 22. "PADCONFIG25_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x64 21. "PADCONFIG25_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x64 15. "PADCONFIG25_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x64 14. "PADCONFIG25_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x64 8. "PADCONFIG25_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x64 7. "PADCONFIG25_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x64 0.--3. "PADCONFIG25_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x68 "CFG0_PADCONFIG26,"
bitfld.long 0x68 31. "PADCONFIG26_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x68 30. "PADCONFIG26_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x68 29. "PADCONFIG26_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x68 28. "PADCONFIG26_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x68 27. "PADCONFIG26_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x68 26. "PADCONFIG26_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x68 25. "PADCONFIG26_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x68 24. "PADCONFIG26_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x68 23. "PADCONFIG26_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x68 22. "PADCONFIG26_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x68 21. "PADCONFIG26_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x68 15. "PADCONFIG26_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x68 14. "PADCONFIG26_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x68 8. "PADCONFIG26_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x68 7. "PADCONFIG26_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x68 0.--3. "PADCONFIG26_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x6C "CFG0_PADCONFIG27,"
bitfld.long 0x6C 31. "PADCONFIG27_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x6C 30. "PADCONFIG27_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x6C 29. "PADCONFIG27_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x6C 28. "PADCONFIG27_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x6C 27. "PADCONFIG27_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x6C 26. "PADCONFIG27_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x6C 25. "PADCONFIG27_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x6C 24. "PADCONFIG27_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x6C 23. "PADCONFIG27_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x6C 22. "PADCONFIG27_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x6C 15. "PADCONFIG27_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x6C 14. "PADCONFIG27_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x6C 8. "PADCONFIG27_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x6C 7. "PADCONFIG27_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x6C 0.--3. "PADCONFIG27_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x70 "CFG0_PADCONFIG28,"
bitfld.long 0x70 31. "PADCONFIG28_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x70 30. "PADCONFIG28_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x70 29. "PADCONFIG28_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x70 28. "PADCONFIG28_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x70 27. "PADCONFIG28_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x70 26. "PADCONFIG28_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x70 25. "PADCONFIG28_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x70 24. "PADCONFIG28_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x70 23. "PADCONFIG28_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x70 22. "PADCONFIG28_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x70 21. "PADCONFIG28_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x70 15. "PADCONFIG28_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x70 14. "PADCONFIG28_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x70 8. "PADCONFIG28_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x70 7. "PADCONFIG28_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x70 0.--3. "PADCONFIG28_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x74 "CFG0_PADCONFIG29,"
bitfld.long 0x74 31. "PADCONFIG29_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x74 30. "PADCONFIG29_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x74 29. "PADCONFIG29_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x74 28. "PADCONFIG29_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x74 27. "PADCONFIG29_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x74 26. "PADCONFIG29_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x74 25. "PADCONFIG29_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x74 24. "PADCONFIG29_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x74 23. "PADCONFIG29_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x74 22. "PADCONFIG29_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x74 21. "PADCONFIG29_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x74 15. "PADCONFIG29_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x74 14. "PADCONFIG29_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x74 8. "PADCONFIG29_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x74 7. "PADCONFIG29_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x74 0.--3. "PADCONFIG29_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x78 "CFG0_PADCONFIG30,"
bitfld.long 0x78 31. "PADCONFIG30_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x78 30. "PADCONFIG30_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x78 29. "PADCONFIG30_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x78 28. "PADCONFIG30_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x78 27. "PADCONFIG30_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x78 26. "PADCONFIG30_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x78 25. "PADCONFIG30_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x78 24. "PADCONFIG30_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x78 23. "PADCONFIG30_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x78 22. "PADCONFIG30_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x78 21. "PADCONFIG30_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x78 15. "PADCONFIG30_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x78 14. "PADCONFIG30_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x78 8. "PADCONFIG30_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x78 7. "PADCONFIG30_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x78 0.--3. "PADCONFIG30_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x7C "CFG0_PADCONFIG31,"
bitfld.long 0x7C 31. "PADCONFIG31_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x7C 30. "PADCONFIG31_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x7C 29. "PADCONFIG31_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x7C 28. "PADCONFIG31_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x7C 27. "PADCONFIG31_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x7C 26. "PADCONFIG31_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x7C 25. "PADCONFIG31_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x7C 24. "PADCONFIG31_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x7C 23. "PADCONFIG31_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x7C 22. "PADCONFIG31_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x7C 15. "PADCONFIG31_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x7C 14. "PADCONFIG31_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x7C 8. "PADCONFIG31_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x7C 7. "PADCONFIG31_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x7C 0.--3. "PADCONFIG31_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x80 "CFG0_PADCONFIG32,"
bitfld.long 0x80 31. "PADCONFIG32_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x80 30. "PADCONFIG32_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x80 29. "PADCONFIG32_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x80 28. "PADCONFIG32_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x80 27. "PADCONFIG32_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x80 26. "PADCONFIG32_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x80 25. "PADCONFIG32_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x80 24. "PADCONFIG32_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x80 23. "PADCONFIG32_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x80 22. "PADCONFIG32_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x80 21. "PADCONFIG32_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x80 15. "PADCONFIG32_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x80 14. "PADCONFIG32_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x80 8. "PADCONFIG32_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x80 7. "PADCONFIG32_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x80 0.--3. "PADCONFIG32_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x84 "CFG0_PADCONFIG33,"
bitfld.long 0x84 31. "PADCONFIG33_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x84 30. "PADCONFIG33_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x84 29. "PADCONFIG33_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x84 28. "PADCONFIG33_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x84 27. "PADCONFIG33_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x84 26. "PADCONFIG33_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x84 25. "PADCONFIG33_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x84 24. "PADCONFIG33_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x84 23. "PADCONFIG33_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x84 22. "PADCONFIG33_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x84 21. "PADCONFIG33_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x84 19.--20. "PADCONFIG33_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x84 18. "PADCONFIG33_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x84 17. "PADCONFIG33_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x84 16. "PADCONFIG33_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x84 15. "PADCONFIG33_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x84 14. "PADCONFIG33_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x84 11.--13. "PADCONFIG33_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x84 8. "PADCONFIG33_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x84 7. "PADCONFIG33_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x84 0.--3. "PADCONFIG33_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
group.long 0x5008++0x07
line.long 0x00 "CFG0_LOCK1_KICK0,"
line.long 0x04 "CFG0_LOCK1_KICK1,"
rgroup.long 0x5100++0x07
line.long 0x00 "CFG0_CLAIMREG_P1_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P1_R1_READONLY,"
group.long 0x6000++0x87
line.long 0x00 "CFG0_PADCONFIG0_PROXY,"
bitfld.long 0x00 31. "PADCONFIG0_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x00 30. "PADCONFIG0_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x00 29. "PADCONFIG0_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x00 28. "PADCONFIG0_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x00 27. "PADCONFIG0_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x00 26. "PADCONFIG0_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x00 25. "PADCONFIG0_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x00 24. "PADCONFIG0_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x00 23. "PADCONFIG0_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x00 22. "PADCONFIG0_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x00 21. "PADCONFIG0_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x00 19.--20. "PADCONFIG0_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "PADCONFIG0_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x00 17. "PADCONFIG0_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x00 16. "PADCONFIG0_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x00 15. "PADCONFIG0_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x00 14. "PADCONFIG0_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x00 11.--13. "PADCONFIG0_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8. "PADCONFIG0_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x00 7. "PADCONFIG0_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--3. "PADCONFIG0_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x04 "CFG0_PADCONFIG1_PROXY,"
bitfld.long 0x04 31. "PADCONFIG1_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x04 30. "PADCONFIG1_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x04 29. "PADCONFIG1_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x04 28. "PADCONFIG1_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x04 27. "PADCONFIG1_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x04 26. "PADCONFIG1_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x04 25. "PADCONFIG1_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x04 24. "PADCONFIG1_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x04 23. "PADCONFIG1_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x04 22. "PADCONFIG1_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x04 21. "PADCONFIG1_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x04 19.--20. "PADCONFIG1_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x04 18. "PADCONFIG1_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x04 17. "PADCONFIG1_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x04 16. "PADCONFIG1_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x04 15. "PADCONFIG1_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x04 14. "PADCONFIG1_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x04 11.--13. "PADCONFIG1_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 8. "PADCONFIG1_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x04 7. "PADCONFIG1_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x04 0.--3. "PADCONFIG1_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x08 "CFG0_PADCONFIG2_PROXY,"
bitfld.long 0x08 31. "PADCONFIG2_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x08 30. "PADCONFIG2_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x08 29. "PADCONFIG2_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x08 28. "PADCONFIG2_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x08 27. "PADCONFIG2_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x08 26. "PADCONFIG2_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x08 25. "PADCONFIG2_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x08 24. "PADCONFIG2_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x08 23. "PADCONFIG2_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x08 22. "PADCONFIG2_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x08 21. "PADCONFIG2_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x08 19.--20. "PADCONFIG2_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x08 18. "PADCONFIG2_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x08 17. "PADCONFIG2_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x08 16. "PADCONFIG2_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x08 15. "PADCONFIG2_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x08 14. "PADCONFIG2_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x08 11.--13. "PADCONFIG2_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 8. "PADCONFIG2_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x08 7. "PADCONFIG2_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x08 0.--3. "PADCONFIG2_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x0C "CFG0_PADCONFIG3_PROXY,"
bitfld.long 0x0C 31. "PADCONFIG3_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x0C 30. "PADCONFIG3_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x0C 29. "PADCONFIG3_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x0C 28. "PADCONFIG3_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x0C 27. "PADCONFIG3_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x0C 26. "PADCONFIG3_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x0C 25. "PADCONFIG3_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x0C 24. "PADCONFIG3_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x0C 23. "PADCONFIG3_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x0C 22. "PADCONFIG3_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x0C 21. "PADCONFIG3_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x0C 19.--20. "PADCONFIG3_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x0C 18. "PADCONFIG3_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x0C 17. "PADCONFIG3_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x0C 16. "PADCONFIG3_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x0C 15. "PADCONFIG3_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x0C 14. "PADCONFIG3_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x0C 11.--13. "PADCONFIG3_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 8. "PADCONFIG3_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x0C 7. "PADCONFIG3_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x0C 0.--3. "PADCONFIG3_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x10 "CFG0_PADCONFIG4_PROXY,"
bitfld.long 0x10 31. "PADCONFIG4_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x10 30. "PADCONFIG4_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x10 29. "PADCONFIG4_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x10 28. "PADCONFIG4_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x10 27. "PADCONFIG4_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x10 26. "PADCONFIG4_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x10 25. "PADCONFIG4_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x10 24. "PADCONFIG4_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x10 23. "PADCONFIG4_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x10 22. "PADCONFIG4_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x10 21. "PADCONFIG4_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x10 15. "PADCONFIG4_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x10 14. "PADCONFIG4_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 8. "PADCONFIG4_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x10 7. "PADCONFIG4_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x10 0.--3. "PADCONFIG4_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x14 "CFG0_PADCONFIG5_PROXY,"
bitfld.long 0x14 31. "PADCONFIG5_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x14 30. "PADCONFIG5_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x14 29. "PADCONFIG5_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x14 28. "PADCONFIG5_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x14 27. "PADCONFIG5_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x14 26. "PADCONFIG5_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x14 25. "PADCONFIG5_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x14 24. "PADCONFIG5_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x14 23. "PADCONFIG5_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x14 22. "PADCONFIG5_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x14 21. "PADCONFIG5_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x14 15. "PADCONFIG5_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x14 14. "PADCONFIG5_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 8. "PADCONFIG5_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x14 7. "PADCONFIG5_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x14 0.--3. "PADCONFIG5_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x18 "CFG0_PADCONFIG6_PROXY,"
bitfld.long 0x18 31. "PADCONFIG6_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x18 30. "PADCONFIG6_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x18 29. "PADCONFIG6_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x18 28. "PADCONFIG6_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x18 27. "PADCONFIG6_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x18 26. "PADCONFIG6_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x18 25. "PADCONFIG6_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x18 24. "PADCONFIG6_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x18 23. "PADCONFIG6_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x18 22. "PADCONFIG6_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x18 21. "PADCONFIG6_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x18 15. "PADCONFIG6_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x18 14. "PADCONFIG6_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 8. "PADCONFIG6_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x18 7. "PADCONFIG6_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x18 0.--3. "PADCONFIG6_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C "CFG0_PADCONFIG7_PROXY,"
bitfld.long 0x1C 31. "PADCONFIG7_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C 30. "PADCONFIG7_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C 29. "PADCONFIG7_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x1C 28. "PADCONFIG7_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x1C 27. "PADCONFIG7_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C 26. "PADCONFIG7_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x1C 25. "PADCONFIG7_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C 24. "PADCONFIG7_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x1C 23. "PADCONFIG7_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x1C 22. "PADCONFIG7_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C 15. "PADCONFIG7_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x1C 14. "PADCONFIG7_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1C 8. "PADCONFIG7_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x1C 7. "PADCONFIG7_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x1C 0.--3. "PADCONFIG7_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x20 "CFG0_PADCONFIG8_PROXY,"
bitfld.long 0x20 31. "PADCONFIG8_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x20 30. "PADCONFIG8_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x20 29. "PADCONFIG8_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x20 28. "PADCONFIG8_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x20 27. "PADCONFIG8_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x20 26. "PADCONFIG8_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x20 25. "PADCONFIG8_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x20 24. "PADCONFIG8_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x20 23. "PADCONFIG8_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x20 22. "PADCONFIG8_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x20 21. "PADCONFIG8_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x20 15. "PADCONFIG8_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x20 14. "PADCONFIG8_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 8. "PADCONFIG8_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x20 7. "PADCONFIG8_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x20 0.--3. "PADCONFIG8_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x24 "CFG0_PADCONFIG9_PROXY,"
bitfld.long 0x24 31. "PADCONFIG9_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x24 30. "PADCONFIG9_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x24 29. "PADCONFIG9_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x24 28. "PADCONFIG9_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x24 27. "PADCONFIG9_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x24 26. "PADCONFIG9_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x24 25. "PADCONFIG9_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x24 24. "PADCONFIG9_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x24 23. "PADCONFIG9_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x24 22. "PADCONFIG9_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x24 21. "PADCONFIG9_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x24 15. "PADCONFIG9_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x24 14. "PADCONFIG9_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x24 8. "PADCONFIG9_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x24 7. "PADCONFIG9_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x24 0.--3. "PADCONFIG9_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x28 "CFG0_PADCONFIG10_PROXY,"
bitfld.long 0x28 31. "PADCONFIG10_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x28 30. "PADCONFIG10_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x28 29. "PADCONFIG10_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x28 28. "PADCONFIG10_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x28 27. "PADCONFIG10_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x28 26. "PADCONFIG10_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x28 25. "PADCONFIG10_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x28 24. "PADCONFIG10_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x28 23. "PADCONFIG10_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x28 22. "PADCONFIG10_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x28 21. "PADCONFIG10_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x28 15. "PADCONFIG10_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x28 14. "PADCONFIG10_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 8. "PADCONFIG10_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x28 7. "PADCONFIG10_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x28 0.--3. "PADCONFIG10_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2C "CFG0_PADCONFIG11_PROXY,"
bitfld.long 0x2C 31. "PADCONFIG11_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x2C 30. "PADCONFIG11_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x2C 29. "PADCONFIG11_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x2C 28. "PADCONFIG11_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x2C 27. "PADCONFIG11_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x2C 26. "PADCONFIG11_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2C 25. "PADCONFIG11_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x2C 24. "PADCONFIG11_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x2C 23. "PADCONFIG11_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x2C 22. "PADCONFIG11_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x2C 15. "PADCONFIG11_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x2C 14. "PADCONFIG11_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2C 8. "PADCONFIG11_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x2C 7. "PADCONFIG11_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x2C 0.--3. "PADCONFIG11_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x30 "CFG0_PADCONFIG12_PROXY,"
bitfld.long 0x30 31. "PADCONFIG12_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x30 30. "PADCONFIG12_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x30 29. "PADCONFIG12_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x30 28. "PADCONFIG12_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x30 27. "PADCONFIG12_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x30 26. "PADCONFIG12_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x30 25. "PADCONFIG12_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x30 24. "PADCONFIG12_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x30 23. "PADCONFIG12_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x30 22. "PADCONFIG12_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x30 21. "PADCONFIG12_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x30 15. "PADCONFIG12_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x30 14. "PADCONFIG12_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 8. "PADCONFIG12_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x30 7. "PADCONFIG12_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x30 0.--3. "PADCONFIG12_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x34 "CFG0_PADCONFIG13_PROXY,"
bitfld.long 0x34 31. "PADCONFIG13_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x34 30. "PADCONFIG13_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x34 29. "PADCONFIG13_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x34 28. "PADCONFIG13_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x34 27. "PADCONFIG13_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x34 26. "PADCONFIG13_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x34 25. "PADCONFIG13_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x34 24. "PADCONFIG13_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x34 23. "PADCONFIG13_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x34 22. "PADCONFIG13_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x34 21. "PADCONFIG13_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x34 15. "PADCONFIG13_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x34 14. "PADCONFIG13_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 8. "PADCONFIG13_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x34 7. "PADCONFIG13_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x34 0.--3. "PADCONFIG13_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x38 "CFG0_PADCONFIG14_PROXY,"
bitfld.long 0x38 31. "PADCONFIG14_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x38 30. "PADCONFIG14_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x38 29. "PADCONFIG14_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x38 28. "PADCONFIG14_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x38 27. "PADCONFIG14_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x38 26. "PADCONFIG14_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x38 25. "PADCONFIG14_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x38 24. "PADCONFIG14_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x38 23. "PADCONFIG14_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x38 22. "PADCONFIG14_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x38 21. "PADCONFIG14_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x38 15. "PADCONFIG14_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x38 14. "PADCONFIG14_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 8. "PADCONFIG14_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x38 7. "PADCONFIG14_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x38 0.--3. "PADCONFIG14_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x3C "CFG0_PADCONFIG15_PROXY,"
bitfld.long 0x3C 31. "PADCONFIG15_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x3C 30. "PADCONFIG15_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x3C 29. "PADCONFIG15_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x3C 28. "PADCONFIG15_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x3C 27. "PADCONFIG15_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x3C 26. "PADCONFIG15_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x3C 25. "PADCONFIG15_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x3C 24. "PADCONFIG15_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x3C 23. "PADCONFIG15_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x3C 22. "PADCONFIG15_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x3C 15. "PADCONFIG15_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x3C 14. "PADCONFIG15_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x3C 8. "PADCONFIG15_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x3C 7. "PADCONFIG15_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x3C 0.--3. "PADCONFIG15_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x40 "CFG0_PADCONFIG16_PROXY,"
bitfld.long 0x40 31. "PADCONFIG16_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x40 30. "PADCONFIG16_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x40 29. "PADCONFIG16_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x40 28. "PADCONFIG16_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x40 27. "PADCONFIG16_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x40 26. "PADCONFIG16_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x40 25. "PADCONFIG16_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x40 24. "PADCONFIG16_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x40 23. "PADCONFIG16_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x40 22. "PADCONFIG16_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x40 21. "PADCONFIG16_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x40 15. "PADCONFIG16_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x40 14. "PADCONFIG16_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x40 8. "PADCONFIG16_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x40 7. "PADCONFIG16_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x40 0.--3. "PADCONFIG16_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x44 "CFG0_PADCONFIG17_PROXY,"
bitfld.long 0x44 31. "PADCONFIG17_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x44 30. "PADCONFIG17_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x44 29. "PADCONFIG17_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x44 28. "PADCONFIG17_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x44 27. "PADCONFIG17_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x44 26. "PADCONFIG17_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x44 25. "PADCONFIG17_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x44 24. "PADCONFIG17_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x44 23. "PADCONFIG17_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x44 22. "PADCONFIG17_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x44 21. "PADCONFIG17_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x44 15. "PADCONFIG17_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x44 14. "PADCONFIG17_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x44 8. "PADCONFIG17_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x44 7. "PADCONFIG17_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x44 0.--3. "PADCONFIG17_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x48 "CFG0_PADCONFIG18_PROXY,"
bitfld.long 0x48 31. "PADCONFIG18_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x48 30. "PADCONFIG18_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x48 29. "PADCONFIG18_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x48 28. "PADCONFIG18_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x48 27. "PADCONFIG18_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x48 26. "PADCONFIG18_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x48 25. "PADCONFIG18_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x48 24. "PADCONFIG18_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x48 23. "PADCONFIG18_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x48 22. "PADCONFIG18_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x48 21. "PADCONFIG18_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x48 15. "PADCONFIG18_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x48 14. "PADCONFIG18_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x48 8. "PADCONFIG18_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x48 7. "PADCONFIG18_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x48 0.--3. "PADCONFIG18_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x4C "CFG0_PADCONFIG19_PROXY,"
bitfld.long 0x4C 31. "PADCONFIG19_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x4C 30. "PADCONFIG19_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x4C 29. "PADCONFIG19_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x4C 28. "PADCONFIG19_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x4C 27. "PADCONFIG19_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x4C 26. "PADCONFIG19_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x4C 25. "PADCONFIG19_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x4C 24. "PADCONFIG19_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x4C 23. "PADCONFIG19_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x4C 22. "PADCONFIG19_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x4C 15. "PADCONFIG19_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x4C 14. "PADCONFIG19_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4C 8. "PADCONFIG19_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x4C 7. "PADCONFIG19_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x4C 0.--3. "PADCONFIG19_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x50 "CFG0_PADCONFIG20_PROXY,"
bitfld.long 0x50 31. "PADCONFIG20_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x50 30. "PADCONFIG20_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x50 29. "PADCONFIG20_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x50 28. "PADCONFIG20_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x50 27. "PADCONFIG20_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x50 26. "PADCONFIG20_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x50 25. "PADCONFIG20_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x50 24. "PADCONFIG20_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x50 23. "PADCONFIG20_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x50 22. "PADCONFIG20_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x50 21. "PADCONFIG20_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x50 15. "PADCONFIG20_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x50 14. "PADCONFIG20_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x50 8. "PADCONFIG20_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x50 7. "PADCONFIG20_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x50 0.--3. "PADCONFIG20_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x54 "CFG0_PADCONFIG21_PROXY,"
bitfld.long 0x54 31. "PADCONFIG21_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x54 30. "PADCONFIG21_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x54 29. "PADCONFIG21_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x54 28. "PADCONFIG21_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x54 27. "PADCONFIG21_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x54 26. "PADCONFIG21_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x54 25. "PADCONFIG21_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x54 24. "PADCONFIG21_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x54 23. "PADCONFIG21_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x54 22. "PADCONFIG21_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x54 21. "PADCONFIG21_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x54 15. "PADCONFIG21_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x54 14. "PADCONFIG21_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x54 8. "PADCONFIG21_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x54 7. "PADCONFIG21_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x54 0.--3. "PADCONFIG21_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x58 "CFG0_PADCONFIG22_PROXY,"
bitfld.long 0x58 31. "PADCONFIG22_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x58 30. "PADCONFIG22_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x58 29. "PADCONFIG22_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x58 28. "PADCONFIG22_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x58 27. "PADCONFIG22_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x58 26. "PADCONFIG22_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x58 25. "PADCONFIG22_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x58 24. "PADCONFIG22_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x58 23. "PADCONFIG22_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x58 22. "PADCONFIG22_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x58 21. "PADCONFIG22_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x58 15. "PADCONFIG22_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x58 14. "PADCONFIG22_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x58 8. "PADCONFIG22_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x58 7. "PADCONFIG22_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x58 0.--3. "PADCONFIG22_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x5C "CFG0_PADCONFIG23_PROXY,"
bitfld.long 0x5C 31. "PADCONFIG23_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x5C 30. "PADCONFIG23_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x5C 29. "PADCONFIG23_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x5C 28. "PADCONFIG23_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x5C 27. "PADCONFIG23_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x5C 26. "PADCONFIG23_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x5C 25. "PADCONFIG23_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x5C 24. "PADCONFIG23_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x5C 23. "PADCONFIG23_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x5C 22. "PADCONFIG23_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x5C 15. "PADCONFIG23_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x5C 14. "PADCONFIG23_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x5C 8. "PADCONFIG23_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x5C 7. "PADCONFIG23_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x5C 0.--3. "PADCONFIG23_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x60 "CFG0_PADCONFIG24_PROXY,"
bitfld.long 0x60 31. "PADCONFIG24_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x60 30. "PADCONFIG24_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x60 29. "PADCONFIG24_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x60 28. "PADCONFIG24_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x60 27. "PADCONFIG24_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x60 26. "PADCONFIG24_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x60 25. "PADCONFIG24_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x60 24. "PADCONFIG24_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x60 23. "PADCONFIG24_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x60 22. "PADCONFIG24_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x60 21. "PADCONFIG24_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x60 15. "PADCONFIG24_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x60 14. "PADCONFIG24_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x60 8. "PADCONFIG24_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x60 7. "PADCONFIG24_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x60 0.--3. "PADCONFIG24_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x64 "CFG0_PADCONFIG25_PROXY,"
bitfld.long 0x64 31. "PADCONFIG25_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x64 30. "PADCONFIG25_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x64 29. "PADCONFIG25_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x64 28. "PADCONFIG25_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x64 27. "PADCONFIG25_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x64 26. "PADCONFIG25_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x64 25. "PADCONFIG25_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x64 24. "PADCONFIG25_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x64 23. "PADCONFIG25_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x64 22. "PADCONFIG25_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x64 21. "PADCONFIG25_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x64 15. "PADCONFIG25_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x64 14. "PADCONFIG25_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x64 8. "PADCONFIG25_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x64 7. "PADCONFIG25_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x64 0.--3. "PADCONFIG25_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x68 "CFG0_PADCONFIG26_PROXY,"
bitfld.long 0x68 31. "PADCONFIG26_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x68 30. "PADCONFIG26_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x68 29. "PADCONFIG26_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x68 28. "PADCONFIG26_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x68 27. "PADCONFIG26_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x68 26. "PADCONFIG26_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x68 25. "PADCONFIG26_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x68 24. "PADCONFIG26_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x68 23. "PADCONFIG26_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x68 22. "PADCONFIG26_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x68 21. "PADCONFIG26_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x68 15. "PADCONFIG26_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x68 14. "PADCONFIG26_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x68 8. "PADCONFIG26_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x68 7. "PADCONFIG26_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x68 0.--3. "PADCONFIG26_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x6C "CFG0_PADCONFIG27_PROXY,"
bitfld.long 0x6C 31. "PADCONFIG27_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x6C 30. "PADCONFIG27_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x6C 29. "PADCONFIG27_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x6C 28. "PADCONFIG27_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x6C 27. "PADCONFIG27_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x6C 26. "PADCONFIG27_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x6C 25. "PADCONFIG27_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x6C 24. "PADCONFIG27_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x6C 23. "PADCONFIG27_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x6C 22. "PADCONFIG27_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x6C 15. "PADCONFIG27_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x6C 14. "PADCONFIG27_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x6C 8. "PADCONFIG27_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x6C 7. "PADCONFIG27_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x6C 0.--3. "PADCONFIG27_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x70 "CFG0_PADCONFIG28_PROXY,"
bitfld.long 0x70 31. "PADCONFIG28_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x70 30. "PADCONFIG28_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x70 29. "PADCONFIG28_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x70 28. "PADCONFIG28_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x70 27. "PADCONFIG28_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x70 26. "PADCONFIG28_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x70 25. "PADCONFIG28_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x70 24. "PADCONFIG28_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x70 23. "PADCONFIG28_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x70 22. "PADCONFIG28_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x70 21. "PADCONFIG28_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x70 15. "PADCONFIG28_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x70 14. "PADCONFIG28_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x70 8. "PADCONFIG28_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x70 7. "PADCONFIG28_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x70 0.--3. "PADCONFIG28_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x74 "CFG0_PADCONFIG29_PROXY,"
bitfld.long 0x74 31. "PADCONFIG29_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x74 30. "PADCONFIG29_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x74 29. "PADCONFIG29_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x74 28. "PADCONFIG29_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x74 27. "PADCONFIG29_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x74 26. "PADCONFIG29_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x74 25. "PADCONFIG29_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x74 24. "PADCONFIG29_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x74 23. "PADCONFIG29_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x74 22. "PADCONFIG29_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x74 21. "PADCONFIG29_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x74 15. "PADCONFIG29_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x74 14. "PADCONFIG29_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x74 8. "PADCONFIG29_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x74 7. "PADCONFIG29_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x74 0.--3. "PADCONFIG29_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x78 "CFG0_PADCONFIG30_PROXY,"
bitfld.long 0x78 31. "PADCONFIG30_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x78 30. "PADCONFIG30_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x78 29. "PADCONFIG30_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x78 28. "PADCONFIG30_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x78 27. "PADCONFIG30_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x78 26. "PADCONFIG30_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x78 25. "PADCONFIG30_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x78 24. "PADCONFIG30_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x78 23. "PADCONFIG30_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x78 22. "PADCONFIG30_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x78 21. "PADCONFIG30_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x78 15. "PADCONFIG30_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x78 14. "PADCONFIG30_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x78 8. "PADCONFIG30_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x78 7. "PADCONFIG30_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x78 0.--3. "PADCONFIG30_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x7C "CFG0_PADCONFIG31_PROXY,"
bitfld.long 0x7C 31. "PADCONFIG31_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x7C 30. "PADCONFIG31_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x7C 29. "PADCONFIG31_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x7C 28. "PADCONFIG31_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x7C 27. "PADCONFIG31_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x7C 26. "PADCONFIG31_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x7C 25. "PADCONFIG31_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x7C 24. "PADCONFIG31_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x7C 23. "PADCONFIG31_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x7C 22. "PADCONFIG31_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x7C 15. "PADCONFIG31_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x7C 14. "PADCONFIG31_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x7C 8. "PADCONFIG31_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x7C 7. "PADCONFIG31_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x7C 0.--3. "PADCONFIG31_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x80 "CFG0_PADCONFIG32_PROXY,"
bitfld.long 0x80 31. "PADCONFIG32_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x80 30. "PADCONFIG32_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x80 29. "PADCONFIG32_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x80 28. "PADCONFIG32_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x80 27. "PADCONFIG32_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x80 26. "PADCONFIG32_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x80 25. "PADCONFIG32_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x80 24. "PADCONFIG32_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x80 23. "PADCONFIG32_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x80 22. "PADCONFIG32_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x80 21. "PADCONFIG32_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x80 15. "PADCONFIG32_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x80 14. "PADCONFIG32_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x80 8. "PADCONFIG32_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x80 7. "PADCONFIG32_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x80 0.--3. "PADCONFIG32_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x84 "CFG0_PADCONFIG33_PROXY,"
bitfld.long 0x84 31. "PADCONFIG33_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x84 30. "PADCONFIG33_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x84 29. "PADCONFIG33_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x84 28. "PADCONFIG33_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x84 27. "PADCONFIG33_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x84 26. "PADCONFIG33_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x84 25. "PADCONFIG33_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x84 24. "PADCONFIG33_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x84 23. "PADCONFIG33_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x84 22. "PADCONFIG33_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x84 21. "PADCONFIG33_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x84 19.--20. "PADCONFIG33_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x84 18. "PADCONFIG33_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x84 17. "PADCONFIG33_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x84 16. "PADCONFIG33_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x84 15. "PADCONFIG33_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x84 14. "PADCONFIG33_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x84 11.--13. "PADCONFIG33_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x84 8. "PADCONFIG33_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x84 7. "PADCONFIG33_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x84 0.--3. "PADCONFIG33_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
group.long 0x7008++0x07
line.long 0x00 "CFG0_LOCK1_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK1_KICK1_PROXY,"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x7100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P1_R$1,"
repeat.end
tree.end
tree "WKUP_PBIST0"
base ad:0x2B500000
group.long 0x00++0x7F
line.long 0x00 "MEM_RF0L,"
line.long 0x04 "MEM_RF1L,"
line.long 0x08 "MEM_RF2L,"
line.long 0x0C "MEM_RF3L,"
line.long 0x10 "MEM_RF4L,"
line.long 0x14 "MEM_RF5L,"
line.long 0x18 "MEM_RF6L,"
line.long 0x1C "MEM_RF7L,"
line.long 0x20 "MEM_RF8L,"
line.long 0x24 "MEM_RF9L,"
line.long 0x28 "MEM_RF10L,"
line.long 0x2C "MEM_RF11L,"
line.long 0x30 "MEM_RF12L,"
line.long 0x34 "MEM_RF13L,"
line.long 0x38 "MEM_RF14L,"
line.long 0x3C "MEM_RF15L,"
line.long 0x40 "MEM_RF0U,"
line.long 0x44 "MEM_RF1U,"
line.long 0x48 "MEM_RF2U,"
line.long 0x4C "MEM_RF3U,"
line.long 0x50 "MEM_RF4U,"
line.long 0x54 "MEM_RF5U,"
line.long 0x58 "MEM_RF6U,"
line.long 0x5C "MEM_RF7U,"
line.long 0x60 "MEM_RF8U,"
line.long 0x64 "MEM_RF9U,"
line.long 0x68 "MEM_RF10U,"
line.long 0x6C "MEM_RF11U,"
line.long 0x70 "MEM_RF12U,"
line.long 0x74 "MEM_RF13U,"
line.long 0x78 "MEM_RF14U,"
line.long 0x7C "MEM_RF15U,"
group.long 0x100++0x27
line.long 0x00 "MEM_A0,"
hexmask.long.word 0x00 0.--15. 1. "A0,Variable Address Register 0 (A0)"
line.long 0x04 "MEM_A1,"
hexmask.long.word 0x04 0.--15. 1. "A1,Variable Address Register 1 (A1)"
line.long 0x08 "MEM_A2,"
hexmask.long.word 0x08 0.--15. 1. "A2,Variable Address Register 2 (A2)"
line.long 0x0C "MEM_A3,"
hexmask.long.word 0x0C 0.--15. 1. "A3,Variable Address Register 3 (A3)"
line.long 0x10 "MEM_L0,"
hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)"
line.long 0x14 "MEM_L1,"
hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)"
line.long 0x18 "MEM_L2,"
hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)"
line.long 0x1C "MEM_L3,"
hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)"
line.long 0x20 "MEM_D,"
hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)"
hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)"
line.long 0x24 "MEM_E,"
hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)"
hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)"
group.long 0x130++0x3F
line.long 0x00 "MEM_CA0,"
hexmask.long.word 0x00 0.--15. 1. "CA0,Constant Address Register 0 (CA0)"
line.long 0x04 "MEM_CA1,"
hexmask.long.word 0x04 0.--15. 1. "CA1,Constant Address Register 1 (CA1)"
line.long 0x08 "MEM_CA2,"
hexmask.long.word 0x08 0.--15. 1. "CA2,Constant Address Register 2 (CA2)"
line.long 0x0C "MEM_CA3,"
hexmask.long.word 0x0C 0.--15. 1. "CA3,Constant Address Register 3 (CA3)"
line.long 0x10 "MEM_CL0,"
hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)"
line.long 0x14 "MEM_CL1,"
hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)"
line.long 0x18 "MEM_CL2,"
hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)"
line.long 0x1C "MEM_CL3,"
hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)"
line.long 0x20 "MEM_I0,"
hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)"
line.long 0x24 "MEM_I1,"
hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)"
line.long 0x28 "MEM_I2,"
hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)"
line.long 0x2C "MEM_I3,"
hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)"
line.long 0x30 "MEM_RAMT,"
hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS"
hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS"
hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR"
bitfld.long 0x30 2.--5. "PLS,Pipeline Latency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3"
line.long 0x34 "MEM_DLR,"
hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)"
bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1"
bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1"
bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1"
bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1"
bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1"
newline
bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1"
bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1"
bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1"
bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1"
bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1"
bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1"
line.long 0x38 "MEM_CMS,"
bitfld.long 0x38 0.--3. "CMS,Clock Mux Select (CMS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "MEM_STR,"
bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1"
bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1"
bitfld.long 0x3C 2. "STOP,Stop" "0,1"
bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1"
bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1"
group.quad 0x170++0x07
line.quad 0x00 "MEM_SCR,"
hexmask.quad.byte 0x00 56.--63. 1. "SCR7,Address Scrambling Register 7"
hexmask.quad.byte 0x00 48.--55. 1. "SCR6,Address Scrambling Register 6"
hexmask.quad.byte 0x00 40.--47. 1. "SCR5,Address Scrambling Register 5"
hexmask.quad.byte 0x00 32.--39. 1. "SCR4,Address Scrambling Register 4"
hexmask.quad.byte 0x00 24.--31. 1. "SCR3,Address Scrambling Register 3"
hexmask.quad.byte 0x00 16.--23. 1. "SCR2,Address Scrambling Register 2"
newline
hexmask.quad.byte 0x00 8.--15. 1. "SCR1,Address Scrambling Register 1"
hexmask.quad.byte 0x00 0.--7. 1. "SCR0,Address Scrambling Register 0"
group.long 0x178++0x13
line.long 0x00 "MEM_CSR,"
hexmask.long.byte 0x00 24.--31. 1. "CSR3,Chip Select 3 (CSR3)"
hexmask.long.byte 0x00 16.--23. 1. "CSR2,Chip Select 2 (CSR2)"
hexmask.long.byte 0x00 8.--15. 1. "CSR1,Chip Select 1(CSR1)"
hexmask.long.byte 0x00 0.--7. 1. "CSR0,Chip Select 0 (CSR0)"
line.long 0x04 "MEM_FDLY,"
hexmask.long.byte 0x04 0.--7. 1. "FDLY,Fail Delay (FDLY)"
line.long 0x08 "MEM_PACT,"
bitfld.long 0x08 0. "PACT,PBIST Activate (PACT)" "0,1"
line.long 0x0C "MEM_PID,"
bitfld.long 0x0C 0.--4. "PID,PBIST ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "MEM_OVER,"
bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1"
bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1"
bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1"
bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1"
rgroup.quad 0x190++0x17
line.quad 0x00 "MEM_FSRF,"
bitfld.quad 0x00 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1"
bitfld.quad 0x00 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1"
line.quad 0x08 "MEM_FSRC,"
bitfld.quad 0x08 32.--35. "FSRC1,Fail Status Count - Port 1 (FSRC1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 0.--3. "FSRC0,Fail Status Count - Port 0 (FSRC0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.quad 0x10 "MEM_FSRA,"
hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)"
hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)"
rgroup.long 0x1A8++0x03
line.long 0x00 "MEM_FSRDL0,"
rgroup.long 0x1B0++0x17
line.long 0x00 "MEM_FSRDL1,"
line.long 0x04 "MEM_MARGIN_MODE,"
bitfld.long 0x04 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3"
bitfld.long 0x04 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3"
line.long 0x08 "MEM_WRENZ,"
bitfld.long 0x08 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3"
line.long 0x0C "MEM_PAGE_PGS,"
bitfld.long 0x0C 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3"
line.long 0x10 "MEM_ROM,"
bitfld.long 0x10 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3"
line.long 0x14 "MEM_ALGO,"
hexmask.long.byte 0x14 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)"
hexmask.long.byte 0x14 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)"
hexmask.long.byte 0x14 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)"
hexmask.long.byte 0x14 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)"
group.quad 0x1C8++0x07
line.quad 0x00 "MEM_RINFO,"
hexmask.quad.byte 0x00 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)"
hexmask.quad.byte 0x00 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)"
hexmask.quad.byte 0x00 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)"
hexmask.quad.byte 0x00 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)"
hexmask.quad.byte 0x00 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)"
hexmask.quad.byte 0x00 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)"
newline
hexmask.quad.byte 0x00 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)"
hexmask.quad.byte 0x00 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)"
tree.end
tree "WKUP_PLL0_CFG"
base ad:0x4040000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_pll0_PID,"
bitfld.long 0x00 30.--31. "SCHEME,PID follows new scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit - Processors" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "MODULE,Module functional identifier"
bitfld.long 0x00 11.--15. "MISC,Misc revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,custom revision number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x08++0x03
line.long 0x00 "CFG_pll0_CFG,"
hexmask.long.word 0x00 16.--31. 1. "HSDIV_PRSNT,High Speed Divider Presence Each bit Indicates the presence of High Speed dividers 0-15"
bitfld.long 0x00 11.--12. "SSM_TYPE,Spread spectrum module presence Field values (Others are reserved)" "SSM is not present,SSM is present,Reserved,Reserved"
newline
bitfld.long 0x00 8. "SSM_WVTBL,Spread spectrum wave table presence" "SSM Wave table is not present,SSM Wave table is present"
bitfld.long 0x00 0.--1. "PLL_TYPE,Indicates PLL type Field values (Others are reserved)" "Fractional PLL,FractionalF PLL,De-Skew PLL,?..."
group.long 0x10++0x07
line.long 0x00 "CFG_pll0_LOCKKEY0,"
hexmask.long 0x00 1.--31. 1. "KEY,Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers"
rbitfld.long 0x00 0. "UNLOCKED,Unlock status" "0,1"
line.long 0x04 "CFG_pll0_LOCKKEY1,"
group.long 0x20++0x07
line.long 0x00 "CFG_pll0_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass enable" "Synchronously select PLL and associated HSDIV..,Synchronously select the reference clock for all.."
bitfld.long 0x00 16. "BYP_ON_LOCKLOSS,Bypass on loss of PLL lock" "Do not automatically switch to ref clock source..,Switch to ref clock source when PLL losses lock"
newline
bitfld.long 0x00 15. "PLL_EN,PLL enable" "PLL is disabled,PLL is enabled"
bitfld.long 0x00 8. "INTL_BYP_EN,PLL internal bypass enable" "Output clocks are derived from the VCO clock,Output clocks are derived from the FREF.."
newline
bitfld.long 0x00 5. "CLK_4PH_EN,Enable 4-phase clock generator" "0,1"
bitfld.long 0x00 4. "CLK_POSTDIV_EN,Post divide CLK enable" "Post divide powered down,Post divide enabled"
newline
bitfld.long 0x00 1. "DSM_EN,Delta-Sigma modulator enable" "Delta-Sigma modulator is disabled (use integer..,Delta-Sigma modulator is enabled (use fractional.."
bitfld.long 0x00 0. "DAC_EN,Enable fractional noise canceling DAC This bit has no function (DAC is always disabled) in integer divide mode (when dsm_en=0)" "Fractional NC DAC is disabled (for Test modes..,Fractional NC DAC is enabled (ignored in integer.."
line.long 0x04 "CFG_pll0_STAT,"
bitfld.long 0x04 0. "LOCK,PLL lock status" "PLL is not locked,PLL is locked"
group.long 0x30++0x0B
line.long 0x00 "CFG_pll0_FREQ_CTRL0,"
abitfld.long 0x00 0.--11. "FB_DIV_INT,PLL feedback divider (integer portion) In Integer mode values of" "0x010=Divide by 16,0x011=Divide by,0x140=Divide by,0xC80=Divide by 3200,0xFFF=Not supported"
line.long 0x04 "CFG_pll0_FREQ_CTRL1,"
abitfld.long 0x04 0.--23. "FB_DIV_FRAC,PLL feedback divider (fractional portion) Supports values of 0 to 0.999999940395" "0x000001=.000000059605 (1/(2^24)),0x000002=.000000119209 (2/(2^24)),0x800000=.500000000000,0xFFFFFF=.999999940395 (1677215/(2^24))"
line.long 0x08 "CFG_pll0_DIV_CTRL,"
bitfld.long 0x08 24.--26. "POST_DIV2,Secondary post divider" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16.--18. "POST_DIV1,Primary post divider" "Reserved (do not use),Divide by 1,Divide by 2,Divide by 3,Divide by 4,Divide by 5,Divide by 6,Divide by 7"
newline
bitfld.long 0x08 0.--5. "REF_DIV,Reference clock pre-divider" "Reserved /(do not use/),Divide by 1,Divide by,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Divide by 63"
group.long 0x40++0x07
line.long 0x00 "CFG_pll0_SS_CTRL,"
bitfld.long 0x00 31. "BYPASS_EN,Bypass the SS modulator" "Spread spectrum modulation is enabled,SSMOD is bypassed"
hexmask.long.byte 0x00 18.--25. 1. "WV_TBLE_MAXADDR,Wave table max address"
newline
bitfld.long 0x00 15. "RESET,SSM reset" "0,1"
bitfld.long 0x00 4. "DOWNSPREAD_EN,Selects center spread or down spread clock variance" "Center spread,Down spread"
newline
bitfld.long 0x00 0. "WAVE_SEL,Wave pattern select External wave table should only be selected if PLL_CFG_ssm_wvtbl = 1 Field values (Others are reserved)" "Use 128 point triangle wave table,Use external wave table"
line.long 0x04 "CFG_pll0_SS_SPREAD,"
bitfld.long 0x04 16.--19. "MOD_DIV,Input clock divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--4. "SPREAD,Sets the spread modulation depth" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x60++0x07
line.long 0x00 "CFG_pll0_CAL_CTRL,"
bitfld.long 0x00 31. "CAL_EN,Calibration enable to actively adjust for input skew" "Disabled,Enabled"
bitfld.long 0x00 20. "FAST_CAL,Fast calibration enabled" "Normal operation,Used for initial calibration if initial value.."
newline
bitfld.long 0x00 16.--18. "CAL_CNT,Calibration loop programmable counter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15. "CAL_BYP,Calibration bypass" "Use the calibration output to set the phase..,Use the cal_in input value to set the phase.."
newline
hexmask.long.word 0x00 0.--11. 1. "CAL_IN,Calibration input When cal_byp is 1'b0 this represents the initial condition for calibration"
line.long 0x04 "CFG_pll0_CAL_STAT,"
bitfld.long 0x04 31. "CAL_LOCK,Reserved for future use" "0,1"
bitfld.long 0x04 16.--19. "LOCK_CNT,Reserved for future use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 0.--11. 1. "CAL_OUT,Output of the calibration block if cal_byp = 1'b0"
repeat 5. (list 0. 1. 2. 3. 4. )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x80)++0x03
line.long 0x00 "CFG_pll0_HSDIV_CTRL$1,"
bitfld.long 0x00 31. "RESET,SSM reset" "0,1"
bitfld.long 0x00 15. "CLKOUT_EN,CLKOUT1 enable" "Synchronously disable CLKOUT1,Synchronously enable CLKOUT1"
newline
bitfld.long 0x00 8. "SYNC_DIS,Disable divider synchronization logic" "Changes to DIV value synchronized to prevent..,Changes are asynchronous"
hexmask.long.byte 0x00 0.--6. 1. "HSDIV,CLKOUT0 divider value (HSDIV1+1) Allowed values are 0-127"
repeat.end
tree.end
tree "WKUP_PSC0"
base ad:0x4000000
rgroup.long 0x00++0x03
line.long 0x00 "VBUS_PID,The peripheral identification register is a constant register that contains the ID and ID revision number for that module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x10++0x0B
line.long 0x00 "VBUS_GBLCTL,This register contains global control to PSC"
hexmask.long.byte 0x00 8.--15. 1. "IO_ANA_CTL,General purpose IO/Analog PowerDown control"
line.long 0x04 "VBUS_GBLSTAT,This register shows the PSC global status"
hexmask.long.word 0x04 16.--27. 1. "EF_SMRFLEX,Smart reflex class0 bits"
bitfld.long 0x04 0. "OVRIDE,PSC Override Status" "0,1"
line.long 0x08 "VBUS_INTEVAL,This register has no storage"
bitfld.long 0x08 19. "GOSET,GOSTAT Interrupt Set" "0,1"
bitfld.long 0x08 18. "EPCSET,External Power Control Interrupt Set" "0,1"
bitfld.long 0x08 17. "ERRSET,Combined Interrupt Set" "0,1"
bitfld.long 0x08 2. "EPCEV,External Power Control Interrupt Set" "0,1"
bitfld.long 0x08 1. "ERREV,Re_evaluate Error Interrupt" "0,1"
bitfld.long 0x08 0. "ALLEV,Re_evaluate combined PSC interrupt" "0,1"
rgroup.long 0x40++0x03
line.long 0x00 "VBUS_MERRPR,This register records pending error conditions for all modules"
group.long 0x50++0x03
line.long 0x00 "VBUS_MERRCR,This register has no storage"
rgroup.long 0x60++0x03
line.long 0x00 "VBUS_PERRPR,This register records pending error conditions for each power domain"
group.long 0x68++0x03
line.long 0x00 "VBUS_PERRCR,This register has no storage"
rgroup.long 0x70++0x03
line.long 0x00 "VBUS_EPCPR,This register records pending external power control conditions"
group.long 0x78++0x03
line.long 0x00 "VBUS_EPCCR,This register has no storage"
rgroup.long 0x100++0x0B
line.long 0x00 "VBUS_RAILSTAT,This register is a read-only and shows the current rail requestor whose request is being granted and the current value of the counter associated with this requestor"
bitfld.long 0x00 24.--28. "RAILNUM,Indicates Current Rail Requestor being processed by GPSC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 0.--7. 1. "RAILCNT,Indicates the current rail counter value"
line.long 0x04 "VBUS_RAILCTL,This register is user programmable"
hexmask.long.byte 0x04 8.--15. 1. "RAILCTR1,Rail Counter Value 1"
hexmask.long.byte 0x04 0.--7. 1. "RAILCTR0,Rail Counter Value 0"
line.long 0x08 "VBUS_RAILSEL,User can use this register to select the counter value (RAILCTL) for each power domain"
group.long 0x120++0x03
line.long 0x00 "VBUS_PTCMD,This is a pseudo-command register with no actual storage"
rgroup.long 0x128++0x03
line.long 0x00 "VBUS_PTSTAT,This is a status register"
rgroup.long 0x200++0x03
line.long 0x00 "VBUS_PDSTAT,This is a status register"
bitfld.long 0x00 11. "EMUIHB,Emulation Alters Domain State" "0,1"
bitfld.long 0x00 10. "PWRBAD,Power Bad error" "0,1"
bitfld.long 0x00 9. "PORDONE,POR Done Input Status" "0,1"
bitfld.long 0x00 8. "PORZ,PORz output actual status" "0,1"
bitfld.long 0x00 0.--4. "STATE,Current Power Domain State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x300++0x03
line.long 0x00 "VBUS_PDCTL,This is a control register"
bitfld.long 0x00 31. "FORCE,Force Bit" "0,1"
bitfld.long 0x00 29. "PWRSW,Power shorting Switch Control" "0,1"
bitfld.long 0x00 28. "ISO,Isolation Cell control" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "WAKECNT,RAM wake count delay value"
bitfld.long 0x00 12.--14. "PDMODE,Power Down mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "EMUIHBIE,Emulation alters domain state" "0,1"
bitfld.long 0x00 8. "EPCGOOD,External Power Control Power Good Indication" "0,1"
bitfld.long 0x00 0. "NEXT,User_Desired Next Power Domain State" "0,1"
rgroup.long 0x400++0x03
line.long 0x00 "VBUS_PDCFG,This is a status register"
bitfld.long 0x00 3. "ICEPICK,Icepick support" "0,1"
bitfld.long 0x00 1. "MEMSLPKWK,Memory sleep-wake domain" "0,1"
bitfld.long 0x00 0. "ALWAYSON,Always on power domain" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "VBUS_MDCFG,This is a constant register showing some PSC settings for easy debug"
bitfld.long 0x00 16.--20. "PWRDOM,Indicates which power domain this module belongs to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 15. "AUTOONLY," "0,1"
bitfld.long 0x00 14. "RESETISO," "0,1"
bitfld.long 0x00 13. "NEXTLOCK," "0,1"
bitfld.long 0x00 12. "ASYNC,Async Lpsc" "0,1"
bitfld.long 0x00 11. "ICEPICK,IcePick support" "0,1"
bitfld.long 0x00 10. "PERMDIS,Permanently disable" "0,1"
bitfld.long 0x00 9. "PLLHANDSHAKE,RTL parameter PLL_HANDSHAKE" "0,1"
newline
bitfld.long 0x00 6.--8. "NUMSCRDISBALE,Number of PWR_SCR_DISABLE interfaces required on LPSC" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--5. "NUMCLKEN,Number of PWR_CLK_EN interfaces required on LPSC" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "NUMCLK,Number of PWR_CLKSTOP interfaces required on LPSC" "0,1,2,3,4,5,6,7"
rgroup.long 0x800++0x03
line.long 0x00 "VBUS_MDSTAT,This register shows the status of each module"
bitfld.long 0x00 17. "EMUIHB,Emulation Alters Module State" "0,1"
bitfld.long 0x00 16. "EMURST,Emulation Alters Reset" "0,1"
bitfld.long 0x00 12. "MCKOUT,Actual modclk output to module" "0,1"
bitfld.long 0x00 11. "MRSTDONE,Module reset initialization done status" "0,1"
bitfld.long 0x00 10. "MRSTZ,Module reset actual status" "0,1"
bitfld.long 0x00 9. "LRSTDONE,Module local reset initialization done status" "0,1"
bitfld.long 0x00 8. "LRSTZ,Module local reset actual status" "0,1"
bitfld.long 0x00 0.--5. "STATE,These bits indicate the current module state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xA00++0x03
line.long 0x00 "VBUS_MDCTL,This register provides specific control for the individual module"
bitfld.long 0x00 31. "FORCE,Force Bit" "0,1"
bitfld.long 0x00 12. "RESETISO,Reset Isolation" "0,1"
bitfld.long 0x00 11. "BLKCHIP1RST,Block Chip_1_Reset" "0,1"
bitfld.long 0x00 10. "EMUIHBIE,Emulation Alters Module State" "0,1"
bitfld.long 0x00 9. "EMURSTIE,Emulation Alter Reset Interrupt Enable" "0,1"
bitfld.long 0x00 8. "LRSTZ,Module local reset control" "0,1"
bitfld.long 0x00 0.--4. "NEXT,Module Next State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "WKUP_RTI0_CFG"
base ad:0x2B000000
group.long 0x00++0x1B
line.long 0x00 "CFG_GCTRL,"
bitfld.long 0x00 16.--19. "NTUSEL,These bits determine which NTU input signal is used as external timebase" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
bitfld.long 0x00 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting" "stop counters in debug mode,continue counting in debug mode"
newline
bitfld.long 0x00 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1)" "stop counters,start counters"
bitfld.long 0x00 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters"
line.long 0x04 "CFG_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "CFG_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
bitfld.long 0x08 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "CFG_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "CFG_FRC0,"
line.long 0x14 "CFG_UC0,"
line.long 0x18 "CFG_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "CFG_CAFRC0,"
line.long 0x04 "CFG_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "CFG_FRC1,"
line.long 0x04 "CFG_UC1,"
line.long 0x08 "CFG_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "CFG_CAFRC1,"
line.long 0x04 "CFG_CAUC1,"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x08 0x10 0x18 )
group.long ($2+0x50)++0x03
line.long 0x00 "CFG_COMP$1,"
repeat.end
group.long 0x54++0x03
line.long 0x00 "CFG_UDCP0,"
group.long 0x5C++0x03
line.long 0x00 "CFG_UDCP1,"
group.long 0x64++0x03
line.long 0x00 "CFG_UDCP2,"
group.long 0x6C++0x0B
line.long 0x00 "CFG_UDCP3,"
line.long 0x04 "CFG_TBLCOMP,"
line.long 0x08 "CFG_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "CFG_SETINT,"
bitfld.long 0x00 18. "SETOVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 17. "SETOVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 11. "SETDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 3. "SETINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 2. "SETINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 1. "SETINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 0. "SETINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "CFG_CLEARINT,"
bitfld.long 0x04 18. "CLEAROVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 17. "CLEAROVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 16. "CLEARTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 11. "CLEARDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 3. "CLEARINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 2. "CLEARINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 1. "CLEARINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 0. "CLEARINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "CFG_INTFLAG,"
bitfld.long 0x08 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 3. "INT3,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "CFG_DWDCTRL,"
line.long 0x04 "CFG_DWDPRLD,"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value"
line.long 0x08 "CFG_WDSTATUS,"
bitfld.long 0x08 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 1. "DWDST,status flag and is maintained for compatibility reasons" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 0. "AWDST,User and priviledge mode (read)" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "CFG_WDKEY,"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate"
line.long 0x10 "CFG_DWDCNTR,"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF"
line.long 0x14 "CFG_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,User and privilege mode (read) privileged mode (write)" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "CFG_WWDSIZECTRL,"
line.long 0x1C "CFG_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "CFG_COMP0CLR,"
line.long 0x24 "CFG_COMP1CLR,"
line.long 0x28 "CFG_COMP2CLR,"
line.long 0x2C "CFG_COMP3CLR,"
tree.end
tree "WKUP_TIMER0_CFG"
base ad:0x2B100000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "WKUP_TIMER1_CFG"
base ad:0x2B110000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
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bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
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bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
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bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "WKUP_UART0"
base ad:0x2B300000
group.long 0x00++0x03
line.long 0x00 "MEM_DLL,Divisor Latches Low Register"
hexmask.long.byte 0x00 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value"
rgroup.long 0x00++0x03
line.long 0x00 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
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hexmask.long.byte 0x00 0.--7. 1. "RHR,Receive holding register"
group.long 0x00++0x07
line.long 0x00 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
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hexmask.long.byte 0x00 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER"
line.long 0x04 "MEM_DLH,Divisor Latches High Register"
hexmask.long.byte 0x04 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value"
group.long 0x04++0x03
line.long 0x00 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt"
bitfld.long 0x00 6.--7. "NOT_USED2," "0,1,2,3"
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bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
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bitfld.long 0x00 4. "NOT_USED1," "0,1"
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bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
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bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
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bitfld.long 0x00 1. "THR_IT," "0,1"
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bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x03
line.long 0x00 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt"
bitfld.long 0x00 7. "EOF_IT," "0,1"
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bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
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bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
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bitfld.long 0x00 4. "STS_FIFO_TRIG_IT," "0,1"
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bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
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bitfld.long 0x00 2. "LAST_RX_BYTE_IT," "0,1"
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bitfld.long 0x00 1. "THR_IT," "0,1"
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bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x07
line.long 0x00 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
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bitfld.long 0x00 7. "CTS_IT," "0,1"
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bitfld.long 0x00 6. "RTS_IT," "0,1"
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bitfld.long 0x00 5. "XOFF_IT," "0,1"
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bitfld.long 0x00 4. "SLEEP_MODE," "0,1"
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bitfld.long 0x00 3. "MODEM_STS_IT," "0,1"
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bitfld.long 0x00 2. "LINE_STS_IT," "0,1"
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bitfld.long 0x00 1. "THR_IT," "0,1"
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bitfld.long 0x00 0. "RHR_IT," "0,1"
line.long 0x04 "MEM_EFR,Enhanced Feature Register"
bitfld.long 0x04 7. "AUTO_CTS_EN,Auto-CTS enable bit" "Normal operation,Auto-CTS flow control is enabled i.e"
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bitfld.long 0x04 6. "AUTO_RTS_EN,Auto-RTS enable bit" "Normal operation,Auto- RTS flow control is enabled i.e"
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bitfld.long 0x04 5. "SPECIAL_CHAR_DETECT," "0,1"
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bitfld.long 0x04 4. "ENHANCED_EN,Enhanced functions write enable bit" "Disables writing to IER bits 4-7 FCR bits 4-5..,Enables writing to IER bits 4-7 FCR bits 4-5 and.."
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bitfld.long 0x04 0.--3. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "MEM_FCR,Notes: Bits 4 and 5 can only be written to when EFR[4] = 1 Bits 0 to 3 can be changed only when the baud clock is not running (DLL and DLH set to 0) See Table 31 for FCR[5:4] setting restriction when SCR[6]=1 See Table 32 for FCR[7:6] setting.."
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
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bitfld.long 0x00 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] =" "8 characters,16 characters,56 characters,60 characters If SCR[7] = 0 and.."
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bitfld.long 0x00 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] =" "8 spaces,16 spaces,32 spaces,56 spaces If SCR[6] = 0.."
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bitfld.long 0x00 3. "DMA_MODE,This register is considered if SCR[0] = 0" "0,1"
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bitfld.long 0x00 2. "TX_FIFO_CLEAR," "0,1"
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bitfld.long 0x00 1. "RX_FIFO_CLEAR," "0,1"
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bitfld.long 0x00 0. "FIFO_EN," "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner"
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
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bitfld.long 0x00 3. "RX_OE_IT," "0,1"
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bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
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bitfld.long 0x00 1. "THR_IT," "0,1"
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bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner"
bitfld.long 0x00 7. "EOF_IT," "0,1"
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bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
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bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
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bitfld.long 0x00 4. "STS_FIFO_IT," "0,1"
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bitfld.long 0x00 3. "RX_OE_IT," "0,1"
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bitfld.long 0x00 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
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bitfld.long 0x00 1. "THR_IT," "0,1"
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bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x0B
line.long 0x00 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
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bitfld.long 0x00 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
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bitfld.long 0x00 1.--5. "IT_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "IT_PENDING," "0,1"
line.long 0x04 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception.Note: As soon as LCR[6] is set to 1. the TX line is forced to 0 and remains in this state as long as LCR[6] = 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
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bitfld.long 0x04 7. "DIV_EN," "0,1"
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bitfld.long 0x04 6. "BREAK_EN,Break control bit" "0,1"
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bitfld.long 0x04 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]" "0,1"
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bitfld.long 0x04 4. "PARITY_TYPE1," "0,1"
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bitfld.long 0x04 3. "PARITY_EN," "0,1"
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bitfld.long 0x04 2. "NB_STOP,Specifies the number of stop bits" "0,1"
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bitfld.long 0x04 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3"
line.long 0x08 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
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rbitfld.long 0x08 7. "RESERVED," "0,1"
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bitfld.long 0x08 6. "TCR_TLR," "0,1"
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bitfld.long 0x08 5. "XON_EN," "0,1"
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bitfld.long 0x08 4. "LOOPBACK_EN," "0,1"
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bitfld.long 0x08 3. "CD_STS_CH," "0,1"
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bitfld.long 0x08 2. "RI_STS_CH," "0,1"
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bitfld.long 0x08 1. "RTS,In loop back controls MSR[4]" "0,1"
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bitfld.long 0x08 0. "DTR," "0,1"
group.long 0x10++0x07
line.long 0x00 "MEM_XON1_ADDR1,XON1/ADDR1 Register"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes"
line.long 0x04 "MEM_LSR_CIR,"
bitfld.long 0x04 7. "THR_EMPTY," "0,1"
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bitfld.long 0x04 6. "RESERVED," "0,1"
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bitfld.long 0x04 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR)" "0,1"
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bitfld.long 0x04 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "MEM_LSR_IRDA,"
bitfld.long 0x00 7. "THR_EMPTY," "0,1"
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bitfld.long 0x00 6. "STS_FIFO_FULL," "0,1"
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bitfld.long 0x00 5. "RX_LAST_BYTE," "0,1"
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bitfld.long 0x00 4. "FRAME_TOO_LONG," "0,1"
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bitfld.long 0x00 3. "ABORT," "0,1"
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bitfld.long 0x00 2. "CRC," "0,1"
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bitfld.long 0x00 1. "STS_FIFO_E," "0,1"
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bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "MEM_LSR_UART,"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
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bitfld.long 0x00 7. "RX_FIFO_STS," "0,1"
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bitfld.long 0x00 6. "TX_SR_E," "0,1"
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bitfld.long 0x00 5. "TX_FIFO_E," "0,1"
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bitfld.long 0x00 4. "RX_BI," "0,1"
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bitfld.long 0x00 3. "RX_FE," "0,1"
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bitfld.long 0x00 2. "RX_PE," "0,1"
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bitfld.long 0x00 1. "RX_OE," "0,1"
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bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x07
line.long 0x00 "MEM_XON2_ADDR2,XON2/ADDR2 Register"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes"
line.long 0x04 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "NCD_STS,This bit is the complement of the DCD* input" "0,1"
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bitfld.long 0x04 6. "NRI_STS,This bit is the complement of the RI* input" "0,1"
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bitfld.long 0x04 5. "NDSR_STS,This bit is the complement of the DSR* input" "0,1"
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bitfld.long 0x04 4. "NCTS_STS,This bit is the complement of the CTS* input" "0,1"
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bitfld.long 0x04 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed" "0,1"
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bitfld.long 0x04 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high" "0,1"
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bitfld.long 0x04 1. "DSR_STS," "0,1"
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bitfld.long 0x04 0. "CTS_STS," "0,1"
group.long 0x18++0x03
line.long 0x00 "MEM_TCR,Transmission Control Register"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x07
line.long 0x00 "MEM_XOFF1,XOFF1 Register"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes"
line.long 0x04 "MEM_SPR,This read/write register does not control the module in anyway"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
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hexmask.long.byte 0x04 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x03
line.long 0x00 "MEM_TLR,Trigger Level Register"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x0F
line.long 0x00 "MEM_XOFF2,XOFF2 Register"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes"
line.long 0x04 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR)"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "FRAME_END_MODE,IrDA mode only" "0,1"
newline
bitfld.long 0x04 6. "SIP_MODE,MIR/FIR modes only" "0,1"
newline
bitfld.long 0x04 5. "SCT,Store and control the transmission" "0,1"
newline
bitfld.long 0x04 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1"
newline
bitfld.long 0x04 3. "IR_SLEEP," "0,1"
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bitfld.long 0x04 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7"
line.long 0x08 "MEM_MDR2,IR-IrDA and IR-CIR modes only.MDR2[0] describes the status of the interrupt in IIR[5]"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x08 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1"
newline
bitfld.long 0x08 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block" "0,1"
newline
bitfld.long 0x08 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition" "0,1,2,3"
newline
bitfld.long 0x08 3. "UART_PULSE,UART mode only" "0,1"
newline
bitfld.long 0x08 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode" "0,1,2,3"
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rbitfld.long 0x08 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is" "0,1"
line.long 0x0C "MEM_SFLSR,IrDA modes only.Reading this register effectively reads frame status information from the status FIFO (this register doesn't physically exist)"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0C 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 4. "OE_ERROR," "0,1"
newline
bitfld.long 0x0C 3. "FRAME_TOO_LONG_ERROR," "0,1"
newline
bitfld.long 0x0C 2. "ABORT_DETECT," "0,1"
newline
bitfld.long 0x0C 1. "CRC_ERROR," "0,1"
newline
bitfld.long 0x0C 0. "RESERVED0," "0,1"
group.long 0x28++0x07
line.long 0x00 "MEM_TXFLL,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes)"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
line.long 0x04 "MEM_RESUME,IR-IrDA and IR-CIR modes only.This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x04 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x07
line.long 0x00 "MEM_TXFLH,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes)"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "TXFLH,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "MEM_RXFLL,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x04 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x07
line.long 0x00 "MEM_SFREGL,IrDA modes only.The frame lengths of received frames are written into the status FIFO"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "SFREGL,LSB part of the frame length"
line.long 0x04 "MEM_RXFLH,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x04 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--3. "RXFLH,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x34++0x07
line.long 0x00 "MEM_SFREGH,IrDA modes only.The frame lengths of received frames are written into the status FIFO"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "SFREGH,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MEM_BLR,IrDA modes only.Note that BLR[6] is used to select whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR Mode"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "STS_FIFO_RESET,Status FIFO reset" "0,1"
newline
bitfld.long 0x04 6. "XBOF_TYPE,SIR xBOF select" "0,1"
newline
rbitfld.long 0x04 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x38++0x13
line.long 0x00 "MEM_UASR,UART Autobauding Status Register"
bitfld.long 0x00 6.--7. "PARITY_TYPE," "?,Parity space,Even Parity,Odd Parity"
newline
bitfld.long 0x00 5. "BIT_BY_CHAR," "0,1"
newline
bitfld.long 0x00 0.--4. "SPEED,Used to report the speed identified" "No speed identified,115200 bauds,57600 bauds,38400 bauds,28800 bauds,19200 bauds,14400 bauds,9600 bauds,4800 bauds,2400 bauds,1200 bauds,?..."
line.long 0x04 "MEM_ACREG,IR-IrDA and IR-CIR modes only"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "PULSE_TYPE,SIR pulse width select" "0,1"
newline
bitfld.long 0x04 6. "SD_MOD,Primary output used to configure transceivers" "0,1"
newline
bitfld.long 0x04 5. "DIS_IR_RX," "0,1"
newline
bitfld.long 0x04 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt" "0,1"
newline
bitfld.long 0x04 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission" "0,1"
newline
bitfld.long 0x04 2. "SCTX_EN,Store and controlled TX start" "0,1"
newline
bitfld.long 0x04 1. "ABORT_EN,Frame Abort" "0,1"
newline
bitfld.long 0x04 0. "EOT_EN,EOT [end of transmission] bit" "0,1"
line.long 0x08 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x08 7. "RX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x08 6. "TX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x08 5. "DSR_IT," "0,1"
newline
bitfld.long 0x08 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1"
newline
bitfld.long 0x08 3. "TX_EMPTY_CTL_IT," "0,1"
newline
bitfld.long 0x08 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3"
newline
bitfld.long 0x08 0. "DMA_MODE_CTL," "0,1"
line.long 0x0C "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0C 3.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 2. "DMA_COUNTER_RST," "0,1"
newline
rbitfld.long 0x0C 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1"
newline
rbitfld.long 0x0C 0. "TX_FIFO_FULL," "0,1"
line.long 0x10 "MEM_EBLR,IR-IrDA and IR-CIR modes only.In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,"
newline
abitfld.long 0x10 0.--7. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification" "0x00=feature disabled,0x01=generate RX_STOP interrupt after receiving..,0xFF=generate RX_STOP interrupt after receiving.."
rgroup.long 0x50++0x57
line.long 0x00 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module"
bitfld.long 0x00 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function revision number of module"
newline
bitfld.long 0x00 11.--15. "RTL,Rtl revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x04 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3"
newline
bitfld.long 0x04 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1"
newline
bitfld.long 0x04 1. "SOFTRESET,Software reset" "0,1"
newline
bitfld.long 0x04 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
line.long 0x08 "MEM_SYSS,"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x08 1.--7. 1. "RESERVED,"
newline
bitfld.long 0x08 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x0C "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0C 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
newline
bitfld.long 0x0C 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0C 5. "EVENT_5_RHR_INTERRUPT," "0,1"
newline
bitfld.long 0x0C 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 1. "EVENT_1_DSR_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x10 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x10 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]"
line.long 0x14 "MEM_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x14 0.--7. 1. "RXFIFO_LVL,"
line.long 0x18 "MEM_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x18 0.--7. 1. "TXFIFO_LVL,"
line.long 0x1C "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x1C 3.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 2. "RHR_IT_DIS," "0,1"
newline
bitfld.long 0x1C 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt" "0,1"
newline
bitfld.long 0x1C 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt" "0,1"
line.long 0x20 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x20 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x20 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1"
newline
bitfld.long 0x20 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1"
line.long 0x24 "MEM_FREQ_SEL,Sample per bit value selector"
hexmask.long.byte 0x24 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used"
line.long 0x28 "MEM_ABAUD_1ST_CHAR,Unused"
line.long 0x2C "MEM_BAUD_2ND_CHAR,Unused"
line.long 0x30 "MEM_MDR3,Mode definition register 3"
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED2,"
newline
bitfld.long 0x30 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
newline
bitfld.long 0x30 3. "DIR_POL,RS-485 External Transceiver Direction Polarity" "TX,TX"
newline
bitfld.long 0x30 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1"
newline
bitfld.long 0x30 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x30 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1"
line.long 0x34 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level.MDR3[2] SET_TX_DMA_THRESHOLD must be one and must be value + tx_trigger_level <= 64 (TX FIFO size).If not. 64-tx_trigger_level will be used w/o modifying the value of this register"
bitfld.long 0x34 0.--5. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "MEM_MDR4,Mode definition register 4"
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x38 7. "RESERVED," "0,1"
newline
bitfld.long 0x38 6. "MODE9,9-bit character length" "0,1"
newline
bitfld.long 0x38 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7"
line.long 0x3C "MEM_EFR2,Enhanced Features Register 2"
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0x3C 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
newline
bitfld.long 0x3C 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
newline
bitfld.long 0x3C 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
newline
bitfld.long 0x3C 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
newline
bitfld.long 0x3C 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
newline
bitfld.long 0x3C 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1"
newline
bitfld.long 0x3C 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1"
newline
bitfld.long 0x3C 0. "ENDIAN,Endianness" "0,1"
line.long 0x40 "MEM_ECR,Enhanced Control register"
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x40 6.--7. "RESERVED," "0,1,2,3"
newline
bitfld.long 0x40 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
newline
bitfld.long 0x40 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x40 3. "RX_EN,Enables/Disables the receiver" "0,1"
newline
bitfld.long 0x40 2. "TX_RST,Writing '1' resets the transmitter" "0,1"
newline
bitfld.long 0x40 1. "RX_RST,Writing '1' resets the receiver" "0,1"
newline
bitfld.long 0x40 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1"
line.long 0x44 "MEM_TIMEGUARD,Timeguard"
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x44 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices"
line.long 0x48 "MEM_TIMEOUTL,Timeout lower byte"
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x48 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0"
line.long 0x4C "MEM_TIMEOUTH,Timeout higher byte"
hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0"
line.long 0x50 "MEM_SCCR,Smartcard (ISO7816) mode Control Register"
hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0x50 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error" "0,1"
newline
bitfld.long 0x50 6. "INACK,Inhibit NACK when receiving even if an error is received" "0,1"
newline
rbitfld.long 0x50 3.--5. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x50 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge" "0,1,2,3,4,5,6,7"
line.long 0x54 "MEM_ERHR,Extended Receive Holding Register"
hexmask.long.tbyte 0x54 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x54 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR"
group.long 0xA4++0x0F
line.long 0x00 "MEM_ETHR,Extended Transmit Holding Register"
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x00 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR"
line.long 0x04 "MEM_MAR,Multidrop Address Register"
hexmask.long.byte 0x04 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x08 "MEM_MMR,Multidrop Mask Register"
hexmask.long.byte 0x08 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0x0C "MEM_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0x0C 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
endif
sif (cpuis("AM62*X-CR5"))
tree "CBASS_MISC_PERI0_ERR"
base ad:0x201F0000
rgroup.long 0x00++0x07
line.long 0x00 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "CTRL_MMR0_CFG0"
base ad:0x100000
rgroup.long 0x00++0x03
line.long 0x00 "CFG0_PID,"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16,"
newline
bitfld.long 0x00 11.--15. "PID_MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "PID_CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x08++0x03
line.long 0x00 "CFG0_MMR_CFG1,"
bitfld.long 0x00 31. "MMR_CFG1_PROXY_EN,Proxy addressing activated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions"
group.long 0x1008++0x2B
line.long 0x00 "CFG0_LOCK0_KICK0,"
line.long 0x04 "CFG0_LOCK0_KICK1,"
line.long 0x08 "CFG0_intr_raw_status,"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "CFG0_intr_enabled_status_clear,"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "CFG0_intr_enable,"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "CFG0_intr_enable_clear,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "CFG0_eoi,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value"
line.long 0x1C "CFG0_fault_address,"
line.long 0x20 "CFG0_fault_type_status,"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "CFG0_fault_attr_status,"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "CFG0_fault_clear,"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
rgroup.long 0x1100++0x1B
line.long 0x00 "CFG0_CLAIMREG_P0_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P0_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P0_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P0_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P0_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P0_R5_READONLY,"
line.long 0x18 "CFG0_CLAIMREG_P0_R6_READONLY,"
rgroup.long 0x2000++0x03
line.long 0x00 "CFG0_PID_PROXY,"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16_PROXY,"
newline
bitfld.long 0x00 11.--15. "PID_MISC_PROXY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR_PROXY," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "PID_CUSTOM_PROXY," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR_PROXY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x2008++0x03
line.long 0x00 "CFG0_MMR_CFG1_PROXY,"
bitfld.long 0x00 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing activated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions"
group.long 0x3008++0x2B
line.long 0x00 "CFG0_LOCK0_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK0_KICK1_PROXY,"
line.long 0x08 "CFG0_intr_raw_status_PROXY,"
bitfld.long 0x08 3. "PROXY_ERR_PROXY,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR_PROXY,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR_PROXY,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR_PROXY,Protection violation error" "0,1"
line.long 0x0C "CFG0_intr_enabled_status_clear_PROXY,"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR_PROXY,Protection violation error" "0,1"
line.long 0x10 "CFG0_intr_enable_PROXY,"
bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable" "0,1"
line.long 0x14 "CFG0_intr_enable_clear_PROXY,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear" "0,1"
line.long 0x18 "CFG0_eoi_PROXY,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value"
line.long 0x1C "CFG0_fault_address_PROXY,"
line.long 0x20 "CFG0_fault_type_status_PROXY,"
bitfld.long 0x20 6. "FAULT_NS_PROXY,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE_PROXY,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "CFG0_fault_attr_status_PROXY,"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID_PROXY,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID"
line.long 0x28 "CFG0_fault_clear_PROXY,"
bitfld.long 0x28 0. "FAULT_CLR_PROXY,Fault clear" "0,1"
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x3100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P0_R$1,"
repeat.end
group.long 0x4044++0x07
line.long 0x00 "CFG0_ENET1_CTRL,"
bitfld.long 0x00 4. "ENET1_CTRL_RGMII_ID_MODE,Port1 RGMII internal transmit delay selection" "Internal transmit delay,No intenal transmit delay"
newline
bitfld.long 0x00 0.--2. "ENET1_CTRL_PORT_MODE_SEL,Selects Ethernet switch Port1 interface Field values (others are reserved)" "GMII/MII (not supported),RMII,RGMII,SGMII (not supported),QSGMII (not supported),XFI (not supported),QSGMII_SUB (not supported),Reserved"
line.long 0x04 "CFG0_ENET2_CTRL,"
bitfld.long 0x04 4. "ENET2_CTRL_RGMII_ID_MODE,Port2 RGMII internal transmit delay selection" "Internal transmit delay,No intenal transmit delay"
newline
bitfld.long 0x04 0.--2. "ENET2_CTRL_PORT_MODE_SEL,Selects Ethernet switch Port2 interface Field values (others are reserved)" "GMII/MII (not supported),RMII,RGMII,SGMII (not supported),QSGMII (not supported),XFI (not supported),QSGMII_SUB (not supported),Reserved"
group.long 0x4100++0x03
line.long 0x00 "CFG0_ICSSM0_CTRL0,"
abitfld.long 0x00 0.--19. "ICSSM0_CTRL0_GPM_BIDI,Controls operation of the ICSSM0 PRU0_GPO pins" "0x00000=In GPO mode pin n functions as GPM..,0x00001=In GPO mode pin n functions as GPM.."
group.long 0x4130++0x03
line.long 0x00 "CFG0_EPWM_TB_CLKEN,"
bitfld.long 0x00 2. "EPWM_TB_CLKEN_EPWM2_TB_CLKEN,Activates Timebase Clock of EPWM2 When Set" "0,1"
newline
bitfld.long 0x00 1. "EPWM_TB_CLKEN_EPWM1_TB_CLKEN,Activates Timebase Clock of EPWM1 When Set" "0,1"
newline
bitfld.long 0x00 0. "EPWM_TB_CLKEN_EPWM0_TB_CLKEN,Activates Timebase Clock of EPWM0 When Set" "0,1"
group.long 0x4140++0x0B
line.long 0x00 "CFG0_EPWM0_CTRL,"
bitfld.long 0x00 8.--10. "EPWM0_CTRL_SYNCIN_SEL,Selects the source of the EPWM0 synchronization input Field values (others are reserved)" "EPWM0_SYNCIN Pin,None,Time Sync Router 19,Compare Event Router 32,ICSSM Host Interrupt 6,None,None,None"
newline
bitfld.long 0x00 4. "EPWM0_CTRL_EALLOW,Activate write access to EPWM tripzone registers" "Deactivated,Activated"
line.long 0x04 "CFG0_EPWM1_CTRL,"
bitfld.long 0x04 4. "EPWM1_CTRL_EALLOW,Activate write access to EPWM tripzone registers" "Deactivated,Activated"
line.long 0x08 "CFG0_EPWM2_CTRL,"
bitfld.long 0x08 4. "EPWM2_CTRL_EALLOW,Activate write access to EPWM tripzone registers" "Deactivated,Activated"
group.long 0x4170++0x07
line.long 0x00 "CFG0_SOCA_SEL,"
bitfld.long 0x00 0.--1. "SOCA_SEL_SOCA_SEL,Selects the SOC A output source Field values (others are reserved)" "OR of all EPWM SOCA outputs,ICSSM Host Interrupt 1,None,None"
line.long 0x04 "CFG0_SOCB_SEL,"
bitfld.long 0x04 0.--1. "SOCB_SEL_SOCB_SEL,Selects the SOC B output source Field values (others are reserved)" "OR of all EPWM SOCB ouputs,ICSSM Host Interrupt 1,None,None"
group.long 0x4180++0x0B
line.long 0x00 "CFG0_EQEP0_CTRL,"
bitfld.long 0x00 0.--4. "EQEP0_CTRL_SOCA_SEL,Selects the source of SOCA input for EQEP0 Field values (others are reserved): undefined - undefined undefined - undefined" "?,?,EPWM SOCA_OUT,EPWM SOCB_OUT,MCU_TIMER0 PWM,MCU_TIMER1 PWM,MCU_TIMER2 PWM,MCU_TIMER3 PWM,TIMER0 PWM,TIMER1 PWM,TIMER2 PWM,TIMER3 PWM,TIMER4 PWM,TIMER5 PWM,TIMER6 PWM,TIMER7 PWM,WKUP TIMER0 PWM,WKUP TIMER1 PWM,?,?,ICSSM PR1 IEP0,?,?,?,ICSSM PR1 HOST INTR PEND4,ICSSM PR1 HOST INTR PEND5,?..."
line.long 0x04 "CFG0_EQEP1_CTRL,"
bitfld.long 0x04 0.--4. "EQEP1_CTRL_SOCA_SEL,Selects the source of SOCA input for EQEP1 Field values (others are reserved): undefined - undefined undefined - undefined" "?,?,EPWM SOCA_OUT,EPWM SOCB_OUT,MCU_TIMER0 PWM,MCU_TIMER1 PWM,MCU_TIMER2 PWM,MCU_TIMER3 PWM,TIMER0 PWM,TIMER1 PWM,TIMER2 PWM,TIMER3 PWM,TIMER4 PWM,TIMER5 PWM,TIMER6 PWM,TIMER7 PWM,WKUP TIMER0 PWM,WKUP TIMER1 PWM,?,?,ICSSM PR1 IEP0,?,?,?,ICSSM PR1 HOST INTR PEND4,ICSSM PR1 HOST INTR PEND5,?..."
line.long 0x08 "CFG0_EQEP2_CTRL,"
bitfld.long 0x08 0.--4. "EQEP2_CTRL_SOCA_SEL,Selects the source of SOCA input for EQEP2 Field values (others are reserved): undefined - undefined undefined - undefined" "?,?,EPWM SOCA_OUT,EPWM SOCB_OUT,MCU_TIMER0 PWM,MCU_TIMER1 PWM,MCU_TIMER2 PWM,MCU_TIMER3 PWM,TIMER0 PWM,TIMER1 PWM,TIMER2 PWM,TIMER3 PWM,TIMER4 PWM,TIMER5 PWM,TIMER6 PWM,TIMER7 PWM,WKUP TIMER0 PWM,WKUP TIMER1 PWM,?,?,ICSSM PR1 IEP0,?,?,?,ICSSM PR1 HOST INTR PEND4,ICSSM PR1 HOST INTR PEND5,?..."
rgroup.long 0x41A0++0x03
line.long 0x00 "CFG0_EQEP_STAT,"
bitfld.long 0x00 2. "EQEP_STAT_PHASE_ERR2,EQEP2 Phase error status" "No error,Phase error occurred"
newline
bitfld.long 0x00 1. "EQEP_STAT_PHASE_ERR1,EQEP1 Phase error status" "No error,Phase error occurred"
newline
bitfld.long 0x00 0. "EQEP_STAT_PHASE_ERR0,EQEP0 Phase error status" "No error,Phase error occurred"
group.long 0x4204++0x03
line.long 0x00 "CFG0_TIMER1_CTRL,"
bitfld.long 0x00 8. "TIMER1_CTRL_CASCADE_EN,Activates cascading of TIMER1 to TIMER0" "0,1"
group.long 0x420C++0x03
line.long 0x00 "CFG0_TIMER3_CTRL,"
bitfld.long 0x00 8. "TIMER3_CTRL_CASCADE_EN,Activates cascading of TIMER3 to TIMER2" "0,1"
group.long 0x4214++0x03
line.long 0x00 "CFG0_TIMER5_CTRL,"
bitfld.long 0x00 8. "TIMER5_CTRL_CASCADE_EN,Activates cascading of TIMER5 to TIMER4" "0,1"
group.long 0x421C++0x03
line.long 0x00 "CFG0_TIMER7_CTRL,"
bitfld.long 0x00 8. "TIMER7_CTRL_CASCADE_EN,Activates cascading of TIMER7 to TIMER6" "0,1"
rgroup.long 0x44C0++0x0B
line.long 0x00 "CFG0_EMMC0_STAT,"
bitfld.long 0x00 0. "EMMC0_STAT_SIG1P8_EN,Status of 1.8V Signal Activate from EMMC0 Module" "0,1"
line.long 0x04 "CFG0_EMMC1_STAT,"
bitfld.long 0x04 0. "EMMC1_STAT_SIG1P8_EN,Status of 1.8V Signal Activate from EMMC1 Module" "0,1"
line.long 0x08 "CFG0_EMMC2_STAT,"
bitfld.long 0x08 0. "EMMC2_STAT_SIG1P8_EN,Status of 1.8V Signal Activate from EMMC2 Module" "0,1"
group.long 0x4700++0x03
line.long 0x00 "CFG0_FSS_CTRL,"
bitfld.long 0x00 8. "FSS_CTRL_S0_BOOT_SIZE,Selects the size of the boot block to be used for the S0 (OSPI0) flash interface" "S0 boot size is 64 MB,S0 boot size is 128 MB"
newline
bitfld.long 0x00 0.--5. "FSS_CTRL_S0_BOOT_SEG,Selects the boot block to be used for the S0 (OSPI0) flash interface" "Use block 0,Use block,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Use block 63"
rgroup.long 0x4750++0x03
line.long 0x00 "CFG0_DCC_STAT,"
bitfld.long 0x00 16. "DCC_STAT_MCU_DCC0_INTR_DONE,MCU_DCC0 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 6. "DCC_STAT_DCC6_INTR_DONE,DCC6 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 5. "DCC_STAT_DCC5_INTR_DONE,DCC5 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 4. "DCC_STAT_DCC4_INTR_DONE,DCC4 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 3. "DCC_STAT_DCC3_INTR_DONE,DCC3 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 2. "DCC_STAT_DCC2_INTR_DONE,DCC2 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 1. "DCC_STAT_DCC1_INTR_DONE,DCC1 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 0. "DCC_STAT_DCC0_INTR_DONE,DCC0 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
group.long 0x5008++0x07
line.long 0x00 "CFG0_LOCK1_KICK0,"
line.long 0x04 "CFG0_LOCK1_KICK1,"
rgroup.long 0x5100++0x3B
line.long 0x00 "CFG0_CLAIMREG_P1_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P1_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P1_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P1_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P1_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P1_R5_READONLY,"
line.long 0x18 "CFG0_CLAIMREG_P1_R6_READONLY,"
line.long 0x1C "CFG0_CLAIMREG_P1_R7_READONLY,"
line.long 0x20 "CFG0_CLAIMREG_P1_R8_READONLY,"
line.long 0x24 "CFG0_CLAIMREG_P1_R9_READONLY,"
line.long 0x28 "CFG0_CLAIMREG_P1_R10_READONLY,"
line.long 0x2C "CFG0_CLAIMREG_P1_R11_READONLY,"
line.long 0x30 "CFG0_CLAIMREG_P1_R12_READONLY,"
line.long 0x34 "CFG0_CLAIMREG_P1_R13_READONLY,"
line.long 0x38 "CFG0_CLAIMREG_P1_R14_READONLY,"
group.long 0x6044++0x07
line.long 0x00 "CFG0_ENET1_CTRL_PROXY,"
bitfld.long 0x00 4. "ENET1_CTRL_RGMII_ID_MODE_PROXY,Port1 RGMII internal transmit delay selection" "Internal transmit delay,No intenal transmit delay"
newline
bitfld.long 0x00 0.--2. "ENET1_CTRL_PORT_MODE_SEL_PROXY,Selects Ethernet switch Port1 interface Field values (others are reserved)" "GMII/MII (not supported),RMII,RGMII,SGMII (not supported),QSGMII (not supported),XFI (not supported),QSGMII_SUB (not supported),Reserved"
line.long 0x04 "CFG0_ENET2_CTRL_PROXY,"
bitfld.long 0x04 4. "ENET2_CTRL_RGMII_ID_MODE_PROXY,Port2 RGMII internal transmit delay selection" "Internal transmit delay,No intenal transmit delay"
newline
bitfld.long 0x04 0.--2. "ENET2_CTRL_PORT_MODE_SEL_PROXY,Selects Ethernet switch Port2 interface Field values (others are reserved)" "GMII/MII (not supported),RMII,RGMII,SGMII (not supported),QSGMII (not supported),XFI (not supported),QSGMII_SUB (not supported),Reserved"
group.long 0x6100++0x03
line.long 0x00 "CFG0_ICSSM0_CTRL0_PROXY,"
abitfld.long 0x00 0.--19. "ICSSM0_CTRL0_GPM_BIDI_PROXY,Controls operation of the ICSSM0 PRU0_GPO pins" "0x00000=In GPO mode pin n functions as GPM..,0x00001=In GPO mode pin n functions as GPM.."
group.long 0x6130++0x03
line.long 0x00 "CFG0_EPWM_TB_CLKEN_PROXY,"
bitfld.long 0x00 2. "EPWM_TB_CLKEN_EPWM2_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM2 When Set" "0,1"
newline
bitfld.long 0x00 1. "EPWM_TB_CLKEN_EPWM1_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM1 When Set" "0,1"
newline
bitfld.long 0x00 0. "EPWM_TB_CLKEN_EPWM0_TB_CLKEN_PROXY,Activates Timebase Clock of EPWM0 When Set" "0,1"
group.long 0x6140++0x0B
line.long 0x00 "CFG0_EPWM0_CTRL_PROXY,"
bitfld.long 0x00 8.--10. "EPWM0_CTRL_SYNCIN_SEL_PROXY,Selects the source of the EPWM0 synchronization input Field values (others are reserved)" "EPWM0_SYNCIN Pin,None,Time Sync Router 19,Compare Event Router 32,ICSSM Host Interrupt 6,None,None,None"
newline
bitfld.long 0x00 4. "EPWM0_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers" "Deactivated,Activated"
line.long 0x04 "CFG0_EPWM1_CTRL_PROXY,"
bitfld.long 0x04 4. "EPWM1_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers" "Deactivated,Activated"
line.long 0x08 "CFG0_EPWM2_CTRL_PROXY,"
bitfld.long 0x08 4. "EPWM2_CTRL_EALLOW_PROXY,Activate write access to EPWM tripzone registers" "Deactivated,Activated"
group.long 0x6170++0x07
line.long 0x00 "CFG0_SOCA_SEL_PROXY,"
bitfld.long 0x00 0.--1. "SOCA_SEL_SOCA_SEL_PROXY,Selects the SOC A output source Field values (others are reserved)" "OR of all EPWM SOCA outputs,ICSSM Host Interrupt 1,None,None"
line.long 0x04 "CFG0_SOCB_SEL_PROXY,"
bitfld.long 0x04 0.--1. "SOCB_SEL_SOCB_SEL_PROXY,Selects the SOC B output source Field values (others are reserved)" "OR of all EPWM SOCB ouputs,ICSSM Host Interrupt 1,None,None"
group.long 0x6180++0x0B
line.long 0x00 "CFG0_EQEP0_CTRL_PROXY,"
bitfld.long 0x00 0.--4. "EQEP0_CTRL_SOCA_SEL_PROXY,Selects the source of SOCA input for EQEP0 Field values (others are reserved): undefined - undefined undefined - undefined" "?,?,EPWM SOCA_OUT,EPWM SOCB_OUT,MCU_TIMER0 PWM,MCU_TIMER1 PWM,MCU_TIMER2 PWM,MCU_TIMER3 PWM,TIMER0 PWM,TIMER1 PWM,TIMER2 PWM,TIMER3 PWM,TIMER4 PWM,TIMER5 PWM,TIMER6 PWM,TIMER7 PWM,WKUP TIMER0 PWM,WKUP TIMER1 PWM,?,?,ICSSM PR1 IEP0,?,?,?,ICSSM PR1 HOST INTR PEND4,ICSSM PR1 HOST INTR PEND5,?..."
line.long 0x04 "CFG0_EQEP1_CTRL_PROXY,"
bitfld.long 0x04 0.--4. "EQEP1_CTRL_SOCA_SEL_PROXY,Selects the source of SOCA input for EQEP1 Field values (others are reserved): undefined - undefined undefined - undefined" "?,?,EPWM SOCA_OUT,EPWM SOCB_OUT,MCU_TIMER0 PWM,MCU_TIMER1 PWM,MCU_TIMER2 PWM,MCU_TIMER3 PWM,TIMER0 PWM,TIMER1 PWM,TIMER2 PWM,TIMER3 PWM,TIMER4 PWM,TIMER5 PWM,TIMER6 PWM,TIMER7 PWM,WKUP TIMER0 PWM,WKUP TIMER1 PWM,?,?,ICSSM PR1 IEP0,?,?,?,ICSSM PR1 HOST INTR PEND4,ICSSM PR1 HOST INTR PEND5,?..."
line.long 0x08 "CFG0_EQEP2_CTRL_PROXY,"
bitfld.long 0x08 0.--4. "EQEP2_CTRL_SOCA_SEL_PROXY,Selects the source of SOCA input for EQEP2 Field values (others are reserved): undefined - undefined undefined - undefined" "?,?,EPWM SOCA_OUT,EPWM SOCB_OUT,MCU_TIMER0 PWM,MCU_TIMER1 PWM,MCU_TIMER2 PWM,MCU_TIMER3 PWM,TIMER0 PWM,TIMER1 PWM,TIMER2 PWM,TIMER3 PWM,TIMER4 PWM,TIMER5 PWM,TIMER6 PWM,TIMER7 PWM,WKUP TIMER0 PWM,WKUP TIMER1 PWM,?,?,ICSSM PR1 IEP0,?,?,?,ICSSM PR1 HOST INTR PEND4,ICSSM PR1 HOST INTR PEND5,?..."
rgroup.long 0x61A0++0x03
line.long 0x00 "CFG0_EQEP_STAT_PROXY,"
bitfld.long 0x00 2. "EQEP_STAT_PHASE_ERR2_PROXY,EQEP2 Phase error status" "No error,Phase error occurred"
newline
bitfld.long 0x00 1. "EQEP_STAT_PHASE_ERR1_PROXY,EQEP1 Phase error status" "No error,Phase error occurred"
newline
bitfld.long 0x00 0. "EQEP_STAT_PHASE_ERR0_PROXY,EQEP0 Phase error status" "No error,Phase error occurred"
group.long 0x6204++0x03
line.long 0x00 "CFG0_TIMER1_CTRL_PROXY,"
bitfld.long 0x00 8. "TIMER1_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER1 to TIMER0" "0,1"
group.long 0x620C++0x03
line.long 0x00 "CFG0_TIMER3_CTRL_PROXY,"
bitfld.long 0x00 8. "TIMER3_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER3 to TIMER2" "0,1"
group.long 0x6214++0x03
line.long 0x00 "CFG0_TIMER5_CTRL_PROXY,"
bitfld.long 0x00 8. "TIMER5_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER5 to TIMER4" "0,1"
group.long 0x621C++0x03
line.long 0x00 "CFG0_TIMER7_CTRL_PROXY,"
bitfld.long 0x00 8. "TIMER7_CTRL_CASCADE_EN_PROXY,Activates cascading of TIMER7 to TIMER6" "0,1"
rgroup.long 0x64C0++0x0B
line.long 0x00 "CFG0_EMMC0_STAT_PROXY,"
bitfld.long 0x00 0. "EMMC0_STAT_SIG1P8_EN_PROXY,Status of 1.8V Signal Activate from EMMC0 Module" "0,1"
line.long 0x04 "CFG0_EMMC1_STAT_PROXY,"
bitfld.long 0x04 0. "EMMC1_STAT_SIG1P8_EN_PROXY,Status of 1.8V Signal Activate from EMMC1 Module" "0,1"
line.long 0x08 "CFG0_EMMC2_STAT_PROXY,"
bitfld.long 0x08 0. "EMMC2_STAT_SIG1P8_EN_PROXY,Status of 1.8V Signal Activate from EMMC2 Module" "0,1"
group.long 0x6700++0x03
line.long 0x00 "CFG0_FSS_CTRL_PROXY,"
bitfld.long 0x00 8. "FSS_CTRL_S0_BOOT_SIZE_PROXY,Selects the size of the boot block to be used for the S0 (OSPI0) flash interface" "S0 boot size is 64 MB,S0 boot size is 128 MB"
newline
bitfld.long 0x00 0.--5. "FSS_CTRL_S0_BOOT_SEG_PROXY,Selects the boot block to be used for the S0 (OSPI0) flash interface" "Use block 0,Use block,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Use block 63"
rgroup.long 0x6750++0x03
line.long 0x00 "CFG0_DCC_STAT_PROXY,"
bitfld.long 0x00 16. "DCC_STAT_MCU_DCC0_INTR_DONE_PROXY,MCU_DCC0 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 6. "DCC_STAT_DCC6_INTR_DONE_PROXY,DCC6 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 5. "DCC_STAT_DCC5_INTR_DONE_PROXY,DCC5 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 4. "DCC_STAT_DCC4_INTR_DONE_PROXY,DCC4 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 3. "DCC_STAT_DCC3_INTR_DONE_PROXY,DCC3 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 2. "DCC_STAT_DCC2_INTR_DONE_PROXY,DCC2 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 1. "DCC_STAT_DCC1_INTR_DONE_PROXY,DCC1 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
newline
bitfld.long 0x00 0. "DCC_STAT_DCC0_INTR_DONE_PROXY,DCC0 Done Interrupt Status" "No Interrupt Pending,Interrupt Pending"
group.long 0x7008++0x07
line.long 0x00 "CFG0_LOCK1_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK1_KICK1_PROXY,"
repeat 15. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
group.long ($2+0x7100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P1_R$1,"
repeat.end
group.long 0x8000++0x03
line.long 0x00 "CFG0_OBSCLK0_CTRL,"
bitfld.long 0x00 16. "OBSCLK0_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the OBSCLK0 divider value" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "OBSCLK0_CTRL_CLK_DIV,OBSCLK0 output divider Divides the selected clock by clkdiv+1 for output to the OBSCLK0 pins"
newline
bitfld.long 0x00 0.--4. "OBSCLK0_CTRL_CLK_SEL,OBSCLK0 clock source selection" "MAIN_PLL0_HSDIV0_CLKOUT,MAIN_PLL1_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV0_CLKOUT,MAIN_PLL8_HSDIV0_CLKOUT,MAIN_PLL12_HSDIV0_CLKOUT,CLK_12M_RC,HFOSC0_CLKOUT_32K,PLLCTRL_OBSCLK,HFOSC0_CLKOUT,CLK_32K,cpsw2g_cpts_genf0,cpsw2g_cpts_genf1,MCU_PLL0_HSDIV0_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,MAIN_PLL16_HSDIV0_CLKOUT,MAIN_PLL17_HSDIV0_CLKOUT,MAIN_SYSCLK0,DEVICE_CLKOUT_32K,?..."
group.long 0x8010++0x03
line.long 0x00 "CFG0_CLKOUT_CTRL,"
bitfld.long 0x00 0. "CLKOUT_CTRL_CLK_SEL,Selects CLKOUT clock source Field values (others are reserved)" "MAIN_PLL2_HSDIV1_CLKOUT / 5,MAIN_PLL2_HSDIV1_CLKOUT / 10"
group.long 0x8040++0x03
line.long 0x00 "CFG0_ICSSM0_CLKSEL,"
bitfld.long 0x00 16.--18. "ICSSM0_CLKSEL_IEP_CLKSEL,Selects the ICSSM0 IEP clock source Field values (others are reserved)" "MAIN_PLL2_HSDIV5_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,CPGEMAC_CPTS_RFT_CLK,reserved,MCU_EXT_REFCLK0,EXT_REFCLK1,MCU_SYSCLK0,MAIN_SYSCLK0"
newline
bitfld.long 0x00 0. "ICSSM0_CLKSEL_CORE_CLKSEL,Selects the ICSSM0 functional clock source Field values (others are reserved)" "MAIN_PLL2_HSDIV0_CLKOUT,MAIN_PLL0_HSDIV9_CLKOUT"
group.long 0x8060++0x0B
line.long 0x00 "CFG0_MAIN_PLL0_CLKSEL,"
bitfld.long 0x00 31. "MAIN_PLL0_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL0" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL0_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset" "Exit bypass mode (based on MAIN..,Maintain bypass mode"
line.long 0x04 "CFG0_MAIN_PLL1_CLKSEL,"
bitfld.long 0x04 31. "MAIN_PLL1_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL1 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x04 23. "MAIN_PLL1_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
line.long 0x08 "CFG0_MAIN_PLL2_CLKSEL,"
bitfld.long 0x08 31. "MAIN_PLL2_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL2 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x08 23. "MAIN_PLL2_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
group.long 0x8080++0x03
line.long 0x00 "CFG0_MAIN_PLL8_CLKSEL,"
bitfld.long 0x00 31. "MAIN_PLL8_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL8" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL8_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset" "Exit bypass mode (based on MAIN..,Maintain bypass mode"
group.long 0x8090++0x03
line.long 0x00 "CFG0_MAIN_PLL12_CLKSEL,"
bitfld.long 0x00 31. "MAIN_PLL12_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL12" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL12_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset" "Exit bypass mode (based on MAIN..,Maintain bypass mode"
group.long 0x80A0++0x07
line.long 0x00 "CFG0_MAIN_PLL16_CLKSEL,"
bitfld.long 0x00 31. "MAIN_PLL16_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL16 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL16_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
line.long 0x04 "CFG0_MAIN_PLL17_CLKSEL,"
bitfld.long 0x04 31. "MAIN_PLL17_CLKSEL_BYPASS_SW_OVRD,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL17 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x04 23. "MAIN_PLL17_CLKSEL_BYP_WARM_RST,PLL bypass mode after warm reset" "0,1"
group.long 0x8140++0x03
line.long 0x00 "CFG0_CPSW_CLKSEL,"
bitfld.long 0x00 0.--2. "CPSW_CLKSEL_CPTS_CLKSEL,Selects the clock source for the CPSW Ethernet switch Common Platform Time Stamp module Field values (others are reserved)" "MAIN_PLL2_HSDIV5_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,CP_GEMAC_CPTS0_RFT_CLK (Pin),Reserved,MCU_EXT_REFCLK0 (Pin),EXT_REFCLK1 (Pin),MCU_SYSCLK0,MAIN_SYSCLK0"
group.long 0x8160++0x03
line.long 0x00 "CFG0_EMMC0_CLKSEL,"
bitfld.long 0x00 16. "EMMC0_CLKSEL_EMMCSD_IO_CLKLB_SEL,Selects IO Pad Loopback for the MMC Module Field values (others are reserved)" "Loopback from Unbonded Pad MMCSD0_CLKLB,Loopback from IO Pin MMCSD0_CLK"
newline
bitfld.long 0x00 0. "EMMC0_CLKSEL_EMMCSD_REFCLK_SEL,Selects the functional clock for the MMC Module Field values (others are reserved)" "MAIN_PLL0_HSDIV5_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT"
group.long 0x8168++0x07
line.long 0x00 "CFG0_EMMC1_CLKSEL,"
bitfld.long 0x00 16. "EMMC1_CLKSEL_EMMCSD_IO_CLKLB_SEL,Selects IO Pad Loopback for the MMC Module Field values (others are reserved)" "Loopback from Unbonded Pad MMCSD1_CLKLB,Loopback from IO Pin MMCSD1_CLK"
newline
bitfld.long 0x00 0. "EMMC1_CLKSEL_EMMCSD_REFCLK_SEL,Selects the functional clock for the MMC Module Field values (others are reserved)" "MAIN_PLL0_HSDIV5_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT"
line.long 0x04 "CFG0_EMMC2_CLKSEL,"
bitfld.long 0x04 16. "EMMC2_CLKSEL_EMMCSD_IO_CLKLB_SEL,Selects IO Pad Loopback for the MMC Module Field values (others are reserved)" "Loopback from Unbonded Pad MMCSD2_CLKLB,Loopback from IO Pin MMCSD2_CLK"
newline
bitfld.long 0x04 0. "EMMC2_CLKSEL_EMMCSD_REFCLK_SEL,Selects the functional clock for the MMC Module Field values (others are reserved)" "MAIN_PLL0_HSDIV5_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT"
group.long 0x8180++0x03
line.long 0x00 "CFG0_GPMC_CLKSEL,"
bitfld.long 0x00 0. "GPMC_CLKSEL_CLK_SEL,Selects the GPMC clock source: Field values (others are reserved)" "MAIN_PLL0_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV7_CLKOUT"
group.long 0x81B0++0x1F
line.long 0x00 "CFG0_TIMER0_CLKSEL,"
bitfld.long 0x00 0.--3. "TIMER0_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x04 "CFG0_TIMER1_CLKSEL,"
bitfld.long 0x04 0.--3. "TIMER1_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x08 "CFG0_TIMER2_CLKSEL,"
bitfld.long 0x08 0.--3. "TIMER2_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x0C "CFG0_TIMER3_CLKSEL,"
bitfld.long 0x0C 0.--3. "TIMER3_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x10 "CFG0_TIMER4_CLKSEL,"
bitfld.long 0x10 0.--3. "TIMER4_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x14 "CFG0_TIMER5_CLKSEL,"
bitfld.long 0x14 0.--3. "TIMER5_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x18 "CFG0_TIMER6_CLKSEL,"
bitfld.long 0x18 0.--3. "TIMER6_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x1C "CFG0_TIMER7_CLKSEL,"
bitfld.long 0x1C 0.--3. "TIMER7_CLKSEL_CLK_SEL,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
group.long 0x8200++0x0B
line.long 0x00 "CFG0_SPI0_CLKSEL,"
bitfld.long 0x00 16. "SPI0_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
line.long 0x04 "CFG0_SPI1_CLKSEL,"
bitfld.long 0x04 16. "SPI1_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
line.long 0x08 "CFG0_SPI2_CLKSEL,"
bitfld.long 0x08 16. "SPI2_CLKSEL_MSTR_LB_CLKSEL,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
group.long 0x8240++0x1B
line.long 0x00 "CFG0_USART0_CLK_CTRL,"
bitfld.long 0x00 16. "USART0_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART0 clock programmable divider value" "0,1"
newline
bitfld.long 0x00 0.--1. "USART0_CLK_CTRL_CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x04 "CFG0_USART1_CLK_CTRL,"
bitfld.long 0x04 16. "USART1_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART1 clock programmable divider value" "0,1"
newline
bitfld.long 0x04 0.--1. "USART1_CLK_CTRL_CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x08 "CFG0_USART2_CLK_CTRL,"
bitfld.long 0x08 16. "USART2_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART2 clock programmable divider value" "0,1"
newline
bitfld.long 0x08 0.--1. "USART2_CLK_CTRL_CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x0C "CFG0_USART3_CLK_CTRL,"
bitfld.long 0x0C 16. "USART3_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART3 clock programmable divider value" "0,1"
newline
bitfld.long 0x0C 0.--1. "USART3_CLK_CTRL_CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x10 "CFG0_USART4_CLK_CTRL,"
bitfld.long 0x10 16. "USART4_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART4 clock programmable divider value" "0,1"
newline
bitfld.long 0x10 0.--1. "USART4_CLK_CTRL_CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x14 "CFG0_USART5_CLK_CTRL,"
bitfld.long 0x14 16. "USART5_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART5 clock programmable divider value" "0,1"
newline
bitfld.long 0x14 0.--1. "USART5_CLK_CTRL_CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x18 "CFG0_USART6_CLK_CTRL,"
bitfld.long 0x18 16. "USART6_CLK_CTRL_CLK_DIV_LD,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART6 clock programmable divider value" "0,1"
newline
bitfld.long 0x18 0.--1. "USART6_CLK_CTRL_CLK_DIV,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
group.long 0x8280++0x1B
line.long 0x00 "CFG0_USART0_CLKSEL,"
bitfld.long 0x00 0. "USART0_CLKSEL_CLK_SEL,Selects the clock source for UART0: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x04 "CFG0_USART1_CLKSEL,"
bitfld.long 0x04 0. "USART1_CLKSEL_CLK_SEL,Selects the clock source for UART1: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x08 "CFG0_USART2_CLKSEL,"
bitfld.long 0x08 0. "USART2_CLKSEL_CLK_SEL,Selects the clock source for UART2: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x0C "CFG0_USART3_CLKSEL,"
bitfld.long 0x0C 0. "USART3_CLKSEL_CLK_SEL,Selects the clock source for UART3: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x10 "CFG0_USART4_CLKSEL,"
bitfld.long 0x10 0. "USART4_CLKSEL_CLK_SEL,Selects the clock source for UART4: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x14 "CFG0_USART5_CLKSEL,"
bitfld.long 0x14 0. "USART5_CLKSEL_CLK_SEL,Selects the clock source for UART5: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x18 "CFG0_USART6_CLKSEL,"
bitfld.long 0x18 0. "USART6_CLKSEL_CLK_SEL,Selects the clock source for UART6: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
group.long 0x82E0++0x07
line.long 0x00 "CFG0_AUDIO_REFCLK0_CTRL,"
bitfld.long 0x00 15. "AUDIO_REFCLK0_CTRL_CLKOUT_EN,AUDIO_REFCLK 0 output activate This bit is inverted to drive the active low output buffer activate" "AUDIO_EXT_REFCLK0 pin is configured as an input,AUDIO_EXT_REFCLK0 pin is configured as an output"
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bitfld.long 0x00 0.--2. "AUDIO_REFCLK0_CTRL_CLK_SEL,Selects the source of AUDIO_REFCLK0 Field values (others are reserved)" "MCASP0_AHCLKR,MCASP1_AHCLKR,MCASP2_AHCLKR,MCASP0_AHCLKX,MCASP1_AHCLKX,MCASP2_AHCLKX,MAIN_PLL1_HSDIV6_CLKOUT,MAIN_PLL1_HSDIV8_CLKOUT"
line.long 0x04 "CFG0_AUDIO_REFCLK1_CTRL,"
bitfld.long 0x04 15. "AUDIO_REFCLK1_CTRL_CLKOUT_EN,AUDIO_REFCLK 1 output activate This bit is inverted to drive the active low output buffer activate" "AUDIO_EXT_REFCLK1 pin is configured as an input,AUDIO_EXT_REFCLK1 pin is configured as an output"
newline
bitfld.long 0x04 0.--2. "AUDIO_REFCLK1_CTRL_CLK_SEL,Selects the source of AUDIO_REFCLK1 Field values (others are reserved)" "MCASP0_AHCLKR,MCASP1_AHCLKR,MCASP2_AHCLKR,MCASP0_AHCLKX,MCASP1_AHCLKX,MCASP2_AHCLKX,MAIN_PLL1_HSDIV6_CLKOUT,MAIN_PLL1_HSDIV8_CLKOUT"
group.long 0x8300++0x03
line.long 0x00 "CFG0_DPI0_CLK_CTRL,"
bitfld.long 0x00 9. "DPI0_CLK_CTRL_SYNC_CLK_INVDIS,Clock edge select for DPI0 sync outputs" "HSYNC and VSYNC are driven on the falling edge..,HSYNC and VSYNC are driven on the rising edge of.."
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bitfld.long 0x00 8. "DPI0_CLK_CTRL_DATA_CLK_INVDIS,Clock edge select for DPI0 data outputs" "DATA and DE are driven on the falling edge of clk,DATA and DE are driven on the rising edge of clk.."
group.long 0x8320++0x03
line.long 0x00 "CFG0_DSS_DISPC0_CLKSEL1,"
bitfld.long 0x00 0. "DSS_DISPC0_CLKSEL1_DPI1_PCLK,DPI Lane 1 pixel Clock Source Field values (others are reserved)" "MAIN_PLL17_HSDIV0_CLKOUT,VOUT0_EXTPCLKIN"
group.long 0x8330++0x0B
line.long 0x00 "CFG0_MCASP0_CLKSEL,"
bitfld.long 0x00 0. "MCASP0_CLKSEL_AUXCLK_SEL,Selects the AUXCLK input source for McASP0 Field values (others are reserved)" "MAIN_PLL2_HSDIV8_CLKOUT,MAIN_PLL1_HSDIV6_CLKOUT"
line.long 0x04 "CFG0_MCASP1_CLKSEL,"
bitfld.long 0x04 0. "MCASP1_CLKSEL_AUXCLK_SEL,Selects the AUXCLK input source for McASP0 Field values (others are reserved)" "MAIN_PLL2_HSDIV8_CLKOUT,MAIN_PLL1_HSDIV6_CLKOUT"
line.long 0x08 "CFG0_MCASP2_CLKSEL,"
bitfld.long 0x08 0. "MCASP2_CLKSEL_AUXCLK_SEL,Selects the AUXCLK input source for McASP0 Field values (others are reserved)" "MAIN_PLL2_HSDIV8_CLKOUT,MAIN_PLL1_HSDIV6_CLKOUT"
group.long 0x8350++0x0B
line.long 0x00 "CFG0_MCASP0_AHCLKSEL,"
bitfld.long 0x00 8.--9. "MCASP0_AHCLKSEL_AHCLKX_SEL,Selects the AHCLKX input source for McASP0 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
newline
bitfld.long 0x00 0.--1. "MCASP0_AHCLKSEL_AHCLKR_SEL,Selects the AHCLKR input source for McASP0 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
line.long 0x04 "CFG0_MCASP1_AHCLKSEL,"
bitfld.long 0x04 8.--9. "MCASP1_AHCLKSEL_AHCLKX_SEL,Selects the AHCLKX input source for McASP1 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
newline
bitfld.long 0x04 0.--1. "MCASP1_AHCLKSEL_AHCLKR_SEL,Selects the AHCLKR input source for McASP1 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
line.long 0x08 "CFG0_MCASP2_AHCLKSEL,"
bitfld.long 0x08 8.--9. "MCASP2_AHCLKSEL_AHCLKX_SEL,Selects the AHCLKX input source for McASP2 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
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bitfld.long 0x08 0.--1. "MCASP2_AHCLKSEL_AHCLKR_SEL,Selects the AHCLKR input source for McASP2 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
group.long 0x8380++0x0F
line.long 0x00 "CFG0_WWD0_CLKSEL,"
bitfld.long 0x00 31. "WWD0_CLKSEL_WRTLOCK,When set locks WWD0_CLKSEL from further writes until the next module reset" "0,1"
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bitfld.long 0x00 0.--1. "WWD0_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
line.long 0x04 "CFG0_WWD1_CLKSEL,"
bitfld.long 0x04 31. "WWD1_CLKSEL_WRTLOCK,When set locks WWD1_CLKSEL from further writes until the next module reset" "0,1"
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bitfld.long 0x04 0.--1. "WWD1_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
line.long 0x08 "CFG0_WWD2_CLKSEL,"
bitfld.long 0x08 31. "WWD2_CLKSEL_WRTLOCK,When set locks WWD2_CLKSEL from further writes until the next module reset" "0,1"
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bitfld.long 0x08 0.--1. "WWD2_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
line.long 0x0C "CFG0_WWD3_CLKSEL,"
bitfld.long 0x0C 31. "WWD3_CLKSEL_WRTLOCK,When set locks WWD3_CLKSEL from further writes until the next module reset" "0,1"
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bitfld.long 0x0C 0.--1. "WWD3_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
group.long 0x83BC++0x03
line.long 0x00 "CFG0_WWD15_CLKSEL,"
bitfld.long 0x00 31. "WWD15_CLKSEL_WRTLOCK,When set locks WWD15_CLKSEL from further writes until the next module reset" "0,1"
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bitfld.long 0x00 0.--1. "WWD15_CLKSEL_CLK_SEL,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
group.long 0x8480++0x03
line.long 0x00 "CFG0_MCAN0_CLKSEL,"
bitfld.long 0x00 0.--1. "MCAN0_CLKSEL_CLK_SEL,MAIN MCAN_CLK selection" "MAIN_PLL0_HSDIV4_CLKOUT,MCU_EXT_REFCLK0,EXT_REFCLK1 (pin),HFOSC0_CLKOUT"
group.long 0x8500++0x03
line.long 0x00 "CFG0_OSPI0_CLKSEL,"
bitfld.long 0x00 4. "OSPI0_CLKSEL_LOOPCLK_SEL,OBSPI0 Loopback clock source Field values (others are reserved)" "Board Level Loopback,Internal Loopback"
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bitfld.long 0x00 0. "OSPI0_CLKSEL_CLK_SEL,OSPI0 reference clock selection Field values (others are reserved)" "MAIN_PLL0_HSDIV1_CLKOUT,MAIN_PLL1_HSDIV5_CLKOUT"
group.long 0x8600++0x13
line.long 0x00 "CFG0_OLDI0_DAT0_IO_CTRL,"
bitfld.long 0x00 31. "OLDI0_DAT0_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
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bitfld.long 0x00 30. "OLDI0_DAT0_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
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bitfld.long 0x00 24.--25. "OLDI0_DAT0_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x00 16.--19. "OLDI0_DAT0_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 13. "OLDI0_DAT0_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
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bitfld.long 0x00 12. "OLDI0_DAT0_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
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bitfld.long 0x00 11. "OLDI0_DAT0_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
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bitfld.long 0x00 10. "OLDI0_DAT0_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
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bitfld.long 0x00 9. "OLDI0_DAT0_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
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bitfld.long 0x00 8. "OLDI0_DAT0_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
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bitfld.long 0x00 1.--3. "OLDI0_DAT0_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. "OLDI0_DAT0_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x04 "CFG0_OLDI0_DAT1_IO_CTRL,"
bitfld.long 0x04 31. "OLDI0_DAT1_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
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bitfld.long 0x04 30. "OLDI0_DAT1_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
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bitfld.long 0x04 24.--25. "OLDI0_DAT1_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
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bitfld.long 0x04 16.--19. "OLDI0_DAT1_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 13. "OLDI0_DAT1_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
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bitfld.long 0x04 12. "OLDI0_DAT1_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
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bitfld.long 0x04 11. "OLDI0_DAT1_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
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bitfld.long 0x04 10. "OLDI0_DAT1_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
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bitfld.long 0x04 9. "OLDI0_DAT1_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
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bitfld.long 0x04 8. "OLDI0_DAT1_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
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bitfld.long 0x04 1.--3. "OLDI0_DAT1_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 0. "OLDI0_DAT1_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x08 "CFG0_OLDI0_DAT2_IO_CTRL,"
bitfld.long 0x08 31. "OLDI0_DAT2_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
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bitfld.long 0x08 30. "OLDI0_DAT2_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
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bitfld.long 0x08 24.--25. "OLDI0_DAT2_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
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bitfld.long 0x08 16.--19. "OLDI0_DAT2_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 13. "OLDI0_DAT2_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
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bitfld.long 0x08 12. "OLDI0_DAT2_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
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bitfld.long 0x08 11. "OLDI0_DAT2_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
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bitfld.long 0x08 10. "OLDI0_DAT2_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
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bitfld.long 0x08 9. "OLDI0_DAT2_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
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bitfld.long 0x08 8. "OLDI0_DAT2_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
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bitfld.long 0x08 1.--3. "OLDI0_DAT2_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 0. "OLDI0_DAT2_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x0C "CFG0_OLDI0_DAT3_IO_CTRL,"
bitfld.long 0x0C 31. "OLDI0_DAT3_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
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bitfld.long 0x0C 30. "OLDI0_DAT3_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
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bitfld.long 0x0C 24.--25. "OLDI0_DAT3_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x0C 16.--19. "OLDI0_DAT3_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 13. "OLDI0_DAT3_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
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bitfld.long 0x0C 12. "OLDI0_DAT3_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
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bitfld.long 0x0C 11. "OLDI0_DAT3_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
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bitfld.long 0x0C 10. "OLDI0_DAT3_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x0C 9. "OLDI0_DAT3_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
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bitfld.long 0x0C 8. "OLDI0_DAT3_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 1.--3. "OLDI0_DAT3_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "OLDI0_DAT3_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x10 "CFG0_OLDI0_CLK_IO_CTRL,"
bitfld.long 0x10 31. "OLDI0_CLK_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
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bitfld.long 0x10 30. "OLDI0_CLK_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
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bitfld.long 0x10 24.--25. "OLDI0_CLK_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
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bitfld.long 0x10 16.--19. "OLDI0_CLK_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 13. "OLDI0_CLK_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x10 12. "OLDI0_CLK_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 11. "OLDI0_CLK_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 10. "OLDI0_CLK_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x10 9. "OLDI0_CLK_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x10 8. "OLDI0_CLK_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 1.--3. "OLDI0_CLK_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0. "OLDI0_CLK_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
group.long 0x8620++0x13
line.long 0x00 "CFG0_OLDI1_DAT0_IO_CTRL,"
bitfld.long 0x00 31. "OLDI1_DAT0_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x00 30. "OLDI1_DAT0_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x00 24.--25. "OLDI1_DAT0_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x00 16.--19. "OLDI1_DAT0_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13. "OLDI1_DAT0_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x00 12. "OLDI1_DAT0_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 11. "OLDI1_DAT0_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 10. "OLDI1_DAT0_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x00 9. "OLDI1_DAT0_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x00 8. "OLDI1_DAT0_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 1.--3. "OLDI1_DAT0_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "OLDI1_DAT0_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x04 "CFG0_OLDI1_DAT1_IO_CTRL,"
bitfld.long 0x04 31. "OLDI1_DAT1_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x04 30. "OLDI1_DAT1_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x04 24.--25. "OLDI1_DAT1_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x04 16.--19. "OLDI1_DAT1_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 13. "OLDI1_DAT1_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x04 12. "OLDI1_DAT1_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 11. "OLDI1_DAT1_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 10. "OLDI1_DAT1_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x04 9. "OLDI1_DAT1_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x04 8. "OLDI1_DAT1_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 1.--3. "OLDI1_DAT1_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "OLDI1_DAT1_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x08 "CFG0_OLDI1_DAT2_IO_CTRL,"
bitfld.long 0x08 31. "OLDI1_DAT2_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x08 30. "OLDI1_DAT2_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x08 24.--25. "OLDI1_DAT2_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x08 16.--19. "OLDI1_DAT2_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 13. "OLDI1_DAT2_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x08 12. "OLDI1_DAT2_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 11. "OLDI1_DAT2_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 10. "OLDI1_DAT2_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x08 9. "OLDI1_DAT2_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x08 8. "OLDI1_DAT2_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 1.--3. "OLDI1_DAT2_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0. "OLDI1_DAT2_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x0C "CFG0_OLDI1_DAT3_IO_CTRL,"
bitfld.long 0x0C 31. "OLDI1_DAT3_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x0C 30. "OLDI1_DAT3_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x0C 24.--25. "OLDI1_DAT3_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x0C 16.--19. "OLDI1_DAT3_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 13. "OLDI1_DAT3_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x0C 12. "OLDI1_DAT3_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 11. "OLDI1_DAT3_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 10. "OLDI1_DAT3_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x0C 9. "OLDI1_DAT3_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x0C 8. "OLDI1_DAT3_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 1.--3. "OLDI1_DAT3_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "OLDI1_DAT3_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x10 "CFG0_OLDI1_CLK_IO_CTRL,"
bitfld.long 0x10 31. "OLDI1_CLK_IO_CTRL_VBIAS_SEL,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x10 30. "OLDI1_CLK_IO_CTRL_BIASEN,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x10 24.--25. "OLDI1_CLK_IO_CTRL_TXTRIM,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x10 16.--19. "OLDI1_CLK_IO_CTRL_TXDRV,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 13. "OLDI1_CLK_IO_CTRL_TXCM,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x10 12. "OLDI1_CLK_IO_CTRL_TXEN,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 11. "OLDI1_CLK_IO_CTRL_TX_TRISTATE,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 10. "OLDI1_CLK_IO_CTRL_LVDS_HYST_EN,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x10 9. "OLDI1_CLK_IO_CTRL_RXCM_EN,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x10 8. "OLDI1_CLK_IO_CTRL_RXEN,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 1.--3. "OLDI1_CLK_IO_CTRL_RTERM_VAL,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0. "OLDI1_CLK_IO_CTRL_RTERM_EN,Controls LVDS Receiver RTERM_EN" "0,1"
group.long 0x8700++0x07
line.long 0x00 "CFG0_OLDI_PD_CTRL,"
rbitfld.long 0x00 31. "OLDI_PD_CTRL_BGOK,Status of the Bandgap" "0,1"
newline
bitfld.long 0x00 8. "OLDI_PD_CTRL_PD_BG,When Set forces the LVDS Bandgap into Power Down" "0,1"
newline
bitfld.long 0x00 1. "OLDI_PD_CTRL_PD_OLDI1,When Set overrides the biase_en of all OLDI1 LVDS IO to force power down" "0,1"
newline
bitfld.long 0x00 0. "OLDI_PD_CTRL_PD_OLDI0,When Set overrides the biase_en of all OLDI0 LVDS IO to force power down" "0,1"
line.long 0x04 "CFG0_OLDI_LB_CTRL,"
bitfld.long 0x04 0. "OLDI_LB_CTRL_OLDI_SEL,When" "OLDI0 loopback data is routed to DSS,OLDI1 loopback data is routed to DSS"
group.long 0x9008++0x07
line.long 0x00 "CFG0_LOCK2_KICK0,"
line.long 0x04 "CFG0_LOCK2_KICK1,"
rgroup.long 0x9100++0x3B
line.long 0x00 "CFG0_CLAIMREG_P2_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P2_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P2_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P2_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P2_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P2_R5_READONLY,"
line.long 0x18 "CFG0_CLAIMREG_P2_R6_READONLY,"
line.long 0x1C "CFG0_CLAIMREG_P2_R7_READONLY,"
line.long 0x20 "CFG0_CLAIMREG_P2_R8_READONLY,"
line.long 0x24 "CFG0_CLAIMREG_P2_R9_READONLY,"
line.long 0x28 "CFG0_CLAIMREG_P2_R10_READONLY,"
line.long 0x2C "CFG0_CLAIMREG_P2_R11_READONLY,"
line.long 0x30 "CFG0_CLAIMREG_P2_R12_READONLY,"
line.long 0x34 "CFG0_CLAIMREG_P2_R13_READONLY,"
line.long 0x38 "CFG0_CLAIMREG_P2_R14_READONLY,"
group.long 0xA000++0x03
line.long 0x00 "CFG0_OBSCLK0_CTRL_PROXY,"
bitfld.long 0x00 16. "OBSCLK0_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the OBSCLK0 divider value" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "OBSCLK0_CTRL_CLK_DIV_PROXY,OBSCLK0 output divider Divides the selected clock by clkdiv+1 for output to the OBSCLK0 pins"
newline
bitfld.long 0x00 0.--4. "OBSCLK0_CTRL_CLK_SEL_PROXY,OBSCLK0 clock source selection" "MAIN_PLL0_HSDIV0_CLKOUT,MAIN_PLL1_HSDIV0_CLKOUT,MAIN_PLL2_HSDIV0_CLKOUT,MAIN_PLL8_HSDIV0_CLKOUT,MAIN_PLL12_HSDIV0_CLKOUT,CLK_12M_RC,HFOSC0_CLKOUT_32K,PLLCTRL_OBSCLK,HFOSC0_CLKOUT,CLK_32K,cpsw2g_cpts_genf0,cpsw2g_cpts_genf1,MCU_PLL0_HSDIV0_CLKOUT,MAIN_PLL15_HSDIV0_CLKOUT,MAIN_PLL16_HSDIV0_CLKOUT,MAIN_PLL17_HSDIV0_CLKOUT,MAIN_SYSCLK0,DEVICE_CLKOUT_32K,?..."
group.long 0xA010++0x03
line.long 0x00 "CFG0_CLKOUT_CTRL_PROXY,"
bitfld.long 0x00 0. "CLKOUT_CTRL_CLK_SEL_PROXY,Selects CLKOUT clock source Field values (others are reserved)" "MAIN_PLL2_HSDIV1_CLKOUT / 5,MAIN_PLL2_HSDIV1_CLKOUT / 10"
group.long 0xA040++0x03
line.long 0x00 "CFG0_ICSSM0_CLKSEL_PROXY,"
bitfld.long 0x00 16.--18. "ICSSM0_CLKSEL_IEP_CLKSEL_PROXY,Selects the ICSSM0 IEP clock source Field values (others are reserved)" "MAIN_PLL2_HSDIV5_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,CPGEMAC_CPTS_RFT_CLK,reserved,MCU_EXT_REFCLK0,EXT_REFCLK1,MCU_SYSCLK0,MAIN_SYSCLK0"
newline
bitfld.long 0x00 0. "ICSSM0_CLKSEL_CORE_CLKSEL_PROXY,Selects the ICSSM0 functional clock source Field values (others are reserved)" "MAIN_PLL2_HSDIV0_CLKOUT,MAIN_PLL0_HSDIV9_CLKOUT"
group.long 0xA060++0x0B
line.long 0x00 "CFG0_MAIN_PLL0_CLKSEL_PROXY,"
bitfld.long 0x00 31. "MAIN_PLL0_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL0" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL0_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset" "Exit bypass mode (based on MAIN..,Maintain bypass mode"
line.long 0x04 "CFG0_MAIN_PLL1_CLKSEL_PROXY,"
bitfld.long 0x04 31. "MAIN_PLL1_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL1 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x04 23. "MAIN_PLL1_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset" "0,1"
line.long 0x08 "CFG0_MAIN_PLL2_CLKSEL_PROXY,"
bitfld.long 0x08 31. "MAIN_PLL2_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL2 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x08 23. "MAIN_PLL2_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset" "0,1"
group.long 0xA080++0x03
line.long 0x00 "CFG0_MAIN_PLL8_CLKSEL_PROXY,"
bitfld.long 0x00 31. "MAIN_PLL8_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL8" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL8_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset" "Exit bypass mode (based on MAIN..,Maintain bypass mode"
group.long 0xA090++0x03
line.long 0x00 "CFG0_MAIN_PLL12_CLKSEL_PROXY,"
bitfld.long 0x00 31. "MAIN_PLL12_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override When set activates software control of exit from bypass mode on a main_reset_z for MAIN PLL12" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL12_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset" "Exit bypass mode (based on MAIN..,Maintain bypass mode"
group.long 0xA0A0++0x07
line.long 0x00 "CFG0_MAIN_PLL16_CLKSEL_PROXY,"
bitfld.long 0x00 31. "MAIN_PLL16_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL16 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x00 23. "MAIN_PLL16_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset" "0,1"
line.long 0x04 "CFG0_MAIN_PLL17_CLKSEL_PROXY,"
bitfld.long 0x04 31. "MAIN_PLL17_CLKSEL_BYPASS_SW_OVRD_PROXY,PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL17 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled" "0,1"
newline
bitfld.long 0x04 23. "MAIN_PLL17_CLKSEL_BYP_WARM_RST_PROXY,PLL bypass mode after warm reset" "0,1"
group.long 0xA140++0x03
line.long 0x00 "CFG0_CPSW_CLKSEL_PROXY,"
bitfld.long 0x00 0.--2. "CPSW_CLKSEL_CPTS_CLKSEL_PROXY,Selects the clock source for the CPSW Ethernet switch Common Platform Time Stamp module Field values (others are reserved)" "MAIN_PLL2_HSDIV5_CLKOUT,MAIN_PLL0_HSDIV6_CLKOUT,CP_GEMAC_CPTS0_RFT_CLK (Pin),Reserved,MCU_EXT_REFCLK0 (Pin),EXT_REFCLK1 (Pin),MCU_SYSCLK0,MAIN_SYSCLK0"
group.long 0xA160++0x03
line.long 0x00 "CFG0_EMMC0_CLKSEL_PROXY,"
bitfld.long 0x00 16. "EMMC0_CLKSEL_EMMCSD_IO_CLKLB_SEL_PROXY,Selects IO Pad Loopback for the MMC Module Field values (others are reserved)" "Loopback from Unbonded Pad MMCSD0_CLKLB,Loopback from IO Pin MMCSD0_CLK"
newline
bitfld.long 0x00 0. "EMMC0_CLKSEL_EMMCSD_REFCLK_SEL_PROXY,Selects the functional clock for the MMC Module Field values (others are reserved)" "MAIN_PLL0_HSDIV5_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT"
group.long 0xA168++0x07
line.long 0x00 "CFG0_EMMC1_CLKSEL_PROXY,"
bitfld.long 0x00 16. "EMMC1_CLKSEL_EMMCSD_IO_CLKLB_SEL_PROXY,Selects IO Pad Loopback for the MMC Module Field values (others are reserved)" "Loopback from Unbonded Pad MMCSD1_CLKLB,Loopback from IO Pin MMCSD1_CLK"
newline
bitfld.long 0x00 0. "EMMC1_CLKSEL_EMMCSD_REFCLK_SEL_PROXY,Selects the functional clock for the MMC Module Field values (others are reserved)" "MAIN_PLL0_HSDIV5_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT"
line.long 0x04 "CFG0_EMMC2_CLKSEL_PROXY,"
bitfld.long 0x04 16. "EMMC2_CLKSEL_EMMCSD_IO_CLKLB_SEL_PROXY,Selects IO Pad Loopback for the MMC Module Field values (others are reserved)" "Loopback from Unbonded Pad MMCSD2_CLKLB,Loopback from IO Pin MMCSD2_CLK"
newline
bitfld.long 0x04 0. "EMMC2_CLKSEL_EMMCSD_REFCLK_SEL_PROXY,Selects the functional clock for the MMC Module Field values (others are reserved)" "MAIN_PLL0_HSDIV5_CLKOUT,MAIN_PLL2_HSDIV2_CLKOUT"
group.long 0xA180++0x03
line.long 0x00 "CFG0_GPMC_CLKSEL_PROXY,"
bitfld.long 0x00 0. "GPMC_CLKSEL_CLK_SEL_PROXY,Selects the GPMC clock source: Field values (others are reserved)" "MAIN_PLL0_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV7_CLKOUT"
group.long 0xA1B0++0x1F
line.long 0x00 "CFG0_TIMER0_CLKSEL_PROXY,"
bitfld.long 0x00 0.--3. "TIMER0_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x04 "CFG0_TIMER1_CLKSEL_PROXY,"
bitfld.long 0x04 0.--3. "TIMER1_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x08 "CFG0_TIMER2_CLKSEL_PROXY,"
bitfld.long 0x08 0.--3. "TIMER2_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x0C "CFG0_TIMER3_CLKSEL_PROXY,"
bitfld.long 0x0C 0.--3. "TIMER3_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x10 "CFG0_TIMER4_CLKSEL_PROXY,"
bitfld.long 0x10 0.--3. "TIMER4_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x14 "CFG0_TIMER5_CLKSEL_PROXY,"
bitfld.long 0x14 0.--3. "TIMER5_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x18 "CFG0_TIMER6_CLKSEL_PROXY,"
bitfld.long 0x18 0.--3. "TIMER6_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
line.long 0x1C "CFG0_TIMER7_CLKSEL_PROXY,"
bitfld.long 0x1C 0.--3. "TIMER7_CLKSEL_CLK_SEL_PROXY,Timer functional clock input select mux control (Reserved values default to HFOSC1_CLK) Field values (others are reserved)" "HFOSC0_CLKOUT,FINAL_CLKOUT_32K,MAIN_PLL0_HSDIV7_CLKOUT,CLK_12M_RC,MCU_EXT_REFCLK0 (pin),EXT_REFCLK1 (pin),Reserved,CPSW2G_CPTS_RFT_CLK,MAIN_PLL1_HSDIV3_CLKOUT,MAIN_PLL2_HSDIV6_CLKOUT,CPSW2G_CPTS_GENF0,CPSW2G_CPTS_GENF1,Reserved,Reserved,Reserved,Reserved"
group.long 0xA200++0x0B
line.long 0x00 "CFG0_SPI0_CLKSEL_PROXY,"
bitfld.long 0x00 16. "SPI0_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
line.long 0x04 "CFG0_SPI1_CLKSEL_PROXY,"
bitfld.long 0x04 16. "SPI1_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
line.long 0x08 "CFG0_SPI2_CLKSEL_PROXY,"
bitfld.long 0x08 16. "SPI2_CLKSEL_MSTR_LB_CLKSEL_PROXY,Controller mode receive capture clock loopback selection" "Internal clock loopback,Loopback from pad"
group.long 0xA240++0x1B
line.long 0x00 "CFG0_USART0_CLK_CTRL_PROXY,"
bitfld.long 0x00 16. "USART0_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART0 clock programmable divider value" "0,1"
newline
bitfld.long 0x00 0.--1. "USART0_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x04 "CFG0_USART1_CLK_CTRL_PROXY,"
bitfld.long 0x04 16. "USART1_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART1 clock programmable divider value" "0,1"
newline
bitfld.long 0x04 0.--1. "USART1_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x08 "CFG0_USART2_CLK_CTRL_PROXY,"
bitfld.long 0x08 16. "USART2_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART2 clock programmable divider value" "0,1"
newline
bitfld.long 0x08 0.--1. "USART2_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x0C "CFG0_USART3_CLK_CTRL_PROXY,"
bitfld.long 0x0C 16. "USART3_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART3 clock programmable divider value" "0,1"
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bitfld.long 0x0C 0.--1. "USART3_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x10 "CFG0_USART4_CLK_CTRL_PROXY,"
bitfld.long 0x10 16. "USART4_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART4 clock programmable divider value" "0,1"
newline
bitfld.long 0x10 0.--1. "USART4_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x14 "CFG0_USART5_CLK_CTRL_PROXY,"
bitfld.long 0x14 16. "USART5_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART5 clock programmable divider value" "0,1"
newline
bitfld.long 0x14 0.--1. "USART5_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
line.long 0x18 "CFG0_USART6_CLK_CTRL_PROXY,"
bitfld.long 0x18 16. "USART6_CLK_CTRL_CLK_DIV_LD_PROXY,Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART6 clock programmable divider value" "0,1"
newline
bitfld.long 0x18 0.--1. "USART6_CLK_CTRL_CLK_DIV_PROXY,Selects the clock divider value" "Divide by 1,Divide by 2,Divide by 3,Divide by 4"
group.long 0xA280++0x1B
line.long 0x00 "CFG0_USART0_CLKSEL_PROXY,"
bitfld.long 0x00 0. "USART0_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART0: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x04 "CFG0_USART1_CLKSEL_PROXY,"
bitfld.long 0x04 0. "USART1_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART1: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x08 "CFG0_USART2_CLKSEL_PROXY,"
bitfld.long 0x08 0. "USART2_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART2: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x0C "CFG0_USART3_CLKSEL_PROXY,"
bitfld.long 0x0C 0. "USART3_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART3: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x10 "CFG0_USART4_CLKSEL_PROXY,"
bitfld.long 0x10 0. "USART4_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART4: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x14 "CFG0_USART5_CLKSEL_PROXY,"
bitfld.long 0x14 0. "USART5_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART5: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
line.long 0x18 "CFG0_USART6_CLKSEL_PROXY,"
bitfld.long 0x18 0. "USART6_CLKSEL_CLK_SEL_PROXY,Selects the clock source for UART6: Field values (others are reserved)" "MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See..,MAIN_PLL1_HSDIV1_CLKOUT"
group.long 0xA2E0++0x07
line.long 0x00 "CFG0_AUDIO_REFCLK0_CTRL_PROXY,"
bitfld.long 0x00 15. "AUDIO_REFCLK0_CTRL_CLKOUT_EN_PROXY,AUDIO_REFCLK 0 output activate This bit is inverted to drive the active low output buffer activate" "AUDIO_EXT_REFCLK0 pin is configured as an input,AUDIO_EXT_REFCLK0 pin is configured as an output"
newline
bitfld.long 0x00 0.--2. "AUDIO_REFCLK0_CTRL_CLK_SEL_PROXY,Selects the source of AUDIO_REFCLK0 Field values (others are reserved)" "MCASP0_AHCLKR,MCASP1_AHCLKR,MCASP2_AHCLKR,MCASP0_AHCLKX,MCASP1_AHCLKX,MCASP2_AHCLKX,MAIN_PLL1_HSDIV6_CLKOUT,MAIN_PLL1_HSDIV8_CLKOUT"
line.long 0x04 "CFG0_AUDIO_REFCLK1_CTRL_PROXY,"
bitfld.long 0x04 15. "AUDIO_REFCLK1_CTRL_CLKOUT_EN_PROXY,AUDIO_REFCLK 1 output activate This bit is inverted to drive the active low output buffer activate" "AUDIO_EXT_REFCLK1 pin is configured as an input,AUDIO_EXT_REFCLK1 pin is configured as an output"
newline
bitfld.long 0x04 0.--2. "AUDIO_REFCLK1_CTRL_CLK_SEL_PROXY,Selects the source of AUDIO_REFCLK1 Field values (others are reserved)" "MCASP0_AHCLKR,MCASP1_AHCLKR,MCASP2_AHCLKR,MCASP0_AHCLKX,MCASP1_AHCLKX,MCASP2_AHCLKX,MAIN_PLL1_HSDIV6_CLKOUT,MAIN_PLL1_HSDIV8_CLKOUT"
group.long 0xA300++0x03
line.long 0x00 "CFG0_DPI0_CLK_CTRL_PROXY,"
bitfld.long 0x00 9. "DPI0_CLK_CTRL_SYNC_CLK_INVDIS_PROXY,Clock edge select for DPI0 sync outputs" "HSYNC and VSYNC are driven on the falling edge..,HSYNC and VSYNC are driven on the rising edge of.."
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bitfld.long 0x00 8. "DPI0_CLK_CTRL_DATA_CLK_INVDIS_PROXY,Clock edge select for DPI0 data outputs" "DATA and DE are driven on the falling edge of clk,DATA and DE are driven on the rising edge of clk.."
group.long 0xA320++0x03
line.long 0x00 "CFG0_DSS_DISPC0_CLKSEL1_PROXY,"
bitfld.long 0x00 0. "DSS_DISPC0_CLKSEL1_DPI1_PCLK_PROXY,DPI Lane 1 pixel Clock Source Field values (others are reserved)" "MAIN_PLL17_HSDIV0_CLKOUT,VOUT0_EXTPCLKIN"
group.long 0xA330++0x0B
line.long 0x00 "CFG0_MCASP0_CLKSEL_PROXY,"
bitfld.long 0x00 0. "MCASP0_CLKSEL_AUXCLK_SEL_PROXY,Selects the AUXCLK input source for McASP0 Field values (others are reserved)" "MAIN_PLL2_HSDIV8_CLKOUT,MAIN_PLL1_HSDIV6_CLKOUT"
line.long 0x04 "CFG0_MCASP1_CLKSEL_PROXY,"
bitfld.long 0x04 0. "MCASP1_CLKSEL_AUXCLK_SEL_PROXY,Selects the AUXCLK input source for McASP0 Field values (others are reserved)" "MAIN_PLL2_HSDIV8_CLKOUT,MAIN_PLL1_HSDIV6_CLKOUT"
line.long 0x08 "CFG0_MCASP2_CLKSEL_PROXY,"
bitfld.long 0x08 0. "MCASP2_CLKSEL_AUXCLK_SEL_PROXY,Selects the AUXCLK input source for McASP0 Field values (others are reserved)" "MAIN_PLL2_HSDIV8_CLKOUT,MAIN_PLL1_HSDIV6_CLKOUT"
group.long 0xA350++0x0B
line.long 0x00 "CFG0_MCASP0_AHCLKSEL_PROXY,"
bitfld.long 0x00 8.--9. "MCASP0_AHCLKSEL_AHCLKX_SEL_PROXY,Selects the AHCLKX input source for McASP0 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
newline
bitfld.long 0x00 0.--1. "MCASP0_AHCLKSEL_AHCLKR_SEL_PROXY,Selects the AHCLKR input source for McASP0 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
line.long 0x04 "CFG0_MCASP1_AHCLKSEL_PROXY,"
bitfld.long 0x04 8.--9. "MCASP1_AHCLKSEL_AHCLKX_SEL_PROXY,Selects the AHCLKX input source for McASP1 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
newline
bitfld.long 0x04 0.--1. "MCASP1_AHCLKSEL_AHCLKR_SEL_PROXY,Selects the AHCLKR input source for McASP1 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
line.long 0x08 "CFG0_MCASP2_AHCLKSEL_PROXY,"
bitfld.long 0x08 8.--9. "MCASP2_AHCLKSEL_AHCLKX_SEL_PROXY,Selects the AHCLKX input source for McASP2 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
newline
bitfld.long 0x08 0.--1. "MCASP2_AHCLKSEL_AHCLKR_SEL_PROXY,Selects the AHCLKR input source for McASP2 Field values (others are reserved)" "EXT_REFCLK1 (pin),HFOSC0_CLKOUT,AUDIO_EXT_REFCLK0_IN,AUDIO_EXT_REFCLK1_IN"
group.long 0xA380++0x0F
line.long 0x00 "CFG0_WWD0_CLKSEL_PROXY,"
bitfld.long 0x00 31. "WWD0_CLKSEL_WRTLOCK_PROXY,When set locks WWD0_CLKSEL from further writes until the next module reset" "0,1"
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bitfld.long 0x00 0.--1. "WWD0_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
line.long 0x04 "CFG0_WWD1_CLKSEL_PROXY,"
bitfld.long 0x04 31. "WWD1_CLKSEL_WRTLOCK_PROXY,When set locks WWD1_CLKSEL from further writes until the next module reset" "0,1"
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bitfld.long 0x04 0.--1. "WWD1_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
line.long 0x08 "CFG0_WWD2_CLKSEL_PROXY,"
bitfld.long 0x08 31. "WWD2_CLKSEL_WRTLOCK_PROXY,When set locks WWD2_CLKSEL from further writes until the next module reset" "0,1"
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bitfld.long 0x08 0.--1. "WWD2_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
line.long 0x0C "CFG0_WWD3_CLKSEL_PROXY,"
bitfld.long 0x0C 31. "WWD3_CLKSEL_WRTLOCK_PROXY,When set locks WWD3_CLKSEL from further writes until the next module reset" "0,1"
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bitfld.long 0x0C 0.--1. "WWD3_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
group.long 0xA3BC++0x03
line.long 0x00 "CFG0_WWD15_CLKSEL_PROXY,"
bitfld.long 0x00 31. "WWD15_CLKSEL_WRTLOCK_PROXY,When set locks WWD15_CLKSEL from further writes until the next module reset" "0,1"
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bitfld.long 0x00 0.--1. "WWD15_CLKSEL_CLK_SEL_PROXY,Windowed watchdog timer functional clock input select mux control Field values (others are reserved)" "HFOSC0_CLKOUT,DEVICE_CLKOUT_32K,CLK_12M_RC,CLK_32K"
group.long 0xA480++0x03
line.long 0x00 "CFG0_MCAN0_CLKSEL_PROXY,"
bitfld.long 0x00 0.--1. "MCAN0_CLKSEL_CLK_SEL_PROXY,MAIN MCAN_CLK selection" "MAIN_PLL0_HSDIV4_CLKOUT,MCU_EXT_REFCLK0,EXT_REFCLK1 (pin),HFOSC0_CLKOUT"
group.long 0xA500++0x03
line.long 0x00 "CFG0_OSPI0_CLKSEL_PROXY,"
bitfld.long 0x00 4. "OSPI0_CLKSEL_LOOPCLK_SEL_PROXY,OBSPI0 Loopback clock source Field values (others are reserved)" "Board Level Loopback,Internal Loopback"
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bitfld.long 0x00 0. "OSPI0_CLKSEL_CLK_SEL_PROXY,OSPI0 reference clock selection Field values (others are reserved)" "MAIN_PLL0_HSDIV1_CLKOUT,MAIN_PLL1_HSDIV5_CLKOUT"
group.long 0xA600++0x13
line.long 0x00 "CFG0_OLDI0_DAT0_IO_CTRL_PROXY,"
bitfld.long 0x00 31. "OLDI0_DAT0_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
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bitfld.long 0x00 30. "OLDI0_DAT0_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
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bitfld.long 0x00 24.--25. "OLDI0_DAT0_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
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bitfld.long 0x00 16.--19. "OLDI0_DAT0_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13. "OLDI0_DAT0_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
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bitfld.long 0x00 12. "OLDI0_DAT0_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
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bitfld.long 0x00 11. "OLDI0_DAT0_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
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bitfld.long 0x00 10. "OLDI0_DAT0_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
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bitfld.long 0x00 9. "OLDI0_DAT0_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
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bitfld.long 0x00 8. "OLDI0_DAT0_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
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bitfld.long 0x00 1.--3. "OLDI0_DAT0_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "OLDI0_DAT0_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x04 "CFG0_OLDI0_DAT1_IO_CTRL_PROXY,"
bitfld.long 0x04 31. "OLDI0_DAT1_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
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bitfld.long 0x04 30. "OLDI0_DAT1_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
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bitfld.long 0x04 24.--25. "OLDI0_DAT1_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
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bitfld.long 0x04 16.--19. "OLDI0_DAT1_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 13. "OLDI0_DAT1_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
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bitfld.long 0x04 12. "OLDI0_DAT1_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
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bitfld.long 0x04 11. "OLDI0_DAT1_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
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bitfld.long 0x04 10. "OLDI0_DAT1_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
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bitfld.long 0x04 9. "OLDI0_DAT1_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
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bitfld.long 0x04 8. "OLDI0_DAT1_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
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bitfld.long 0x04 1.--3. "OLDI0_DAT1_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "OLDI0_DAT1_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x08 "CFG0_OLDI0_DAT2_IO_CTRL_PROXY,"
bitfld.long 0x08 31. "OLDI0_DAT2_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
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bitfld.long 0x08 30. "OLDI0_DAT2_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
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bitfld.long 0x08 24.--25. "OLDI0_DAT2_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
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bitfld.long 0x08 16.--19. "OLDI0_DAT2_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 13. "OLDI0_DAT2_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
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bitfld.long 0x08 12. "OLDI0_DAT2_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
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bitfld.long 0x08 11. "OLDI0_DAT2_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
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bitfld.long 0x08 10. "OLDI0_DAT2_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
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bitfld.long 0x08 9. "OLDI0_DAT2_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
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bitfld.long 0x08 8. "OLDI0_DAT2_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
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bitfld.long 0x08 1.--3. "OLDI0_DAT2_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0. "OLDI0_DAT2_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x0C "CFG0_OLDI0_DAT3_IO_CTRL_PROXY,"
bitfld.long 0x0C 31. "OLDI0_DAT3_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
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bitfld.long 0x0C 30. "OLDI0_DAT3_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
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bitfld.long 0x0C 24.--25. "OLDI0_DAT3_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
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bitfld.long 0x0C 16.--19. "OLDI0_DAT3_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 13. "OLDI0_DAT3_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
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bitfld.long 0x0C 12. "OLDI0_DAT3_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 11. "OLDI0_DAT3_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
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bitfld.long 0x0C 10. "OLDI0_DAT3_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x0C 9. "OLDI0_DAT3_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x0C 8. "OLDI0_DAT3_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
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bitfld.long 0x0C 1.--3. "OLDI0_DAT3_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "OLDI0_DAT3_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x10 "CFG0_OLDI0_CLK_IO_CTRL_PROXY,"
bitfld.long 0x10 31. "OLDI0_CLK_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x10 30. "OLDI0_CLK_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x10 24.--25. "OLDI0_CLK_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x10 16.--19. "OLDI0_CLK_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 13. "OLDI0_CLK_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x10 12. "OLDI0_CLK_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 11. "OLDI0_CLK_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 10. "OLDI0_CLK_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x10 9. "OLDI0_CLK_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x10 8. "OLDI0_CLK_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 1.--3. "OLDI0_CLK_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0. "OLDI0_CLK_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
group.long 0xA620++0x13
line.long 0x00 "CFG0_OLDI1_DAT0_IO_CTRL_PROXY,"
bitfld.long 0x00 31. "OLDI1_DAT0_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x00 30. "OLDI1_DAT0_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x00 24.--25. "OLDI1_DAT0_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x00 16.--19. "OLDI1_DAT0_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13. "OLDI1_DAT0_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x00 12. "OLDI1_DAT0_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 11. "OLDI1_DAT0_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 10. "OLDI1_DAT0_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x00 9. "OLDI1_DAT0_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x00 8. "OLDI1_DAT0_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x00 1.--3. "OLDI1_DAT0_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0. "OLDI1_DAT0_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x04 "CFG0_OLDI1_DAT1_IO_CTRL_PROXY,"
bitfld.long 0x04 31. "OLDI1_DAT1_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x04 30. "OLDI1_DAT1_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x04 24.--25. "OLDI1_DAT1_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x04 16.--19. "OLDI1_DAT1_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 13. "OLDI1_DAT1_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x04 12. "OLDI1_DAT1_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 11. "OLDI1_DAT1_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 10. "OLDI1_DAT1_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x04 9. "OLDI1_DAT1_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x04 8. "OLDI1_DAT1_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x04 1.--3. "OLDI1_DAT1_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0. "OLDI1_DAT1_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x08 "CFG0_OLDI1_DAT2_IO_CTRL_PROXY,"
bitfld.long 0x08 31. "OLDI1_DAT2_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x08 30. "OLDI1_DAT2_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x08 24.--25. "OLDI1_DAT2_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x08 16.--19. "OLDI1_DAT2_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 13. "OLDI1_DAT2_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x08 12. "OLDI1_DAT2_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 11. "OLDI1_DAT2_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 10. "OLDI1_DAT2_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x08 9. "OLDI1_DAT2_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x08 8. "OLDI1_DAT2_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x08 1.--3. "OLDI1_DAT2_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0. "OLDI1_DAT2_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x0C "CFG0_OLDI1_DAT3_IO_CTRL_PROXY,"
bitfld.long 0x0C 31. "OLDI1_DAT3_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x0C 30. "OLDI1_DAT3_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x0C 24.--25. "OLDI1_DAT3_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x0C 16.--19. "OLDI1_DAT3_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 13. "OLDI1_DAT3_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x0C 12. "OLDI1_DAT3_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 11. "OLDI1_DAT3_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 10. "OLDI1_DAT3_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x0C 9. "OLDI1_DAT3_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x0C 8. "OLDI1_DAT3_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x0C 1.--3. "OLDI1_DAT3_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 0. "OLDI1_DAT3_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
line.long 0x10 "CFG0_OLDI1_CLK_IO_CTRL_PROXY,"
bitfld.long 0x10 31. "OLDI1_CLK_IO_CTRL_VBIAS_SEL_PROXY,Selects LVDS IO Bias Voltage" "0,1"
newline
bitfld.long 0x10 30. "OLDI1_CLK_IO_CTRL_BIASEN_PROXY,Controls LVDS IO BIAS_EN if OLDI is activated" "0,1"
newline
bitfld.long 0x10 24.--25. "OLDI1_CLK_IO_CTRL_TXTRIM_PROXY,Controls LVDS Transmitter TXTRIM" "0,1,2,3"
newline
bitfld.long 0x10 16.--19. "OLDI1_CLK_IO_CTRL_TXDRV_PROXY,Controls LVDS Transmitter TXDRV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 13. "OLDI1_CLK_IO_CTRL_TXCM_PROXY,Controls LVDS Transmitter TX_CM" "0,1"
newline
bitfld.long 0x10 12. "OLDI1_CLK_IO_CTRL_TXEN_PROXY,Controls LVDS Transmitter TXEN if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 11. "OLDI1_CLK_IO_CTRL_TX_TRISTATE_PROXY,Controls LVDS Transmitter TX_TRISTATE input if BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 10. "OLDI1_CLK_IO_CTRL_LVDS_HYST_EN_PROXY,Controls LVDS Receiver Hysteresis" "0,1"
newline
bitfld.long 0x10 9. "OLDI1_CLK_IO_CTRL_RXCM_EN_PROXY,Controls LVDS Receiver RXCM_EN" "0,1"
newline
bitfld.long 0x10 8. "OLDI1_CLK_IO_CTRL_RXEN_PROXY,Controls LVDS Receiver RXEN when BIAS_EN is active" "0,1"
newline
bitfld.long 0x10 1.--3. "OLDI1_CLK_IO_CTRL_RTERM_VAL_PROXY,Controls LVDS Receiver RTERM_VAL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0. "OLDI1_CLK_IO_CTRL_RTERM_EN_PROXY,Controls LVDS Receiver RTERM_EN" "0,1"
group.long 0xA700++0x07
line.long 0x00 "CFG0_OLDI_PD_CTRL_PROXY,"
rbitfld.long 0x00 31. "OLDI_PD_CTRL_BGOK_PROXY,Status of the Bandgap" "0,1"
newline
bitfld.long 0x00 8. "OLDI_PD_CTRL_PD_BG_PROXY,When Set forces the LVDS Bandgap into Power Down" "0,1"
newline
bitfld.long 0x00 1. "OLDI_PD_CTRL_PD_OLDI1_PROXY,When Set overrides the biase_en of all OLDI1 LVDS IO to force power down" "0,1"
newline
bitfld.long 0x00 0. "OLDI_PD_CTRL_PD_OLDI0_PROXY,When Set overrides the biase_en of all OLDI0 LVDS IO to force power down" "0,1"
line.long 0x04 "CFG0_OLDI_LB_CTRL_PROXY,"
bitfld.long 0x04 0. "OLDI_LB_CTRL_OLDI_SEL_PROXY,When" "OLDI0 loopback data is routed to DSS,OLDI1 loopback data is routed to DSS"
group.long 0xB008++0x07
line.long 0x00 "CFG0_LOCK2_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK2_KICK1_PROXY,"
repeat 15. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
group.long ($2+0xB100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P2_R$1,"
repeat.end
group.long 0x10500++0x03
line.long 0x00 "CFG0_MAIN_PLL_TEST_CLKSEL,"
bitfld.long 0x00 17. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL17,Selects the alternate clock source for MAIN PLL17 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 16. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL16,Selects the alternate clock source for MAIN PLL16 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 12. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL12,Selects the alternate clock source for MAIN PLL12 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 8. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL8,Selects the alternate clock source for MAIN PLL8 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 2. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL2,Selects the alternate clock source for MAIN PLL2 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 1. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL1,Selects the alternate clock source for MAIN PLL1 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 0. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL0,Selects the alternate clock source for MAIN PLL0 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
group.long 0x11008++0x07
line.long 0x00 "CFG0_LOCK4_KICK0,"
line.long 0x04 "CFG0_LOCK4_KICK1,"
rgroup.long 0x11100++0x2B
line.long 0x00 "CFG0_CLAIMREG_P4_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P4_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P4_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P4_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P4_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P4_R5_READONLY,"
line.long 0x18 "CFG0_CLAIMREG_P4_R6_READONLY,"
line.long 0x1C "CFG0_CLAIMREG_P4_R7_READONLY,"
line.long 0x20 "CFG0_CLAIMREG_P4_R8_READONLY,"
line.long 0x24 "CFG0_CLAIMREG_P4_R9_READONLY,"
line.long 0x28 "CFG0_CLAIMREG_P4_R10_READONLY,"
group.long 0x12500++0x03
line.long 0x00 "CFG0_MAIN_PLL_TEST_CLKSEL_PROXY,"
bitfld.long 0x00 17. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL17_PROXY,Selects the alternate clock source for MAIN PLL17 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 16. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL16_PROXY,Selects the alternate clock source for MAIN PLL16 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 12. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL12_PROXY,Selects the alternate clock source for MAIN PLL12 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 8. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL8_PROXY,Selects the alternate clock source for MAIN PLL8 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 2. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL2_PROXY,Selects the alternate clock source for MAIN PLL2 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 1. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL1_PROXY,Selects the alternate clock source for MAIN PLL1 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
newline
bitfld.long 0x00 0. "MAIN_PLL_TEST_CLKSEL_CLK_SEL_PLL0_PROXY,Selects the alternate clock source for MAIN PLL0 Field values (others are reserved)" "HFOSC0_CLKOUT,EXT_REFCLK1 pin"
group.long 0x13008++0x07
line.long 0x00 "CFG0_LOCK4_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK4_KICK1_PROXY,"
repeat 11. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 )
group.long ($2+0x13100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P4_R$1,"
repeat.end
group.long 0x19008++0x07
line.long 0x00 "CFG0_LOCK6_KICK0,"
line.long 0x04 "CFG0_LOCK6_KICK1,"
rgroup.long 0x19100++0x23
line.long 0x00 "CFG0_CLAIMREG_P6_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P6_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P6_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P6_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P6_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P6_R5_READONLY,"
line.long 0x18 "CFG0_CLAIMREG_P6_R6_READONLY,"
line.long 0x1C "CFG0_CLAIMREG_P6_R7_READONLY,"
line.long 0x20 "CFG0_CLAIMREG_P6_R8_READONLY,"
group.long 0x1B008++0x07
line.long 0x00 "CFG0_LOCK6_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK6_KICK1_PROXY,"
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
group.long ($2+0x1B100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P6_R$1,"
repeat.end
tree.end
tree "ECAP0_CTL_STS"
base ad:0x23100000
group.long 0x00++0x17
line.long 0x00 "CTL_STS_TSCNT,"
line.long 0x04 "CTL_STS_CNTPHS,"
line.long 0x08 "CTL_STS_CAP1,"
line.long 0x0C "CTL_STS_CAP2,"
line.long 0x10 "CTL_STS_CAP3,"
line.long 0x14 "CTL_STS_CAP4,"
group.long 0x28++0x0B
line.long 0x00 "CTL_STS_ECCTL,"
rbitfld.long 0x00 27.--31. "FILTER," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "APWMPOL,APWM output polarity select: 1'b0 Output is Active High (i.e. Compare value defines High time); 1'b1 Output is Active Low (i.e. Compare value defines Low time); Note: This is applicable only in APWM operating mode" "0,1"
bitfld.long 0x00 25. "CAP_APWM,CAP/APWM operating mode select: 1'b0 ECAP module operates in Capture mode This mode forces the following configuration: 1- Inhibits TSCNT resets via PRD_eq event 2- Inhibits Shadow loads on CAP1 & 2 registers 3- Permits User to enable CAP1-4.." "0,1"
bitfld.long 0x00 24. "SWSYNC,Software forced Counter (TSCNT) sync'ing: 1'b0 Writing a Zero has no effect Reading will always return a zero; 1'b1 Writing a One will force a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits.." "0,1"
bitfld.long 0x00 22.--23. "SYNCO_SEL,Sync-Out select: 2'b00 Select Sync-In event to be the Sync-Out signal (pass through); 2'b01 Select PRD_eq event to be the Sync-Out signal; 2'b10 DISABLE Sync Out Signal; 2'b11 DISABLE Sync Out Signal; Note: Selection PRD_eq is meaningful only.." "0,1,2,3"
bitfld.long 0x00 21. "SYNCI_EN,Counter (TSCNT) Sync-In select mode: 1'b0 Disable Sync-In option 1'b1 Enable Counter (TSCNT) to be loaded from CNTPHS register upon either a SYNCI signal or a S/W force event" "0,1"
bitfld.long 0x00 20. "TSCNTSTP,Counter Stop (freeze) Control: 1'b0 Counter Stopped; 1'b1 Counter Free Running" "0,1"
bitfld.long 0x00 19. "REARM_RESET,One-Shot Re-arming i.e" "0,1"
newline
bitfld.long 0x00 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1-4) of Captures allowed to occur before the CAP(1-4) registers are frozen i.e.Capture sequence is stopped" "0,1,2,3"
bitfld.long 0x00 16. "CONT_ONESHT,Continuous or Oneshot mode control: (applicable only in Capture mode) 1'b0 Operate in Continuous mode 1'b1 Operate in One-Shot mode" "0,1"
bitfld.long 0x00 14.--15. "FREE_SOFT,Emulation Control 2'b00 TSCNT Counter stops immediately on emulation suspend; 2'b01 TSCNT Counter runs until = 0; 2'b1X TSCNT Counter is unaffected by emulation suspend (Run Free)" "0,1,2,3"
bitfld.long 0x00 9.--13. "EVTFLTPS,Event Filter prescale select: 5'b00000 divide by 1 (i.e. no prescale by-pass the prescaler); 5'b00001 divide by 2; 5'b00010 divide by 4; 5'b00011 divide by 6; 5'b00100 divide by 8; 5'b00101 divide by 10;" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a Capture Event: 1'b0 Disable CAP1-4 register loads at capture Event time; 1'b1 Enable CAP1-4 register loads at capture Event time" "0,1"
bitfld.long 0x00 7. "CTRRST4,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 6. "CAP4POL,Capture Event 4 Polarity select: 1'b0 Capture event 4 triggered on a Rising Edge (FE); 1'b1 Capture event 4 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 5. "CTRRST3,Counter Reset on Capture Event" "0,1"
newline
bitfld.long 0x00 4. "CAP3POL,Capture Event 3 Polarity select: 1'b0 Capture event 3 triggered on a Rising Edge (FE); 1'b1 Capture event 3 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 3. "CTRRST2,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 2. "CAP2POL,Capture Event 2 Polarity select: 1'b0 Capture event 2 triggered on a Rising Edge (FE); 1'b1 Capture event 2 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 1. "CTRRST1,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 0. "CAP1POL,Capture Event 1 Polarity select: 1'b0 Capture event 1 triggered on a Rising Edge (FE); 1'b1 Capture event 1 triggered on a Falling Edge (FE)" "0,1"
line.long 0x04 "CTL_STS_ECINT_EN_FLG,"
rbitfld.long 0x04 23. "CMPEQ_FLG,Compare Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Compare register value (ACMP) Reading a 0 indicates no event occurred Note: This flag is only active in APWM mode" "0,1"
rbitfld.long 0x04 22. "PRDEQ_FLG,Period Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Period register value (APER) and was reset" "0,1"
rbitfld.long 0x04 21. "CNTOVF_FLG,Counter Overflow Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) has made the transition from 0xFFFFFFFF 0x00000000 Reading a 0 indicates no event occurred" "0,1"
rbitfld.long 0x04 20. "CEVT4_FLG,Capture Event 4 Status Flag: Reading a 1 on this bit indicates the fourth event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 19. "CEVT3_FLG,Capture Event 3 Status Flag: Reading a 1 on this bit indicates the third event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 18. "CEVT2_FLG,Capture Event 2 Status Flag: Reading a 1 on this bit indicates the second event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 17. "CEVT1_FLG,Capture Event 1 Status Flag: Reading a 1 on this bit indicates the first event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events" "0,1"
newline
bitfld.long 0x04 7. "CMPEQ_EN,Compare Equal Interrupt Enable: 1'b0 Disabled Compare Equal as an Interrupt source; 1'b1 Enable Compare Equal as an Interrupt source" "0,1"
bitfld.long 0x04 6. "PRDEQ_EN,Period Equal Interrupt Enable: 1'b0 Disabled Period Equal as an Interrupt source; 1'b1 Enable Period Equal as an Interrupt source" "0,1"
bitfld.long 0x04 5. "CNTOVF_EN,Counter Overflow Interrupt Enable: 1'b0 Disabled Counter Overflow as an Interrupt source; 1'b1 Enable Counter Overflow as an Interrupt source" "0,1"
bitfld.long 0x04 4. "CEVT4_EN,Capture Event 4 Interrupt Enable: 1'b0 Disabled Capture Event 4 as an Interrupt source: 1'b1 Enable Capture Event 4 as an Interrupt source" "0,1"
bitfld.long 0x04 3. "CEVT3_EN,Capture Event 3 Interrupt Enable: 1'b0 Disabled Capture Event 3 as an Interrupt source: 1'b1 Enable Capture Event 3 as an Interrupt source" "0,1"
bitfld.long 0x04 2. "CEVT2_EN,Capture Event 2 Interrupt Enable: 1'b0 Disabled Capture Event 2 as an Interrupt source: 1'b1 Enable Capture Event 2 as an Interrupt source" "0,1"
bitfld.long 0x04 1. "CEVT1_EN,Capture Event 1 Interrupt Enable: 1'b0 Disabled Capture Event 1 as an Interrupt source: 1'b1 Enable Capture Event 1 as an Interrupt source" "0,1"
line.long 0x08 "CTL_STS_ECINT_CLR_FRC,"
bitfld.long 0x08 23. "CMPEQ_FRC,Force Compare Equal: Writing a 1 to this bit will set the CMPEQ flag bit" "0,1"
bitfld.long 0x08 22. "PRDEQ_FRC,Force Period Equal: Writing a 1 to this bit will set the PRDEQ flag bit" "0,1"
bitfld.long 0x08 21. "CNTOVF_FRC,Force Counter Overflow: Writing a 1 to this bit will set the CNTOVF flag bit" "0,1"
bitfld.long 0x08 20. "CEVT4_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 19. "CEVT3_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 18. "CEVT2_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 17. "CEVT1_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 7. "CMPEQ_CLR,Compare Equal Status Flag: Writing a 1 will clear the CMPEQ flag condition" "0,1"
newline
bitfld.long 0x08 6. "PRDEQ_CLR,Period Equal Status Flag: Writing a 1 will clear the PRDEQ flag condition" "0,1"
bitfld.long 0x08 5. "CNTOVF_CLR,Counter Overflow Status Flag: Writing a 1 will clear the CNTOVF flag condition" "0,1"
bitfld.long 0x08 4. "CEVT4_CLR,Capture Event 4 Status Flag: Writing a 1 will clear the CEVT4 flag condition" "0,1"
bitfld.long 0x08 3. "CEVT3_CLR,Capture Event 3 Status Flag: Writing a 1 will clear the CEVT3 flag condition" "0,1"
bitfld.long 0x08 2. "CEVT2_CLR,Capture Event 2 Status Flag: Writing a 1 will clear the CEVT2 flag condition" "0,1"
bitfld.long 0x08 1. "CEVT1_CLR,Capture Event 1 Status Flag: Writing a 1 will clear the CEVT1 flag condition" "0,1"
bitfld.long 0x08 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "CTL_STS_PID,"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,"
bitfld.long 0x00 11.--15. "RTL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "ECAP1_CTL_STS"
base ad:0x23110000
group.long 0x00++0x17
line.long 0x00 "CTL_STS_TSCNT,"
line.long 0x04 "CTL_STS_CNTPHS,"
line.long 0x08 "CTL_STS_CAP1,"
line.long 0x0C "CTL_STS_CAP2,"
line.long 0x10 "CTL_STS_CAP3,"
line.long 0x14 "CTL_STS_CAP4,"
group.long 0x28++0x0B
line.long 0x00 "CTL_STS_ECCTL,"
rbitfld.long 0x00 27.--31. "FILTER," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "APWMPOL,APWM output polarity select: 1'b0 Output is Active High (i.e. Compare value defines High time); 1'b1 Output is Active Low (i.e. Compare value defines Low time); Note: This is applicable only in APWM operating mode" "0,1"
bitfld.long 0x00 25. "CAP_APWM,CAP/APWM operating mode select: 1'b0 ECAP module operates in Capture mode This mode forces the following configuration: 1- Inhibits TSCNT resets via PRD_eq event 2- Inhibits Shadow loads on CAP1 & 2 registers 3- Permits User to enable CAP1-4.." "0,1"
bitfld.long 0x00 24. "SWSYNC,Software forced Counter (TSCNT) sync'ing: 1'b0 Writing a Zero has no effect Reading will always return a zero; 1'b1 Writing a One will force a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits.." "0,1"
bitfld.long 0x00 22.--23. "SYNCO_SEL,Sync-Out select: 2'b00 Select Sync-In event to be the Sync-Out signal (pass through); 2'b01 Select PRD_eq event to be the Sync-Out signal; 2'b10 DISABLE Sync Out Signal; 2'b11 DISABLE Sync Out Signal; Note: Selection PRD_eq is meaningful only.." "0,1,2,3"
bitfld.long 0x00 21. "SYNCI_EN,Counter (TSCNT) Sync-In select mode: 1'b0 Disable Sync-In option 1'b1 Enable Counter (TSCNT) to be loaded from CNTPHS register upon either a SYNCI signal or a S/W force event" "0,1"
bitfld.long 0x00 20. "TSCNTSTP,Counter Stop (freeze) Control: 1'b0 Counter Stopped; 1'b1 Counter Free Running" "0,1"
bitfld.long 0x00 19. "REARM_RESET,One-Shot Re-arming i.e" "0,1"
newline
bitfld.long 0x00 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1-4) of Captures allowed to occur before the CAP(1-4) registers are frozen i.e.Capture sequence is stopped" "0,1,2,3"
bitfld.long 0x00 16. "CONT_ONESHT,Continuous or Oneshot mode control: (applicable only in Capture mode) 1'b0 Operate in Continuous mode 1'b1 Operate in One-Shot mode" "0,1"
bitfld.long 0x00 14.--15. "FREE_SOFT,Emulation Control 2'b00 TSCNT Counter stops immediately on emulation suspend; 2'b01 TSCNT Counter runs until = 0; 2'b1X TSCNT Counter is unaffected by emulation suspend (Run Free)" "0,1,2,3"
bitfld.long 0x00 9.--13. "EVTFLTPS,Event Filter prescale select: 5'b00000 divide by 1 (i.e. no prescale by-pass the prescaler); 5'b00001 divide by 2; 5'b00010 divide by 4; 5'b00011 divide by 6; 5'b00100 divide by 8; 5'b00101 divide by 10;" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a Capture Event: 1'b0 Disable CAP1-4 register loads at capture Event time; 1'b1 Enable CAP1-4 register loads at capture Event time" "0,1"
bitfld.long 0x00 7. "CTRRST4,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 6. "CAP4POL,Capture Event 4 Polarity select: 1'b0 Capture event 4 triggered on a Rising Edge (FE); 1'b1 Capture event 4 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 5. "CTRRST3,Counter Reset on Capture Event" "0,1"
newline
bitfld.long 0x00 4. "CAP3POL,Capture Event 3 Polarity select: 1'b0 Capture event 3 triggered on a Rising Edge (FE); 1'b1 Capture event 3 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 3. "CTRRST2,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 2. "CAP2POL,Capture Event 2 Polarity select: 1'b0 Capture event 2 triggered on a Rising Edge (FE); 1'b1 Capture event 2 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 1. "CTRRST1,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 0. "CAP1POL,Capture Event 1 Polarity select: 1'b0 Capture event 1 triggered on a Rising Edge (FE); 1'b1 Capture event 1 triggered on a Falling Edge (FE)" "0,1"
line.long 0x04 "CTL_STS_ECINT_EN_FLG,"
rbitfld.long 0x04 23. "CMPEQ_FLG,Compare Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Compare register value (ACMP) Reading a 0 indicates no event occurred Note: This flag is only active in APWM mode" "0,1"
rbitfld.long 0x04 22. "PRDEQ_FLG,Period Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Period register value (APER) and was reset" "0,1"
rbitfld.long 0x04 21. "CNTOVF_FLG,Counter Overflow Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) has made the transition from 0xFFFFFFFF 0x00000000 Reading a 0 indicates no event occurred" "0,1"
rbitfld.long 0x04 20. "CEVT4_FLG,Capture Event 4 Status Flag: Reading a 1 on this bit indicates the fourth event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 19. "CEVT3_FLG,Capture Event 3 Status Flag: Reading a 1 on this bit indicates the third event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 18. "CEVT2_FLG,Capture Event 2 Status Flag: Reading a 1 on this bit indicates the second event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 17. "CEVT1_FLG,Capture Event 1 Status Flag: Reading a 1 on this bit indicates the first event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events" "0,1"
newline
bitfld.long 0x04 7. "CMPEQ_EN,Compare Equal Interrupt Enable: 1'b0 Disabled Compare Equal as an Interrupt source; 1'b1 Enable Compare Equal as an Interrupt source" "0,1"
bitfld.long 0x04 6. "PRDEQ_EN,Period Equal Interrupt Enable: 1'b0 Disabled Period Equal as an Interrupt source; 1'b1 Enable Period Equal as an Interrupt source" "0,1"
bitfld.long 0x04 5. "CNTOVF_EN,Counter Overflow Interrupt Enable: 1'b0 Disabled Counter Overflow as an Interrupt source; 1'b1 Enable Counter Overflow as an Interrupt source" "0,1"
bitfld.long 0x04 4. "CEVT4_EN,Capture Event 4 Interrupt Enable: 1'b0 Disabled Capture Event 4 as an Interrupt source: 1'b1 Enable Capture Event 4 as an Interrupt source" "0,1"
bitfld.long 0x04 3. "CEVT3_EN,Capture Event 3 Interrupt Enable: 1'b0 Disabled Capture Event 3 as an Interrupt source: 1'b1 Enable Capture Event 3 as an Interrupt source" "0,1"
bitfld.long 0x04 2. "CEVT2_EN,Capture Event 2 Interrupt Enable: 1'b0 Disabled Capture Event 2 as an Interrupt source: 1'b1 Enable Capture Event 2 as an Interrupt source" "0,1"
bitfld.long 0x04 1. "CEVT1_EN,Capture Event 1 Interrupt Enable: 1'b0 Disabled Capture Event 1 as an Interrupt source: 1'b1 Enable Capture Event 1 as an Interrupt source" "0,1"
line.long 0x08 "CTL_STS_ECINT_CLR_FRC,"
bitfld.long 0x08 23. "CMPEQ_FRC,Force Compare Equal: Writing a 1 to this bit will set the CMPEQ flag bit" "0,1"
bitfld.long 0x08 22. "PRDEQ_FRC,Force Period Equal: Writing a 1 to this bit will set the PRDEQ flag bit" "0,1"
bitfld.long 0x08 21. "CNTOVF_FRC,Force Counter Overflow: Writing a 1 to this bit will set the CNTOVF flag bit" "0,1"
bitfld.long 0x08 20. "CEVT4_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 19. "CEVT3_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 18. "CEVT2_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 17. "CEVT1_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 7. "CMPEQ_CLR,Compare Equal Status Flag: Writing a 1 will clear the CMPEQ flag condition" "0,1"
newline
bitfld.long 0x08 6. "PRDEQ_CLR,Period Equal Status Flag: Writing a 1 will clear the PRDEQ flag condition" "0,1"
bitfld.long 0x08 5. "CNTOVF_CLR,Counter Overflow Status Flag: Writing a 1 will clear the CNTOVF flag condition" "0,1"
bitfld.long 0x08 4. "CEVT4_CLR,Capture Event 4 Status Flag: Writing a 1 will clear the CEVT4 flag condition" "0,1"
bitfld.long 0x08 3. "CEVT3_CLR,Capture Event 3 Status Flag: Writing a 1 will clear the CEVT3 flag condition" "0,1"
bitfld.long 0x08 2. "CEVT2_CLR,Capture Event 2 Status Flag: Writing a 1 will clear the CEVT2 flag condition" "0,1"
bitfld.long 0x08 1. "CEVT1_CLR,Capture Event 1 Status Flag: Writing a 1 will clear the CEVT1 flag condition" "0,1"
bitfld.long 0x08 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "CTL_STS_PID,"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,"
bitfld.long 0x00 11.--15. "RTL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "ECAP2_CTL_STS"
base ad:0x23120000
group.long 0x00++0x17
line.long 0x00 "CTL_STS_TSCNT,"
line.long 0x04 "CTL_STS_CNTPHS,"
line.long 0x08 "CTL_STS_CAP1,"
line.long 0x0C "CTL_STS_CAP2,"
line.long 0x10 "CTL_STS_CAP3,"
line.long 0x14 "CTL_STS_CAP4,"
group.long 0x28++0x0B
line.long 0x00 "CTL_STS_ECCTL,"
rbitfld.long 0x00 27.--31. "FILTER," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "APWMPOL,APWM output polarity select: 1'b0 Output is Active High (i.e. Compare value defines High time); 1'b1 Output is Active Low (i.e. Compare value defines Low time); Note: This is applicable only in APWM operating mode" "0,1"
bitfld.long 0x00 25. "CAP_APWM,CAP/APWM operating mode select: 1'b0 ECAP module operates in Capture mode This mode forces the following configuration: 1- Inhibits TSCNT resets via PRD_eq event 2- Inhibits Shadow loads on CAP1 & 2 registers 3- Permits User to enable CAP1-4.." "0,1"
bitfld.long 0x00 24. "SWSYNC,Software forced Counter (TSCNT) sync'ing: 1'b0 Writing a Zero has no effect Reading will always return a zero; 1'b1 Writing a One will force a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits.." "0,1"
bitfld.long 0x00 22.--23. "SYNCO_SEL,Sync-Out select: 2'b00 Select Sync-In event to be the Sync-Out signal (pass through); 2'b01 Select PRD_eq event to be the Sync-Out signal; 2'b10 DISABLE Sync Out Signal; 2'b11 DISABLE Sync Out Signal; Note: Selection PRD_eq is meaningful only.." "0,1,2,3"
bitfld.long 0x00 21. "SYNCI_EN,Counter (TSCNT) Sync-In select mode: 1'b0 Disable Sync-In option 1'b1 Enable Counter (TSCNT) to be loaded from CNTPHS register upon either a SYNCI signal or a S/W force event" "0,1"
bitfld.long 0x00 20. "TSCNTSTP,Counter Stop (freeze) Control: 1'b0 Counter Stopped; 1'b1 Counter Free Running" "0,1"
bitfld.long 0x00 19. "REARM_RESET,One-Shot Re-arming i.e" "0,1"
newline
bitfld.long 0x00 17.--18. "STOPVALUE,Stop value for One-Shot mode: This is the number (between 1-4) of Captures allowed to occur before the CAP(1-4) registers are frozen i.e.Capture sequence is stopped" "0,1,2,3"
bitfld.long 0x00 16. "CONT_ONESHT,Continuous or Oneshot mode control: (applicable only in Capture mode) 1'b0 Operate in Continuous mode 1'b1 Operate in One-Shot mode" "0,1"
bitfld.long 0x00 14.--15. "FREE_SOFT,Emulation Control 2'b00 TSCNT Counter stops immediately on emulation suspend; 2'b01 TSCNT Counter runs until = 0; 2'b1X TSCNT Counter is unaffected by emulation suspend (Run Free)" "0,1,2,3"
bitfld.long 0x00 9.--13. "EVTFLTPS,Event Filter prescale select: 5'b00000 divide by 1 (i.e. no prescale by-pass the prescaler); 5'b00001 divide by 2; 5'b00010 divide by 4; 5'b00011 divide by 6; 5'b00100 divide by 8; 5'b00101 divide by 10;" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a Capture Event: 1'b0 Disable CAP1-4 register loads at capture Event time; 1'b1 Enable CAP1-4 register loads at capture Event time" "0,1"
bitfld.long 0x00 7. "CTRRST4,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 6. "CAP4POL,Capture Event 4 Polarity select: 1'b0 Capture event 4 triggered on a Rising Edge (FE); 1'b1 Capture event 4 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 5. "CTRRST3,Counter Reset on Capture Event" "0,1"
newline
bitfld.long 0x00 4. "CAP3POL,Capture Event 3 Polarity select: 1'b0 Capture event 3 triggered on a Rising Edge (FE); 1'b1 Capture event 3 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 3. "CTRRST2,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 2. "CAP2POL,Capture Event 2 Polarity select: 1'b0 Capture event 2 triggered on a Rising Edge (FE); 1'b1 Capture event 2 triggered on a Falling Edge (FE)" "0,1"
bitfld.long 0x00 1. "CTRRST1,Counter Reset on Capture Event" "0,1"
bitfld.long 0x00 0. "CAP1POL,Capture Event 1 Polarity select: 1'b0 Capture event 1 triggered on a Rising Edge (FE); 1'b1 Capture event 1 triggered on a Falling Edge (FE)" "0,1"
line.long 0x04 "CTL_STS_ECINT_EN_FLG,"
rbitfld.long 0x04 23. "CMPEQ_FLG,Compare Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Compare register value (ACMP) Reading a 0 indicates no event occurred Note: This flag is only active in APWM mode" "0,1"
rbitfld.long 0x04 22. "PRDEQ_FLG,Period Equal Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) reached the Period register value (APER) and was reset" "0,1"
rbitfld.long 0x04 21. "CNTOVF_FLG,Counter Overflow Status Flag: Reading a 1 on this bit indicates the Counter (TSCNT) has made the transition from 0xFFFFFFFF 0x00000000 Reading a 0 indicates no event occurred" "0,1"
rbitfld.long 0x04 20. "CEVT4_FLG,Capture Event 4 Status Flag: Reading a 1 on this bit indicates the fourth event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 19. "CEVT3_FLG,Capture Event 3 Status Flag: Reading a 1 on this bit indicates the third event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 18. "CEVT2_FLG,Capture Event 2 Status Flag: Reading a 1 on this bit indicates the second event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 17. "CEVT1_FLG,Capture Event 1 Status Flag: Reading a 1 on this bit indicates the first event occurred at ECAPx pin" "0,1"
rbitfld.long 0x04 16. "INT_FLG,Global Interrupt Status Flag: Reading a 1 on this bit indicates that an interrupt was generated from one of the following events" "0,1"
newline
bitfld.long 0x04 7. "CMPEQ_EN,Compare Equal Interrupt Enable: 1'b0 Disabled Compare Equal as an Interrupt source; 1'b1 Enable Compare Equal as an Interrupt source" "0,1"
bitfld.long 0x04 6. "PRDEQ_EN,Period Equal Interrupt Enable: 1'b0 Disabled Period Equal as an Interrupt source; 1'b1 Enable Period Equal as an Interrupt source" "0,1"
bitfld.long 0x04 5. "CNTOVF_EN,Counter Overflow Interrupt Enable: 1'b0 Disabled Counter Overflow as an Interrupt source; 1'b1 Enable Counter Overflow as an Interrupt source" "0,1"
bitfld.long 0x04 4. "CEVT4_EN,Capture Event 4 Interrupt Enable: 1'b0 Disabled Capture Event 4 as an Interrupt source: 1'b1 Enable Capture Event 4 as an Interrupt source" "0,1"
bitfld.long 0x04 3. "CEVT3_EN,Capture Event 3 Interrupt Enable: 1'b0 Disabled Capture Event 3 as an Interrupt source: 1'b1 Enable Capture Event 3 as an Interrupt source" "0,1"
bitfld.long 0x04 2. "CEVT2_EN,Capture Event 2 Interrupt Enable: 1'b0 Disabled Capture Event 2 as an Interrupt source: 1'b1 Enable Capture Event 2 as an Interrupt source" "0,1"
bitfld.long 0x04 1. "CEVT1_EN,Capture Event 1 Interrupt Enable: 1'b0 Disabled Capture Event 1 as an Interrupt source: 1'b1 Enable Capture Event 1 as an Interrupt source" "0,1"
line.long 0x08 "CTL_STS_ECINT_CLR_FRC,"
bitfld.long 0x08 23. "CMPEQ_FRC,Force Compare Equal: Writing a 1 to this bit will set the CMPEQ flag bit" "0,1"
bitfld.long 0x08 22. "PRDEQ_FRC,Force Period Equal: Writing a 1 to this bit will set the PRDEQ flag bit" "0,1"
bitfld.long 0x08 21. "CNTOVF_FRC,Force Counter Overflow: Writing a 1 to this bit will set the CNTOVF flag bit" "0,1"
bitfld.long 0x08 20. "CEVT4_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 19. "CEVT3_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 18. "CEVT2_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 17. "CEVT1_FRC,Force Capture Event" "0,1"
bitfld.long 0x08 7. "CMPEQ_CLR,Compare Equal Status Flag: Writing a 1 will clear the CMPEQ flag condition" "0,1"
newline
bitfld.long 0x08 6. "PRDEQ_CLR,Period Equal Status Flag: Writing a 1 will clear the PRDEQ flag condition" "0,1"
bitfld.long 0x08 5. "CNTOVF_CLR,Counter Overflow Status Flag: Writing a 1 will clear the CNTOVF flag condition" "0,1"
bitfld.long 0x08 4. "CEVT4_CLR,Capture Event 4 Status Flag: Writing a 1 will clear the CEVT4 flag condition" "0,1"
bitfld.long 0x08 3. "CEVT3_CLR,Capture Event 3 Status Flag: Writing a 1 will clear the CEVT3 flag condition" "0,1"
bitfld.long 0x08 2. "CEVT2_CLR,Capture Event 2 Status Flag: Writing a 1 will clear the CEVT2 flag condition" "0,1"
bitfld.long 0x08 1. "CEVT1_CLR,Capture Event 1 Status Flag: Writing a 1 will clear the CEVT1 flag condition" "0,1"
bitfld.long 0x08 0. "INT_CLR,Global Interrupt Clear Flag: Writing a 1 will clear the INT flag and enable further interrupts to be generated if any of the event flags are set to 1" "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "CTL_STS_PID,"
bitfld.long 0x00 30.--31. "SCHEME," "0,1,2,3"
bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,"
bitfld.long 0x00 11.--15. "RTL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "ELM0"
base ad:0x25010000
rgroup.long 0x00++0x03
line.long 0x00 "MEM_ELM_REVISION,This register contains the IP revision code.(A write to this register has no effect. the same as the reset)"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_0,Read returns 0"
hexmask.long.byte 0x00 0.--7. 1. "REV_NUMBER,IP revision number [RTL] [7:4] Major revision [3:0] Minor revision"
group.long 0x10++0x13
line.long 0x00 "MEM_ELM_SYSCONFIG,This register allows controlling various parameters of the OCP interface"
bitfld.long 0x00 8. "CLOCKACTIVITYOCP,OCP Clock activity when module is in IDLE mode [during wake up mode period]" "0,1"
bitfld.long 0x00 3.--4. "SIDLEMODE,Slave interface power management [IDLE req/ack control]" "0,1,2,3"
newline
bitfld.long 0x00 1. "SOFTRESET,Module Software Reset The bit is automatically reset by the hardware [During reads it always returns 0] It has same effect as the OCP Hardware reset" "0,1"
bitfld.long 0x00 0. "AUTOGATING,Internal OCP clock gating strategy [no module visible impact other than saving power]" "0,1"
line.long 0x04 "MEM_ELM_SYSSTATUS,Internal Reset monitoring (OCP domain)Undefined since:on HW perspective reset state is 0on SW user perspective when module is accessible is 1"
bitfld.long 0x04 0. "RESETDONE,Internal Reset monitoring [OCP domain] Undefined since: on HW perspective reset state is 0 on SW user perspective when module is accessible is 1" "0,1"
line.long 0x08 "MEM_ELM_IRQSTATUS,Interrupt status"
bitfld.long 0x08 8. "PAGE_VALID,Error location status for a full page based on the mask definition Read" "no effect,clear interrupt"
bitfld.long 0x08 7. "LOC_VALID_7,Error location status for syndrome polynomial 7" "no effect,clear interrupt"
newline
bitfld.long 0x08 6. "LOC_VALID_6,Error location status for syndrome polynomial 6" "0,1"
bitfld.long 0x08 5. "LOC_VALID_5,Error location status for syndrome polynomial 5" "0,1"
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bitfld.long 0x08 4. "LOC_VALID_4,Error location status for syndrome polynomial 4" "0,1"
bitfld.long 0x08 3. "LOC_VALID_3,Error location status for syndrome polynomial 3" "0,1"
newline
bitfld.long 0x08 2. "LOC_VALID_2,Error location status for syndrome polynomial 2" "0,1"
bitfld.long 0x08 1. "LOC_VALID_1,Error location status for syndrome polynomial 1" "0,1"
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bitfld.long 0x08 0. "LOC_VALID_0,Error location status for syndrome polynomial 0" "0,1"
line.long 0x0C "MEM_ELM_IRQENABLE,Interrupt enable"
bitfld.long 0x0C 8. "PAGE_MASK,Page interrupt mask bit" "disable interrupt,enable interrupt"
bitfld.long 0x0C 7. "LOCATION_MASK_7,Error location interrupt mask bit for syndrome polynomial 7" "0,1"
newline
bitfld.long 0x0C 6. "LOCATION_MASK_6,Error location interrupt mask bit for syndrome polynomial 6" "0,1"
bitfld.long 0x0C 5. "LOCATION_MASK_5,Error location interrupt mask bit for syndrome polynomial 5" "0,1"
newline
bitfld.long 0x0C 4. "LOCATION_MASK_4,Error location interrupt mask bit for syndrome polynomial 4" "0,1"
bitfld.long 0x0C 3. "LOCATION_MASK_3,Error location interrupt mask bit for syndrome polynomial 3" "0,1"
newline
bitfld.long 0x0C 2. "LOCATION_MASK_2,Error location interrupt mask bit for syndrome polynomial 2" "0,1"
bitfld.long 0x0C 1. "LOCATION_MASK_1,Error location interrupt mask bit for syndrome polynomial 1" "0,1"
newline
bitfld.long 0x0C 0. "LOCATION_MASK_0,Error location interrupt mask bit for syndrome polynomial 0" "disable interrupt,enable interrupt"
line.long 0x10 "MEM_ELM_LOCATION_CONFIG,ECC algorithm parameters"
hexmask.long.word 0x10 16.--26. 1. "ECC_SIZE,Maximum size of the buffers for which the error location engine is used in number of nibbles [4-bits entities]"
bitfld.long 0x10 0.--1. "ECC_BCH_LEVEL,Error correction level" "4 bits,8 bits,16 bits,reserved"
group.long 0x80++0x03
line.long 0x00 "MEM_ELM_PAGE_CTRL,Page definition"
bitfld.long 0x00 7. "SECTOR_7,Set to 1 if syndrome polynomial 7 is part of the page in page mode Must be 0 in continuous mode" "0,1"
bitfld.long 0x00 6. "SECTOR_6,Set to 1 if syndrome polynomial 6 is part of the page in page mode Must be 0 in continuous mode" "0,1"
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bitfld.long 0x00 5. "SECTOR_5,Set to 1 if syndrome polynomial 5 is part of the page in page mode Must be 0 in continuous mode" "0,1"
bitfld.long 0x00 4. "SECTOR_4,Set to 1 if syndrome polynomial 4 is part of the page in page mode Must be 0 in continuous mode" "0,1"
newline
bitfld.long 0x00 3. "SECTOR_3,Set to 1 if syndrome polynomial 3 is part of the page in page mode Must be 0 in continuous mode" "0,1"
bitfld.long 0x00 2. "SECTOR_2,Set to 1 if syndrome polynomial 2 is part of the page in page mode Must be 0 in continuous mode" "0,1"
newline
bitfld.long 0x00 1. "SECTOR_1,Set to 1 if syndrome polynomial 1 is part of the page in page mode Must be 0 in continuous mode" "0,1"
bitfld.long 0x00 0. "SECTOR_0,Set to 1 if syndrome polynomial 0 is part of the page in page mode Must be 0 in continuous mode" "0,1"
group.long 0x400++0x1B
line.long 0x00 "MEM_ELM_SYNDROME_FRAGMENT_0,Input syndrome polynomial bits 0 to 31"
line.long 0x04 "MEM_ELM_SYNDROME_FRAGMENT_1,Input syndrome polynomial bits 32 to 63"
line.long 0x08 "MEM_ELM_SYNDROME_FRAGMENT_2,Input syndrome polynomial bits 64 to 95"
line.long 0x0C "MEM_ELM_SYNDROME_FRAGMENT_3,Input syndrome polynomial bits 96 to 127"
line.long 0x10 "MEM_ELM_SYNDROME_FRAGMENT_4,Input syndrome polynomial bits 128 to 159"
line.long 0x14 "MEM_ELM_SYNDROME_FRAGMENT_5,Input syndrome polynomial bits 160 to 191"
line.long 0x18 "MEM_ELM_SYNDROME_FRAGMENT_6,Input syndrome polynomial bits 192 to 207"
bitfld.long 0x18 16. "SYNDROME_VALID,Syndrome valid bit" "this syndrome polynomial should not be processed,this syndrome polynomial must be processed"
hexmask.long.word 0x18 0.--15. 1. "SYNDROME_6,Syndrome bits 192 to 207"
rgroup.long 0x800++0x03
line.long 0x00 "MEM_ELM_LOCATION_STATUS,Exit status for the syndrome polynomial processing"
bitfld.long 0x00 8. "ECC_CORRECTABLE,Error location process exit status" "ECC error location process failed Number of..,all errors were successfully located Number of.."
bitfld.long 0x00 0.--4. "ECC_NB_ERRORS,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x880)++0x03
line.long 0x00 "MEM_ELM_ERROR_LOCATION_$1,Error location register"
hexmask.long.word 0x00 0.--12. 1. "ECC_ERROR_LOCATION,Error location bit address"
repeat.end
tree.end
tree "EPWM0_EPWM"
base ad:0x23000000
group.word 0x00++0x0B
line.word 0x00 "EPWM_REGS_TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events" "0,1,2,3"
bitfld.word 0x00 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase.." "0,1"
bitfld.word 0x00 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7"
bitfld.word 0x00 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1"
bitfld.word 0x00 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3"
bitfld.word 0x00 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1"
bitfld.word 0x00 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1"
bitfld.word 0x00 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3"
line.word 0x02 "EPWM_REGS_TBSTS,Time-Base Status Register"
bitfld.word 0x02 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1"
bitfld.word 0x02 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1"
rbitfld.word 0x02 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1"
line.word 0x04 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register"
hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x06 "EPWM_REGS_TBPHS,Time Base Phase Register"
line.word 0x08 "EPWM_REGS_TBCNT,Time Base Counter Register"
line.word 0x0A "EPWM_REGS_TBPRD,Time Base Period Register"
group.word 0x0E++0x17
line.word 0x00 "EPWM_REGS_CMPCTL,Counter Compare Control Register"
rbitfld.word 0x00 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
rbitfld.word 0x00 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self.." "0,1"
bitfld.word 0x00 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1"
bitfld.word 0x00 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1"
bitfld.word 0x00 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3"
bitfld.word 0x00 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3"
line.word 0x02 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register"
hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h"
line.word 0x04 "EPWM_REGS_CMPA,Counter Compare A Register"
line.word 0x06 "EPWM_REGS_CMPB,Counter Compare B Register"
line.word 0x08 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A"
bitfld.word 0x08 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x08 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x08 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x08 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x08 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x08 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0x0A "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B"
bitfld.word 0x0A 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x0A 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x0A 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x0A 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x0A 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x0A 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0x0C "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register"
bitfld.word 0x0C 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3"
bitfld.word 0x0C 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1"
bitfld.word 0x0C 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3"
bitfld.word 0x0C 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1"
bitfld.word 0x0C 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3"
line.word 0x0E "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register"
bitfld.word 0x0E 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3"
bitfld.word 0x0E 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3"
line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms the default is EPWMxA In is.." "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3"
bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3"
line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter"
line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter"
line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register"
hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low a one-shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA and.."
hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low a cycle-by-cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA.."
group.word 0x28++0x15
line.word 0x00 "EPWM_REGS_TZCTL,Trip Zone Control Register"
bitfld.word 0x00 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
bitfld.word 0x00 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
line.word 0x02 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register"
bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1"
bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1"
line.word 0x04 "EPWM_REGS_TZFLG,Trip Zone Flag Register"
bitfld.word 0x04 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1"
bitfld.word 0x04 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1"
bitfld.word 0x04 0. "INT,Latched Trip Interrupt Status Flag" "0,1"
line.word 0x06 "EPWM_REGS_TZCLR,Trip Zone Clear Register"
bitfld.word 0x06 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1"
bitfld.word 0x06 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1"
bitfld.word 0x06 0. "INT,Global Interrupt Clear Flag" "0,1"
line.word 0x08 "EPWM_REGS_TZFRC,Trip Zone Force Register"
bitfld.word 0x08 2. "OST,Force a One-Shot Trip Event via Software" "0,1"
bitfld.word 0x08 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1"
line.word 0x0A "EPWM_REGS_ETSEL,Event Trigger Selection Register"
bitfld.word 0x0A 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1"
bitfld.word 0x0A 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7"
line.word 0x0C "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register"
rbitfld.word 0x0C 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled ETSEL[INT] = 0 or the.." "0,1,2,3"
bitfld.word 0x0C 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3"
line.word 0x0E "EPWM_REGS_ETFLG,Event Trigger Flag Register"
bitfld.word 0x0E 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1"
line.word 0x10 "EPWM_REGS_ETCLR,Event Trigger Clear Register"
bitfld.word 0x10 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x12 "EPWM_REGS_ETFRC,Event Trigger Force Register"
bitfld.word 0x12 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1"
line.word 0x14 "EPWM_REGS_PCCTL,PWM Chopper Control Register"
bitfld.word 0x14 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x14 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7"
bitfld.word 0x14 1.--4. "OSHTWTH,One-Shot Pulse Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x14 0. "CHPEN,PWM-chopping Enable" "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "EPWM_REGS_PID,EHRPWM Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,FUNC"
bitfld.long 0x00 11.--15. "R_RTL,RTL version [R] maintained by IP design owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,CUSTOM" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor revision [Y]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "EPWM1_EPWM"
base ad:0x23010000
group.word 0x00++0x0B
line.word 0x00 "EPWM_REGS_TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events" "0,1,2,3"
bitfld.word 0x00 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase.." "0,1"
bitfld.word 0x00 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7"
bitfld.word 0x00 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1"
bitfld.word 0x00 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3"
bitfld.word 0x00 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1"
bitfld.word 0x00 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1"
bitfld.word 0x00 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3"
line.word 0x02 "EPWM_REGS_TBSTS,Time-Base Status Register"
bitfld.word 0x02 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1"
bitfld.word 0x02 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1"
rbitfld.word 0x02 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1"
line.word 0x04 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register"
hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x06 "EPWM_REGS_TBPHS,Time Base Phase Register"
line.word 0x08 "EPWM_REGS_TBCNT,Time Base Counter Register"
line.word 0x0A "EPWM_REGS_TBPRD,Time Base Period Register"
group.word 0x0E++0x17
line.word 0x00 "EPWM_REGS_CMPCTL,Counter Compare Control Register"
rbitfld.word 0x00 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
rbitfld.word 0x00 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self.." "0,1"
bitfld.word 0x00 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1"
bitfld.word 0x00 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1"
bitfld.word 0x00 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3"
bitfld.word 0x00 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3"
line.word 0x02 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register"
hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h"
line.word 0x04 "EPWM_REGS_CMPA,Counter Compare A Register"
line.word 0x06 "EPWM_REGS_CMPB,Counter Compare B Register"
line.word 0x08 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A"
bitfld.word 0x08 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x08 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x08 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x08 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x08 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x08 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0x0A "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B"
bitfld.word 0x0A 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x0A 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x0A 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x0A 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x0A 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x0A 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0x0C "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register"
bitfld.word 0x0C 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3"
bitfld.word 0x0C 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1"
bitfld.word 0x0C 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3"
bitfld.word 0x0C 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1"
bitfld.word 0x0C 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3"
line.word 0x0E "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register"
bitfld.word 0x0E 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3"
bitfld.word 0x0E 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3"
line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms the default is EPWMxA In is.." "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3"
bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3"
line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter"
line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter"
line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register"
hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low a one-shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA and.."
hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low a cycle-by-cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA.."
group.word 0x28++0x15
line.word 0x00 "EPWM_REGS_TZCTL,Trip Zone Control Register"
bitfld.word 0x00 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
bitfld.word 0x00 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
line.word 0x02 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register"
bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1"
bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1"
line.word 0x04 "EPWM_REGS_TZFLG,Trip Zone Flag Register"
bitfld.word 0x04 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1"
bitfld.word 0x04 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1"
bitfld.word 0x04 0. "INT,Latched Trip Interrupt Status Flag" "0,1"
line.word 0x06 "EPWM_REGS_TZCLR,Trip Zone Clear Register"
bitfld.word 0x06 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1"
bitfld.word 0x06 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1"
bitfld.word 0x06 0. "INT,Global Interrupt Clear Flag" "0,1"
line.word 0x08 "EPWM_REGS_TZFRC,Trip Zone Force Register"
bitfld.word 0x08 2. "OST,Force a One-Shot Trip Event via Software" "0,1"
bitfld.word 0x08 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1"
line.word 0x0A "EPWM_REGS_ETSEL,Event Trigger Selection Register"
bitfld.word 0x0A 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1"
bitfld.word 0x0A 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7"
line.word 0x0C "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register"
rbitfld.word 0x0C 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled ETSEL[INT] = 0 or the.." "0,1,2,3"
bitfld.word 0x0C 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3"
line.word 0x0E "EPWM_REGS_ETFLG,Event Trigger Flag Register"
bitfld.word 0x0E 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1"
line.word 0x10 "EPWM_REGS_ETCLR,Event Trigger Clear Register"
bitfld.word 0x10 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x12 "EPWM_REGS_ETFRC,Event Trigger Force Register"
bitfld.word 0x12 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1"
line.word 0x14 "EPWM_REGS_PCCTL,PWM Chopper Control Register"
bitfld.word 0x14 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x14 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7"
bitfld.word 0x14 1.--4. "OSHTWTH,One-Shot Pulse Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x14 0. "CHPEN,PWM-chopping Enable" "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "EPWM_REGS_PID,EHRPWM Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,FUNC"
bitfld.long 0x00 11.--15. "R_RTL,RTL version [R] maintained by IP design owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,CUSTOM" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor revision [Y]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "EPWM2_EPWM"
base ad:0x23020000
group.word 0x00++0x0B
line.word 0x00 "EPWM_REGS_TBCTL,Time-Base Control Register"
bitfld.word 0x00 14.--15. "FREE_SOFT,Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events" "0,1,2,3"
bitfld.word 0x00 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase.." "0,1"
bitfld.word 0x00 10.--12. "CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV]" "0,1,2,3,4,5,6,7"
bitfld.word 0x00 7.--9. "HSPCLKDIV,High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0,1,2,3,4,5,6,7"
bitfld.word 0x00 6. "SWFSYNC,Software Forced Synchronization Pulse" "0,1"
bitfld.word 0x00 4.--5. "SYNCOSEL,Synchronization Output Select These bits select the source of the EPWMxSYNCO signal" "0,1,2,3"
bitfld.word 0x00 3. "PRDLD,Active Period Register Load From Shadow Register Select" "0,1"
bitfld.word 0x00 2. "PHSEN,Counter Register Load From Phase Register Enable" "0,1"
bitfld.word 0x00 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or.." "0,1,2,3"
line.word 0x02 "EPWM_REGS_TBSTS,Time-Base Status Register"
bitfld.word 0x02 2. "CTRMAX,Time-Base Counter Max Latched Status Bit" "0,1"
bitfld.word 0x02 1. "SYNCI,Input Synchronization Latched Status Bit" "0,1"
rbitfld.word 0x02 0. "CTRDIR,Time-Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL[CTRMODE]" "0,1"
line.word 0x04 "EPWM_REGS_TBPHSHR,Time Base Phase High Resolution Register"
hexmask.word.byte 0x04 8.--15. 1. "TBPHSH,Time-base phase high-resolution bits"
line.word 0x06 "EPWM_REGS_TBPHS,Time Base Phase Register"
line.word 0x08 "EPWM_REGS_TBCNT,Time Base Counter Register"
line.word 0x0A "EPWM_REGS_TBPRD,Time Base Period Register"
group.word 0x0E++0x17
line.word 0x00 "EPWM_REGS_CMPCTL,Counter Compare Control Register"
rbitfld.word 0x00 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
rbitfld.word 0x00 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA:CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self.." "0,1"
bitfld.word 0x00 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode" "0,1"
bitfld.word 0x00 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode" "0,1"
bitfld.word 0x00 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]" "0,1,2,3"
bitfld.word 0x00 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]" "0,1,2,3"
line.word 0x02 "EPWM_REGS_CMPAHR,Counter Compare A High Resolution Register"
hexmask.word.byte 0x02 8.--15. 1. "CMPAHR,Compare A High-Resolution register bits for MEP step control A minimum value of 1h is needed to enable HRPWM capabilities Valid MEP range of operation 1-255h"
line.word 0x04 "EPWM_REGS_CMPA,Counter Compare A Register"
line.word 0x06 "EPWM_REGS_CMPB,Counter Compare B Register"
line.word 0x08 "EPWM_REGS_AQCTLA,Action Qualifier Control Register For Output A"
bitfld.word 0x08 10.--11. "CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x08 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x08 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x08 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x08 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x08 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0x0A "EPWM_REGS_AQCTLB,Action Qualifier Control Register For Output B"
bitfld.word 0x0A 10.--11. "CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x0A 8.--9. "CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x0A 6.--7. "CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.word 0x0A 4.--5. "CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.word 0x0A 2.--3. "PRD,Action when the counter equals the period Note: By definition in count up-down mode when the counter equals period the direction is defined as 0 or counting down" "0,1,2,3"
bitfld.word 0x0A 0.--1. "ZRO,Action when counter equals zero Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up" "0,1,2,3"
line.word 0x0C "EPWM_REGS_AQSFRC,Action Qualifier Software Force Register"
bitfld.word 0x0C 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options" "0,1,2,3"
bitfld.word 0x0C 5. "OTSFB,One-Time Software Forced Event on Output B" "0,1"
bitfld.word 0x0C 3.--4. "ACTSFB,Action when One-Time Software Force B Is invoked" "0,1,2,3"
bitfld.word 0x0C 2. "OTSFA,One-Time Software Forced Event on Output A" "0,1"
bitfld.word 0x0C 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked" "0,1,2,3"
line.word 0x0E "EPWM_REGS_AQCSFRC,Action Qualifier Continuous S/W Force Register"
bitfld.word 0x0E 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow.." "0,1,2,3"
bitfld.word 0x0E 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register" "0,1,2,3"
line.word 0x10 "EPWM_REGS_DBCTL,Dead-Band Generator Control Register"
bitfld.word 0x10 4.--5. "IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch This allows you to select the input source to the falling-edge and rising-edge delay To produce classical dead-band waveforms the default is EPWMxA In is.." "0,1,2,3"
bitfld.word 0x10 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule The following descriptions correspond to.." "0,1,2,3"
bitfld.word 0x10 0.--1. "OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay" "0,1,2,3"
line.word 0x12 "EPWM_REGS_DBRED,Dead-Band Generator Rising Edge Delay Count Register"
hexmask.word 0x12 0.--9. 1. "DEL,Rising Edge Delay Count 10 bit counter"
line.word 0x14 "EPWM_REGS_DBFED,Dead-Band Generator Falling Edge Delay Count Register"
hexmask.word 0x14 0.--9. 1. "DEL,Falling Edge Delay Count 10 bit counter"
line.word 0x16 "EPWM_REGS_TZSEL,Trip Zone Select Register"
hexmask.word.byte 0x16 8.--15. 1. "OSHTN,Trip-zone n [TZn] select One-Shot [OSHT] trip-zone enable/disable When any of the enabled pins go low a one-shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA and.."
hexmask.word.byte 0x16 0.--7. 1. "CBCN,Trip-zone n [TZn] select Cycle-by-Cycle [CBC] trip-zone enable/disable When any of the enabled pins go low a cycle-by-cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register is taken on the EPWMxA.."
group.word 0x28++0x15
line.word 0x00 "EPWM_REGS_TZCTL,Trip Zone Control Register"
bitfld.word 0x00 2.--3. "TZB,When a trip event occurs the following action is taken on output EPWMxB Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
bitfld.word 0x00 0.--1. "TZA,When a trip event occurs the following action is taken on output EPWMxA Which trip-zone pins can cause an event is defined in the TZSEL register" "0,1,2,3"
line.word 0x02 "EPWM_REGS_TZEINT,Trip Zone Enable Interrupt Register"
bitfld.word 0x02 2. "OST,Trip-zone One-Shot Interrupt Enable" "0,1"
bitfld.word 0x02 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable" "0,1"
line.word 0x04 "EPWM_REGS_TZFLG,Trip Zone Flag Register"
bitfld.word 0x04 2. "OST,Latched Status Flag for A One-Shot Trip Event" "0,1"
bitfld.word 0x04 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event" "0,1"
bitfld.word 0x04 0. "INT,Latched Trip Interrupt Status Flag" "0,1"
line.word 0x06 "EPWM_REGS_TZCLR,Trip Zone Clear Register"
bitfld.word 0x06 2. "OST,Clear Flag for One-Shot Trip [OST] Latch" "0,1"
bitfld.word 0x06 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch" "0,1"
bitfld.word 0x06 0. "INT,Global Interrupt Clear Flag" "0,1"
line.word 0x08 "EPWM_REGS_TZFRC,Trip Zone Force Register"
bitfld.word 0x08 2. "OST,Force a One-Shot Trip Event via Software" "0,1"
bitfld.word 0x08 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software" "0,1"
line.word 0x0A "EPWM_REGS_ETSEL,Event Trigger Selection Register"
bitfld.word 0x0A 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation" "0,1"
bitfld.word 0x0A 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options" "0,1,2,3,4,5,6,7"
line.word 0x0C "EPWM_REGS_ETPS,Event Trigger Pre-Scale Register"
rbitfld.word 0x0C 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled ETSEL[INT] = 0 or the.." "0,1,2,3"
bitfld.word 0x0C 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set.." "0,1,2,3"
line.word 0x0E "EPWM_REGS_ETFLG,Event Trigger Flag Register"
bitfld.word 0x0E 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag" "0,1"
line.word 0x10 "EPWM_REGS_ETCLR,Event Trigger Clear Register"
bitfld.word 0x10 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit" "0,1"
line.word 0x12 "EPWM_REGS_ETFRC,Event Trigger Force Register"
bitfld.word 0x12 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless" "0,1"
line.word 0x14 "EPWM_REGS_PCCTL,PWM Chopper Control Register"
bitfld.word 0x14 8.--10. "CHPDUTY,Chopping Clock Duty Cycle" "0,1,2,3,4,5,6,7"
bitfld.word 0x14 5.--7. "CHPFREQ,Chopping Clock Frequency" "0,1,2,3,4,5,6,7"
bitfld.word 0x14 1.--4. "OSHTWTH,One-Shot Pulse Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x14 0. "CHPEN,PWM-chopping Enable" "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "EPWM_REGS_PID,EHRPWM Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between the old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,FUNC"
bitfld.long 0x00 11.--15. "R_RTL,RTL version [R] maintained by IP design owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major revision [X]" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,CUSTOM" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor revision [Y]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "EQEP0_REG"
base ad:0x23200000
group.long 0x00++0x23
line.long 0x00 "REG_QPOSCNT,Position Counter"
line.long 0x04 "REG_QPOSINIT,Position Counter Init"
line.long 0x08 "REG_QPOSMAX,Maximum Position Count"
line.long 0x0C "REG_QPOSCMP,Position Compare"
line.long 0x10 "REG_QPOSILAT,Index Position Latch"
line.long 0x14 "REG_QPOSSLAT,Strobe Position Latch"
line.long 0x18 "REG_QPOSLAT,Position Latch"
line.long 0x1C "REG_QUTMR,QEP Unit Timer"
line.long 0x20 "REG_QUPRD,QEP Unit Period"
group.word 0x24++0x1D
line.word 0x00 "REG_QWDTMR,QEP Watchdog Timer"
line.word 0x02 "REG_QWDPRD,QEP Watchdog Period"
line.word 0x04 "REG_QDECCTL_TYPE2,Quadrature Decoder Control"
bitfld.word 0x04 14.--15. "QSRC,Position-counter source selection" "0,1,2,3"
bitfld.word 0x04 13. "SOEN,Sync output-enable" "0,1"
bitfld.word 0x04 12. "SPSEL,Sync output pin selection" "0,1"
bitfld.word 0x04 11. "XCR,External Clock Rate" "0,1"
bitfld.word 0x04 10. "SWAP,CLK/DIR Signal Source for Position Counter" "0,1"
bitfld.word 0x04 9. "IGATE,Index pulse gating option" "0,1"
bitfld.word 0x04 8. "QAP,QEPA input polarity" "0,1"
bitfld.word 0x04 7. "QBP,QEPB input polarity" "0,1"
bitfld.word 0x04 6. "QIP,QEPI input polarity" "0,1"
newline
bitfld.word 0x04 5. "QSP,QEPS input polarity" "0,1"
bitfld.word 0x04 0. "QIDIRE," "0,1"
line.word 0x06 "REG_QEPCTL,QEP Control"
bitfld.word 0x06 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
bitfld.word 0x06 12.--13. "PCRM,Postion counter reset" "0,1,2,3"
bitfld.word 0x06 10.--11. "SEI,Strobe event initialization of position counter" "0,1,2,3"
bitfld.word 0x06 8.--9. "IEI,Index event init of position count" "0,1,2,3"
bitfld.word 0x06 7. "SWI,Software init position counter" "0,1"
bitfld.word 0x06 6. "SEL,Strobe event latch of position counter" "0,1"
bitfld.word 0x06 4.--5. "IEL,Index event latch of position counter [software index marker]" "0,1,2,3"
bitfld.word 0x06 3. "QPEN,Quadrature position counter enable/software reset" "0,1"
bitfld.word 0x06 2. "QCLM,QEP capture latch mode" "0,1"
newline
bitfld.word 0x06 1. "UTE,QEP unit timer enable" "0,1"
bitfld.word 0x06 0. "WDE,QEP watchdog enable" "0,1"
line.word 0x08 "REG_QCAPCTL,Qaudrature Capture Control"
bitfld.word 0x08 15. "CEN,Enable eQEP capture" "0,1"
bitfld.word 0x08 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7"
bitfld.word 0x08 0.--3. "UPPS,Unit position event prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x0A "REG_QPOSCTL,Position Compare Control"
bitfld.word 0x0A 15. "PCSHDW,Position compare of shadow enable" "0,1"
bitfld.word 0x0A 14. "PCLOAD,Position compare of shadow load" "0,1"
bitfld.word 0x0A 13. "PCPOL,Polarity of sync output" "0,1"
bitfld.word 0x0A 12. "PCE,Position compare enable/disable" "0,1"
hexmask.word 0x0A 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width"
line.word 0x0C "REG_QEINT_TYPE1,QEP Interrupt Control"
bitfld.word 0x0C 12. "QMAE,QMA Error Interrupt enable" "0,1"
bitfld.word 0x0C 11. "UTO,Unit time out interrupt enable" "0,1"
bitfld.word 0x0C 10. "IEL,Index event latch interrupt enable" "0,1"
bitfld.word 0x0C 9. "SEL,Strobe event latch interrupt enable" "0,1"
bitfld.word 0x0C 8. "PCM,Position-compare match interrupt enable" "0,1"
bitfld.word 0x0C 7. "PCR,Position-compare ready interrupt enable" "0,1"
bitfld.word 0x0C 6. "PCO,Position counter overflow interrupt enable" "0,1"
bitfld.word 0x0C 5. "PCU,Position counter underflow interrupt enable" "0,1"
bitfld.word 0x0C 4. "WTO,Watchdog time out interrupt enable" "0,1"
newline
bitfld.word 0x0C 3. "QDC,Quadrature direction change interrupt enable" "0,1"
bitfld.word 0x0C 2. "QPE,Quadrature phase error interrupt enable" "0,1"
bitfld.word 0x0C 1. "PCE,Position counter error interrupt enable" "0,1"
line.word 0x0E "REG_QFLG_TYPE1,QEP Interrupt Flag"
bitfld.word 0x0E 12. "QMAE,QMA Error interrupt flag" "0,1"
bitfld.word 0x0E 11. "UTO,Unit time out interrupt flag" "0,1"
bitfld.word 0x0E 10. "IEL,Index event latch interrupt flag" "0,1"
bitfld.word 0x0E 9. "SEL,Strobe event latch interrupt flag" "0,1"
bitfld.word 0x0E 8. "PCM,eQEP compare match event interrupt flag" "0,1"
bitfld.word 0x0E 7. "PCR,Position-compare ready interrupt flag" "0,1"
bitfld.word 0x0E 6. "PCO,Position counter overflow interrupt flag" "0,1"
bitfld.word 0x0E 5. "PCU,Position counter underflow interrupt flag" "0,1"
bitfld.word 0x0E 4. "WTO,Watchdog timeout interrupt flag" "0,1"
newline
bitfld.word 0x0E 3. "QDC,Quadrature direction change interrupt flag" "0,1"
bitfld.word 0x0E 2. "PHE,Quadrature phase error interrupt flag" "0,1"
bitfld.word 0x0E 1. "PCE,Position counter error interrupt flag" "0,1"
bitfld.word 0x0E 0. "INT,Global interrupt status flag" "0,1"
line.word 0x10 "REG_QCLR_TYPE1,QEP Interrupt Clear"
bitfld.word 0x10 12. "QMAE,Clear QMA Error interrupt flag" "0,1"
bitfld.word 0x10 11. "UTO,Clear unit time out interrupt flag" "0,1"
bitfld.word 0x10 10. "IEL,Clear index event latch interrupt flag" "0,1"
bitfld.word 0x10 9. "SEL,Clear strobe event latch interrupt flag" "0,1"
bitfld.word 0x10 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1"
bitfld.word 0x10 7. "PCR,Clear position-compare ready interrupt flag" "0,1"
bitfld.word 0x10 6. "PCO,Clear position counter overflow interrupt flag" "0,1"
bitfld.word 0x10 5. "PCU,Clear position counter underflow interrupt flag" "0,1"
bitfld.word 0x10 4. "WTO,Clear watchdog timeout interrupt flag" "0,1"
newline
bitfld.word 0x10 3. "QDC,Clear quadrature direction change interrupt flag" "0,1"
bitfld.word 0x10 2. "PHE,Clear quadrature phase error interrupt flag" "0,1"
bitfld.word 0x10 1. "PCE,Clear position counter error interrupt flag" "0,1"
bitfld.word 0x10 0. "INT,Global interrupt clear flag" "0,1"
line.word 0x12 "REG_QFRC_TYPE1,QEP Interrupt Force"
bitfld.word 0x12 12. "QMAE,Force QMA error interrupt" "0,1"
bitfld.word 0x12 11. "UTO,Force unit time out interrupt" "0,1"
bitfld.word 0x12 10. "IEL,Force index event latch interrupt" "0,1"
bitfld.word 0x12 9. "SEL,Force strobe event latch interrupt" "0,1"
bitfld.word 0x12 8. "PCM,Force position-compare match interrupt" "0,1"
bitfld.word 0x12 7. "PCR,Force position-compare ready interrupt" "0,1"
bitfld.word 0x12 6. "PCO,Force position counter overflow interrupt" "0,1"
bitfld.word 0x12 5. "PCU,Force position counter underflow interrupt" "0,1"
bitfld.word 0x12 4. "WTO,Force watchdog time out interrupt" "0,1"
newline
bitfld.word 0x12 3. "QDC,Force quadrature direction change interrupt" "0,1"
bitfld.word 0x12 2. "PHE,Force quadrature phase error interrupt" "0,1"
bitfld.word 0x12 1. "PCE,Force position counter error interrupt" "0,1"
line.word 0x14 "REG_QEPSTS_TYPE1,QEP Status"
bitfld.word 0x14 7. "UPEVNT,Unit position event flag" "0,1"
rbitfld.word 0x14 6. "FIDF,Direction on the first index markerStatus of the direction is latched on the first index event marker" "0,1"
rbitfld.word 0x14 5. "QDF,Quadrature direction flag" "0,1"
rbitfld.word 0x14 4. "QDLF,eQEP direction latch flag" "0,1"
bitfld.word 0x14 3. "COEF,Capture overflow error flag" "0,1"
bitfld.word 0x14 2. "CDEF,Capture direction error flag" "0,1"
bitfld.word 0x14 1. "FIMF,First index marker flag" "0,1"
rbitfld.word 0x14 0. "PCEF,Position counter error flag" "0,1"
line.word 0x16 "REG_QCTMR,QEP Capture Timer"
line.word 0x18 "REG_QCPRD,QEP Capture Period"
line.word 0x1A "REG_QCTMRLAT,QEP Capture Latch"
line.word 0x1C "REG_QCPRDLAT,QEP Capture Period Latch"
repeat 2. (list 1. 2. )(list 0x00 0x2E )
hgroup.word ($2+0x42)++0x01
hide.word 0x00 "REG_Reserved_$1,"
repeat.end
rgroup.long 0x60++0x0F
line.long 0x00 "REG_REV_TYPE2,QEP Revision Number"
bitfld.long 0x00 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP" "0,1,2,3,4,5,6,7"
line.long 0x04 "REG_QEPSTROBESEL,QEP Strobe select register"
bitfld.long 0x04 0.--1. "STROBESEL,Strobe source select" "0,1,2,3"
line.long 0x08 "REG_QMACTRL,QMA Control register"
bitfld.long 0x08 0.--2. "MODE,Select Mode for QMA mode:000 : QMA Module is bypassed" "0,1,2,3,4,5,6,7"
line.long 0x0C "REG_QEPSRCSEL,QEP Source Select Register"
bitfld.long 0x0C 12.--15. "QEPSSEL,QEP Strobe source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 8.--11. "QEPISEL,QEP Index source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 4.--7. "QEPBSEL,QEPB source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "QEPASEL,QEPA source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EQEP1_REG"
base ad:0x23210000
group.long 0x00++0x23
line.long 0x00 "REG_QPOSCNT,Position Counter"
line.long 0x04 "REG_QPOSINIT,Position Counter Init"
line.long 0x08 "REG_QPOSMAX,Maximum Position Count"
line.long 0x0C "REG_QPOSCMP,Position Compare"
line.long 0x10 "REG_QPOSILAT,Index Position Latch"
line.long 0x14 "REG_QPOSSLAT,Strobe Position Latch"
line.long 0x18 "REG_QPOSLAT,Position Latch"
line.long 0x1C "REG_QUTMR,QEP Unit Timer"
line.long 0x20 "REG_QUPRD,QEP Unit Period"
group.word 0x24++0x1D
line.word 0x00 "REG_QWDTMR,QEP Watchdog Timer"
line.word 0x02 "REG_QWDPRD,QEP Watchdog Period"
line.word 0x04 "REG_QDECCTL_TYPE2,Quadrature Decoder Control"
bitfld.word 0x04 14.--15. "QSRC,Position-counter source selection" "0,1,2,3"
bitfld.word 0x04 13. "SOEN,Sync output-enable" "0,1"
bitfld.word 0x04 12. "SPSEL,Sync output pin selection" "0,1"
bitfld.word 0x04 11. "XCR,External Clock Rate" "0,1"
bitfld.word 0x04 10. "SWAP,CLK/DIR Signal Source for Position Counter" "0,1"
bitfld.word 0x04 9. "IGATE,Index pulse gating option" "0,1"
bitfld.word 0x04 8. "QAP,QEPA input polarity" "0,1"
bitfld.word 0x04 7. "QBP,QEPB input polarity" "0,1"
bitfld.word 0x04 6. "QIP,QEPI input polarity" "0,1"
newline
bitfld.word 0x04 5. "QSP,QEPS input polarity" "0,1"
bitfld.word 0x04 0. "QIDIRE," "0,1"
line.word 0x06 "REG_QEPCTL,QEP Control"
bitfld.word 0x06 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
bitfld.word 0x06 12.--13. "PCRM,Postion counter reset" "0,1,2,3"
bitfld.word 0x06 10.--11. "SEI,Strobe event initialization of position counter" "0,1,2,3"
bitfld.word 0x06 8.--9. "IEI,Index event init of position count" "0,1,2,3"
bitfld.word 0x06 7. "SWI,Software init position counter" "0,1"
bitfld.word 0x06 6. "SEL,Strobe event latch of position counter" "0,1"
bitfld.word 0x06 4.--5. "IEL,Index event latch of position counter [software index marker]" "0,1,2,3"
bitfld.word 0x06 3. "QPEN,Quadrature position counter enable/software reset" "0,1"
bitfld.word 0x06 2. "QCLM,QEP capture latch mode" "0,1"
newline
bitfld.word 0x06 1. "UTE,QEP unit timer enable" "0,1"
bitfld.word 0x06 0. "WDE,QEP watchdog enable" "0,1"
line.word 0x08 "REG_QCAPCTL,Qaudrature Capture Control"
bitfld.word 0x08 15. "CEN,Enable eQEP capture" "0,1"
bitfld.word 0x08 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7"
bitfld.word 0x08 0.--3. "UPPS,Unit position event prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x0A "REG_QPOSCTL,Position Compare Control"
bitfld.word 0x0A 15. "PCSHDW,Position compare of shadow enable" "0,1"
bitfld.word 0x0A 14. "PCLOAD,Position compare of shadow load" "0,1"
bitfld.word 0x0A 13. "PCPOL,Polarity of sync output" "0,1"
bitfld.word 0x0A 12. "PCE,Position compare enable/disable" "0,1"
hexmask.word 0x0A 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width"
line.word 0x0C "REG_QEINT_TYPE1,QEP Interrupt Control"
bitfld.word 0x0C 12. "QMAE,QMA Error Interrupt enable" "0,1"
bitfld.word 0x0C 11. "UTO,Unit time out interrupt enable" "0,1"
bitfld.word 0x0C 10. "IEL,Index event latch interrupt enable" "0,1"
bitfld.word 0x0C 9. "SEL,Strobe event latch interrupt enable" "0,1"
bitfld.word 0x0C 8. "PCM,Position-compare match interrupt enable" "0,1"
bitfld.word 0x0C 7. "PCR,Position-compare ready interrupt enable" "0,1"
bitfld.word 0x0C 6. "PCO,Position counter overflow interrupt enable" "0,1"
bitfld.word 0x0C 5. "PCU,Position counter underflow interrupt enable" "0,1"
bitfld.word 0x0C 4. "WTO,Watchdog time out interrupt enable" "0,1"
newline
bitfld.word 0x0C 3. "QDC,Quadrature direction change interrupt enable" "0,1"
bitfld.word 0x0C 2. "QPE,Quadrature phase error interrupt enable" "0,1"
bitfld.word 0x0C 1. "PCE,Position counter error interrupt enable" "0,1"
line.word 0x0E "REG_QFLG_TYPE1,QEP Interrupt Flag"
bitfld.word 0x0E 12. "QMAE,QMA Error interrupt flag" "0,1"
bitfld.word 0x0E 11. "UTO,Unit time out interrupt flag" "0,1"
bitfld.word 0x0E 10. "IEL,Index event latch interrupt flag" "0,1"
bitfld.word 0x0E 9. "SEL,Strobe event latch interrupt flag" "0,1"
bitfld.word 0x0E 8. "PCM,eQEP compare match event interrupt flag" "0,1"
bitfld.word 0x0E 7. "PCR,Position-compare ready interrupt flag" "0,1"
bitfld.word 0x0E 6. "PCO,Position counter overflow interrupt flag" "0,1"
bitfld.word 0x0E 5. "PCU,Position counter underflow interrupt flag" "0,1"
bitfld.word 0x0E 4. "WTO,Watchdog timeout interrupt flag" "0,1"
newline
bitfld.word 0x0E 3. "QDC,Quadrature direction change interrupt flag" "0,1"
bitfld.word 0x0E 2. "PHE,Quadrature phase error interrupt flag" "0,1"
bitfld.word 0x0E 1. "PCE,Position counter error interrupt flag" "0,1"
bitfld.word 0x0E 0. "INT,Global interrupt status flag" "0,1"
line.word 0x10 "REG_QCLR_TYPE1,QEP Interrupt Clear"
bitfld.word 0x10 12. "QMAE,Clear QMA Error interrupt flag" "0,1"
bitfld.word 0x10 11. "UTO,Clear unit time out interrupt flag" "0,1"
bitfld.word 0x10 10. "IEL,Clear index event latch interrupt flag" "0,1"
bitfld.word 0x10 9. "SEL,Clear strobe event latch interrupt flag" "0,1"
bitfld.word 0x10 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1"
bitfld.word 0x10 7. "PCR,Clear position-compare ready interrupt flag" "0,1"
bitfld.word 0x10 6. "PCO,Clear position counter overflow interrupt flag" "0,1"
bitfld.word 0x10 5. "PCU,Clear position counter underflow interrupt flag" "0,1"
bitfld.word 0x10 4. "WTO,Clear watchdog timeout interrupt flag" "0,1"
newline
bitfld.word 0x10 3. "QDC,Clear quadrature direction change interrupt flag" "0,1"
bitfld.word 0x10 2. "PHE,Clear quadrature phase error interrupt flag" "0,1"
bitfld.word 0x10 1. "PCE,Clear position counter error interrupt flag" "0,1"
bitfld.word 0x10 0. "INT,Global interrupt clear flag" "0,1"
line.word 0x12 "REG_QFRC_TYPE1,QEP Interrupt Force"
bitfld.word 0x12 12. "QMAE,Force QMA error interrupt" "0,1"
bitfld.word 0x12 11. "UTO,Force unit time out interrupt" "0,1"
bitfld.word 0x12 10. "IEL,Force index event latch interrupt" "0,1"
bitfld.word 0x12 9. "SEL,Force strobe event latch interrupt" "0,1"
bitfld.word 0x12 8. "PCM,Force position-compare match interrupt" "0,1"
bitfld.word 0x12 7. "PCR,Force position-compare ready interrupt" "0,1"
bitfld.word 0x12 6. "PCO,Force position counter overflow interrupt" "0,1"
bitfld.word 0x12 5. "PCU,Force position counter underflow interrupt" "0,1"
bitfld.word 0x12 4. "WTO,Force watchdog time out interrupt" "0,1"
newline
bitfld.word 0x12 3. "QDC,Force quadrature direction change interrupt" "0,1"
bitfld.word 0x12 2. "PHE,Force quadrature phase error interrupt" "0,1"
bitfld.word 0x12 1. "PCE,Force position counter error interrupt" "0,1"
line.word 0x14 "REG_QEPSTS_TYPE1,QEP Status"
bitfld.word 0x14 7. "UPEVNT,Unit position event flag" "0,1"
rbitfld.word 0x14 6. "FIDF,Direction on the first index markerStatus of the direction is latched on the first index event marker" "0,1"
rbitfld.word 0x14 5. "QDF,Quadrature direction flag" "0,1"
rbitfld.word 0x14 4. "QDLF,eQEP direction latch flag" "0,1"
bitfld.word 0x14 3. "COEF,Capture overflow error flag" "0,1"
bitfld.word 0x14 2. "CDEF,Capture direction error flag" "0,1"
bitfld.word 0x14 1. "FIMF,First index marker flag" "0,1"
rbitfld.word 0x14 0. "PCEF,Position counter error flag" "0,1"
line.word 0x16 "REG_QCTMR,QEP Capture Timer"
line.word 0x18 "REG_QCPRD,QEP Capture Period"
line.word 0x1A "REG_QCTMRLAT,QEP Capture Latch"
line.word 0x1C "REG_QCPRDLAT,QEP Capture Period Latch"
repeat 2. (list 1. 2. )(list 0x00 0x2E )
hgroup.word ($2+0x42)++0x01
hide.word 0x00 "REG_Reserved_$1,"
repeat.end
rgroup.long 0x60++0x0F
line.long 0x00 "REG_REV_TYPE2,QEP Revision Number"
bitfld.long 0x00 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP" "0,1,2,3,4,5,6,7"
line.long 0x04 "REG_QEPSTROBESEL,QEP Strobe select register"
bitfld.long 0x04 0.--1. "STROBESEL,Strobe source select" "0,1,2,3"
line.long 0x08 "REG_QMACTRL,QMA Control register"
bitfld.long 0x08 0.--2. "MODE,Select Mode for QMA mode:000 : QMA Module is bypassed" "0,1,2,3,4,5,6,7"
line.long 0x0C "REG_QEPSRCSEL,QEP Source Select Register"
bitfld.long 0x0C 12.--15. "QEPSSEL,QEP Strobe source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 8.--11. "QEPISEL,QEP Index source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 4.--7. "QEPBSEL,QEPB source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "QEPASEL,QEPA source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EQEP2_REG"
base ad:0x23220000
group.long 0x00++0x23
line.long 0x00 "REG_QPOSCNT,Position Counter"
line.long 0x04 "REG_QPOSINIT,Position Counter Init"
line.long 0x08 "REG_QPOSMAX,Maximum Position Count"
line.long 0x0C "REG_QPOSCMP,Position Compare"
line.long 0x10 "REG_QPOSILAT,Index Position Latch"
line.long 0x14 "REG_QPOSSLAT,Strobe Position Latch"
line.long 0x18 "REG_QPOSLAT,Position Latch"
line.long 0x1C "REG_QUTMR,QEP Unit Timer"
line.long 0x20 "REG_QUPRD,QEP Unit Period"
group.word 0x24++0x1D
line.word 0x00 "REG_QWDTMR,QEP Watchdog Timer"
line.word 0x02 "REG_QWDPRD,QEP Watchdog Period"
line.word 0x04 "REG_QDECCTL_TYPE2,Quadrature Decoder Control"
bitfld.word 0x04 14.--15. "QSRC,Position-counter source selection" "0,1,2,3"
bitfld.word 0x04 13. "SOEN,Sync output-enable" "0,1"
bitfld.word 0x04 12. "SPSEL,Sync output pin selection" "0,1"
bitfld.word 0x04 11. "XCR,External Clock Rate" "0,1"
bitfld.word 0x04 10. "SWAP,CLK/DIR Signal Source for Position Counter" "0,1"
bitfld.word 0x04 9. "IGATE,Index pulse gating option" "0,1"
bitfld.word 0x04 8. "QAP,QEPA input polarity" "0,1"
bitfld.word 0x04 7. "QBP,QEPB input polarity" "0,1"
bitfld.word 0x04 6. "QIP,QEPI input polarity" "0,1"
newline
bitfld.word 0x04 5. "QSP,QEPS input polarity" "0,1"
bitfld.word 0x04 0. "QIDIRE," "0,1"
line.word 0x06 "REG_QEPCTL,QEP Control"
bitfld.word 0x06 14.--15. "FREE_SOFT,Emulation mode" "0,1,2,3"
bitfld.word 0x06 12.--13. "PCRM,Postion counter reset" "0,1,2,3"
bitfld.word 0x06 10.--11. "SEI,Strobe event initialization of position counter" "0,1,2,3"
bitfld.word 0x06 8.--9. "IEI,Index event init of position count" "0,1,2,3"
bitfld.word 0x06 7. "SWI,Software init position counter" "0,1"
bitfld.word 0x06 6. "SEL,Strobe event latch of position counter" "0,1"
bitfld.word 0x06 4.--5. "IEL,Index event latch of position counter [software index marker]" "0,1,2,3"
bitfld.word 0x06 3. "QPEN,Quadrature position counter enable/software reset" "0,1"
bitfld.word 0x06 2. "QCLM,QEP capture latch mode" "0,1"
newline
bitfld.word 0x06 1. "UTE,QEP unit timer enable" "0,1"
bitfld.word 0x06 0. "WDE,QEP watchdog enable" "0,1"
line.word 0x08 "REG_QCAPCTL,Qaudrature Capture Control"
bitfld.word 0x08 15. "CEN,Enable eQEP capture" "0,1"
bitfld.word 0x08 4.--6. "CCPS,eQEP capture timer clock prescaler" "0,1,2,3,4,5,6,7"
bitfld.word 0x08 0.--3. "UPPS,Unit position event prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.word 0x0A "REG_QPOSCTL,Position Compare Control"
bitfld.word 0x0A 15. "PCSHDW,Position compare of shadow enable" "0,1"
bitfld.word 0x0A 14. "PCLOAD,Position compare of shadow load" "0,1"
bitfld.word 0x0A 13. "PCPOL,Polarity of sync output" "0,1"
bitfld.word 0x0A 12. "PCE,Position compare enable/disable" "0,1"
hexmask.word 0x0A 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width"
line.word 0x0C "REG_QEINT_TYPE1,QEP Interrupt Control"
bitfld.word 0x0C 12. "QMAE,QMA Error Interrupt enable" "0,1"
bitfld.word 0x0C 11. "UTO,Unit time out interrupt enable" "0,1"
bitfld.word 0x0C 10. "IEL,Index event latch interrupt enable" "0,1"
bitfld.word 0x0C 9. "SEL,Strobe event latch interrupt enable" "0,1"
bitfld.word 0x0C 8. "PCM,Position-compare match interrupt enable" "0,1"
bitfld.word 0x0C 7. "PCR,Position-compare ready interrupt enable" "0,1"
bitfld.word 0x0C 6. "PCO,Position counter overflow interrupt enable" "0,1"
bitfld.word 0x0C 5. "PCU,Position counter underflow interrupt enable" "0,1"
bitfld.word 0x0C 4. "WTO,Watchdog time out interrupt enable" "0,1"
newline
bitfld.word 0x0C 3. "QDC,Quadrature direction change interrupt enable" "0,1"
bitfld.word 0x0C 2. "QPE,Quadrature phase error interrupt enable" "0,1"
bitfld.word 0x0C 1. "PCE,Position counter error interrupt enable" "0,1"
line.word 0x0E "REG_QFLG_TYPE1,QEP Interrupt Flag"
bitfld.word 0x0E 12. "QMAE,QMA Error interrupt flag" "0,1"
bitfld.word 0x0E 11. "UTO,Unit time out interrupt flag" "0,1"
bitfld.word 0x0E 10. "IEL,Index event latch interrupt flag" "0,1"
bitfld.word 0x0E 9. "SEL,Strobe event latch interrupt flag" "0,1"
bitfld.word 0x0E 8. "PCM,eQEP compare match event interrupt flag" "0,1"
bitfld.word 0x0E 7. "PCR,Position-compare ready interrupt flag" "0,1"
bitfld.word 0x0E 6. "PCO,Position counter overflow interrupt flag" "0,1"
bitfld.word 0x0E 5. "PCU,Position counter underflow interrupt flag" "0,1"
bitfld.word 0x0E 4. "WTO,Watchdog timeout interrupt flag" "0,1"
newline
bitfld.word 0x0E 3. "QDC,Quadrature direction change interrupt flag" "0,1"
bitfld.word 0x0E 2. "PHE,Quadrature phase error interrupt flag" "0,1"
bitfld.word 0x0E 1. "PCE,Position counter error interrupt flag" "0,1"
bitfld.word 0x0E 0. "INT,Global interrupt status flag" "0,1"
line.word 0x10 "REG_QCLR_TYPE1,QEP Interrupt Clear"
bitfld.word 0x10 12. "QMAE,Clear QMA Error interrupt flag" "0,1"
bitfld.word 0x10 11. "UTO,Clear unit time out interrupt flag" "0,1"
bitfld.word 0x10 10. "IEL,Clear index event latch interrupt flag" "0,1"
bitfld.word 0x10 9. "SEL,Clear strobe event latch interrupt flag" "0,1"
bitfld.word 0x10 8. "PCM,Clear eQEP compare match event interrupt flag" "0,1"
bitfld.word 0x10 7. "PCR,Clear position-compare ready interrupt flag" "0,1"
bitfld.word 0x10 6. "PCO,Clear position counter overflow interrupt flag" "0,1"
bitfld.word 0x10 5. "PCU,Clear position counter underflow interrupt flag" "0,1"
bitfld.word 0x10 4. "WTO,Clear watchdog timeout interrupt flag" "0,1"
newline
bitfld.word 0x10 3. "QDC,Clear quadrature direction change interrupt flag" "0,1"
bitfld.word 0x10 2. "PHE,Clear quadrature phase error interrupt flag" "0,1"
bitfld.word 0x10 1. "PCE,Clear position counter error interrupt flag" "0,1"
bitfld.word 0x10 0. "INT,Global interrupt clear flag" "0,1"
line.word 0x12 "REG_QFRC_TYPE1,QEP Interrupt Force"
bitfld.word 0x12 12. "QMAE,Force QMA error interrupt" "0,1"
bitfld.word 0x12 11. "UTO,Force unit time out interrupt" "0,1"
bitfld.word 0x12 10. "IEL,Force index event latch interrupt" "0,1"
bitfld.word 0x12 9. "SEL,Force strobe event latch interrupt" "0,1"
bitfld.word 0x12 8. "PCM,Force position-compare match interrupt" "0,1"
bitfld.word 0x12 7. "PCR,Force position-compare ready interrupt" "0,1"
bitfld.word 0x12 6. "PCO,Force position counter overflow interrupt" "0,1"
bitfld.word 0x12 5. "PCU,Force position counter underflow interrupt" "0,1"
bitfld.word 0x12 4. "WTO,Force watchdog time out interrupt" "0,1"
newline
bitfld.word 0x12 3. "QDC,Force quadrature direction change interrupt" "0,1"
bitfld.word 0x12 2. "PHE,Force quadrature phase error interrupt" "0,1"
bitfld.word 0x12 1. "PCE,Force position counter error interrupt" "0,1"
line.word 0x14 "REG_QEPSTS_TYPE1,QEP Status"
bitfld.word 0x14 7. "UPEVNT,Unit position event flag" "0,1"
rbitfld.word 0x14 6. "FIDF,Direction on the first index markerStatus of the direction is latched on the first index event marker" "0,1"
rbitfld.word 0x14 5. "QDF,Quadrature direction flag" "0,1"
rbitfld.word 0x14 4. "QDLF,eQEP direction latch flag" "0,1"
bitfld.word 0x14 3. "COEF,Capture overflow error flag" "0,1"
bitfld.word 0x14 2. "CDEF,Capture direction error flag" "0,1"
bitfld.word 0x14 1. "FIMF,First index marker flag" "0,1"
rbitfld.word 0x14 0. "PCEF,Position counter error flag" "0,1"
line.word 0x16 "REG_QCTMR,QEP Capture Timer"
line.word 0x18 "REG_QCPRD,QEP Capture Period"
line.word 0x1A "REG_QCTMRLAT,QEP Capture Latch"
line.word 0x1C "REG_QCPRDLAT,QEP Capture Period Latch"
repeat 2. (list 1. 2. )(list 0x00 0x2E )
hgroup.word ($2+0x42)++0x01
hide.word 0x00 "REG_Reserved_$1,"
repeat.end
rgroup.long 0x60++0x0F
line.long 0x00 "REG_REV_TYPE2,QEP Revision Number"
bitfld.long 0x00 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP" "0,1,2,3,4,5,6,7"
line.long 0x04 "REG_QEPSTROBESEL,QEP Strobe select register"
bitfld.long 0x04 0.--1. "STROBESEL,Strobe source select" "0,1,2,3"
line.long 0x08 "REG_QMACTRL,QMA Control register"
bitfld.long 0x08 0.--2. "MODE,Select Mode for QMA mode:000 : QMA Module is bypassed" "0,1,2,3,4,5,6,7"
line.long 0x0C "REG_QEPSRCSEL,QEP Source Select Register"
bitfld.long 0x0C 12.--15. "QEPSSEL,QEP Strobe source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 8.--11. "QEPISEL,QEP Index source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 4.--7. "QEPBSEL,QEPB source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "QEPASEL,QEPA source select:0000: From device Pins [Default].0001-1111: Device dependent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
repeat 2. (list 0. 1. )(list ad:0x600000 ad:0x601000 )
tree "GPIO$1"
base $2
rgroup.long 0x00++0x0B
line.long 0x00 "MEM_pid,GPIO Periperal ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Current scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function code assigned to TCP3"
bitfld.long 0x00 11.--15. "RTL,RTL Version R code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version code" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision Y code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MEM_PCR,Peripheral Control Register"
bitfld.long 0x04 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1"
bitfld.long 0x04 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend" "0,1"
line.long 0x08 "MEM_BINTEN,Bit Interrupt Enable Register"
abitfld.long 0x08 0.--15. "EN,Per bank interrupt enable" "0x0000=disable,0x0001=enable"
group.long 0x10++0x0B
line.long 0x00 "MEM_DIR01,Direction Register"
abitfld.long 0x00 16.--31. "DIR1,Direction of GPIO bank 1 bits " "0x0000=output,0x0001=input"
abitfld.long 0x00 0.--15. "DIR0,Direction of GPIO bank 0 bits " "0x0000=output,0x0001=input"
line.long 0x04 "MEM_OUT_DATA01,Output Drive State Register"
hexmask.long.word 0x04 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x04 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x08 "MEM_SET_DATA01,Set Output Drive State Register"
hexmask.long.word 0x08 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state"
hexmask.long.word 0x08 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state"
repeat 4. (list 01. 23. 45. 67. )(list 0x00 0x28 0x50 0x78 )
group.long ($2+0x1C)++0x03
line.long 0x00 "MEM_CLR_DATA$1,Clear Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
repeat.end
rgroup.long 0x20++0x23
line.long 0x00 "MEM_IN_DATA01,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN1,Status of GPIO bank 1 bits"
hexmask.long.word 0x00 0.--15. 1. "IN0,Status of GPIO bank 0 bits"
line.long 0x04 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits"
line.long 0x0C "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits"
line.long 0x14 "MEM_INTSTAT01,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT1,Status of GPIO bank 0 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT0,Status of GPIO bank 0 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR23,Direction Register"
abitfld.long 0x18 16.--31. "DIR3,Direction of GPIO bank 3 bits " "0x0000=output,0x0001=input"
abitfld.long 0x18 0.--15. "DIR2,Direction of GPIO bank 2 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA23,Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA23,Set Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state"
rgroup.long 0x48++0x23
line.long 0x00 "MEM_IN_DATA23,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN3,Status of GPIO bank 3 bits"
hexmask.long.word 0x00 0.--15. 1. "IN2,Status of GPIO bank 2 bits"
line.long 0x04 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits"
line.long 0x0C "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits"
line.long 0x14 "MEM_INTSTAT23,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT3,Status of GPIO bank 2 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT2,Status of GPIO bank 2 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR45,Direction Register"
abitfld.long 0x18 16.--31. "DIR5,Direction of GPIO bank 5 bits " "0x0000=output,0x0001=input"
abitfld.long 0x18 0.--15. "DIR4,Direction of GPIO bank 4 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA45,Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA45,Set Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state"
rgroup.long 0x70++0x23
line.long 0x00 "MEM_IN_DATA45,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN5,Status of GPIO bank 5 bits"
hexmask.long.word 0x00 0.--15. 1. "IN4,Status of GPIO bank 4 bits"
line.long 0x04 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits"
line.long 0x0C "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits"
line.long 0x14 "MEM_INTSTAT45,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT5,Status of GPIO bank 4 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT4,Status of GPIO bank 4 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR67,Direction Register"
abitfld.long 0x18 16.--31. "DIR7,Direction of GPIO bank 7 bits " "0x0000=output,0x0001=input"
abitfld.long 0x18 0.--15. "DIR6,Direction of GPIO bank 6 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA67,Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA67,Set Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state"
rgroup.long 0x98++0x3F
line.long 0x00 "MEM_IN_DATA67,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN7,Status of GPIO bank 7 bits"
hexmask.long.word 0x00 0.--15. 1. "IN6,Status of GPIO bank 6 bits"
line.long 0x04 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits"
line.long 0x0C "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits"
line.long 0x14 "MEM_INTSTAT67,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT7,Status of GPIO bank 6 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT6,Status of GPIO bank 6 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR8,Direction Register"
abitfld.long 0x18 0.--15. "DIR8,Direction of GPIO bank 8 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA8,Output Drive State Register"
hexmask.long.word 0x1C 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA8,Set Output Drive State Register"
hexmask.long.word 0x20 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state"
line.long 0x24 "MEM_CLR_DATA8,Clear Output Drive State Register"
hexmask.long.word 0x24 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
line.long 0x28 "MEM_IN_DATA8,Bank Status Register"
hexmask.long.word 0x28 0.--15. 1. "IN8,Status of GPIO bank 8 bits"
line.long 0x2C "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register"
hexmask.long.word 0x2C 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits"
line.long 0x30 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register"
hexmask.long.word 0x30 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits"
line.long 0x34 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register"
hexmask.long.word 0x34 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits"
line.long 0x38 "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register"
hexmask.long.word 0x38 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits"
line.long 0x3C "MEM_INTSTAT8,Bank Interrupt Status Register"
abitfld.long 0x3C 0.--15. "STAT8,Status of GPIO bank 8 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
tree.end
repeat.end
tree "I2C0_CFG"
base ad:0x20000000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x04 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x04 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x00 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
newline
bitfld.long 0x00 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Autoidle bit" "0,1"
group.long 0x20++0x2F
line.long 0x00 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
line.long 0x04 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x08 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x08 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x08 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x08 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x08 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x08 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x08 8. "BF,Bus Free IRQ enabled status" "0,1"
newline
bitfld.long 0x08 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x08 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x08 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x08 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x08 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x0C "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector"
bitfld.long 0x0C 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0C 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0C 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0C 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x0C 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0C 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0C 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0C 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x0C 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0C 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0C 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0C 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x0C 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0C 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0C 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector"
bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1"
newline
bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x14 "CFG_I2C_WE,I2C wakeup enable vector (legacy)"
bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x18 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set"
bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set"
bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x20 "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear"
bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear"
bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x28 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable"
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x2C "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable"
bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x07
line.long 0x00 "CFG_I2C_IE,I2C interrupt enable vector (legacy)"
bitfld.long 0x00 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x00 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x00 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x00 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x00 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x00 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x00 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x00 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x00 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x00 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x00 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x00 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x00 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x00 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x00 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x04 "CFG_I2C_STAT,I2C interrupt status vector (legacy)"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
rgroup.long 0x90++0x0F
line.long 0x00 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x00 0. "RDONE,Reset done bit" "0,1"
line.long 0x04 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x04 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x04 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
bitfld.long 0x04 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
newline
bitfld.long 0x04 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
bitfld.long 0x04 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x08 0.--15. 1. "DCOUNT,Data count"
line.long 0x0C "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x0C 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x33
line.long 0x00 "CFG_I2C_CON,I2C configuration register"
bitfld.long 0x00 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x00 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x00 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x00 10. "MST,Master/slave mode" "0,1"
newline
bitfld.long 0x00 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x00 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x00 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x00 6. "XOA1,Expand Own address 1" "0,1"
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bitfld.long 0x00 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x00 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x00 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x00 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x04 "CFG_I2C_OA,Own address register"
bitfld.long 0x04 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "OA,Own address"
line.long 0x08 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x08 0.--9. 1. "SA,Slave address"
line.long 0x0C "CFG_I2C_PSC,I2C Clock Prescaler Register"
abitfld.long 0x0C 0.--7. "PSC,Fast/Standard mode prescale sampling clock divider value" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
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rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
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bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
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bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
line.long 0x1C "CFG_I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x1C 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
bitfld.long 0x1C 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1C 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x20 0.--9. 1. "OA1,Own address 1"
line.long 0x24 "CFG_I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x24 0.--9. 1. "OA2,Own address 2"
line.long 0x28 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x28 0.--9. 1. "OA3,Own address 3"
line.long 0x2C "CFG_I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x2C 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x2C 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x2C 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x2C 0. "OA0_ACT,Own Address 0 active" "0,1"
line.long 0x30 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x30 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x30 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x30 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x30 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree "I2C1_CFG"
base ad:0x20010000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x04 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x04 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x00 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
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bitfld.long 0x00 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Autoidle bit" "0,1"
group.long 0x20++0x2F
line.long 0x00 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
line.long 0x04 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
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bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
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bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x08 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x08 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x08 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x08 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x08 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x08 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x08 8. "BF,Bus Free IRQ enabled status" "0,1"
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bitfld.long 0x08 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x08 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x08 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
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bitfld.long 0x08 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x08 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x0C "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector"
bitfld.long 0x0C 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0C 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0C 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0C 11. "ROVR,Receive overrun enable set" "0,1"
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bitfld.long 0x0C 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0C 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0C 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0C 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x0C 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0C 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0C 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0C 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x0C 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0C 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0C 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector"
bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1"
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bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x14 "CFG_I2C_WE,I2C wakeup enable vector (legacy)"
bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x18 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set"
bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set"
bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x20 "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear"
bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear"
bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x28 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable"
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x2C "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable"
bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x07
line.long 0x00 "CFG_I2C_IE,I2C interrupt enable vector (legacy)"
bitfld.long 0x00 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x00 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x00 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x00 11. "ROVR,Receive overrun enable set" "0,1"
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bitfld.long 0x00 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x00 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x00 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x00 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x00 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x00 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x00 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x00 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x00 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x00 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x00 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x04 "CFG_I2C_STAT,I2C interrupt status vector (legacy)"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
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bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
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bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
rgroup.long 0x90++0x0F
line.long 0x00 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x00 0. "RDONE,Reset done bit" "0,1"
line.long 0x04 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x04 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x04 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
bitfld.long 0x04 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
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bitfld.long 0x04 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
bitfld.long 0x04 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x08 0.--15. 1. "DCOUNT,Data count"
line.long 0x0C "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x0C 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x33
line.long 0x00 "CFG_I2C_CON,I2C configuration register"
bitfld.long 0x00 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x00 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x00 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x00 10. "MST,Master/slave mode" "0,1"
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bitfld.long 0x00 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x00 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x00 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x00 6. "XOA1,Expand Own address 1" "0,1"
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bitfld.long 0x00 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x00 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x00 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x00 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x04 "CFG_I2C_OA,Own address register"
bitfld.long 0x04 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "OA,Own address"
line.long 0x08 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x08 0.--9. 1. "SA,Slave address"
line.long 0x0C "CFG_I2C_PSC,I2C Clock Prescaler Register"
abitfld.long 0x0C 0.--7. "PSC,Fast/Standard mode prescale sampling clock divider value" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
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rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
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bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
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bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
line.long 0x1C "CFG_I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x1C 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
bitfld.long 0x1C 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1C 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x20 0.--9. 1. "OA1,Own address 1"
line.long 0x24 "CFG_I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x24 0.--9. 1. "OA2,Own address 2"
line.long 0x28 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x28 0.--9. 1. "OA3,Own address 3"
line.long 0x2C "CFG_I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x2C 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x2C 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x2C 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x2C 0. "OA0_ACT,Own Address 0 active" "0,1"
line.long 0x30 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x30 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x30 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x30 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x30 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree "I2C2_CFG"
base ad:0x20020000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x04 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x04 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x00 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
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bitfld.long 0x00 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Autoidle bit" "0,1"
group.long 0x20++0x2F
line.long 0x00 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
line.long 0x04 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
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bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x08 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x08 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x08 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x08 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x08 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x08 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x08 8. "BF,Bus Free IRQ enabled status" "0,1"
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bitfld.long 0x08 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x08 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x08 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x08 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x08 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x0C "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector"
bitfld.long 0x0C 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0C 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0C 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0C 11. "ROVR,Receive overrun enable set" "0,1"
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bitfld.long 0x0C 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0C 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0C 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0C 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x0C 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0C 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0C 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0C 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x0C 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0C 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0C 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector"
bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1"
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bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x14 "CFG_I2C_WE,I2C wakeup enable vector (legacy)"
bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x18 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set"
bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set"
bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x20 "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear"
bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear"
bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x28 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable"
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x2C "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable"
bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x07
line.long 0x00 "CFG_I2C_IE,I2C interrupt enable vector (legacy)"
bitfld.long 0x00 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x00 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x00 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x00 11. "ROVR,Receive overrun enable set" "0,1"
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bitfld.long 0x00 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x00 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x00 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x00 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x00 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x00 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x00 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x00 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x00 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x00 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x00 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x04 "CFG_I2C_STAT,I2C interrupt status vector (legacy)"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
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bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
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bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
rgroup.long 0x90++0x0F
line.long 0x00 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x00 0. "RDONE,Reset done bit" "0,1"
line.long 0x04 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x04 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x04 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
bitfld.long 0x04 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
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bitfld.long 0x04 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
bitfld.long 0x04 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x08 0.--15. 1. "DCOUNT,Data count"
line.long 0x0C "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x0C 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x33
line.long 0x00 "CFG_I2C_CON,I2C configuration register"
bitfld.long 0x00 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x00 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x00 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x00 10. "MST,Master/slave mode" "0,1"
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bitfld.long 0x00 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x00 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x00 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x00 6. "XOA1,Expand Own address 1" "0,1"
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bitfld.long 0x00 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x00 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x00 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x00 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x04 "CFG_I2C_OA,Own address register"
bitfld.long 0x04 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "OA,Own address"
line.long 0x08 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x08 0.--9. 1. "SA,Slave address"
line.long 0x0C "CFG_I2C_PSC,I2C Clock Prescaler Register"
abitfld.long 0x0C 0.--7. "PSC,Fast/Standard mode prescale sampling clock divider value" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
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rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
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bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
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bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
line.long 0x1C "CFG_I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x1C 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
bitfld.long 0x1C 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1C 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x20 0.--9. 1. "OA1,Own address 1"
line.long 0x24 "CFG_I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x24 0.--9. 1. "OA2,Own address 2"
line.long 0x28 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x28 0.--9. 1. "OA3,Own address 3"
line.long 0x2C "CFG_I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x2C 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x2C 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x2C 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x2C 0. "OA0_ACT,Own Address 0 active" "0,1"
line.long 0x30 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x30 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x30 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x30 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x30 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree "I2C3_CFG"
base ad:0x20030000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x04 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x04 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x00 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
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bitfld.long 0x00 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Autoidle bit" "0,1"
group.long 0x20++0x2F
line.long 0x00 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
line.long 0x04 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x08 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x08 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x08 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x08 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x08 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x08 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x08 8. "BF,Bus Free IRQ enabled status" "0,1"
newline
bitfld.long 0x08 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x08 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x08 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x08 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x08 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x0C "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector"
bitfld.long 0x0C 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0C 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0C 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0C 11. "ROVR,Receive overrun enable set" "0,1"
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bitfld.long 0x0C 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0C 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0C 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0C 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
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bitfld.long 0x0C 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0C 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0C 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0C 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x0C 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0C 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0C 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector"
bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1"
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bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
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bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x14 "CFG_I2C_WE,I2C wakeup enable vector (legacy)"
bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x18 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set"
bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set"
bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x20 "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear"
bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear"
bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x28 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable"
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x2C "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable"
bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1"
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bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1"
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bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x07
line.long 0x00 "CFG_I2C_IE,I2C interrupt enable vector (legacy)"
bitfld.long 0x00 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x00 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x00 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x00 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x00 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x00 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x00 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x00 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x00 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x00 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x00 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x00 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x00 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x00 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x00 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x04 "CFG_I2C_STAT,I2C interrupt status vector (legacy)"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
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bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
rgroup.long 0x90++0x0F
line.long 0x00 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x00 0. "RDONE,Reset done bit" "0,1"
line.long 0x04 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x04 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x04 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
bitfld.long 0x04 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
newline
bitfld.long 0x04 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
bitfld.long 0x04 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x08 0.--15. 1. "DCOUNT,Data count"
line.long 0x0C "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x0C 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x33
line.long 0x00 "CFG_I2C_CON,I2C configuration register"
bitfld.long 0x00 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x00 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x00 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x00 10. "MST,Master/slave mode" "0,1"
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bitfld.long 0x00 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x00 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x00 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x00 6. "XOA1,Expand Own address 1" "0,1"
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bitfld.long 0x00 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x00 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x00 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x00 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x04 "CFG_I2C_OA,Own address register"
bitfld.long 0x04 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "OA,Own address"
line.long 0x08 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x08 0.--9. 1. "SA,Slave address"
line.long 0x0C "CFG_I2C_PSC,I2C Clock Prescaler Register"
abitfld.long 0x0C 0.--7. "PSC,Fast/Standard mode prescale sampling clock divider value" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
newline
rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
newline
bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
newline
bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
line.long 0x1C "CFG_I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x1C 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
bitfld.long 0x1C 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1C 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x20 0.--9. 1. "OA1,Own address 1"
line.long 0x24 "CFG_I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x24 0.--9. 1. "OA2,Own address 2"
line.long 0x28 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x28 0.--9. 1. "OA3,Own address 3"
line.long 0x2C "CFG_I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x2C 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x2C 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x2C 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x2C 0. "OA0_ACT,Own Address 0 active" "0,1"
line.long 0x30 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x30 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x30 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x30 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x30 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree "MAILBOX0_CLUSTER_0_REGS0"
base ad:0x29000000
rgroup.long 0x00++0x03
line.long 0x00 "REGS0_MAILBOX_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU identifier" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module family"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR_REV,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Special version number" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR_REV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "REGS0_MAILBOX_SYSCONFIG,This register contains parameters to control the whole Mailbox system"
bitfld.long 0x00 0. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware" "0,1"
group.long 0x40++0x03
line.long 0x00 "REGS0_MAILBOX_MESSAGE,The message register stores the next to-be-read message of the mailbox"
rgroup.long 0x80++0x03
line.long 0x00 "REGS0_MAILBOX_FIFOSTATUS,The FIFO status register has the status of the Mailbox[a] FIFO"
bitfld.long 0x00 0. "FIFO_FULL,Full flag for Mailbox m" "0,1"
rgroup.long 0xC0++0x03
line.long 0x00 "REGS0_MAILBOX_MSGSTATUS,The message status register has the status of the messages in Mailbox[a]"
bitfld.long 0x00 0.--2. "NUM_MESSAGES,Number of messages in Mailbox[a]" "0,1,2,3,4,5,6,7"
group.long 0x140++0x03
line.long 0x00 "REGS0_MAILBOX_IRQ_EOI,This is the EOI register with which the software is enabled to do the interrupt clearance"
bitfld.long 0x00 3. "EOI3,Software EOI signal for the user 3 interrupt" "0,1"
bitfld.long 0x00 2. "EOI2,Software EOI signal for the user 2 interrupt" "0,1"
bitfld.long 0x00 1. "EOI1,Software EOI signal for the user 1 interrupt" "0,1"
bitfld.long 0x00 0. "EOI0,Software EOI signal for the user 0 interrupt" "0,1"
group.long 0x100++0x0F
line.long 0x00 "REGS0_MAILBOX_IRQ_STATUS_RAW,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user .Software may also write 1 to a given bit to set this bit to test interrupt.."
bitfld.long 0x00 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full" "0,1"
bitfld.long 0x00 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15" "0,1"
bitfld.long 0x00 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full" "0,1"
bitfld.long 0x00 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14" "0,1"
bitfld.long 0x00 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full" "0,1"
newline
bitfld.long 0x00 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13" "0,1"
bitfld.long 0x00 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full" "0,1"
bitfld.long 0x00 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12" "0,1"
bitfld.long 0x00 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full" "0,1"
bitfld.long 0x00 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11" "0,1"
newline
bitfld.long 0x00 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full" "0,1"
bitfld.long 0x00 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10" "0,1"
bitfld.long 0x00 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full" "0,1"
bitfld.long 0x00 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9" "0,1"
bitfld.long 0x00 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full" "0,1"
newline
bitfld.long 0x00 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8" "0,1"
bitfld.long 0x00 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full" "0,1"
bitfld.long 0x00 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7" "0,1"
bitfld.long 0x00 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full" "0,1"
bitfld.long 0x00 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6" "0,1"
newline
bitfld.long 0x00 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full" "0,1"
bitfld.long 0x00 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5" "0,1"
bitfld.long 0x00 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full" "0,1"
bitfld.long 0x00 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4" "0,1"
bitfld.long 0x00 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full" "0,1"
newline
bitfld.long 0x00 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3" "0,1"
bitfld.long 0x00 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full" "0,1"
bitfld.long 0x00 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2" "0,1"
bitfld.long 0x00 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full" "0,1"
bitfld.long 0x00 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1" "0,1"
newline
bitfld.long 0x00 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full" "0,1"
bitfld.long 0x00 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0" "0,1"
line.long 0x04 "REGS0_MAILBOX_IRQ_STATUS_CLR,The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information.Software may also write 1 to a.."
bitfld.long 0x04 31. "NOTFULLSTATUSMB15,1 if Mailbox 15 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 30. "NEWMSGSTATUSMB15,1 if there are messages present in Mailbox 15 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 29. "NOTFULLSTATUSMB14,1 if Mailbox 14 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 28. "NEWMSGSTATUSMB14,1 if there are messages present in Mailbox 14 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 27. "NOTFULLSTATUSMB13,1 if Mailbox 13 is not full and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 26. "NEWMSGSTATUSMB13,1 if there are messages present in Mailbox 13 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 25. "NOTFULLSTATUSMB12,1 if Mailbox 12 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 24. "NEWMSGSTATUSMB12,1 if there are messages present in Mailbox 12 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 23. "NOTFULLSTATUSMB11,1 if Mailbox 11 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 22. "NEWMSGSTATUSMB11,1 if there are messages present in Mailbox 11 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 21. "NOTFULLSTATUSMB10,1 if Mailbox 10 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 20. "NEWMSGSTATUSMB10,1 if there are messages present in Mailbox 10 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 19. "NOTFULLSTATUSMB9,1 if Mailbox 9 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 18. "NEWMSGSTATUSMB9,1 if there are messages present in Mailbox 9 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 17. "NOTFULLSTATUSMB8,1 if Mailbox 8 is not full and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 16. "NEWMSGSTATUSMB8,1 if there are messages present in Mailbox 8 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 15. "NOTFULLSTATUSMB7,1 if Mailbox 7 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 14. "NEWMSGSTATUSMB7,1 if there are messages present in Mailbox 7 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 13. "NOTFULLSTATUSMB6,1 if Mailbox 6 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 12. "NEWMSGSTATUSMB6,1 if there are messages present in Mailbox 6 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 11. "NOTFULLSTATUSMB5,1 if Mailbox 5 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 10. "NEWMSGSTATUSMB5,1 if there are messages present in Mailbox 5 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 9. "NOTFULLSTATUSMB4,1 if Mailbox 4 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 8. "NEWMSGSTATUSMB4,1 if there are messages present in Mailbox 4 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 7. "NOTFULLSTATUSMB3,1 if Mailbox 3 is not full and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 6. "NEWMSGSTATUSMB3,1 if there are messages present in Mailbox 3 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 5. "NOTFULLSTATUSMB2,1 if Mailbox 2 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 4. "NEWMSGSTATUSMB2,1 if there are messages present in Mailbox 2 and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 3. "NOTFULLSTATUSMB1,1 if Mailbox 1 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 2. "NEWMSGSTATUSMB1,1 if there are messages present in Mailbox 1 and this interrupt bit is enabled" "0,1"
newline
bitfld.long 0x04 1. "NOTFULLSTATUSMB0,1 if Mailbox 0 is not full and this interrupt bit is enabled" "0,1"
bitfld.long 0x04 0. "NEWMSGSTATUSMB0,1 if there are messages present in Mailbox 0 and this interrupt bit is enabled" "0,1"
line.long 0x08 "REGS0_MAILBOX_IRQ_ENABLE_SET,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a].Read value is the current enable bits for each interrupt source.Write 1 to a bit enables an interrupt source"
bitfld.long 0x08 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x08 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x08 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt" "0,1"
line.long 0x0C "REGS0_MAILBOX_IRQ_ENABLE_CLR,The interrupt enable register allows software to mask/unmask the module internal source of interrupt for the user [a].Read value is the current enable bits for each interrupt sourc.Write 1 to a bit disables an interrupt source"
bitfld.long 0x0C 31. "NOTFULLENABLEMB15,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 30. "NEWMSGENABLEMB15,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 29. "NOTFULLENABLEMB14,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 28. "NEWMSGENABLEMB14,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 27. "NOTFULLENABLEMB13,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 26. "NEWMSGENABLEMB13,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 25. "NOTFULLENABLEMB12,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 24. "NEWMSGENABLEMB12,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 23. "NOTFULLENABLEMB11,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 22. "NEWMSGENABLEMB11,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 21. "NOTFULLENABLEMB10,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 20. "NEWMSGENABLEMB10,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 19. "NOTFULLENABLEMB9,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 18. "NEWMSGENABLEMB9,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 17. "NOTFULLENABLEMB8,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 16. "NEWMSGENABLEMB8,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 15. "NOTFULLENABLEMB7,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 14. "NEWMSGENABLEMB7,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 13. "NOTFULLENABLEMB6,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 12. "NEWMSGENABLEMB6,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 11. "NOTFULLENABLEMB5,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 10. "NEWMSGENABLEMB5,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 9. "NOTFULLENABLEMB4,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 8. "NEWMSGENABLEMB4,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 7. "NOTFULLENABLEMB3,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 6. "NEWMSGENABLEMB3,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 5. "NOTFULLENABLEMB2,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 4. "NEWMSGENABLEMB2,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 3. "NOTFULLENABLEMB1,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 2. "NEWMSGENABLEMB1,Read value is current enable state for this interrupt" "0,1"
newline
bitfld.long 0x0C 1. "NOTFULLENABLEMB0,Read value is current enable state for this interrupt" "0,1"
bitfld.long 0x0C 0. "NEWMSGENABLEMB0,Read value is current enable state for this interrupt" "0,1"
tree.end
tree "MCAN0_CFG"
base ad:0x20701000
rgroup.long 0x00++0x07
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CREL,Release dependent constant (version + date)"
bitfld.long 0x00 28.--31. "REL,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "STEP,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month"
hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ENDN,Constant 0x8765 4321"
hgroup.long 0x08++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CUST,Optional customer-specific register"
group.long 0x0C++0x23
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_DBTP,Configuration of data phase bit timing. transmitter delay compensation enable"
bitfld.long 0x00 23. "TDC,Transmitter Delay Compensation" "0,1"
bitfld.long 0x00 16.--20. "DBRP,Data Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "DTSEG1,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "DSJW,Data resynchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TEST,Test mode selection"
rbitfld.long 0x04 7. "RX,Receive Pin" "0,1"
bitfld.long 0x04 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
bitfld.long 0x04 4. "LBCK,Loop Back Mode" "0,1"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RWD,Monitors the READY output of the Message RAM"
hexmask.long.byte 0x08 8.--15. 1. "WDV,Watchdog Value"
hexmask.long.byte 0x08 0.--7. 1. "WDC,Watchdog Counter Value"
line.long 0x0C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_CCCR,Operation mode configuration"
bitfld.long 0x0C 15. "NISO,Non ISO Operation" "CAN FD frame format according to ISO 11898-1:2015,CAN FD frame format according to Bosch CAN FD.."
bitfld.long 0x0C 14. "TXP,Transmit Pause" "0,1"
bitfld.long 0x0C 13. "EFBI,Edge Filtering during Bus Integration" "0,1"
bitfld.long 0x0C 12. "PXHD,Protocol Exception Handling Disable" "0,1"
newline
bitfld.long 0x0C 9. "BRSE,Bit Rate Switch Enable" "0,1"
bitfld.long 0x0C 8. "FDOE,FD Operation Enable" "0,1"
bitfld.long 0x0C 7. "TEST,Test Mode enable" "0,1"
bitfld.long 0x0C 6. "DAR,Disable Automatic Retransmission" "0,1"
newline
bitfld.long 0x0C 5. "MON,Bus Monitoring Mode" "0,1"
bitfld.long 0x0C 4. "CSR,Clock Stop Request" "0,1"
rbitfld.long 0x0C 3. "CSA,Clock Stop Acknowledge" "0,1"
bitfld.long 0x0C 2. "ASM,Restricted Operation Mode" "0,1"
newline
bitfld.long 0x0C 1. "CCE,Configuration Change Enable" "0,1"
bitfld.long 0x0C 0. "INIT,Initialization" "0,1"
line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NBTP,Configuration of arbitration phase bit timing"
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width"
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCC,Timestamp counter prescaler setting. selection of internal/external timestamp vector"
bitfld.long 0x14 16.--19. "TCP,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3"
line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TSCV,Read/reset timestamp counter"
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter"
line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCC,Configuration of timeout period. selection of timeout counter operation mode"
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period"
bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3"
bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1"
line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TOCV,Read/reset timeout counter"
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter"
repeat 14. (list 00. 11. 22. 33. 44. 55. 66. 77. 88. 99. 1010. 1111. 1212. 1313. )(list 0x00 0x04 0x08 0x0C 0x1C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x5C )
hgroup.long ($2+0x30)++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved$1,Reserved field"
repeat.end
rgroup.long 0x40++0x0B
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ECR,State of Rx/Tx Error Counter. CAN Error Logging"
hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging"
bitfld.long 0x00 15. "RP,Receive Error Passive" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter"
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_PSR,CAN protocol controller status. transmitter delay compensation value"
hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
bitfld.long 0x04 14. "PXE,Protocol Exception Event" "0,1"
bitfld.long 0x04 13. "RFDF,Received a CAN FD Message" "0,1"
bitfld.long 0x04 12. "RBRS,BRS flag of last received CAN FD Message" "0,1"
newline
bitfld.long 0x04 11. "RESI,ESI flag of last received CAN FD Message" "0,1"
bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "BO,Bus_Off status" "0,1"
bitfld.long 0x04 6. "EW,Warning Status" "0,1"
newline
bitfld.long 0x04 5. "EP,Error Passive" "0,1"
bitfld.long 0x04 3.--4. "ACT,Activity" "0,1,2,3"
bitfld.long 0x04 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TDCR,configuration of transmitter delay compensation offset and filter window length"
hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
group.long 0x50++0x0F
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IR,Interrupt flags"
bitfld.long 0x00 29. "ARA,Access to Reserved Address" "0,1"
bitfld.long 0x00 28. "PED,Protocol Error in data Phase" "0,1"
bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "0,1"
newline
bitfld.long 0x00 25. "BO,Bus_Off Status" "0,1"
bitfld.long 0x00 24. "EW,Warning Status" "0,1"
bitfld.long 0x00 23. "EP,Error Passive" "0,1"
bitfld.long 0x00 22. "ELO,Error Logging Overflow" "0,1"
newline
bitfld.long 0x00 21. "BEU,Bit Error Uncorrected" "0,1"
bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
bitfld.long 0x00 18. "TOO,Timeout Occurred" "0,1"
bitfld.long 0x00 17. "MRAF,Message RAM Access Failure" "0,1"
newline
bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "0,1"
bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "0,1"
bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
newline
bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "0,1"
bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "0,1"
bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "0,1"
bitfld.long 0x00 9. "TC,Transmission Complete" "0,1"
newline
bitfld.long 0x00 8. "HPM,High Priority Message" "0,1"
bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "0,1"
bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
newline
bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "0,1"
bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
newline
bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "0,1"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_IE,Interrupt enable/disable"
bitfld.long 0x04 29. "ARAE,Access to Reserve Address Interrupt Enable" "0,1"
bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1"
bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1"
bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "0,1"
newline
bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "0,1"
bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "0,1"
bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
newline
bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
newline
bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1"
bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
bitfld.long 0x04 8. "HPME,High Priority message Interrupt Enable" "0,1"
bitfld.long 0x04 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILS,Interrupt line select (m_can_int0 or m_can_int1)"
bitfld.long 0x08 29. "ARAL,Access to Reserve Address Interrupt Line" "0,1"
bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1"
bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1"
bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "0,1"
newline
bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "0,1"
bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
newline
bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
newline
bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1"
newline
bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x08 8. "HPML,High Priority message Interrupt Line" "0,1"
bitfld.long 0x08 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
line.long 0x0C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ILE,Enable/disable interrupt lines m_can_int0 / m_can_int1"
bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "0,1"
bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "0,1"
group.long 0x80++0x0B
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_GFC,Handling of non-matching frames and remote frames"
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
bitfld.long 0x00 1. "RRFS,reject Remote Frames Standard" "0,1"
bitfld.long 0x00 0. "RRFE,reject Remote Frames Extended" "0,1"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_SIDFC,Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x04 16.--23. 1. "LSS,List Size Standard"
hexmask.long.word 0x04 2.--15. 1. "FLSSA,Filter List Standard Start Address"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDFC,Number of filter elements. pointer to start of filter list"
hexmask.long.byte 0x08 16.--22. 1. "LSE,List Size Extended"
hexmask.long.word 0x08 2.--15. 1. "FLESA,Filter List Extended Start Address"
group.long 0x90++0x07
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_XIDAM,29-bit logical AND mask for J1939"
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_HPMS,Status monitoring of incoming high priority messages"
bitfld.long 0x04 15. "FLST,Filter List" "0,1"
hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index"
bitfld.long 0x04 6.--7. "MSI,Message Storage Indicator" "0,1,2,3"
bitfld.long 0x04 0.--5. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
group.long ($2+0x98)++0x03
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_NDAT$1,NewDat flags of dedicated Rx buffers 0-31"
bitfld.long 0x00 31. "ND31,New Data" "0,1"
bitfld.long 0x00 30. "ND30,New Data" "0,1"
bitfld.long 0x00 29. "ND29,New Data" "0,1"
bitfld.long 0x00 28. "ND28,New Data" "0,1"
newline
bitfld.long 0x00 27. "ND27,New Data" "0,1"
bitfld.long 0x00 26. "ND26,New Data" "0,1"
bitfld.long 0x00 25. "ND25,New Data" "0,1"
bitfld.long 0x00 24. "ND24,New Data" "0,1"
newline
bitfld.long 0x00 23. "ND23,New Data" "0,1"
bitfld.long 0x00 22. "ND22,New Data" "0,1"
bitfld.long 0x00 21. "ND21,New Data" "0,1"
bitfld.long 0x00 20. "ND20,New Data" "0,1"
newline
bitfld.long 0x00 19. "ND19,New Data" "0,1"
bitfld.long 0x00 18. "ND18,New Data" "0,1"
bitfld.long 0x00 17. "ND17,New Data" "0,1"
bitfld.long 0x00 16. "ND16,New Data" "0,1"
newline
bitfld.long 0x00 15. "ND15,New Data" "0,1"
bitfld.long 0x00 14. "ND14,New Data" "0,1"
bitfld.long 0x00 13. "ND13,New Data" "0,1"
bitfld.long 0x00 12. "ND12,New Data" "0,1"
newline
bitfld.long 0x00 11. "ND11,New Data" "0,1"
bitfld.long 0x00 10. "ND10,New Data" "0,1"
bitfld.long 0x00 9. "ND9,New Data" "0,1"
bitfld.long 0x00 8. "ND8,New Data" "0,1"
newline
bitfld.long 0x00 7. "ND7,New Data" "0,1"
bitfld.long 0x00 6. "ND6,New Data" "0,1"
bitfld.long 0x00 5. "ND5,New Data" "0,1"
bitfld.long 0x00 4. "ND4,New Data" "0,1"
newline
bitfld.long 0x00 3. "ND3,New Data" "0,1"
bitfld.long 0x00 2. "ND2,New Data" "0,1"
bitfld.long 0x00 1. "ND1,New Data" "0,1"
bitfld.long 0x00 0. "ND0,New Data" "0,1"
repeat.end
group.long 0xA0++0x47
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0C,FIFO 0 operation mode. watermark. size and start address"
bitfld.long 0x00 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
hexmask.long.byte 0x00 16.--22. 1. "F0S,Rx FIFO 0 Size"
hexmask.long.word 0x00 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0S,FIFO 0 message lost/full indication. put index. get index and fill level"
bitfld.long 0x04 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x04 24. "F0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x04 16.--21. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 8.--13. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x04 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF0A,FIFO 0 acknowledge last index of read buffers. updates get index and fill level"
bitfld.long 0x08 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXBC,Start address of Rx buffer section"
hexmask.long.word 0x0C 2.--15. 1. "RBSA,Rx Buffer Start Address"
line.long 0x10 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1C,FIFO 1 operation mode. watermark. size and start address"
bitfld.long 0x10 31. "F1OM,Rx FIFO 1 Operation Mode" "0,1"
hexmask.long.byte 0x10 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
hexmask.long.byte 0x10 16.--22. 1. "F1S,Rx FIFO 1 Size"
hexmask.long.word 0x10 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
line.long 0x14 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1S,FIFO 1 message lost/full indication. put index. get index and fill level"
bitfld.long 0x14 30.--31. "DMS,Debug Message Status" "0,1,2,3"
bitfld.long 0x14 25. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x14 24. "F1F,Rx FIFO 1 Full" "0,1"
bitfld.long 0x14 16.--21. "F1PI,Rx FIFO 1 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 8.--13. "F1GI,Rx FIFO 1 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x14 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
line.long 0x18 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXF1A,FIFO 1 acknowledge last index of read buffers. updates get index and fill level"
bitfld.long 0x18 0.--5. "F1AI,Rx FIFO 1 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_RXESC,Configure data field size for storage of accepted frames"
bitfld.long 0x1C 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x20 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBC,Configure Tx FIFO/Queue mode. Tx FIFO/Queue size. number of dedicated Tx buffers. Tx buffer start address"
bitfld.long 0x20 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
bitfld.long 0x20 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x20 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 2.--15. 1. "TBSA,Tx Buffers Start Address"
line.long 0x24 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXFQS,Tx FIFO/Queue full indication and put index. Tx FIFO get index and fill level"
bitfld.long 0x24 21. "TFQF,Tx FIFO/Queue Full" "0,1"
bitfld.long 0x24 16.--20. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 8.--12. "TFGI,Tx Queue Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x24 0.--5. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x28 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXESC,Configure data field size for frame transmission"
bitfld.long 0x28 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x2C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBRP,Tx buffers with pending transmission request"
bitfld.long 0x2C 31. "TRP31,Transmission Request Pending" "0,1"
bitfld.long 0x2C 30. "TRP30,Transmission Request Pending" "0,1"
bitfld.long 0x2C 29. "TRP29,Transmission Request Pending" "0,1"
bitfld.long 0x2C 28. "TRP28,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 27. "TRP27,Transmission Request Pending" "0,1"
bitfld.long 0x2C 26. "TRP26,Transmission Request Pending" "0,1"
bitfld.long 0x2C 25. "TRP25,Transmission Request Pending" "0,1"
bitfld.long 0x2C 24. "TRP24,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 23. "TRP23,Transmission Request Pending" "0,1"
bitfld.long 0x2C 22. "TRP22,Transmission Request Pending" "0,1"
bitfld.long 0x2C 21. "TRP21,Transmission Request Pending" "0,1"
bitfld.long 0x2C 20. "TRP20,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 19. "TRP19,Transmission Request Pending" "0,1"
bitfld.long 0x2C 18. "TRP18,Transmission Request Pending" "0,1"
bitfld.long 0x2C 17. "TRP17,Transmission Request Pending" "0,1"
bitfld.long 0x2C 16. "TRP16,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 15. "TRP15,Transmission Request Pending" "0,1"
bitfld.long 0x2C 14. "TRP14,Transmission Request Pending" "0,1"
bitfld.long 0x2C 13. "TRP13,Transmission Request Pending" "0,1"
bitfld.long 0x2C 12. "TRP12,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 11. "TRP11,Transmission Request Pending" "0,1"
bitfld.long 0x2C 10. "TRP10,Transmission Request Pending" "0,1"
bitfld.long 0x2C 9. "TRP9,Transmission Request Pending" "0,1"
bitfld.long 0x2C 8. "TRP8,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 7. "TRP7,Transmission Request Pending" "0,1"
bitfld.long 0x2C 6. "TRP6,Transmission Request Pending" "0,1"
bitfld.long 0x2C 5. "TRP5,Transmission Request Pending" "0,1"
bitfld.long 0x2C 4. "TRP4,Transmission Request Pending" "0,1"
newline
bitfld.long 0x2C 3. "TRP3,Transmission Request Pending" "0,1"
bitfld.long 0x2C 2. "TRP2,Transmission Request Pending" "0,1"
bitfld.long 0x2C 1. "TRP1,Transmission Request Pending" "0,1"
bitfld.long 0x2C 0. "TRP0,Transmission Request Pending" "0,1"
line.long 0x30 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBAR,Add transmission requests"
bitfld.long 0x30 31. "AR31,Add request" "0,1"
bitfld.long 0x30 30. "AR30,Add request" "0,1"
bitfld.long 0x30 29. "AR29,Add request" "0,1"
bitfld.long 0x30 28. "AR28,Add request" "0,1"
newline
bitfld.long 0x30 27. "AR27,Add request" "0,1"
bitfld.long 0x30 26. "AR26,Add request" "0,1"
bitfld.long 0x30 25. "AR25,Add request" "0,1"
bitfld.long 0x30 24. "AR24,Add request" "0,1"
newline
bitfld.long 0x30 23. "AR23,Add request" "0,1"
bitfld.long 0x30 22. "AR22,Add request" "0,1"
bitfld.long 0x30 21. "AR21,Add request" "0,1"
bitfld.long 0x30 20. "AR20,Add request" "0,1"
newline
bitfld.long 0x30 19. "AR19,Add request" "0,1"
bitfld.long 0x30 18. "AR18,Add request" "0,1"
bitfld.long 0x30 17. "AR17,Add request" "0,1"
bitfld.long 0x30 16. "AR16,Add request" "0,1"
newline
bitfld.long 0x30 15. "AR15,Add request" "0,1"
bitfld.long 0x30 14. "AR14,Add request" "0,1"
bitfld.long 0x30 13. "AR13,Add request" "0,1"
bitfld.long 0x30 12. "AR12,Add request" "0,1"
newline
bitfld.long 0x30 11. "AR11,Add request" "0,1"
bitfld.long 0x30 10. "AR10,Add request" "0,1"
bitfld.long 0x30 9. "AR9,Add request" "0,1"
bitfld.long 0x30 8. "AR8,Add request" "0,1"
newline
bitfld.long 0x30 7. "AR7,Add request" "0,1"
bitfld.long 0x30 6. "AR6,Add request" "0,1"
bitfld.long 0x30 5. "AR5,Add request" "0,1"
bitfld.long 0x30 4. "AR4,Add request" "0,1"
newline
bitfld.long 0x30 3. "AR3,Add request" "0,1"
bitfld.long 0x30 2. "AR2,Add request" "0,1"
bitfld.long 0x30 1. "AR1,Add request" "0,1"
bitfld.long 0x30 0. "AR0,Add request" "0,1"
line.long 0x34 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCR,Request cancellation of pending transmissions"
bitfld.long 0x34 31. "CR31,Cancellation Request" "0,1"
bitfld.long 0x34 30. "CR30,Cancellation Request" "0,1"
bitfld.long 0x34 29. "CR29,Cancellation Request" "0,1"
bitfld.long 0x34 28. "CR28,Cancellation Request" "0,1"
newline
bitfld.long 0x34 27. "CR27,Cancellation Request" "0,1"
bitfld.long 0x34 26. "CR26,Cancellation Request" "0,1"
bitfld.long 0x34 25. "CR25,Cancellation Request" "0,1"
bitfld.long 0x34 24. "CR24,Cancellation Request" "0,1"
newline
bitfld.long 0x34 23. "CR23,Cancellation Request" "0,1"
bitfld.long 0x34 22. "CR22,Cancellation Request" "0,1"
bitfld.long 0x34 21. "CR21,Cancellation Request" "0,1"
bitfld.long 0x34 20. "CR20,Cancellation Request" "0,1"
newline
bitfld.long 0x34 19. "CR19,Cancellation Request" "0,1"
bitfld.long 0x34 18. "CR18,Cancellation Request" "0,1"
bitfld.long 0x34 17. "CR17,Cancellation Request" "0,1"
bitfld.long 0x34 16. "CR16,Cancellation Request" "0,1"
newline
bitfld.long 0x34 15. "CR15,Cancellation Request" "0,1"
bitfld.long 0x34 14. "CR14,Cancellation Request" "0,1"
bitfld.long 0x34 13. "CR13,Cancellation Request" "0,1"
bitfld.long 0x34 12. "CR12,Cancellation Request" "0,1"
newline
bitfld.long 0x34 11. "CR11,Cancellation Request" "0,1"
bitfld.long 0x34 10. "CR10,Cancellation Request" "0,1"
bitfld.long 0x34 9. "CR9,Cancellation Request" "0,1"
bitfld.long 0x34 8. "CR8,Cancellation Request" "0,1"
newline
bitfld.long 0x34 7. "CR7,Cancellation Request" "0,1"
bitfld.long 0x34 6. "CR6,Cancellation Request" "0,1"
bitfld.long 0x34 5. "CR5,Cancellation Request" "0,1"
bitfld.long 0x34 4. "CR4,Cancellation Request" "0,1"
newline
bitfld.long 0x34 3. "CR3,Cancellation Request" "0,1"
bitfld.long 0x34 2. "CR2,Cancellation Request" "0,1"
bitfld.long 0x34 1. "CR1,Cancellation Request" "0,1"
bitfld.long 0x34 0. "CR0,Cancellation Request" "0,1"
line.long 0x38 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTO,Signals successful transmissions. set when corresponding TXBRP flag is cleared"
bitfld.long 0x38 31. "TO31,Transmission Occurred" "0,1"
bitfld.long 0x38 30. "TO30,Transmission Occurred" "0,1"
bitfld.long 0x38 29. "TO29,Transmission Occurred" "0,1"
bitfld.long 0x38 28. "TO28,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 27. "TO27,Transmission Occurred" "0,1"
bitfld.long 0x38 26. "TO26,Transmission Occurred" "0,1"
bitfld.long 0x38 25. "TO25,Transmission Occurred" "0,1"
bitfld.long 0x38 24. "TO24,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 23. "TO23,Transmission Occurred" "0,1"
bitfld.long 0x38 22. "TO22,Transmission Occurred" "0,1"
bitfld.long 0x38 21. "TO21,Transmission Occurred" "0,1"
bitfld.long 0x38 20. "TO20,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 19. "TO19,Transmission Occurred" "0,1"
bitfld.long 0x38 18. "TO18,Transmission Occurred" "0,1"
bitfld.long 0x38 17. "TO17,Transmission Occurred" "0,1"
bitfld.long 0x38 16. "TO16,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 15. "TO15,Transmission Occurred" "0,1"
bitfld.long 0x38 14. "TO14,Transmission Occurred" "0,1"
bitfld.long 0x38 13. "TO13,Transmission Occurred" "0,1"
bitfld.long 0x38 12. "TO12,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 11. "TO11,Transmission Occurred" "0,1"
bitfld.long 0x38 10. "TO10,Transmission Occurred" "0,1"
bitfld.long 0x38 9. "TO9,Transmission Occurred" "0,1"
bitfld.long 0x38 8. "TO8,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 7. "TO7,Transmission Occurred" "0,1"
bitfld.long 0x38 6. "TO6,Transmission Occurred" "0,1"
bitfld.long 0x38 5. "TO5,Transmission Occurred" "0,1"
bitfld.long 0x38 4. "TO4,Transmission Occurred" "0,1"
newline
bitfld.long 0x38 3. "TO3,Transmission Occurred" "0,1"
bitfld.long 0x38 2. "TO2,Transmission Occurred" "0,1"
bitfld.long 0x38 1. "TO1,Transmission Occurred" "0,1"
bitfld.long 0x38 0. "TO0,Transmission Occurred" "0,1"
line.long 0x3C "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCF,Signals successful transmit cancellation. set when corresponding TXBRP flag is cleared after cancellation request"
bitfld.long 0x3C 31. "CF31,Cancellation Finished" "0,1"
bitfld.long 0x3C 30. "CF30,Cancellation Finished" "0,1"
bitfld.long 0x3C 29. "CF29,Cancellation Finished" "0,1"
bitfld.long 0x3C 28. "CF28,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 27. "CF27,Cancellation Finished" "0,1"
bitfld.long 0x3C 26. "CF26,Cancellation Finished" "0,1"
bitfld.long 0x3C 25. "CF25,Cancellation Finished" "0,1"
bitfld.long 0x3C 24. "CF24,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 23. "CF23,Cancellation Finished" "0,1"
bitfld.long 0x3C 22. "CF22,Cancellation Finished" "0,1"
bitfld.long 0x3C 21. "CF21,Cancellation Finished" "0,1"
bitfld.long 0x3C 20. "CF20,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 19. "CF19,Cancellation Finished" "0,1"
bitfld.long 0x3C 18. "CF18,Cancellation Finished" "0,1"
bitfld.long 0x3C 17. "CF17,Cancellation Finished" "0,1"
bitfld.long 0x3C 16. "CF16,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 15. "CF15,Cancellation Finished" "0,1"
bitfld.long 0x3C 14. "CF14,Cancellation Finished" "0,1"
bitfld.long 0x3C 13. "CF13,Cancellation Finished" "0,1"
bitfld.long 0x3C 12. "CF12,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 11. "CF11,Cancellation Finished" "0,1"
bitfld.long 0x3C 10. "CF10,Cancellation Finished" "0,1"
bitfld.long 0x3C 9. "CF9,Cancellation Finished" "0,1"
bitfld.long 0x3C 8. "CF8,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 7. "CF7,Cancellation Finished" "0,1"
bitfld.long 0x3C 6. "CF6,Cancellation Finished" "0,1"
bitfld.long 0x3C 5. "CF5,Cancellation Finished" "0,1"
bitfld.long 0x3C 4. "CF4,Cancellation Finished" "0,1"
newline
bitfld.long 0x3C 3. "CF3,Cancellation Finished" "0,1"
bitfld.long 0x3C 2. "CF2,Cancellation Finished" "0,1"
bitfld.long 0x3C 1. "CF1,Cancellation Finished" "0,1"
bitfld.long 0x3C 0. "CF0,Cancellation Finished" "0,1"
line.long 0x40 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBTIE,Enable transmit interrupts for selected Tx buffers"
bitfld.long 0x40 31. "TIE31,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 30. "TIE30,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 29. "TIE29,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 28. "TIE28,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 27. "TIE27,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 26. "TIE26,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 25. "TIE25,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 24. "TIE24,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 23. "TIE23,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 22. "TIE22,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 21. "TIE21,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 20. "TIE20,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 19. "TIE19,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 18. "TIE18,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 17. "TIE17,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 16. "TIE16,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 15. "TIE15,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 14. "TIE14,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 13. "TIE13,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 12. "TIE12,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 11. "TIE11,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 10. "TIE10,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 9. "TIE9,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 8. "TIE8,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 7. "TIE7,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 6. "TIE6,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 5. "TIE5,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 4. "TIE4,Transmission Interrupt Enable" "0,1"
newline
bitfld.long 0x40 3. "TIE3,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 2. "TIE2,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 1. "TIE1,Transmission Interrupt Enable" "0,1"
bitfld.long 0x40 0. "TIE0,Transmission Interrupt Enable" "0,1"
line.long 0x44 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXBCIE,Enable cancellation finished interrupts for selected Tx buffers"
bitfld.long 0x44 31. "CFIE31,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 30. "CFIE30,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 29. "CFIE29,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 28. "CFIE28,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 27. "CFIE27,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 26. "CFIE26,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 25. "CFIE25,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 24. "CFIE24,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 23. "CFIE23,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 22. "CFIE22,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 21. "CFIE21,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 20. "CFIE20,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 19. "CFIE19,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 18. "CFIE18,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 17. "CFIE17,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 16. "CFIE16,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 15. "CFIE15,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 14. "CFIE14,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 13. "CFIE13,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 12. "CFIE12,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 11. "CFIE11,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 10. "CFIE10,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 9. "CFIE9,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 8. "CFIE8,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 7. "CFIE7,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 6. "CFIE6,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 5. "CFIE5,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 4. "CFIE4,Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x44 3. "CFIE3,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 2. "CFIE2,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 1. "CFIE1,Cancellation Finished Interrupt Enable" "0,1"
bitfld.long 0x44 0. "CFIE0,Cancellation Finished Interrupt Enable" "0,1"
repeat 3. (list 1414. 1515. 1616. )(list 0x00 0x04 0x14 )
hgroup.long ($2+0xE8)++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_reserved$1,Reserved Field"
repeat.end
group.long 0xF0++0x0B
line.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFC,Tx event FIFO watermark. size and start address"
bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address"
line.long 0x04 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFS,Tx event FIFO element lost/full indication. put index. get index. and fill level"
bitfld.long 0x04 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x04 24. "EFF,Event FIFO Full" "0,1"
bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 0.--5. "EFFL,Event FIFO Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_TXEFA,Tx event FIFO acknowledge last index of read elements. updates get index and fill level"
bitfld.long 0x08 0.--4. "EFAI,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hgroup.long 0x100++0x03
hide.long 0x00 "MCAN_WRAP__MCAN_CFG_VBP__MCAN_REGS_ReservUpper256,Reserved Field"
tree.end
tree "MCAN0_ECC_AGGR"
base ad:0x24018000
rgroup.long 0x00++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_revision,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
newline
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x0B
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ecc_vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_misc_status,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_reserved_svbus,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3C++0x07
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "MSGMEM_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "MSGMEM_ENABLE_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "MSGMEM_WRAP__ECC_AGGR_VBP__REGS_aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
tree.end
tree "MCAN0_MSGMEM_RAM"
base ad:0x20708000
group.long 0x00++0x03
line.long 0x00 "MSGMEM_WRAP__MSGMEM_VBP__RAM_RAM_REG,The RAM memory words provide memory mapped random access data storage"
hexmask.long.byte 0x00 24.--31. 1. "BYTE3,This is the MS byte"
hexmask.long.byte 0x00 16.--23. 1. "BYTE2,This is the UM byte"
hexmask.long.byte 0x00 8.--15. 1. "BYTE1,This is the LM byte"
hexmask.long.byte 0x00 0.--7. 1. "BYTE0,This is the LS byte"
tree.end
tree "MCAN0_SS"
base ad:0x20700000
rgroup.long 0x00++0x2B
line.long 0x00 "MMR__MMRVBP__MCANSS_REGS_MCANSS_PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MMR__MMRVBP__MCANSS_REGS_MCANSS_CTRL,The Control Register contains general control bits for the MCANSS"
bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1"
bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
bitfld.long 0x04 4. "WAKEUPREQEN,Wakeup Request Enable" "0,1"
bitfld.long 0x04 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1"
line.long 0x08 "MMR__MMRVBP__MCANSS_REGS_MCANSS_STAT,The Status register provide general status bits for the MCANSS"
bitfld.long 0x08 2. "ENABLE_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1"
bitfld.long 0x08 1. "MEM_INIT_DONE," "0,1"
line.long 0x0C "MMR__MMRVBP__MCANSS_REGS_MCANSS_ICS,Write to clear interrupt bits"
bitfld.long 0x0C 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x10 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IRS,Read raw interrupt status"
bitfld.long 0x10 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x14 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IECS,Write to clear interrupt enable bits"
bitfld.long 0x14 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x18 "MMR__MMRVBP__MCANSS_REGS_MCANSS_IE,Read interrupt Enable"
bitfld.long 0x18 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x1C "MMR__MMRVBP__MCANSS_REGS_MCANSS_IES,Read Enabled Interrupts"
bitfld.long 0x1C 0. "EXT_TS_CNTR_OVFL,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x20 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EOI,End of Interrupt Register"
hexmask.long.byte 0x20 0.--7. 1. "EOI,Write with bit position of targeted interrupt"
line.long 0x24 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_PRESCALER,External TImeStamp PreScaler"
hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALER,External Timestamp Prescaler reload value"
line.long 0x28 "MMR__MMRVBP__MCANSS_REGS_MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,External TImeStamp Unserviced Interrupts Counter"
bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "MCSPI0_CFG"
base ad:0x20100000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned"
bitfld.long 0x00 11.--15. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e"
hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored"
bitfld.long 0x04 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1"
group.long 0x10++0x03
line.long 0x00 "CFG_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3"
bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset [Optional]" "0,1"
rgroup.long 0x100++0x03
line.long 0x00 "CFG_REVISION,This register contains the hard coded RTL revision number"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_13,Reads returns 0"
hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21"
group.long 0x110++0x73
line.long 0x00 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface"
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED_14,Reads returns 0"
bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3"
rbitfld.long 0x00 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,WakeUp feature control" "0,1"
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bitfld.long 0x00 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1"
line.long 0x04 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0"
rbitfld.long 0x04 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x08 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1"
bitfld.long 0x08 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x08 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1"
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bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1"
bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1"
bitfld.long 0x08 11. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1"
bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1"
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bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1"
bitfld.long 0x08 7. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1"
bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1"
bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1"
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bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1"
bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1"
bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1"
bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1"
line.long 0x0C "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis"
hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reads return 0"
bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1"
bitfld.long 0x0C 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x0C 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1"
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bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1"
bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1"
bitfld.long 0x0C 11. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1"
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bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 7. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1"
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bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1"
line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis"
hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0"
bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode"
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x14 11. "SSB,Set status bit" "0,1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1"
bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1"
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bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1"
bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the CLKSPI.." "0,1"
bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface"
hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1"
bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1"
bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1"
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bitfld.long 0x18 2. "MS,Master/ Slave" "0,1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1"
bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1"
line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0"
bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x1C 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1"
line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0"
hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0"
hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EN,Channel Enable" "0,1"
line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x2C "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x30 "CFG_CH1CONF,This register is dedicated to the configuration of the channel"
bitfld.long 0x30 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x30 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x30 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x30 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x30 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x30 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x30 18. "IS,Input Select" "0,1"
bitfld.long 0x30 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x30 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x30 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x30 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x30 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x30 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x30 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x30 0. "PHA,SPICLK phase" "0,1"
line.long 0x34 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1"
hexmask.long 0x34 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x34 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x34 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x34 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x34 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x34 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x34 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x34 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x38 "CFG_CH1CTRL,This register is dedicated to enable the channel 1"
hexmask.long.word 0x38 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x38 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x38 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x38 0. "EN,Channel Enable" "0,1"
line.long 0x3C "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x40 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x44 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2"
bitfld.long 0x44 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x44 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x44 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x44 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x44 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x44 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x44 18. "IS,Input Select" "0,1"
bitfld.long 0x44 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x44 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x44 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x44 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x44 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x44 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x44 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x44 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x44 0. "PHA,SPICLK phase" "0,1"
line.long 0x48 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2"
hexmask.long 0x48 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x48 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x48 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x48 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x48 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x48 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x48 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x48 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x4C "CFG_CH2CTRL,This register is dedicated to enable the channel 2"
hexmask.long.word 0x4C 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x4C 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x4C 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x4C 0. "EN,Channel Enable" "0,1"
line.long 0x50 "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x54 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x58 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3"
bitfld.long 0x58 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x58 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x58 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x58 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x58 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x58 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x58 18. "IS,Input Select" "0,1"
bitfld.long 0x58 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x58 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x58 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x58 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x58 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x58 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x58 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x58 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x58 0. "PHA,SPICLK phase" "0,1"
line.long 0x5C "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3"
hexmask.long 0x5C 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x5C 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x5C 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x5C 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x5C 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x5C 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x5C 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x5C 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x60 "CFG_CH3CTRL,This register is dedicated to enable the channel 3"
hexmask.long.word 0x60 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x60 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x60 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x60 0. "EN,Channel Enable" "0,1"
line.long 0x64 "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x68 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x6C "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer"
hexmask.long.word 0x6C 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index"
hexmask.long.byte 0x6C 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.."
hexmask.long.byte 0x6C 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.."
line.long 0x70 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled"
rgroup.long 0x1A0++0x03
line.long 0x00 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled"
tree.end
tree "MCSPI1_CFG"
base ad:0x20110000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned"
bitfld.long 0x00 11.--15. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e"
hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored"
bitfld.long 0x04 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1"
group.long 0x10++0x03
line.long 0x00 "CFG_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3"
bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset [Optional]" "0,1"
rgroup.long 0x100++0x03
line.long 0x00 "CFG_REVISION,This register contains the hard coded RTL revision number"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_13,Reads returns 0"
hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21"
group.long 0x110++0x73
line.long 0x00 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface"
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED_14,Reads returns 0"
bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3"
rbitfld.long 0x00 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,WakeUp feature control" "0,1"
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bitfld.long 0x00 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1"
line.long 0x04 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0"
rbitfld.long 0x04 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x08 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1"
bitfld.long 0x08 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x08 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1"
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bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1"
bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1"
bitfld.long 0x08 11. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1"
bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1"
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bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1"
bitfld.long 0x08 7. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1"
bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1"
bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1"
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bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1"
bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1"
bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1"
bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1"
line.long 0x0C "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis"
hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reads return 0"
bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1"
bitfld.long 0x0C 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x0C 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1"
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bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1"
bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1"
bitfld.long 0x0C 11. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1"
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bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 7. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1"
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bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1"
line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis"
hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0"
bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode"
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x14 11. "SSB,Set status bit" "0,1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1"
bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1"
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bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1"
bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the CLKSPI.." "0,1"
bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface"
hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1"
bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1"
bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1"
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bitfld.long 0x18 2. "MS,Master/ Slave" "0,1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1"
bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1"
line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0"
bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x1C 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1"
line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0"
hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0"
hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EN,Channel Enable" "0,1"
line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x2C "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x30 "CFG_CH1CONF,This register is dedicated to the configuration of the channel"
bitfld.long 0x30 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x30 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x30 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x30 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x30 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x30 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x30 18. "IS,Input Select" "0,1"
bitfld.long 0x30 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x30 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x30 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x30 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x30 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x30 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x30 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x30 0. "PHA,SPICLK phase" "0,1"
line.long 0x34 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1"
hexmask.long 0x34 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x34 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x34 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x34 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x34 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x34 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x34 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x34 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x38 "CFG_CH1CTRL,This register is dedicated to enable the channel 1"
hexmask.long.word 0x38 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x38 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x38 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x38 0. "EN,Channel Enable" "0,1"
line.long 0x3C "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x40 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x44 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2"
bitfld.long 0x44 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x44 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x44 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x44 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x44 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x44 19. "TURBO,Turbo mode" "0,1"
newline
bitfld.long 0x44 18. "IS,Input Select" "0,1"
bitfld.long 0x44 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x44 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x44 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x44 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x44 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x44 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x44 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x44 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x44 0. "PHA,SPICLK phase" "0,1"
line.long 0x48 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2"
hexmask.long 0x48 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x48 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x48 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x48 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x48 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
newline
rbitfld.long 0x48 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x48 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x48 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x4C "CFG_CH2CTRL,This register is dedicated to enable the channel 2"
hexmask.long.word 0x4C 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x4C 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x4C 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x4C 0. "EN,Channel Enable" "0,1"
line.long 0x50 "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x54 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x58 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3"
bitfld.long 0x58 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x58 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
newline
bitfld.long 0x58 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x58 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x58 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x58 19. "TURBO,Turbo mode" "0,1"
newline
bitfld.long 0x58 18. "IS,Input Select" "0,1"
bitfld.long 0x58 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x58 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x58 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x58 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
newline
bitfld.long 0x58 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x58 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x58 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x58 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x58 0. "PHA,SPICLK phase" "0,1"
line.long 0x5C "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3"
hexmask.long 0x5C 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x5C 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x5C 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x5C 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x5C 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
newline
rbitfld.long 0x5C 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x5C 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x5C 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x60 "CFG_CH3CTRL,This register is dedicated to enable the channel 3"
hexmask.long.word 0x60 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x60 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x60 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x60 0. "EN,Channel Enable" "0,1"
line.long 0x64 "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x68 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x6C "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer"
hexmask.long.word 0x6C 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index"
hexmask.long.byte 0x6C 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.."
hexmask.long.byte 0x6C 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.."
line.long 0x70 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled"
rgroup.long 0x1A0++0x03
line.long 0x00 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled"
tree.end
tree "MCSPI2_CFG"
base ad:0x20120000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_HL_REV,IP Revision Identifier (X.Y.R)Used by software to track features. bugs. and compatibility"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned"
bitfld.long 0x00 11.--15. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3"
bitfld.long 0x00 0.--5. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_HL_HWINFO,Information about the IP module's hardware configuration. i.e"
hexmask.long 0x04 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored"
bitfld.long 0x04 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1"
bitfld.long 0x04 1.--5. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1"
group.long 0x10++0x03
line.long 0x00 "CFG_HL_SYSCONFIG,Clock management configuration"
bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3"
bitfld.long 0x00 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset [Optional]" "0,1"
rgroup.long 0x100++0x03
line.long 0x00 "CFG_REVISION,This register contains the hard coded RTL revision number"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED_13,Reads returns 0"
hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21"
group.long 0x110++0x73
line.long 0x00 "CFG_SYSCONFIG,This register allows controlling various parameters of the OCP interface"
hexmask.long.tbyte 0x00 10.--31. 1. "RESERVED_14,Reads returns 0"
bitfld.long 0x00 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3"
rbitfld.long 0x00 5.--7. "RESERVED_15,Reads returns 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "SIDLEMODE,Power management" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,WakeUp feature control" "0,1"
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bitfld.long 0x00 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1"
line.long 0x04 "CFG_SYSSTATUS,This register provides status information about the module excluding the interrupt status information"
hexmask.long 0x04 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0"
rbitfld.long 0x04 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x08 "CFG_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt"
hexmask.long.word 0x08 18.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x08 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1"
bitfld.long 0x08 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x08 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1"
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bitfld.long 0x08 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1"
bitfld.long 0x08 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1"
bitfld.long 0x08 11. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1"
bitfld.long 0x08 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1"
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bitfld.long 0x08 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1"
bitfld.long 0x08 7. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x08 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1"
bitfld.long 0x08 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1"
bitfld.long 0x08 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1"
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bitfld.long 0x08 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1"
bitfld.long 0x08 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1"
bitfld.long 0x08 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1"
bitfld.long 0x08 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1"
line.long 0x0C "CFG_IRQENABLE,This register allows to enable/disable the module internal sources of interrupt. on an event-by-event basis"
hexmask.long.word 0x0C 18.--31. 1. "RESERVED,Reads return 0"
bitfld.long 0x0C 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1"
bitfld.long 0x0C 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
bitfld.long 0x0C 15. "RESERVED,Reads returns 0" "0,1"
bitfld.long 0x0C 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1"
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bitfld.long 0x0C 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1"
bitfld.long 0x0C 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1"
bitfld.long 0x0C 11. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1"
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bitfld.long 0x0C 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1"
bitfld.long 0x0C 7. "RESERVED,Reads return 0" "0,1"
bitfld.long 0x0C 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1"
bitfld.long 0x0C 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1"
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bitfld.long 0x0C 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1"
bitfld.long 0x0C 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1"
line.long 0x10 "CFG_WAKEUPENABLE,The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis"
hexmask.long 0x10 1.--31. 1. "RESERVED_18,Reads returns 0"
bitfld.long 0x10 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1"
line.long 0x14 "CFG_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus. or externally to device IO pads. when the module is configured in system test (SYSTEST) mode"
hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x14 11. "SSB,Set status bit" "0,1"
bitfld.long 0x14 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1"
bitfld.long 0x14 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1"
bitfld.long 0x14 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1"
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bitfld.long 0x14 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1"
bitfld.long 0x14 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the CLKSPI.." "0,1"
bitfld.long 0x14 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1"
bitfld.long 0x14 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
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bitfld.long 0x14 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
bitfld.long 0x14 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1"
line.long 0x18 "CFG_MODULCTRL,This register is dedicated to the configuration of the serial port interface"
hexmask.long.tbyte 0x18 9.--31. 1. "RESERVED,Reads returns 0"
bitfld.long 0x18 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1"
bitfld.long 0x18 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1"
bitfld.long 0x18 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7"
bitfld.long 0x18 3. "SYSTEM_TEST,Enables the system test mode" "0,1"
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bitfld.long 0x18 2. "MS,Master/ Slave" "0,1"
bitfld.long 0x18 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1"
bitfld.long 0x18 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1"
line.long 0x1C "CFG_CH0CONF,This register is dedicated to the configuration of the channel 0"
bitfld.long 0x1C 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x1C 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x1C 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x1C 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x1C 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x1C 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x1C 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3"
bitfld.long 0x1C 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x1C 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x1C 18. "IS,Input Select" "0,1"
bitfld.long 0x1C 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x1C 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x1C 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x1C 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x1C 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x1C 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x1C 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x1C 0. "PHA,SPICLK phase" "0,1"
line.long 0x20 "CFG_CH0STAT,This register provides status information about transmitter and receiver registers of channel 0"
hexmask.long 0x20 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x20 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x20 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x20 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x20 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x20 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x20 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x20 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x24 "CFG_CH0CTRL,This register is dedicated to enable the channel 0"
hexmask.long.word 0x24 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x24 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x24 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EN,Channel Enable" "0,1"
line.long 0x28 "CFG_TX0,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x2C "CFG_RX0,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x30 "CFG_CH1CONF,This register is dedicated to the configuration of the channel"
bitfld.long 0x30 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x30 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x30 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x30 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x30 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x30 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x30 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x30 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x30 18. "IS,Input Select" "0,1"
bitfld.long 0x30 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x30 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x30 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x30 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x30 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x30 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x30 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x30 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x30 0. "PHA,SPICLK phase" "0,1"
line.long 0x34 "CFG_CH1STAT,This register provides status information about transmitter and receiver registers of channel 1"
hexmask.long 0x34 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x34 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x34 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x34 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x34 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x34 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x34 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x34 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x38 "CFG_CH1CTRL,This register is dedicated to enable the channel 1"
hexmask.long.word 0x38 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x38 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x38 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x38 0. "EN,Channel Enable" "0,1"
line.long 0x3C "CFG_TX1,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x40 "CFG_RX1,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x44 "CFG_CH2CONF,This register is dedicated to the configuration of the channel 2"
bitfld.long 0x44 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x44 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x44 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
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bitfld.long 0x44 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x44 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x44 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x44 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x44 19. "TURBO,Turbo mode" "0,1"
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bitfld.long 0x44 18. "IS,Input Select" "0,1"
bitfld.long 0x44 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x44 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x44 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x44 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
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bitfld.long 0x44 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x44 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x44 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x44 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x44 1. "POL,SPICLK polarity" "0,1"
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bitfld.long 0x44 0. "PHA,SPICLK phase" "0,1"
line.long 0x48 "CFG_CH2STAT,This register provides status information about transmitter and receiver registers of channel 2"
hexmask.long 0x48 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x48 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x48 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x48 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x48 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
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rbitfld.long 0x48 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x48 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x48 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x4C "CFG_CH2CTRL,This register is dedicated to enable the channel 2"
hexmask.long.word 0x4C 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x4C 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x4C 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x4C 0. "EN,Channel Enable" "0,1"
line.long 0x50 "CFG_TX2,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x54 "CFG_RX2,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x58 "CFG_CH3CONF,This register is dedicated to the configuration of the channel 3"
bitfld.long 0x58 30.--31. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1"
bitfld.long 0x58 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1"
bitfld.long 0x58 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3"
newline
bitfld.long 0x58 24. "SBPOL,Start bit polarity" "0,1"
bitfld.long 0x58 23. "SBE,Start bit enable for SPI transfer" "0,1"
bitfld.long 0x58 21.--22. "RESERVED,read returns 0" "0,1,2,3"
bitfld.long 0x58 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1"
bitfld.long 0x58 19. "TURBO,Turbo mode" "0,1"
newline
bitfld.long 0x58 18. "IS,Input Select" "0,1"
bitfld.long 0x58 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1"
bitfld.long 0x58 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1"
bitfld.long 0x58 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1"
bitfld.long 0x58 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1"
newline
bitfld.long 0x58 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3"
bitfld.long 0x58 7.--11. "WL,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x58 6. "EPOL,SPIEN polarity" "0,1"
bitfld.long 0x58 2.--5. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x58 1. "POL,SPICLK polarity" "0,1"
newline
bitfld.long 0x58 0. "PHA,SPICLK phase" "0,1"
line.long 0x5C "CFG_CH3STAT,This register provides status information about transmitter and receiver registers of channel 3"
hexmask.long 0x5C 7.--31. 1. "RESERVED,Read returns 0"
rbitfld.long 0x5C 6. "RXFFF,Channel i FIFO Receive Buffer Full Status" "0,1"
rbitfld.long 0x5C 5. "RXFFE,Channel i FIFO Receive Buffer Empty Status" "0,1"
rbitfld.long 0x5C 4. "TXFFF,Channel i FIFO Transmit Buffer Full Status" "0,1"
rbitfld.long 0x5C 3. "TXFFE,Channel i FIFO Transmit Buffer Empty Status" "0,1"
newline
rbitfld.long 0x5C 2. "EOT,Channel i End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1"
rbitfld.long 0x5C 1. "TXS,Channel i Transmitter Register Status" "0,1"
rbitfld.long 0x5C 0. "RXS,Channel i Receiver Register Status" "0,1"
line.long 0x60 "CFG_CH3CTRL,This register is dedicated to enable the channel 3"
hexmask.long.word 0x60 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x60 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio"
hexmask.long.byte 0x60 1.--7. 1. "RESERVED,Read returns 0"
bitfld.long 0x60 0. "EN,Channel Enable" "0,1"
line.long 0x64 "CFG_TX3,This register contains a single SPI word to transmit on the serial link. what ever SPI word length is"
line.long 0x68 "CFG_RX3,This register contains a single SPI word received through the serial link. what ever SPI word length is"
line.long 0x6C "CFG_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer"
hexmask.long.word 0x6C 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index"
hexmask.long.byte 0x6C 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.."
hexmask.long.byte 0x6C 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.."
line.long 0x70 "CFG_DAFTX,This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled"
rgroup.long 0x1A0++0x03
line.long 0x00 "CFG_DAFRX,This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled"
tree.end
tree "MCU_GPIO0"
base ad:0x4201000
rgroup.long 0x00++0x0B
line.long 0x00 "MEM_pid,GPIO Periperal ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Current scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function code assigned to TCP3"
bitfld.long 0x00 11.--15. "RTL,RTL Version R code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version code" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision Y code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MEM_PCR,Peripheral Control Register"
bitfld.long 0x04 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode" "0,1"
bitfld.long 0x04 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend" "0,1"
line.long 0x08 "MEM_BINTEN,Bit Interrupt Enable Register"
abitfld.long 0x08 0.--15. "EN,Per bank interrupt enable" "0x0000=disable,0x0001=enable"
group.long 0x10++0x0B
line.long 0x00 "MEM_DIR01,Direction Register"
abitfld.long 0x00 16.--31. "DIR1,Direction of GPIO bank 1 bits " "0x0000=output,0x0001=input"
abitfld.long 0x00 0.--15. "DIR0,Direction of GPIO bank 0 bits " "0x0000=output,0x0001=input"
line.long 0x04 "MEM_OUT_DATA01,Output Drive State Register"
hexmask.long.word 0x04 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x04 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x08 "MEM_SET_DATA01,Set Output Drive State Register"
hexmask.long.word 0x08 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state"
hexmask.long.word 0x08 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state"
repeat 4. (list 01. 23. 45. 67. )(list 0x00 0x28 0x50 0x78 )
group.long ($2+0x1C)++0x03
line.long 0x00 "MEM_CLR_DATA$1,Clear Output Drive State Register"
hexmask.long.word 0x00 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
hexmask.long.word 0x00 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
repeat.end
rgroup.long 0x20++0x23
line.long 0x00 "MEM_IN_DATA01,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN1,Status of GPIO bank 1 bits"
hexmask.long.word 0x00 0.--15. 1. "IN0,Status of GPIO bank 0 bits"
line.long 0x04 "MEM_SET_RIS_TRIG01,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG01,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits"
line.long 0x0C "MEM_SET_FAL_TRIG01,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG01,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits"
line.long 0x14 "MEM_INTSTAT01,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT1,Status of GPIO bank 0 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT0,Status of GPIO bank 0 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR23,Direction Register"
abitfld.long 0x18 16.--31. "DIR3,Direction of GPIO bank 3 bits " "0x0000=output,0x0001=input"
abitfld.long 0x18 0.--15. "DIR2,Direction of GPIO bank 2 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA23,Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA23,Set Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state"
rgroup.long 0x48++0x23
line.long 0x00 "MEM_IN_DATA23,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN3,Status of GPIO bank 3 bits"
hexmask.long.word 0x00 0.--15. 1. "IN2,Status of GPIO bank 2 bits"
line.long 0x04 "MEM_SET_RIS_TRIG23,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG23,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits"
line.long 0x0C "MEM_SET_FAL_TRIG23,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG23,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits"
line.long 0x14 "MEM_INTSTAT23,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT3,Status of GPIO bank 2 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT2,Status of GPIO bank 2 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR45,Direction Register"
abitfld.long 0x18 16.--31. "DIR5,Direction of GPIO bank 5 bits " "0x0000=output,0x0001=input"
abitfld.long 0x18 0.--15. "DIR4,Direction of GPIO bank 4 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA45,Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA45,Set Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state"
rgroup.long 0x70++0x23
line.long 0x00 "MEM_IN_DATA45,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN5,Status of GPIO bank 5 bits"
hexmask.long.word 0x00 0.--15. 1. "IN4,Status of GPIO bank 4 bits"
line.long 0x04 "MEM_SET_RIS_TRIG45,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG45,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits"
line.long 0x0C "MEM_SET_FAL_TRIG45,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG45,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits"
line.long 0x14 "MEM_INTSTAT45,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT5,Status of GPIO bank 4 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT4,Status of GPIO bank 4 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR67,Direction Register"
abitfld.long 0x18 16.--31. "DIR7,Direction of GPIO bank 7 bits " "0x0000=output,0x0001=input"
abitfld.long 0x18 0.--15. "DIR6,Direction of GPIO bank 6 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA67,Output Drive State Register"
hexmask.long.word 0x1C 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input Reading it returns the output drive state"
hexmask.long.word 0x1C 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA67,Set Output Drive State Register"
hexmask.long.word 0x20 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state"
hexmask.long.word 0x20 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state"
rgroup.long 0x98++0x3F
line.long 0x00 "MEM_IN_DATA67,Bank Status Register"
hexmask.long.word 0x00 16.--31. 1. "IN7,Status of GPIO bank 7 bits"
hexmask.long.word 0x00 0.--15. 1. "IN6,Status of GPIO bank 6 bits"
line.long 0x04 "MEM_SET_RIS_TRIG67,Set Rising Edge Detection Register"
hexmask.long.word 0x04 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x04 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits"
line.long 0x08 "MEM_CLR_RIS_TRIG67,Clear Rising Edge Detection Register"
hexmask.long.word 0x08 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits"
hexmask.long.word 0x08 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits"
line.long 0x0C "MEM_SET_FAL_TRIG67,Set Falling Edge Detection Register"
hexmask.long.word 0x0C 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x0C 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits"
line.long 0x10 "MEM_CLR_FAL_TRIG67,Clear Falling Edge Detection Register"
hexmask.long.word 0x10 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits"
hexmask.long.word 0x10 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits"
line.long 0x14 "MEM_INTSTAT67,Bank Interrupt Status Register"
abitfld.long 0x14 16.--31. "STAT7,Status of GPIO bank 6 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
abitfld.long 0x14 0.--15. "STAT6,Status of GPIO bank 6 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
line.long 0x18 "MEM_DIR8,Direction Register"
abitfld.long 0x18 0.--15. "DIR8,Direction of GPIO bank 8 bits " "0x0000=output,0x0001=input"
line.long 0x1C "MEM_OUT_DATA8,Output Drive State Register"
hexmask.long.word 0x1C 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input Reading it returns the output drive state"
line.long 0x20 "MEM_SET_DATA8,Set Output Drive State Register"
hexmask.long.word 0x20 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state"
line.long 0x24 "MEM_CLR_DATA8,Clear Output Drive State Register"
hexmask.long.word 0x24 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO Reading it returns the output drive state"
line.long 0x28 "MEM_IN_DATA8,Bank Status Register"
hexmask.long.word 0x28 0.--15. 1. "IN8,Status of GPIO bank 8 bits"
line.long 0x2C "MEM_SET_RIS_TRIG8,Set Rising Edge Detection Register"
hexmask.long.word 0x2C 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits"
line.long 0x30 "MEM_CLR_RIS_TRIG8,Clear Rising Edge Detection Register"
hexmask.long.word 0x30 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits"
line.long 0x34 "MEM_SET_FAL_TRIG8,Set Falling Edge Detection Register"
hexmask.long.word 0x34 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits"
line.long 0x38 "MEM_CLR_FAL_TRIG8,Clear Falling Edge Detection Register"
hexmask.long.word 0x38 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits"
line.long 0x3C "MEM_INTSTAT8,Bank Interrupt Status Register"
abitfld.long 0x3C 0.--15. "STAT8,Status of GPIO bank 8 bits interrupt Reading back" "0x0000=interrupt hasnt occurred since last..,0x0001=interrupt occurred"
tree.end
tree "MCU_TIMER0_CFG"
base ad:0x4800000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "MCU_TIMER1_CFG"
base ad:0x4810000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "MCU_TIMER2_CFG"
base ad:0x4820000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "MCU_TIMER3_CFG"
base ad:0x4830000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "SPINLOCK0"
base ad:0x2A000000
rgroup.long 0x00++0x03
line.long 0x00 "REGS_SPLOCK_ID,This is the standard TI peripheral ID register that exists at address 0 in the peripheral space"
bitfld.long 0x00 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,BU identifier" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNCTION,Module family"
bitfld.long 0x00 11.--15. "RTL_VER,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_REV,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Special version number" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR_REV,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x07
line.long 0x00 "REGS_SPLOCK_SYSCONFIG,Provides the SOFTRESET register for backwards compatibility with OMAP Spinlock"
bitfld.long 0x00 1. "SOFT_RESET,Module Software Reset The bit is automatically reset by the hardware" "0,1"
line.long 0x04 "REGS_SPLOCK_SYSTATUS,Provides information about the Spinlock module"
hexmask.long.byte 0x04 24.--31. 1. "NUM_LOCKS,Module configuration parameter n the total number of spinlocks divided by 32"
bitfld.long 0x04 7. "IN_USE7,In-Use flag 7 covering lock registers" "All lock registers 224 - 255 are in the Not..,At least one of the lock registers 224 - 255 are.."
newline
bitfld.long 0x04 6. "IN_USE6,In-Use flag 6 covering lock registers" "All lock registers 192 - 223 are in the Not..,At least one of the lock registers 192 - 223 are.."
bitfld.long 0x04 5. "IN_USE5,In-Use flag 5 covering lock registers" "All lock registers 160 - 191 are in the Not..,At least one of the lock registers 160 - 191 are.."
newline
bitfld.long 0x04 4. "IN_USE4,In-Use flag 4 covering lock registers" "All lock registers 128 - 159 are in the Not..,At least one of the lock registers 128 - 159 are.."
bitfld.long 0x04 3. "IN_USE3,In-Use flag 3 covering lock registers" "All lock registers 96 - 127 are in the Not Taken..,At least one of the lock registers 96 - 127 are.."
newline
bitfld.long 0x04 2. "IN_USE2,In-Use flag 2 covering lock registers" "All lock registers 64 - 95 are in the Not Taken..,At least one of the lock registers 64 - 95 are.."
bitfld.long 0x04 1. "IN_USE1,In-Use flag 1 covering lock registers" "All lock registers 32 - 63 are in the Not Taken..,At least one of the lock registers 32 - 63 are.."
newline
bitfld.long 0x04 0. "IN_USE0,In-Use flag 0 covering lock registers" "All lock registers 0 - 31 are in the Not Taken..,At least one of the lock registers 0 - 31 are in.."
group.long 0x800++0x03
line.long 0x00 "REGS_LOCK,The Lock[a] register is read and written to perform lock and unlock operations on lock 'a'"
bitfld.long 0x00 0. "TAKEN,Lock Status" "Free the lock by setting..,No effect"
tree.end
tree "PADCFG_CTRL0_CFG0"
base ad:0xF0000
rgroup.long 0x00++0x0B
line.long 0x00 "CFG0_PID,"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16,"
newline
bitfld.long 0x00 11.--15. "PID_MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "PID_CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG0_MMR_CFG0,"
hexmask.long.word 0x04 16.--31. 1. "MMR_CFG0_CFG_REV,Major configuration release"
newline
hexmask.long.word 0x04 0.--15. 1. "MMR_CFG0_SPEC_REV,Minor spec-only revision"
line.long 0x08 "CFG0_MMR_CFG1,"
bitfld.long 0x08 31. "MMR_CFG1_PROXY_EN,Proxy addressing enabled" "0,1"
newline
hexmask.long.byte 0x08 0.--7. 1. "MMR_CFG1_PARTITIONS,Indicates present partitions"
group.long 0x1008++0x2B
line.long 0x00 "CFG0_LOCK0_KICK0,"
line.long 0x04 "CFG0_LOCK0_KICK1,"
line.long 0x08 "CFG0_intr_raw_status,"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
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bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
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bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "CFG0_intr_enabled_status_clear,"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "CFG0_intr_enable,"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "CFG0_intr_enable_clear,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "CFG0_eoi,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value"
line.long 0x1C "CFG0_fault_address,"
line.long 0x20 "CFG0_fault_type_status,"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "CFG0_fault_attr_status,"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "CFG0_fault_clear,"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
rgroup.long 0x1100++0x03
line.long 0x00 "CFG0_CLAIMREG_P0_R0_READONLY,"
rgroup.long 0x2000++0x0B
line.long 0x00 "CFG0_PID_PROXY,"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16_PROXY,"
newline
bitfld.long 0x00 11.--15. "PID_MISC_PROXY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR_PROXY," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "PID_CUSTOM_PROXY," "0,1,2,3"
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bitfld.long 0x00 0.--5. "PID_MINOR_PROXY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG0_MMR_CFG0_PROXY,"
hexmask.long.word 0x04 16.--31. 1. "MMR_CFG0_CFG_REV_PROXY,Major configuration release"
newline
hexmask.long.word 0x04 0.--15. 1. "MMR_CFG0_SPEC_REV_PROXY,Minor spec-only revision"
line.long 0x08 "CFG0_MMR_CFG1_PROXY,"
bitfld.long 0x08 31. "MMR_CFG1_PROXY_EN_PROXY,Proxy addressing enabled" "0,1"
newline
hexmask.long.byte 0x08 0.--7. 1. "MMR_CFG1_PARTITIONS_PROXY,Indicates present partitions"
group.long 0x3008++0x2B
line.long 0x00 "CFG0_LOCK0_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK0_KICK1_PROXY,"
line.long 0x08 "CFG0_intr_raw_status_PROXY,"
bitfld.long 0x08 3. "PROXY_ERR_PROXY,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR_PROXY,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR_PROXY,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR_PROXY,Protection violation error" "0,1"
line.long 0x0C "CFG0_intr_enabled_status_clear_PROXY,"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR_PROXY,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR_PROXY,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR_PROXY,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR_PROXY,Protection violation error" "0,1"
line.long 0x10 "CFG0_intr_enable_PROXY,"
bitfld.long 0x10 3. "PROXY_ERR_EN_PROXY,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN_PROXY,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN_PROXY,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN_PROXY,Protection violation error enable" "0,1"
line.long 0x14 "CFG0_intr_enable_clear_PROXY,"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR_PROXY,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR_PROXY,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR_PROXY,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR_PROXY,Protection violation error enable clear" "0,1"
line.long 0x18 "CFG0_eoi_PROXY,"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR_PROXY,EOI vector value"
line.long 0x1C "CFG0_fault_address_PROXY,"
line.long 0x20 "CFG0_fault_type_status_PROXY,"
bitfld.long 0x20 6. "FAULT_NS_PROXY,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE_PROXY,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "CFG0_fault_attr_status_PROXY,"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID_PROXY,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID_PROXY,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID_PROXY,Privilege ID"
line.long 0x28 "CFG0_fault_clear_PROXY,"
bitfld.long 0x28 0. "FAULT_CLR_PROXY,Fault clear" "0,1"
group.long 0x3100++0x03
line.long 0x00 "CFG0_CLAIMREG_P0_R0,"
group.long 0x4000++0x2AB
line.long 0x00 "CFG0_PADCONFIG0,"
bitfld.long 0x00 31. "PADCONFIG0_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x00 30. "PADCONFIG0_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x00 29. "PADCONFIG0_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x00 28. "PADCONFIG0_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x00 27. "PADCONFIG0_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x00 26. "PADCONFIG0_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x00 25. "PADCONFIG0_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x00 24. "PADCONFIG0_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x00 23. "PADCONFIG0_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x00 22. "PADCONFIG0_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x00 21. "PADCONFIG0_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x00 19.--20. "PADCONFIG0_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "PADCONFIG0_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x00 17. "PADCONFIG0_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x00 16. "PADCONFIG0_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x00 15. "PADCONFIG0_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x00 14. "PADCONFIG0_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x00 11.--13. "PADCONFIG0_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8. "PADCONFIG0_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x00 7. "PADCONFIG0_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--3. "PADCONFIG0_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x04 "CFG0_PADCONFIG1,"
bitfld.long 0x04 31. "PADCONFIG1_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x04 30. "PADCONFIG1_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x04 29. "PADCONFIG1_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x04 28. "PADCONFIG1_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x04 27. "PADCONFIG1_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x04 26. "PADCONFIG1_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x04 25. "PADCONFIG1_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x04 24. "PADCONFIG1_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x04 23. "PADCONFIG1_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x04 22. "PADCONFIG1_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x04 21. "PADCONFIG1_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x04 19.--20. "PADCONFIG1_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x04 18. "PADCONFIG1_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x04 17. "PADCONFIG1_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x04 16. "PADCONFIG1_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x04 15. "PADCONFIG1_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x04 14. "PADCONFIG1_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x04 11.--13. "PADCONFIG1_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 8. "PADCONFIG1_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x04 7. "PADCONFIG1_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x04 0.--3. "PADCONFIG1_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x08 "CFG0_PADCONFIG2,"
bitfld.long 0x08 31. "PADCONFIG2_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x08 30. "PADCONFIG2_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x08 29. "PADCONFIG2_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x08 28. "PADCONFIG2_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x08 27. "PADCONFIG2_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x08 26. "PADCONFIG2_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x08 25. "PADCONFIG2_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x08 24. "PADCONFIG2_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x08 23. "PADCONFIG2_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x08 22. "PADCONFIG2_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x08 21. "PADCONFIG2_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x08 19.--20. "PADCONFIG2_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x08 18. "PADCONFIG2_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x08 17. "PADCONFIG2_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x08 16. "PADCONFIG2_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x08 15. "PADCONFIG2_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x08 14. "PADCONFIG2_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x08 11.--13. "PADCONFIG2_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 8. "PADCONFIG2_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x08 7. "PADCONFIG2_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x08 0.--3. "PADCONFIG2_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x0C "CFG0_PADCONFIG3,"
bitfld.long 0x0C 31. "PADCONFIG3_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x0C 30. "PADCONFIG3_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x0C 29. "PADCONFIG3_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x0C 28. "PADCONFIG3_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x0C 27. "PADCONFIG3_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x0C 26. "PADCONFIG3_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x0C 25. "PADCONFIG3_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x0C 24. "PADCONFIG3_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x0C 23. "PADCONFIG3_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x0C 22. "PADCONFIG3_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x0C 21. "PADCONFIG3_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x0C 19.--20. "PADCONFIG3_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x0C 18. "PADCONFIG3_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x0C 17. "PADCONFIG3_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x0C 16. "PADCONFIG3_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x0C 15. "PADCONFIG3_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x0C 14. "PADCONFIG3_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x0C 11.--13. "PADCONFIG3_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 8. "PADCONFIG3_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x0C 7. "PADCONFIG3_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x0C 0.--3. "PADCONFIG3_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x10 "CFG0_PADCONFIG4,"
bitfld.long 0x10 31. "PADCONFIG4_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x10 30. "PADCONFIG4_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x10 29. "PADCONFIG4_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x10 28. "PADCONFIG4_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x10 27. "PADCONFIG4_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x10 26. "PADCONFIG4_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x10 25. "PADCONFIG4_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x10 24. "PADCONFIG4_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x10 23. "PADCONFIG4_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x10 22. "PADCONFIG4_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x10 21. "PADCONFIG4_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x10 15. "PADCONFIG4_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x10 14. "PADCONFIG4_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 8. "PADCONFIG4_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x10 7. "PADCONFIG4_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x10 0.--3. "PADCONFIG4_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x14 "CFG0_PADCONFIG5,"
bitfld.long 0x14 31. "PADCONFIG5_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x14 30. "PADCONFIG5_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x14 29. "PADCONFIG5_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x14 28. "PADCONFIG5_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x14 27. "PADCONFIG5_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x14 26. "PADCONFIG5_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x14 25. "PADCONFIG5_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x14 24. "PADCONFIG5_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x14 23. "PADCONFIG5_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x14 22. "PADCONFIG5_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x14 21. "PADCONFIG5_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x14 15. "PADCONFIG5_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x14 14. "PADCONFIG5_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 8. "PADCONFIG5_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x14 7. "PADCONFIG5_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x14 0.--3. "PADCONFIG5_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x18 "CFG0_PADCONFIG6,"
bitfld.long 0x18 31. "PADCONFIG6_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x18 30. "PADCONFIG6_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x18 29. "PADCONFIG6_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x18 28. "PADCONFIG6_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x18 27. "PADCONFIG6_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x18 26. "PADCONFIG6_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x18 25. "PADCONFIG6_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x18 24. "PADCONFIG6_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x18 23. "PADCONFIG6_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x18 22. "PADCONFIG6_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x18 21. "PADCONFIG6_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x18 15. "PADCONFIG6_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x18 14. "PADCONFIG6_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 8. "PADCONFIG6_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x18 7. "PADCONFIG6_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x18 0.--3. "PADCONFIG6_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C "CFG0_PADCONFIG7,"
bitfld.long 0x1C 31. "PADCONFIG7_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C 30. "PADCONFIG7_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C 29. "PADCONFIG7_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1C 28. "PADCONFIG7_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1C 27. "PADCONFIG7_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C 26. "PADCONFIG7_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1C 25. "PADCONFIG7_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C 24. "PADCONFIG7_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1C 23. "PADCONFIG7_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1C 22. "PADCONFIG7_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C 15. "PADCONFIG7_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x1C 14. "PADCONFIG7_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C 8. "PADCONFIG7_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1C 7. "PADCONFIG7_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1C 0.--3. "PADCONFIG7_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x20 "CFG0_PADCONFIG8,"
bitfld.long 0x20 31. "PADCONFIG8_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x20 30. "PADCONFIG8_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x20 29. "PADCONFIG8_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x20 28. "PADCONFIG8_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x20 27. "PADCONFIG8_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x20 26. "PADCONFIG8_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x20 25. "PADCONFIG8_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x20 24. "PADCONFIG8_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x20 23. "PADCONFIG8_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x20 22. "PADCONFIG8_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x20 21. "PADCONFIG8_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x20 15. "PADCONFIG8_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x20 14. "PADCONFIG8_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 8. "PADCONFIG8_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x20 7. "PADCONFIG8_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x20 0.--3. "PADCONFIG8_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x24 "CFG0_PADCONFIG9,"
bitfld.long 0x24 31. "PADCONFIG9_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x24 30. "PADCONFIG9_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x24 29. "PADCONFIG9_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x24 28. "PADCONFIG9_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x24 27. "PADCONFIG9_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x24 26. "PADCONFIG9_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x24 25. "PADCONFIG9_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x24 24. "PADCONFIG9_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x24 23. "PADCONFIG9_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x24 22. "PADCONFIG9_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x24 21. "PADCONFIG9_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x24 15. "PADCONFIG9_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x24 14. "PADCONFIG9_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 8. "PADCONFIG9_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x24 7. "PADCONFIG9_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x24 0.--3. "PADCONFIG9_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x28 "CFG0_PADCONFIG10,"
bitfld.long 0x28 31. "PADCONFIG10_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x28 30. "PADCONFIG10_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x28 29. "PADCONFIG10_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x28 28. "PADCONFIG10_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x28 27. "PADCONFIG10_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x28 26. "PADCONFIG10_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x28 25. "PADCONFIG10_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x28 24. "PADCONFIG10_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x28 23. "PADCONFIG10_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x28 22. "PADCONFIG10_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x28 21. "PADCONFIG10_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x28 15. "PADCONFIG10_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x28 14. "PADCONFIG10_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 8. "PADCONFIG10_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x28 7. "PADCONFIG10_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x28 0.--3. "PADCONFIG10_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2C "CFG0_PADCONFIG11,"
bitfld.long 0x2C 31. "PADCONFIG11_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x2C 30. "PADCONFIG11_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x2C 29. "PADCONFIG11_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x2C 28. "PADCONFIG11_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x2C 27. "PADCONFIG11_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x2C 26. "PADCONFIG11_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2C 25. "PADCONFIG11_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x2C 24. "PADCONFIG11_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x2C 23. "PADCONFIG11_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x2C 22. "PADCONFIG11_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x2C 15. "PADCONFIG11_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x2C 14. "PADCONFIG11_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x2C 8. "PADCONFIG11_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x2C 7. "PADCONFIG11_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x2C 0.--3. "PADCONFIG11_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x30 "CFG0_PADCONFIG12,"
bitfld.long 0x30 31. "PADCONFIG12_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x30 30. "PADCONFIG12_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x30 29. "PADCONFIG12_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x30 28. "PADCONFIG12_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x30 27. "PADCONFIG12_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x30 26. "PADCONFIG12_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x30 25. "PADCONFIG12_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x30 24. "PADCONFIG12_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x30 23. "PADCONFIG12_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x30 22. "PADCONFIG12_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x30 21. "PADCONFIG12_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x30 15. "PADCONFIG12_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x30 14. "PADCONFIG12_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x30 8. "PADCONFIG12_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x30 7. "PADCONFIG12_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x30 0.--3. "PADCONFIG12_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x34 "CFG0_PADCONFIG13,"
bitfld.long 0x34 31. "PADCONFIG13_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x34 30. "PADCONFIG13_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x34 29. "PADCONFIG13_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x34 28. "PADCONFIG13_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x34 27. "PADCONFIG13_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x34 26. "PADCONFIG13_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x34 25. "PADCONFIG13_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x34 24. "PADCONFIG13_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x34 23. "PADCONFIG13_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x34 22. "PADCONFIG13_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x34 21. "PADCONFIG13_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x34 15. "PADCONFIG13_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x34 14. "PADCONFIG13_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x34 8. "PADCONFIG13_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x34 7. "PADCONFIG13_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x34 0.--3. "PADCONFIG13_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x38 "CFG0_PADCONFIG14,"
bitfld.long 0x38 31. "PADCONFIG14_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x38 30. "PADCONFIG14_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x38 29. "PADCONFIG14_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x38 28. "PADCONFIG14_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x38 27. "PADCONFIG14_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x38 26. "PADCONFIG14_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x38 25. "PADCONFIG14_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x38 24. "PADCONFIG14_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x38 23. "PADCONFIG14_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x38 22. "PADCONFIG14_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x38 21. "PADCONFIG14_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x38 15. "PADCONFIG14_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x38 14. "PADCONFIG14_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x38 8. "PADCONFIG14_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x38 7. "PADCONFIG14_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x38 0.--3. "PADCONFIG14_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x3C "CFG0_PADCONFIG15,"
bitfld.long 0x3C 31. "PADCONFIG15_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x3C 30. "PADCONFIG15_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x3C 29. "PADCONFIG15_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x3C 28. "PADCONFIG15_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x3C 27. "PADCONFIG15_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x3C 26. "PADCONFIG15_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x3C 25. "PADCONFIG15_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x3C 24. "PADCONFIG15_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x3C 23. "PADCONFIG15_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x3C 22. "PADCONFIG15_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x3C 15. "PADCONFIG15_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x3C 14. "PADCONFIG15_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x3C 8. "PADCONFIG15_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x3C 7. "PADCONFIG15_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x3C 0.--3. "PADCONFIG15_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x40 "CFG0_PADCONFIG16,"
bitfld.long 0x40 31. "PADCONFIG16_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x40 30. "PADCONFIG16_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x40 29. "PADCONFIG16_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x40 28. "PADCONFIG16_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x40 27. "PADCONFIG16_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x40 26. "PADCONFIG16_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x40 25. "PADCONFIG16_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x40 24. "PADCONFIG16_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x40 23. "PADCONFIG16_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x40 22. "PADCONFIG16_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x40 21. "PADCONFIG16_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x40 15. "PADCONFIG16_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x40 14. "PADCONFIG16_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x40 8. "PADCONFIG16_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x40 7. "PADCONFIG16_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x40 0.--3. "PADCONFIG16_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x44 "CFG0_PADCONFIG17,"
bitfld.long 0x44 31. "PADCONFIG17_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x44 30. "PADCONFIG17_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x44 29. "PADCONFIG17_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x44 28. "PADCONFIG17_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x44 27. "PADCONFIG17_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x44 26. "PADCONFIG17_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x44 25. "PADCONFIG17_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x44 24. "PADCONFIG17_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x44 23. "PADCONFIG17_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x44 22. "PADCONFIG17_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x44 21. "PADCONFIG17_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x44 15. "PADCONFIG17_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x44 14. "PADCONFIG17_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x44 8. "PADCONFIG17_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x44 7. "PADCONFIG17_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x44 0.--3. "PADCONFIG17_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x48 "CFG0_PADCONFIG18,"
bitfld.long 0x48 31. "PADCONFIG18_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x48 30. "PADCONFIG18_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x48 29. "PADCONFIG18_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x48 28. "PADCONFIG18_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x48 27. "PADCONFIG18_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x48 26. "PADCONFIG18_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x48 25. "PADCONFIG18_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x48 24. "PADCONFIG18_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x48 23. "PADCONFIG18_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x48 22. "PADCONFIG18_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x48 21. "PADCONFIG18_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x48 15. "PADCONFIG18_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x48 14. "PADCONFIG18_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x48 8. "PADCONFIG18_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x48 7. "PADCONFIG18_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x48 0.--3. "PADCONFIG18_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x4C "CFG0_PADCONFIG19,"
bitfld.long 0x4C 31. "PADCONFIG19_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x4C 30. "PADCONFIG19_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x4C 29. "PADCONFIG19_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x4C 28. "PADCONFIG19_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x4C 27. "PADCONFIG19_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x4C 26. "PADCONFIG19_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x4C 25. "PADCONFIG19_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x4C 24. "PADCONFIG19_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x4C 23. "PADCONFIG19_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x4C 22. "PADCONFIG19_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x4C 15. "PADCONFIG19_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x4C 14. "PADCONFIG19_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4C 8. "PADCONFIG19_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x4C 7. "PADCONFIG19_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x4C 0.--3. "PADCONFIG19_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x50 "CFG0_PADCONFIG20,"
bitfld.long 0x50 31. "PADCONFIG20_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x50 30. "PADCONFIG20_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x50 29. "PADCONFIG20_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x50 28. "PADCONFIG20_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x50 27. "PADCONFIG20_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x50 26. "PADCONFIG20_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x50 25. "PADCONFIG20_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x50 24. "PADCONFIG20_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x50 23. "PADCONFIG20_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x50 22. "PADCONFIG20_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x50 21. "PADCONFIG20_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x50 15. "PADCONFIG20_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x50 14. "PADCONFIG20_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x50 8. "PADCONFIG20_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x50 7. "PADCONFIG20_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x50 0.--3. "PADCONFIG20_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x54 "CFG0_PADCONFIG21,"
bitfld.long 0x54 31. "PADCONFIG21_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x54 30. "PADCONFIG21_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x54 29. "PADCONFIG21_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x54 28. "PADCONFIG21_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x54 27. "PADCONFIG21_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x54 26. "PADCONFIG21_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x54 25. "PADCONFIG21_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x54 24. "PADCONFIG21_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x54 23. "PADCONFIG21_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x54 22. "PADCONFIG21_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x54 21. "PADCONFIG21_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x54 15. "PADCONFIG21_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x54 14. "PADCONFIG21_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x54 8. "PADCONFIG21_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x54 7. "PADCONFIG21_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x54 0.--3. "PADCONFIG21_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x58 "CFG0_PADCONFIG22,"
bitfld.long 0x58 31. "PADCONFIG22_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x58 30. "PADCONFIG22_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x58 29. "PADCONFIG22_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x58 28. "PADCONFIG22_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x58 27. "PADCONFIG22_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x58 26. "PADCONFIG22_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x58 25. "PADCONFIG22_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x58 24. "PADCONFIG22_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x58 23. "PADCONFIG22_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x58 22. "PADCONFIG22_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x58 21. "PADCONFIG22_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x58 15. "PADCONFIG22_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x58 14. "PADCONFIG22_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x58 8. "PADCONFIG22_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x58 7. "PADCONFIG22_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x58 0.--3. "PADCONFIG22_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x5C "CFG0_PADCONFIG23,"
bitfld.long 0x5C 31. "PADCONFIG23_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x5C 30. "PADCONFIG23_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x5C 29. "PADCONFIG23_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x5C 28. "PADCONFIG23_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x5C 27. "PADCONFIG23_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x5C 26. "PADCONFIG23_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x5C 25. "PADCONFIG23_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x5C 24. "PADCONFIG23_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x5C 23. "PADCONFIG23_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x5C 22. "PADCONFIG23_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x5C 15. "PADCONFIG23_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x5C 14. "PADCONFIG23_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x5C 8. "PADCONFIG23_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x5C 7. "PADCONFIG23_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x5C 0.--3. "PADCONFIG23_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x60 "CFG0_PADCONFIG24,"
bitfld.long 0x60 31. "PADCONFIG24_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x60 30. "PADCONFIG24_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x60 29. "PADCONFIG24_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x60 28. "PADCONFIG24_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x60 27. "PADCONFIG24_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x60 26. "PADCONFIG24_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x60 25. "PADCONFIG24_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x60 24. "PADCONFIG24_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x60 23. "PADCONFIG24_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x60 22. "PADCONFIG24_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x60 21. "PADCONFIG24_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x60 15. "PADCONFIG24_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x60 14. "PADCONFIG24_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x60 8. "PADCONFIG24_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x60 7. "PADCONFIG24_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x60 0.--3. "PADCONFIG24_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x64 "CFG0_PADCONFIG25,"
bitfld.long 0x64 31. "PADCONFIG25_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x64 30. "PADCONFIG25_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x64 29. "PADCONFIG25_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x64 28. "PADCONFIG25_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x64 27. "PADCONFIG25_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x64 26. "PADCONFIG25_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x64 25. "PADCONFIG25_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x64 24. "PADCONFIG25_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x64 23. "PADCONFIG25_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x64 22. "PADCONFIG25_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x64 21. "PADCONFIG25_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x64 15. "PADCONFIG25_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x64 14. "PADCONFIG25_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x64 8. "PADCONFIG25_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x64 7. "PADCONFIG25_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x64 0.--3. "PADCONFIG25_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x68 "CFG0_PADCONFIG26,"
bitfld.long 0x68 31. "PADCONFIG26_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x68 30. "PADCONFIG26_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x68 29. "PADCONFIG26_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x68 28. "PADCONFIG26_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x68 27. "PADCONFIG26_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x68 26. "PADCONFIG26_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x68 25. "PADCONFIG26_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x68 24. "PADCONFIG26_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x68 23. "PADCONFIG26_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x68 22. "PADCONFIG26_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x68 21. "PADCONFIG26_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x68 15. "PADCONFIG26_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x68 14. "PADCONFIG26_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x68 8. "PADCONFIG26_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x68 7. "PADCONFIG26_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x68 0.--3. "PADCONFIG26_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x6C "CFG0_PADCONFIG27,"
bitfld.long 0x6C 31. "PADCONFIG27_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x6C 30. "PADCONFIG27_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x6C 29. "PADCONFIG27_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x6C 28. "PADCONFIG27_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x6C 27. "PADCONFIG27_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x6C 26. "PADCONFIG27_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x6C 25. "PADCONFIG27_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x6C 24. "PADCONFIG27_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x6C 23. "PADCONFIG27_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x6C 22. "PADCONFIG27_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x6C 15. "PADCONFIG27_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x6C 14. "PADCONFIG27_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x6C 8. "PADCONFIG27_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x6C 7. "PADCONFIG27_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x6C 0.--3. "PADCONFIG27_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x70 "CFG0_PADCONFIG28,"
bitfld.long 0x70 31. "PADCONFIG28_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x70 30. "PADCONFIG28_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x70 29. "PADCONFIG28_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x70 28. "PADCONFIG28_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x70 27. "PADCONFIG28_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x70 26. "PADCONFIG28_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x70 25. "PADCONFIG28_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x70 24. "PADCONFIG28_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x70 23. "PADCONFIG28_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x70 22. "PADCONFIG28_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x70 21. "PADCONFIG28_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x70 15. "PADCONFIG28_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x70 14. "PADCONFIG28_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x70 8. "PADCONFIG28_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x70 7. "PADCONFIG28_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x70 0.--3. "PADCONFIG28_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x74 "CFG0_PADCONFIG29,"
bitfld.long 0x74 31. "PADCONFIG29_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x74 30. "PADCONFIG29_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x74 29. "PADCONFIG29_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x74 28. "PADCONFIG29_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x74 27. "PADCONFIG29_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x74 26. "PADCONFIG29_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x74 25. "PADCONFIG29_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x74 24. "PADCONFIG29_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x74 23. "PADCONFIG29_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x74 22. "PADCONFIG29_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x74 21. "PADCONFIG29_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x74 15. "PADCONFIG29_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x74 14. "PADCONFIG29_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x74 8. "PADCONFIG29_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x74 7. "PADCONFIG29_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x74 0.--3. "PADCONFIG29_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x78 "CFG0_PADCONFIG30,"
bitfld.long 0x78 31. "PADCONFIG30_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x78 30. "PADCONFIG30_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x78 29. "PADCONFIG30_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x78 28. "PADCONFIG30_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x78 27. "PADCONFIG30_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x78 26. "PADCONFIG30_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x78 25. "PADCONFIG30_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x78 24. "PADCONFIG30_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x78 23. "PADCONFIG30_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x78 22. "PADCONFIG30_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x78 21. "PADCONFIG30_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x78 15. "PADCONFIG30_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x78 14. "PADCONFIG30_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x78 8. "PADCONFIG30_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x78 7. "PADCONFIG30_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x78 0.--3. "PADCONFIG30_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x7C "CFG0_PADCONFIG31,"
bitfld.long 0x7C 31. "PADCONFIG31_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x7C 30. "PADCONFIG31_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x7C 29. "PADCONFIG31_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x7C 28. "PADCONFIG31_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x7C 27. "PADCONFIG31_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x7C 26. "PADCONFIG31_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x7C 25. "PADCONFIG31_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x7C 24. "PADCONFIG31_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x7C 23. "PADCONFIG31_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x7C 22. "PADCONFIG31_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x7C 15. "PADCONFIG31_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x7C 14. "PADCONFIG31_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x7C 8. "PADCONFIG31_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x7C 7. "PADCONFIG31_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x7C 0.--3. "PADCONFIG31_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x80 "CFG0_PADCONFIG32,"
bitfld.long 0x80 31. "PADCONFIG32_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x80 30. "PADCONFIG32_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x80 29. "PADCONFIG32_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x80 28. "PADCONFIG32_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x80 27. "PADCONFIG32_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x80 26. "PADCONFIG32_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x80 25. "PADCONFIG32_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x80 24. "PADCONFIG32_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x80 23. "PADCONFIG32_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x80 22. "PADCONFIG32_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x80 21. "PADCONFIG32_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x80 15. "PADCONFIG32_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x80 14. "PADCONFIG32_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x80 8. "PADCONFIG32_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x80 7. "PADCONFIG32_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x80 0.--3. "PADCONFIG32_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x84 "CFG0_PADCONFIG33,"
bitfld.long 0x84 31. "PADCONFIG33_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x84 30. "PADCONFIG33_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x84 29. "PADCONFIG33_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x84 28. "PADCONFIG33_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x84 27. "PADCONFIG33_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x84 26. "PADCONFIG33_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x84 25. "PADCONFIG33_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x84 24. "PADCONFIG33_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x84 23. "PADCONFIG33_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x84 22. "PADCONFIG33_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x84 21. "PADCONFIG33_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x84 19.--20. "PADCONFIG33_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x84 18. "PADCONFIG33_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x84 17. "PADCONFIG33_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x84 16. "PADCONFIG33_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x84 15. "PADCONFIG33_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x84 14. "PADCONFIG33_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x84 11.--13. "PADCONFIG33_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x84 8. "PADCONFIG33_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x84 7. "PADCONFIG33_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x84 0.--3. "PADCONFIG33_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x88 "CFG0_PADCONFIG34,"
bitfld.long 0x88 31. "PADCONFIG34_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x88 30. "PADCONFIG34_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x88 29. "PADCONFIG34_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x88 28. "PADCONFIG34_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x88 27. "PADCONFIG34_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x88 26. "PADCONFIG34_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x88 25. "PADCONFIG34_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x88 24. "PADCONFIG34_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x88 23. "PADCONFIG34_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x88 22. "PADCONFIG34_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x88 21. "PADCONFIG34_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x88 19.--20. "PADCONFIG34_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x88 18. "PADCONFIG34_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x88 17. "PADCONFIG34_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x88 16. "PADCONFIG34_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x88 15. "PADCONFIG34_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x88 14. "PADCONFIG34_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x88 11.--13. "PADCONFIG34_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x88 8. "PADCONFIG34_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x88 7. "PADCONFIG34_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x88 0.--3. "PADCONFIG34_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x8C "CFG0_PADCONFIG35,"
bitfld.long 0x8C 31. "PADCONFIG35_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x8C 30. "PADCONFIG35_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x8C 29. "PADCONFIG35_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x8C 28. "PADCONFIG35_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x8C 27. "PADCONFIG35_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x8C 26. "PADCONFIG35_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x8C 25. "PADCONFIG35_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x8C 24. "PADCONFIG35_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x8C 23. "PADCONFIG35_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x8C 22. "PADCONFIG35_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x8C 21. "PADCONFIG35_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x8C 19.--20. "PADCONFIG35_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x8C 18. "PADCONFIG35_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x8C 17. "PADCONFIG35_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x8C 16. "PADCONFIG35_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x8C 15. "PADCONFIG35_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x8C 14. "PADCONFIG35_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x8C 11.--13. "PADCONFIG35_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x8C 8. "PADCONFIG35_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x8C 7. "PADCONFIG35_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x8C 0.--3. "PADCONFIG35_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x90 "CFG0_PADCONFIG36,"
bitfld.long 0x90 31. "PADCONFIG36_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x90 30. "PADCONFIG36_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x90 29. "PADCONFIG36_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x90 28. "PADCONFIG36_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x90 27. "PADCONFIG36_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x90 26. "PADCONFIG36_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x90 25. "PADCONFIG36_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x90 24. "PADCONFIG36_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x90 23. "PADCONFIG36_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x90 22. "PADCONFIG36_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x90 21. "PADCONFIG36_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x90 19.--20. "PADCONFIG36_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x90 18. "PADCONFIG36_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x90 17. "PADCONFIG36_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x90 16. "PADCONFIG36_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x90 15. "PADCONFIG36_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x90 14. "PADCONFIG36_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x90 11.--13. "PADCONFIG36_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x90 8. "PADCONFIG36_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x90 7. "PADCONFIG36_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x90 0.--3. "PADCONFIG36_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x94 "CFG0_PADCONFIG37,"
bitfld.long 0x94 31. "PADCONFIG37_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x94 30. "PADCONFIG37_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x94 29. "PADCONFIG37_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x94 28. "PADCONFIG37_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x94 27. "PADCONFIG37_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x94 26. "PADCONFIG37_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x94 25. "PADCONFIG37_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x94 24. "PADCONFIG37_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x94 23. "PADCONFIG37_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x94 22. "PADCONFIG37_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x94 21. "PADCONFIG37_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x94 19.--20. "PADCONFIG37_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x94 18. "PADCONFIG37_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x94 17. "PADCONFIG37_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x94 16. "PADCONFIG37_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x94 15. "PADCONFIG37_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x94 14. "PADCONFIG37_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x94 11.--13. "PADCONFIG37_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x94 8. "PADCONFIG37_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x94 7. "PADCONFIG37_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x94 0.--3. "PADCONFIG37_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x98 "CFG0_PADCONFIG38,"
bitfld.long 0x98 31. "PADCONFIG38_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x98 30. "PADCONFIG38_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x98 29. "PADCONFIG38_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x98 28. "PADCONFIG38_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x98 27. "PADCONFIG38_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x98 26. "PADCONFIG38_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x98 25. "PADCONFIG38_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x98 24. "PADCONFIG38_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x98 23. "PADCONFIG38_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x98 22. "PADCONFIG38_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x98 21. "PADCONFIG38_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x98 19.--20. "PADCONFIG38_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x98 18. "PADCONFIG38_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x98 17. "PADCONFIG38_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x98 16. "PADCONFIG38_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x98 15. "PADCONFIG38_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x98 14. "PADCONFIG38_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x98 11.--13. "PADCONFIG38_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x98 8. "PADCONFIG38_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x98 7. "PADCONFIG38_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x98 0.--3. "PADCONFIG38_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x9C "CFG0_PADCONFIG39,"
bitfld.long 0x9C 31. "PADCONFIG39_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x9C 30. "PADCONFIG39_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x9C 29. "PADCONFIG39_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x9C 28. "PADCONFIG39_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x9C 27. "PADCONFIG39_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x9C 26. "PADCONFIG39_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x9C 25. "PADCONFIG39_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x9C 24. "PADCONFIG39_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x9C 23. "PADCONFIG39_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x9C 22. "PADCONFIG39_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x9C 21. "PADCONFIG39_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x9C 19.--20. "PADCONFIG39_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x9C 18. "PADCONFIG39_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x9C 17. "PADCONFIG39_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x9C 16. "PADCONFIG39_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x9C 15. "PADCONFIG39_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x9C 14. "PADCONFIG39_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x9C 11.--13. "PADCONFIG39_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x9C 8. "PADCONFIG39_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x9C 7. "PADCONFIG39_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x9C 0.--3. "PADCONFIG39_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xA0 "CFG0_PADCONFIG40,"
bitfld.long 0xA0 31. "PADCONFIG40_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xA0 30. "PADCONFIG40_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xA0 29. "PADCONFIG40_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xA0 28. "PADCONFIG40_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xA0 27. "PADCONFIG40_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xA0 26. "PADCONFIG40_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xA0 25. "PADCONFIG40_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xA0 24. "PADCONFIG40_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xA0 23. "PADCONFIG40_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xA0 22. "PADCONFIG40_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xA0 21. "PADCONFIG40_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xA0 19.--20. "PADCONFIG40_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xA0 18. "PADCONFIG40_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xA0 17. "PADCONFIG40_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xA0 16. "PADCONFIG40_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xA0 15. "PADCONFIG40_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xA0 14. "PADCONFIG40_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xA0 11.--13. "PADCONFIG40_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xA0 8. "PADCONFIG40_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xA0 7. "PADCONFIG40_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xA0 0.--3. "PADCONFIG40_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xA4 "CFG0_PADCONFIG41,"
bitfld.long 0xA4 31. "PADCONFIG41_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xA4 30. "PADCONFIG41_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xA4 29. "PADCONFIG41_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xA4 28. "PADCONFIG41_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xA4 27. "PADCONFIG41_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xA4 26. "PADCONFIG41_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xA4 25. "PADCONFIG41_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xA4 24. "PADCONFIG41_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xA4 23. "PADCONFIG41_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xA4 22. "PADCONFIG41_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xA4 21. "PADCONFIG41_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xA4 19.--20. "PADCONFIG41_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xA4 18. "PADCONFIG41_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xA4 17. "PADCONFIG41_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xA4 16. "PADCONFIG41_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xA4 15. "PADCONFIG41_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xA4 14. "PADCONFIG41_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xA4 11.--13. "PADCONFIG41_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xA4 8. "PADCONFIG41_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xA4 7. "PADCONFIG41_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xA4 0.--3. "PADCONFIG41_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xA8 "CFG0_PADCONFIG42,"
bitfld.long 0xA8 31. "PADCONFIG42_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xA8 30. "PADCONFIG42_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xA8 29. "PADCONFIG42_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xA8 28. "PADCONFIG42_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xA8 27. "PADCONFIG42_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xA8 26. "PADCONFIG42_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xA8 25. "PADCONFIG42_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xA8 24. "PADCONFIG42_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xA8 23. "PADCONFIG42_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xA8 22. "PADCONFIG42_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xA8 21. "PADCONFIG42_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xA8 19.--20. "PADCONFIG42_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xA8 18. "PADCONFIG42_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xA8 17. "PADCONFIG42_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xA8 16. "PADCONFIG42_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xA8 15. "PADCONFIG42_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xA8 14. "PADCONFIG42_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xA8 11.--13. "PADCONFIG42_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xA8 8. "PADCONFIG42_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xA8 7. "PADCONFIG42_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xA8 0.--3. "PADCONFIG42_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xAC "CFG0_PADCONFIG43,"
bitfld.long 0xAC 31. "PADCONFIG43_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xAC 30. "PADCONFIG43_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xAC 29. "PADCONFIG43_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xAC 28. "PADCONFIG43_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xAC 27. "PADCONFIG43_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xAC 26. "PADCONFIG43_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xAC 25. "PADCONFIG43_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xAC 24. "PADCONFIG43_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xAC 23. "PADCONFIG43_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xAC 22. "PADCONFIG43_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xAC 21. "PADCONFIG43_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xAC 19.--20. "PADCONFIG43_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xAC 18. "PADCONFIG43_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xAC 17. "PADCONFIG43_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xAC 16. "PADCONFIG43_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xAC 15. "PADCONFIG43_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xAC 14. "PADCONFIG43_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xAC 11.--13. "PADCONFIG43_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xAC 8. "PADCONFIG43_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xAC 7. "PADCONFIG43_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xAC 0.--3. "PADCONFIG43_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xB0 "CFG0_PADCONFIG44,"
bitfld.long 0xB0 31. "PADCONFIG44_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xB0 30. "PADCONFIG44_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xB0 29. "PADCONFIG44_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xB0 28. "PADCONFIG44_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xB0 27. "PADCONFIG44_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xB0 26. "PADCONFIG44_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xB0 25. "PADCONFIG44_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xB0 24. "PADCONFIG44_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xB0 23. "PADCONFIG44_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xB0 22. "PADCONFIG44_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xB0 21. "PADCONFIG44_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xB0 19.--20. "PADCONFIG44_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xB0 18. "PADCONFIG44_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xB0 17. "PADCONFIG44_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xB0 16. "PADCONFIG44_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xB0 15. "PADCONFIG44_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xB0 14. "PADCONFIG44_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xB0 11.--13. "PADCONFIG44_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xB0 8. "PADCONFIG44_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xB0 7. "PADCONFIG44_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xB0 0.--3. "PADCONFIG44_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xB4 "CFG0_PADCONFIG45,"
bitfld.long 0xB4 31. "PADCONFIG45_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xB4 30. "PADCONFIG45_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xB4 29. "PADCONFIG45_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xB4 28. "PADCONFIG45_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xB4 27. "PADCONFIG45_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xB4 26. "PADCONFIG45_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xB4 25. "PADCONFIG45_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xB4 24. "PADCONFIG45_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xB4 23. "PADCONFIG45_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xB4 22. "PADCONFIG45_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xB4 21. "PADCONFIG45_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xB4 19.--20. "PADCONFIG45_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xB4 18. "PADCONFIG45_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xB4 17. "PADCONFIG45_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xB4 16. "PADCONFIG45_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xB4 15. "PADCONFIG45_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xB4 14. "PADCONFIG45_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xB4 11.--13. "PADCONFIG45_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xB4 8. "PADCONFIG45_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xB4 7. "PADCONFIG45_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xB4 0.--3. "PADCONFIG45_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xB8 "CFG0_PADCONFIG46,"
bitfld.long 0xB8 31. "PADCONFIG46_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xB8 30. "PADCONFIG46_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xB8 29. "PADCONFIG46_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xB8 28. "PADCONFIG46_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xB8 27. "PADCONFIG46_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xB8 26. "PADCONFIG46_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xB8 25. "PADCONFIG46_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xB8 24. "PADCONFIG46_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xB8 23. "PADCONFIG46_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xB8 22. "PADCONFIG46_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xB8 21. "PADCONFIG46_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xB8 19.--20. "PADCONFIG46_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xB8 18. "PADCONFIG46_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xB8 17. "PADCONFIG46_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xB8 16. "PADCONFIG46_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xB8 15. "PADCONFIG46_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xB8 14. "PADCONFIG46_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xB8 11.--13. "PADCONFIG46_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xB8 8. "PADCONFIG46_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xB8 7. "PADCONFIG46_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xB8 0.--3. "PADCONFIG46_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xBC "CFG0_PADCONFIG47,"
bitfld.long 0xBC 31. "PADCONFIG47_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xBC 30. "PADCONFIG47_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xBC 29. "PADCONFIG47_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xBC 28. "PADCONFIG47_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xBC 27. "PADCONFIG47_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xBC 26. "PADCONFIG47_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xBC 25. "PADCONFIG47_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xBC 24. "PADCONFIG47_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xBC 23. "PADCONFIG47_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xBC 22. "PADCONFIG47_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xBC 21. "PADCONFIG47_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xBC 19.--20. "PADCONFIG47_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xBC 18. "PADCONFIG47_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xBC 17. "PADCONFIG47_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xBC 16. "PADCONFIG47_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xBC 15. "PADCONFIG47_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xBC 14. "PADCONFIG47_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xBC 11.--13. "PADCONFIG47_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xBC 8. "PADCONFIG47_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xBC 7. "PADCONFIG47_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xBC 0.--3. "PADCONFIG47_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xC0 "CFG0_PADCONFIG48,"
bitfld.long 0xC0 31. "PADCONFIG48_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xC0 30. "PADCONFIG48_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xC0 29. "PADCONFIG48_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xC0 28. "PADCONFIG48_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xC0 27. "PADCONFIG48_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xC0 26. "PADCONFIG48_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xC0 25. "PADCONFIG48_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xC0 24. "PADCONFIG48_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xC0 23. "PADCONFIG48_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xC0 22. "PADCONFIG48_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xC0 21. "PADCONFIG48_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xC0 19.--20. "PADCONFIG48_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xC0 18. "PADCONFIG48_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xC0 17. "PADCONFIG48_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xC0 16. "PADCONFIG48_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xC0 15. "PADCONFIG48_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xC0 14. "PADCONFIG48_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xC0 11.--13. "PADCONFIG48_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC0 8. "PADCONFIG48_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xC0 7. "PADCONFIG48_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xC0 0.--3. "PADCONFIG48_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xC4 "CFG0_PADCONFIG49,"
bitfld.long 0xC4 31. "PADCONFIG49_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xC4 30. "PADCONFIG49_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xC4 29. "PADCONFIG49_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xC4 28. "PADCONFIG49_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xC4 27. "PADCONFIG49_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xC4 26. "PADCONFIG49_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xC4 25. "PADCONFIG49_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xC4 24. "PADCONFIG49_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xC4 23. "PADCONFIG49_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xC4 22. "PADCONFIG49_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xC4 21. "PADCONFIG49_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xC4 19.--20. "PADCONFIG49_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xC4 18. "PADCONFIG49_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xC4 17. "PADCONFIG49_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xC4 16. "PADCONFIG49_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xC4 15. "PADCONFIG49_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xC4 14. "PADCONFIG49_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xC4 11.--13. "PADCONFIG49_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC4 8. "PADCONFIG49_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xC4 7. "PADCONFIG49_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xC4 0.--3. "PADCONFIG49_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xC8 "CFG0_PADCONFIG50,"
bitfld.long 0xC8 31. "PADCONFIG50_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xC8 30. "PADCONFIG50_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xC8 29. "PADCONFIG50_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xC8 28. "PADCONFIG50_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xC8 27. "PADCONFIG50_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xC8 26. "PADCONFIG50_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xC8 25. "PADCONFIG50_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xC8 24. "PADCONFIG50_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xC8 23. "PADCONFIG50_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xC8 22. "PADCONFIG50_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xC8 21. "PADCONFIG50_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xC8 19.--20. "PADCONFIG50_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xC8 18. "PADCONFIG50_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xC8 17. "PADCONFIG50_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xC8 16. "PADCONFIG50_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xC8 15. "PADCONFIG50_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xC8 14. "PADCONFIG50_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xC8 11.--13. "PADCONFIG50_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC8 8. "PADCONFIG50_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xC8 7. "PADCONFIG50_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xC8 0.--3. "PADCONFIG50_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xCC "CFG0_PADCONFIG51,"
bitfld.long 0xCC 31. "PADCONFIG51_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xCC 30. "PADCONFIG51_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xCC 29. "PADCONFIG51_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xCC 28. "PADCONFIG51_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xCC 27. "PADCONFIG51_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xCC 26. "PADCONFIG51_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xCC 25. "PADCONFIG51_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xCC 24. "PADCONFIG51_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xCC 23. "PADCONFIG51_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xCC 22. "PADCONFIG51_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xCC 21. "PADCONFIG51_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xCC 19.--20. "PADCONFIG51_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xCC 18. "PADCONFIG51_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xCC 17. "PADCONFIG51_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xCC 16. "PADCONFIG51_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xCC 15. "PADCONFIG51_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xCC 14. "PADCONFIG51_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xCC 11.--13. "PADCONFIG51_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xCC 8. "PADCONFIG51_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xCC 7. "PADCONFIG51_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xCC 0.--3. "PADCONFIG51_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xD0 "CFG0_PADCONFIG52,"
bitfld.long 0xD0 31. "PADCONFIG52_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xD0 30. "PADCONFIG52_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xD0 29. "PADCONFIG52_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xD0 28. "PADCONFIG52_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xD0 27. "PADCONFIG52_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xD0 26. "PADCONFIG52_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xD0 25. "PADCONFIG52_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xD0 24. "PADCONFIG52_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xD0 23. "PADCONFIG52_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xD0 22. "PADCONFIG52_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xD0 21. "PADCONFIG52_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xD0 19.--20. "PADCONFIG52_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xD0 18. "PADCONFIG52_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xD0 17. "PADCONFIG52_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xD0 16. "PADCONFIG52_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xD0 15. "PADCONFIG52_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xD0 14. "PADCONFIG52_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xD0 11.--13. "PADCONFIG52_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xD0 8. "PADCONFIG52_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xD0 7. "PADCONFIG52_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xD0 0.--3. "PADCONFIG52_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xD4 "CFG0_PADCONFIG53,"
bitfld.long 0xD4 31. "PADCONFIG53_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xD4 30. "PADCONFIG53_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xD4 29. "PADCONFIG53_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xD4 28. "PADCONFIG53_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xD4 27. "PADCONFIG53_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xD4 26. "PADCONFIG53_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xD4 25. "PADCONFIG53_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xD4 24. "PADCONFIG53_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xD4 23. "PADCONFIG53_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xD4 22. "PADCONFIG53_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xD4 21. "PADCONFIG53_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xD4 19.--20. "PADCONFIG53_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xD4 18. "PADCONFIG53_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xD4 17. "PADCONFIG53_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xD4 16. "PADCONFIG53_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xD4 15. "PADCONFIG53_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xD4 14. "PADCONFIG53_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xD4 11.--13. "PADCONFIG53_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xD4 8. "PADCONFIG53_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xD4 7. "PADCONFIG53_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xD4 0.--3. "PADCONFIG53_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xD8 "CFG0_PADCONFIG54,"
bitfld.long 0xD8 31. "PADCONFIG54_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xD8 30. "PADCONFIG54_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xD8 29. "PADCONFIG54_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xD8 28. "PADCONFIG54_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xD8 27. "PADCONFIG54_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xD8 26. "PADCONFIG54_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xD8 25. "PADCONFIG54_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xD8 24. "PADCONFIG54_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xD8 23. "PADCONFIG54_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xD8 22. "PADCONFIG54_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xD8 21. "PADCONFIG54_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xD8 19.--20. "PADCONFIG54_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xD8 18. "PADCONFIG54_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xD8 17. "PADCONFIG54_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xD8 16. "PADCONFIG54_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xD8 15. "PADCONFIG54_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xD8 14. "PADCONFIG54_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xD8 11.--13. "PADCONFIG54_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xD8 8. "PADCONFIG54_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xD8 7. "PADCONFIG54_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xD8 0.--3. "PADCONFIG54_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xDC "CFG0_PADCONFIG55,"
bitfld.long 0xDC 31. "PADCONFIG55_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xDC 30. "PADCONFIG55_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xDC 29. "PADCONFIG55_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xDC 28. "PADCONFIG55_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xDC 27. "PADCONFIG55_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xDC 26. "PADCONFIG55_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xDC 25. "PADCONFIG55_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xDC 24. "PADCONFIG55_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xDC 23. "PADCONFIG55_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xDC 22. "PADCONFIG55_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xDC 21. "PADCONFIG55_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xDC 19.--20. "PADCONFIG55_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xDC 18. "PADCONFIG55_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xDC 17. "PADCONFIG55_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xDC 16. "PADCONFIG55_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xDC 15. "PADCONFIG55_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xDC 14. "PADCONFIG55_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xDC 11.--13. "PADCONFIG55_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xDC 8. "PADCONFIG55_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xDC 7. "PADCONFIG55_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xDC 0.--3. "PADCONFIG55_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xE0 "CFG0_PADCONFIG56,"
bitfld.long 0xE0 31. "PADCONFIG56_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xE0 30. "PADCONFIG56_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xE0 29. "PADCONFIG56_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xE0 28. "PADCONFIG56_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xE0 27. "PADCONFIG56_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xE0 26. "PADCONFIG56_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xE0 25. "PADCONFIG56_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xE0 24. "PADCONFIG56_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xE0 23. "PADCONFIG56_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xE0 22. "PADCONFIG56_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xE0 21. "PADCONFIG56_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xE0 19.--20. "PADCONFIG56_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xE0 18. "PADCONFIG56_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xE0 17. "PADCONFIG56_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xE0 16. "PADCONFIG56_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xE0 15. "PADCONFIG56_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xE0 14. "PADCONFIG56_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xE0 11.--13. "PADCONFIG56_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xE0 8. "PADCONFIG56_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xE0 7. "PADCONFIG56_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xE0 0.--3. "PADCONFIG56_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xE4 "CFG0_PADCONFIG57,"
bitfld.long 0xE4 31. "PADCONFIG57_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xE4 30. "PADCONFIG57_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xE4 29. "PADCONFIG57_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xE4 28. "PADCONFIG57_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xE4 27. "PADCONFIG57_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xE4 26. "PADCONFIG57_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xE4 25. "PADCONFIG57_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xE4 24. "PADCONFIG57_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xE4 23. "PADCONFIG57_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xE4 22. "PADCONFIG57_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xE4 21. "PADCONFIG57_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xE4 19.--20. "PADCONFIG57_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xE4 18. "PADCONFIG57_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xE4 17. "PADCONFIG57_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xE4 16. "PADCONFIG57_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xE4 15. "PADCONFIG57_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xE4 14. "PADCONFIG57_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xE4 11.--13. "PADCONFIG57_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xE4 8. "PADCONFIG57_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xE4 7. "PADCONFIG57_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xE4 0.--3. "PADCONFIG57_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xE8 "CFG0_PADCONFIG58,"
bitfld.long 0xE8 31. "PADCONFIG58_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xE8 30. "PADCONFIG58_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xE8 29. "PADCONFIG58_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xE8 28. "PADCONFIG58_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xE8 27. "PADCONFIG58_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xE8 26. "PADCONFIG58_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xE8 25. "PADCONFIG58_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xE8 24. "PADCONFIG58_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xE8 23. "PADCONFIG58_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xE8 22. "PADCONFIG58_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xE8 21. "PADCONFIG58_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xE8 19.--20. "PADCONFIG58_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xE8 18. "PADCONFIG58_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xE8 17. "PADCONFIG58_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xE8 16. "PADCONFIG58_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xE8 15. "PADCONFIG58_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xE8 14. "PADCONFIG58_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xE8 11.--13. "PADCONFIG58_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xE8 8. "PADCONFIG58_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xE8 7. "PADCONFIG58_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xE8 0.--3. "PADCONFIG58_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xEC "CFG0_PADCONFIG59,"
bitfld.long 0xEC 31. "PADCONFIG59_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xEC 30. "PADCONFIG59_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xEC 29. "PADCONFIG59_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xEC 28. "PADCONFIG59_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xEC 27. "PADCONFIG59_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xEC 26. "PADCONFIG59_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xEC 25. "PADCONFIG59_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xEC 24. "PADCONFIG59_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xEC 23. "PADCONFIG59_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xEC 22. "PADCONFIG59_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xEC 21. "PADCONFIG59_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xEC 19.--20. "PADCONFIG59_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xEC 18. "PADCONFIG59_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xEC 17. "PADCONFIG59_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xEC 16. "PADCONFIG59_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xEC 15. "PADCONFIG59_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xEC 14. "PADCONFIG59_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xEC 11.--13. "PADCONFIG59_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xEC 8. "PADCONFIG59_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xEC 7. "PADCONFIG59_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xEC 0.--3. "PADCONFIG59_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xF0 "CFG0_PADCONFIG60,"
bitfld.long 0xF0 31. "PADCONFIG60_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xF0 30. "PADCONFIG60_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xF0 29. "PADCONFIG60_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xF0 28. "PADCONFIG60_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xF0 27. "PADCONFIG60_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xF0 26. "PADCONFIG60_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xF0 25. "PADCONFIG60_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xF0 24. "PADCONFIG60_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xF0 23. "PADCONFIG60_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xF0 22. "PADCONFIG60_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xF0 21. "PADCONFIG60_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xF0 19.--20. "PADCONFIG60_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xF0 18. "PADCONFIG60_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xF0 17. "PADCONFIG60_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xF0 16. "PADCONFIG60_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xF0 15. "PADCONFIG60_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xF0 14. "PADCONFIG60_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xF0 11.--13. "PADCONFIG60_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xF0 8. "PADCONFIG60_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xF0 7. "PADCONFIG60_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xF0 0.--3. "PADCONFIG60_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xF4 "CFG0_PADCONFIG61,"
bitfld.long 0xF4 31. "PADCONFIG61_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xF4 30. "PADCONFIG61_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xF4 29. "PADCONFIG61_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xF4 28. "PADCONFIG61_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xF4 27. "PADCONFIG61_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xF4 26. "PADCONFIG61_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xF4 25. "PADCONFIG61_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xF4 24. "PADCONFIG61_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xF4 23. "PADCONFIG61_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xF4 22. "PADCONFIG61_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xF4 21. "PADCONFIG61_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xF4 19.--20. "PADCONFIG61_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xF4 18. "PADCONFIG61_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xF4 17. "PADCONFIG61_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xF4 16. "PADCONFIG61_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xF4 15. "PADCONFIG61_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xF4 14. "PADCONFIG61_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xF4 11.--13. "PADCONFIG61_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xF4 8. "PADCONFIG61_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xF4 7. "PADCONFIG61_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xF4 0.--3. "PADCONFIG61_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xF8 "CFG0_PADCONFIG62,"
bitfld.long 0xF8 31. "PADCONFIG62_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xF8 30. "PADCONFIG62_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xF8 29. "PADCONFIG62_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xF8 28. "PADCONFIG62_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xF8 27. "PADCONFIG62_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xF8 26. "PADCONFIG62_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xF8 25. "PADCONFIG62_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xF8 24. "PADCONFIG62_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xF8 23. "PADCONFIG62_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xF8 22. "PADCONFIG62_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xF8 21. "PADCONFIG62_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xF8 19.--20. "PADCONFIG62_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xF8 18. "PADCONFIG62_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xF8 17. "PADCONFIG62_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xF8 16. "PADCONFIG62_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xF8 15. "PADCONFIG62_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xF8 14. "PADCONFIG62_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xF8 11.--13. "PADCONFIG62_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xF8 8. "PADCONFIG62_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xF8 7. "PADCONFIG62_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xF8 0.--3. "PADCONFIG62_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xFC "CFG0_PADCONFIG63,"
bitfld.long 0xFC 31. "PADCONFIG63_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xFC 30. "PADCONFIG63_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xFC 29. "PADCONFIG63_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xFC 28. "PADCONFIG63_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xFC 27. "PADCONFIG63_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xFC 26. "PADCONFIG63_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xFC 25. "PADCONFIG63_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xFC 24. "PADCONFIG63_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xFC 23. "PADCONFIG63_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xFC 22. "PADCONFIG63_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xFC 21. "PADCONFIG63_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xFC 19.--20. "PADCONFIG63_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xFC 18. "PADCONFIG63_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xFC 17. "PADCONFIG63_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xFC 16. "PADCONFIG63_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xFC 15. "PADCONFIG63_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xFC 14. "PADCONFIG63_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xFC 11.--13. "PADCONFIG63_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xFC 8. "PADCONFIG63_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xFC 7. "PADCONFIG63_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xFC 0.--3. "PADCONFIG63_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x100 "CFG0_PADCONFIG64,"
bitfld.long 0x100 31. "PADCONFIG64_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x100 30. "PADCONFIG64_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x100 29. "PADCONFIG64_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x100 28. "PADCONFIG64_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x100 27. "PADCONFIG64_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x100 26. "PADCONFIG64_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x100 25. "PADCONFIG64_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x100 24. "PADCONFIG64_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x100 23. "PADCONFIG64_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x100 22. "PADCONFIG64_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x100 21. "PADCONFIG64_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x100 19.--20. "PADCONFIG64_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x100 18. "PADCONFIG64_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x100 17. "PADCONFIG64_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x100 16. "PADCONFIG64_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x100 15. "PADCONFIG64_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x100 14. "PADCONFIG64_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x100 11.--13. "PADCONFIG64_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x100 8. "PADCONFIG64_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x100 7. "PADCONFIG64_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x100 0.--3. "PADCONFIG64_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x104 "CFG0_PADCONFIG65,"
bitfld.long 0x104 31. "PADCONFIG65_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x104 30. "PADCONFIG65_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x104 29. "PADCONFIG65_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x104 28. "PADCONFIG65_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x104 27. "PADCONFIG65_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x104 26. "PADCONFIG65_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x104 25. "PADCONFIG65_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x104 24. "PADCONFIG65_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x104 23. "PADCONFIG65_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x104 22. "PADCONFIG65_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x104 21. "PADCONFIG65_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x104 19.--20. "PADCONFIG65_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x104 18. "PADCONFIG65_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x104 17. "PADCONFIG65_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x104 16. "PADCONFIG65_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x104 15. "PADCONFIG65_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x104 14. "PADCONFIG65_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x104 11.--13. "PADCONFIG65_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x104 8. "PADCONFIG65_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x104 7. "PADCONFIG65_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x104 0.--3. "PADCONFIG65_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x108 "CFG0_PADCONFIG66,"
bitfld.long 0x108 31. "PADCONFIG66_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x108 30. "PADCONFIG66_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x108 29. "PADCONFIG66_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x108 28. "PADCONFIG66_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x108 27. "PADCONFIG66_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x108 26. "PADCONFIG66_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x108 25. "PADCONFIG66_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x108 24. "PADCONFIG66_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x108 23. "PADCONFIG66_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x108 22. "PADCONFIG66_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x108 21. "PADCONFIG66_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x108 19.--20. "PADCONFIG66_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x108 18. "PADCONFIG66_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x108 17. "PADCONFIG66_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x108 16. "PADCONFIG66_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x108 15. "PADCONFIG66_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x108 14. "PADCONFIG66_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x108 11.--13. "PADCONFIG66_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x108 8. "PADCONFIG66_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x108 7. "PADCONFIG66_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x108 0.--3. "PADCONFIG66_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x10C "CFG0_PADCONFIG67,"
bitfld.long 0x10C 31. "PADCONFIG67_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x10C 30. "PADCONFIG67_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x10C 29. "PADCONFIG67_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x10C 28. "PADCONFIG67_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x10C 27. "PADCONFIG67_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x10C 26. "PADCONFIG67_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x10C 25. "PADCONFIG67_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x10C 24. "PADCONFIG67_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x10C 23. "PADCONFIG67_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x10C 22. "PADCONFIG67_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x10C 21. "PADCONFIG67_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x10C 19.--20. "PADCONFIG67_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x10C 18. "PADCONFIG67_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x10C 17. "PADCONFIG67_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x10C 16. "PADCONFIG67_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x10C 15. "PADCONFIG67_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x10C 14. "PADCONFIG67_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x10C 11.--13. "PADCONFIG67_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10C 8. "PADCONFIG67_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x10C 7. "PADCONFIG67_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x10C 0.--3. "PADCONFIG67_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x110 "CFG0_PADCONFIG68,"
bitfld.long 0x110 31. "PADCONFIG68_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x110 30. "PADCONFIG68_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x110 29. "PADCONFIG68_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x110 28. "PADCONFIG68_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x110 27. "PADCONFIG68_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x110 26. "PADCONFIG68_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x110 25. "PADCONFIG68_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x110 24. "PADCONFIG68_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x110 23. "PADCONFIG68_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x110 22. "PADCONFIG68_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x110 21. "PADCONFIG68_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x110 19.--20. "PADCONFIG68_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x110 18. "PADCONFIG68_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x110 17. "PADCONFIG68_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x110 16. "PADCONFIG68_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x110 15. "PADCONFIG68_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x110 14. "PADCONFIG68_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x110 11.--13. "PADCONFIG68_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x110 8. "PADCONFIG68_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x110 7. "PADCONFIG68_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x110 0.--3. "PADCONFIG68_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x114 "CFG0_PADCONFIG69,"
bitfld.long 0x114 31. "PADCONFIG69_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x114 30. "PADCONFIG69_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x114 29. "PADCONFIG69_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x114 28. "PADCONFIG69_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x114 27. "PADCONFIG69_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x114 26. "PADCONFIG69_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x114 25. "PADCONFIG69_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x114 24. "PADCONFIG69_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x114 23. "PADCONFIG69_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x114 22. "PADCONFIG69_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x114 21. "PADCONFIG69_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x114 19.--20. "PADCONFIG69_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x114 18. "PADCONFIG69_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x114 17. "PADCONFIG69_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x114 16. "PADCONFIG69_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x114 15. "PADCONFIG69_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x114 14. "PADCONFIG69_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x114 11.--13. "PADCONFIG69_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x114 8. "PADCONFIG69_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x114 7. "PADCONFIG69_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x114 0.--3. "PADCONFIG69_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x118 "CFG0_PADCONFIG70,"
bitfld.long 0x118 31. "PADCONFIG70_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x118 30. "PADCONFIG70_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x118 29. "PADCONFIG70_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x118 28. "PADCONFIG70_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x118 27. "PADCONFIG70_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x118 26. "PADCONFIG70_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x118 25. "PADCONFIG70_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x118 24. "PADCONFIG70_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x118 23. "PADCONFIG70_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x118 22. "PADCONFIG70_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x118 21. "PADCONFIG70_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x118 19.--20. "PADCONFIG70_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x118 18. "PADCONFIG70_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x118 17. "PADCONFIG70_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x118 16. "PADCONFIG70_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x118 15. "PADCONFIG70_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x118 14. "PADCONFIG70_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x118 11.--13. "PADCONFIG70_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x118 8. "PADCONFIG70_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x118 7. "PADCONFIG70_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x118 0.--3. "PADCONFIG70_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x11C "CFG0_PADCONFIG71,"
bitfld.long 0x11C 31. "PADCONFIG71_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x11C 30. "PADCONFIG71_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x11C 29. "PADCONFIG71_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x11C 28. "PADCONFIG71_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x11C 27. "PADCONFIG71_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x11C 26. "PADCONFIG71_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x11C 25. "PADCONFIG71_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x11C 24. "PADCONFIG71_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x11C 23. "PADCONFIG71_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x11C 22. "PADCONFIG71_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x11C 21. "PADCONFIG71_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x11C 19.--20. "PADCONFIG71_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x11C 18. "PADCONFIG71_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x11C 17. "PADCONFIG71_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x11C 16. "PADCONFIG71_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x11C 15. "PADCONFIG71_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x11C 14. "PADCONFIG71_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x11C 11.--13. "PADCONFIG71_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x11C 8. "PADCONFIG71_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x11C 7. "PADCONFIG71_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x11C 0.--3. "PADCONFIG71_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x120 "CFG0_PADCONFIG72,"
bitfld.long 0x120 31. "PADCONFIG72_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x120 30. "PADCONFIG72_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x120 29. "PADCONFIG72_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x120 28. "PADCONFIG72_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x120 27. "PADCONFIG72_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x120 26. "PADCONFIG72_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x120 25. "PADCONFIG72_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x120 24. "PADCONFIG72_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x120 23. "PADCONFIG72_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x120 22. "PADCONFIG72_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x120 21. "PADCONFIG72_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x120 19.--20. "PADCONFIG72_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x120 18. "PADCONFIG72_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x120 17. "PADCONFIG72_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x120 16. "PADCONFIG72_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x120 15. "PADCONFIG72_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x120 14. "PADCONFIG72_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x120 11.--13. "PADCONFIG72_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x120 8. "PADCONFIG72_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x120 7. "PADCONFIG72_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x120 0.--3. "PADCONFIG72_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x124 "CFG0_PADCONFIG73,"
bitfld.long 0x124 31. "PADCONFIG73_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x124 30. "PADCONFIG73_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x124 29. "PADCONFIG73_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x124 28. "PADCONFIG73_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x124 27. "PADCONFIG73_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x124 26. "PADCONFIG73_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x124 25. "PADCONFIG73_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x124 24. "PADCONFIG73_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x124 23. "PADCONFIG73_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x124 22. "PADCONFIG73_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x124 21. "PADCONFIG73_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x124 19.--20. "PADCONFIG73_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x124 18. "PADCONFIG73_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x124 17. "PADCONFIG73_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x124 16. "PADCONFIG73_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x124 15. "PADCONFIG73_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x124 14. "PADCONFIG73_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x124 11.--13. "PADCONFIG73_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x124 8. "PADCONFIG73_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x124 7. "PADCONFIG73_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x124 0.--3. "PADCONFIG73_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x128 "CFG0_PADCONFIG74,"
bitfld.long 0x128 31. "PADCONFIG74_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x128 30. "PADCONFIG74_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x128 29. "PADCONFIG74_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x128 28. "PADCONFIG74_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x128 27. "PADCONFIG74_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x128 26. "PADCONFIG74_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x128 25. "PADCONFIG74_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x128 24. "PADCONFIG74_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x128 23. "PADCONFIG74_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x128 22. "PADCONFIG74_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x128 21. "PADCONFIG74_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x128 19.--20. "PADCONFIG74_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x128 18. "PADCONFIG74_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x128 17. "PADCONFIG74_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x128 16. "PADCONFIG74_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x128 15. "PADCONFIG74_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x128 14. "PADCONFIG74_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x128 11.--13. "PADCONFIG74_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x128 8. "PADCONFIG74_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x128 7. "PADCONFIG74_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x128 0.--3. "PADCONFIG74_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x12C "CFG0_PADCONFIG75,"
bitfld.long 0x12C 31. "PADCONFIG75_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x12C 30. "PADCONFIG75_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x12C 29. "PADCONFIG75_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x12C 28. "PADCONFIG75_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x12C 27. "PADCONFIG75_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x12C 26. "PADCONFIG75_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x12C 25. "PADCONFIG75_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x12C 24. "PADCONFIG75_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x12C 23. "PADCONFIG75_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x12C 22. "PADCONFIG75_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x12C 21. "PADCONFIG75_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x12C 19.--20. "PADCONFIG75_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x12C 18. "PADCONFIG75_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x12C 17. "PADCONFIG75_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x12C 16. "PADCONFIG75_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x12C 15. "PADCONFIG75_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x12C 14. "PADCONFIG75_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x12C 11.--13. "PADCONFIG75_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x12C 8. "PADCONFIG75_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x12C 7. "PADCONFIG75_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x12C 0.--3. "PADCONFIG75_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x130 "CFG0_PADCONFIG76,"
bitfld.long 0x130 31. "PADCONFIG76_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x130 30. "PADCONFIG76_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x130 29. "PADCONFIG76_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x130 28. "PADCONFIG76_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x130 27. "PADCONFIG76_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x130 26. "PADCONFIG76_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x130 25. "PADCONFIG76_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x130 24. "PADCONFIG76_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x130 23. "PADCONFIG76_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x130 22. "PADCONFIG76_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x130 21. "PADCONFIG76_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x130 19.--20. "PADCONFIG76_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x130 18. "PADCONFIG76_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x130 17. "PADCONFIG76_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x130 16. "PADCONFIG76_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x130 15. "PADCONFIG76_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x130 14. "PADCONFIG76_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x130 11.--13. "PADCONFIG76_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x130 8. "PADCONFIG76_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x130 7. "PADCONFIG76_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x130 0.--3. "PADCONFIG76_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x134 "CFG0_PADCONFIG77,"
bitfld.long 0x134 31. "PADCONFIG77_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x134 30. "PADCONFIG77_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x134 29. "PADCONFIG77_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x134 28. "PADCONFIG77_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x134 27. "PADCONFIG77_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x134 26. "PADCONFIG77_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x134 25. "PADCONFIG77_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x134 24. "PADCONFIG77_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x134 23. "PADCONFIG77_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x134 22. "PADCONFIG77_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x134 21. "PADCONFIG77_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x134 19.--20. "PADCONFIG77_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x134 18. "PADCONFIG77_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x134 17. "PADCONFIG77_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x134 16. "PADCONFIG77_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x134 15. "PADCONFIG77_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x134 14. "PADCONFIG77_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x134 11.--13. "PADCONFIG77_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x134 8. "PADCONFIG77_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x134 7. "PADCONFIG77_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x134 0.--3. "PADCONFIG77_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x138 "CFG0_PADCONFIG78,"
bitfld.long 0x138 31. "PADCONFIG78_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x138 30. "PADCONFIG78_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x138 29. "PADCONFIG78_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x138 28. "PADCONFIG78_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x138 27. "PADCONFIG78_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x138 26. "PADCONFIG78_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x138 25. "PADCONFIG78_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x138 24. "PADCONFIG78_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x138 23. "PADCONFIG78_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x138 22. "PADCONFIG78_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x138 21. "PADCONFIG78_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x138 19.--20. "PADCONFIG78_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x138 18. "PADCONFIG78_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x138 17. "PADCONFIG78_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x138 16. "PADCONFIG78_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x138 15. "PADCONFIG78_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x138 14. "PADCONFIG78_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x138 11.--13. "PADCONFIG78_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x138 8. "PADCONFIG78_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x138 7. "PADCONFIG78_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x138 0.--3. "PADCONFIG78_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x13C "CFG0_PADCONFIG79,"
bitfld.long 0x13C 31. "PADCONFIG79_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x13C 30. "PADCONFIG79_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x13C 29. "PADCONFIG79_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x13C 28. "PADCONFIG79_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x13C 27. "PADCONFIG79_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x13C 26. "PADCONFIG79_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x13C 25. "PADCONFIG79_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x13C 24. "PADCONFIG79_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x13C 23. "PADCONFIG79_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x13C 22. "PADCONFIG79_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x13C 21. "PADCONFIG79_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x13C 19.--20. "PADCONFIG79_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x13C 18. "PADCONFIG79_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x13C 17. "PADCONFIG79_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x13C 16. "PADCONFIG79_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x13C 15. "PADCONFIG79_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x13C 14. "PADCONFIG79_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x13C 11.--13. "PADCONFIG79_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x13C 8. "PADCONFIG79_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x13C 7. "PADCONFIG79_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x13C 0.--3. "PADCONFIG79_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x140 "CFG0_PADCONFIG80,"
bitfld.long 0x140 31. "PADCONFIG80_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x140 30. "PADCONFIG80_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x140 29. "PADCONFIG80_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x140 28. "PADCONFIG80_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x140 27. "PADCONFIG80_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x140 26. "PADCONFIG80_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x140 25. "PADCONFIG80_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x140 24. "PADCONFIG80_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x140 23. "PADCONFIG80_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x140 22. "PADCONFIG80_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x140 21. "PADCONFIG80_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x140 19.--20. "PADCONFIG80_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x140 18. "PADCONFIG80_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x140 17. "PADCONFIG80_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x140 16. "PADCONFIG80_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x140 15. "PADCONFIG80_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x140 14. "PADCONFIG80_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x140 11.--13. "PADCONFIG80_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 8. "PADCONFIG80_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x140 7. "PADCONFIG80_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x140 0.--3. "PADCONFIG80_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x144 "CFG0_PADCONFIG81,"
bitfld.long 0x144 31. "PADCONFIG81_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x144 30. "PADCONFIG81_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x144 29. "PADCONFIG81_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x144 28. "PADCONFIG81_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x144 27. "PADCONFIG81_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x144 26. "PADCONFIG81_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x144 25. "PADCONFIG81_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x144 24. "PADCONFIG81_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x144 23. "PADCONFIG81_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x144 22. "PADCONFIG81_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x144 21. "PADCONFIG81_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x144 19.--20. "PADCONFIG81_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x144 18. "PADCONFIG81_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x144 17. "PADCONFIG81_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x144 16. "PADCONFIG81_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x144 15. "PADCONFIG81_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x144 14. "PADCONFIG81_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x144 11.--13. "PADCONFIG81_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 8. "PADCONFIG81_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x144 7. "PADCONFIG81_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x144 0.--3. "PADCONFIG81_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x148 "CFG0_PADCONFIG82,"
bitfld.long 0x148 31. "PADCONFIG82_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x148 30. "PADCONFIG82_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x148 29. "PADCONFIG82_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x148 28. "PADCONFIG82_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x148 27. "PADCONFIG82_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x148 26. "PADCONFIG82_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x148 25. "PADCONFIG82_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x148 24. "PADCONFIG82_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x148 23. "PADCONFIG82_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x148 22. "PADCONFIG82_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x148 21. "PADCONFIG82_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x148 19.--20. "PADCONFIG82_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x148 18. "PADCONFIG82_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x148 17. "PADCONFIG82_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x148 16. "PADCONFIG82_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x148 15. "PADCONFIG82_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x148 14. "PADCONFIG82_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x148 11.--13. "PADCONFIG82_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x148 8. "PADCONFIG82_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x148 7. "PADCONFIG82_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x148 0.--3. "PADCONFIG82_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x14C "CFG0_PADCONFIG83,"
bitfld.long 0x14C 31. "PADCONFIG83_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x14C 30. "PADCONFIG83_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x14C 29. "PADCONFIG83_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x14C 28. "PADCONFIG83_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x14C 27. "PADCONFIG83_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x14C 26. "PADCONFIG83_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x14C 25. "PADCONFIG83_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x14C 24. "PADCONFIG83_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x14C 23. "PADCONFIG83_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x14C 22. "PADCONFIG83_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x14C 21. "PADCONFIG83_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x14C 19.--20. "PADCONFIG83_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x14C 18. "PADCONFIG83_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x14C 17. "PADCONFIG83_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x14C 16. "PADCONFIG83_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x14C 15. "PADCONFIG83_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x14C 14. "PADCONFIG83_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x14C 11.--13. "PADCONFIG83_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14C 8. "PADCONFIG83_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x14C 7. "PADCONFIG83_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x14C 0.--3. "PADCONFIG83_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x150 "CFG0_PADCONFIG84,"
bitfld.long 0x150 31. "PADCONFIG84_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x150 30. "PADCONFIG84_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x150 29. "PADCONFIG84_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x150 28. "PADCONFIG84_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x150 27. "PADCONFIG84_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x150 26. "PADCONFIG84_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x150 25. "PADCONFIG84_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x150 24. "PADCONFIG84_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x150 23. "PADCONFIG84_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x150 22. "PADCONFIG84_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x150 21. "PADCONFIG84_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x150 19.--20. "PADCONFIG84_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x150 18. "PADCONFIG84_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x150 17. "PADCONFIG84_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x150 16. "PADCONFIG84_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x150 15. "PADCONFIG84_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x150 14. "PADCONFIG84_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x150 11.--13. "PADCONFIG84_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x150 8. "PADCONFIG84_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x150 7. "PADCONFIG84_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x150 0.--3. "PADCONFIG84_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x154 "CFG0_PADCONFIG85,"
bitfld.long 0x154 31. "PADCONFIG85_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x154 30. "PADCONFIG85_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x154 29. "PADCONFIG85_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x154 28. "PADCONFIG85_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x154 27. "PADCONFIG85_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x154 26. "PADCONFIG85_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x154 25. "PADCONFIG85_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x154 24. "PADCONFIG85_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x154 23. "PADCONFIG85_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x154 22. "PADCONFIG85_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x154 21. "PADCONFIG85_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x154 19.--20. "PADCONFIG85_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x154 18. "PADCONFIG85_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x154 17. "PADCONFIG85_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x154 16. "PADCONFIG85_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x154 15. "PADCONFIG85_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x154 14. "PADCONFIG85_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x154 11.--13. "PADCONFIG85_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x154 8. "PADCONFIG85_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x154 7. "PADCONFIG85_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x154 0.--3. "PADCONFIG85_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x158 "CFG0_PADCONFIG86,"
bitfld.long 0x158 31. "PADCONFIG86_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x158 30. "PADCONFIG86_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x158 29. "PADCONFIG86_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x158 28. "PADCONFIG86_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x158 27. "PADCONFIG86_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x158 26. "PADCONFIG86_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x158 25. "PADCONFIG86_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x158 24. "PADCONFIG86_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x158 23. "PADCONFIG86_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x158 22. "PADCONFIG86_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x158 21. "PADCONFIG86_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x158 19.--20. "PADCONFIG86_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x158 18. "PADCONFIG86_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x158 17. "PADCONFIG86_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x158 16. "PADCONFIG86_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x158 15. "PADCONFIG86_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x158 14. "PADCONFIG86_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x158 11.--13. "PADCONFIG86_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x158 8. "PADCONFIG86_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x158 7. "PADCONFIG86_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x158 0.--3. "PADCONFIG86_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x15C "CFG0_PADCONFIG87,"
bitfld.long 0x15C 31. "PADCONFIG87_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x15C 30. "PADCONFIG87_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x15C 29. "PADCONFIG87_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x15C 28. "PADCONFIG87_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x15C 27. "PADCONFIG87_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x15C 26. "PADCONFIG87_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x15C 25. "PADCONFIG87_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x15C 24. "PADCONFIG87_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x15C 23. "PADCONFIG87_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x15C 22. "PADCONFIG87_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x15C 21. "PADCONFIG87_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x15C 19.--20. "PADCONFIG87_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x15C 18. "PADCONFIG87_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x15C 17. "PADCONFIG87_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x15C 16. "PADCONFIG87_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x15C 15. "PADCONFIG87_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x15C 14. "PADCONFIG87_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x15C 11.--13. "PADCONFIG87_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x15C 8. "PADCONFIG87_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x15C 7. "PADCONFIG87_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x15C 0.--3. "PADCONFIG87_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x160 "CFG0_PADCONFIG88,"
bitfld.long 0x160 31. "PADCONFIG88_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x160 30. "PADCONFIG88_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x160 29. "PADCONFIG88_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x160 28. "PADCONFIG88_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x160 27. "PADCONFIG88_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x160 26. "PADCONFIG88_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x160 25. "PADCONFIG88_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x160 24. "PADCONFIG88_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x160 23. "PADCONFIG88_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x160 22. "PADCONFIG88_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x160 21. "PADCONFIG88_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x160 19.--20. "PADCONFIG88_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x160 18. "PADCONFIG88_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x160 17. "PADCONFIG88_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x160 16. "PADCONFIG88_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x160 15. "PADCONFIG88_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x160 14. "PADCONFIG88_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x160 11.--13. "PADCONFIG88_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x160 8. "PADCONFIG88_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x160 7. "PADCONFIG88_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x160 0.--3. "PADCONFIG88_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x164 "CFG0_PADCONFIG89,"
bitfld.long 0x164 31. "PADCONFIG89_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x164 30. "PADCONFIG89_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x164 29. "PADCONFIG89_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x164 28. "PADCONFIG89_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x164 27. "PADCONFIG89_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x164 26. "PADCONFIG89_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x164 25. "PADCONFIG89_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x164 24. "PADCONFIG89_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x164 23. "PADCONFIG89_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x164 22. "PADCONFIG89_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x164 21. "PADCONFIG89_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x164 19.--20. "PADCONFIG89_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x164 18. "PADCONFIG89_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x164 17. "PADCONFIG89_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x164 16. "PADCONFIG89_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x164 15. "PADCONFIG89_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x164 14. "PADCONFIG89_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x164 11.--13. "PADCONFIG89_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x164 8. "PADCONFIG89_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x164 7. "PADCONFIG89_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x164 0.--3. "PADCONFIG89_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x168 "CFG0_PADCONFIG90,"
bitfld.long 0x168 31. "PADCONFIG90_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x168 30. "PADCONFIG90_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x168 29. "PADCONFIG90_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x168 28. "PADCONFIG90_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x168 27. "PADCONFIG90_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x168 26. "PADCONFIG90_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x168 25. "PADCONFIG90_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x168 24. "PADCONFIG90_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x168 23. "PADCONFIG90_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x168 22. "PADCONFIG90_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x168 21. "PADCONFIG90_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x168 19.--20. "PADCONFIG90_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x168 18. "PADCONFIG90_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x168 17. "PADCONFIG90_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x168 16. "PADCONFIG90_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x168 15. "PADCONFIG90_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x168 14. "PADCONFIG90_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x168 11.--13. "PADCONFIG90_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x168 8. "PADCONFIG90_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x168 7. "PADCONFIG90_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x168 0.--3. "PADCONFIG90_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x16C "CFG0_PADCONFIG91,"
bitfld.long 0x16C 31. "PADCONFIG91_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x16C 30. "PADCONFIG91_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x16C 29. "PADCONFIG91_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x16C 28. "PADCONFIG91_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x16C 27. "PADCONFIG91_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x16C 26. "PADCONFIG91_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x16C 25. "PADCONFIG91_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x16C 24. "PADCONFIG91_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x16C 23. "PADCONFIG91_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x16C 22. "PADCONFIG91_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x16C 21. "PADCONFIG91_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x16C 19.--20. "PADCONFIG91_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x16C 18. "PADCONFIG91_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x16C 17. "PADCONFIG91_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x16C 16. "PADCONFIG91_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x16C 15. "PADCONFIG91_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x16C 14. "PADCONFIG91_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x16C 11.--13. "PADCONFIG91_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x16C 8. "PADCONFIG91_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x16C 7. "PADCONFIG91_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x16C 0.--3. "PADCONFIG91_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x170 "CFG0_PADCONFIG92,"
bitfld.long 0x170 31. "PADCONFIG92_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x170 30. "PADCONFIG92_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x170 29. "PADCONFIG92_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x170 28. "PADCONFIG92_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x170 27. "PADCONFIG92_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x170 26. "PADCONFIG92_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x170 25. "PADCONFIG92_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x170 24. "PADCONFIG92_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x170 23. "PADCONFIG92_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x170 22. "PADCONFIG92_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x170 21. "PADCONFIG92_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x170 19.--20. "PADCONFIG92_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x170 18. "PADCONFIG92_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x170 17. "PADCONFIG92_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x170 16. "PADCONFIG92_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x170 15. "PADCONFIG92_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x170 14. "PADCONFIG92_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x170 11.--13. "PADCONFIG92_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x170 8. "PADCONFIG92_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x170 7. "PADCONFIG92_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x170 0.--3. "PADCONFIG92_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x174 "CFG0_PADCONFIG93,"
bitfld.long 0x174 31. "PADCONFIG93_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x174 30. "PADCONFIG93_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x174 29. "PADCONFIG93_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x174 28. "PADCONFIG93_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x174 27. "PADCONFIG93_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x174 26. "PADCONFIG93_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x174 25. "PADCONFIG93_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x174 24. "PADCONFIG93_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x174 23. "PADCONFIG93_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x174 22. "PADCONFIG93_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x174 21. "PADCONFIG93_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x174 19.--20. "PADCONFIG93_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x174 18. "PADCONFIG93_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x174 17. "PADCONFIG93_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x174 16. "PADCONFIG93_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x174 15. "PADCONFIG93_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x174 14. "PADCONFIG93_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x174 11.--13. "PADCONFIG93_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x174 8. "PADCONFIG93_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x174 7. "PADCONFIG93_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x174 0.--3. "PADCONFIG93_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x178 "CFG0_PADCONFIG94,"
bitfld.long 0x178 31. "PADCONFIG94_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x178 30. "PADCONFIG94_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x178 29. "PADCONFIG94_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x178 28. "PADCONFIG94_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x178 27. "PADCONFIG94_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x178 26. "PADCONFIG94_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x178 25. "PADCONFIG94_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x178 24. "PADCONFIG94_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x178 23. "PADCONFIG94_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x178 22. "PADCONFIG94_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x178 21. "PADCONFIG94_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x178 19.--20. "PADCONFIG94_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x178 18. "PADCONFIG94_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x178 17. "PADCONFIG94_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x178 16. "PADCONFIG94_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x178 15. "PADCONFIG94_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x178 14. "PADCONFIG94_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x178 11.--13. "PADCONFIG94_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x178 8. "PADCONFIG94_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x178 7. "PADCONFIG94_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x178 0.--3. "PADCONFIG94_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x17C "CFG0_PADCONFIG95,"
bitfld.long 0x17C 31. "PADCONFIG95_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x17C 30. "PADCONFIG95_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x17C 29. "PADCONFIG95_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x17C 28. "PADCONFIG95_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x17C 27. "PADCONFIG95_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x17C 26. "PADCONFIG95_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x17C 25. "PADCONFIG95_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x17C 24. "PADCONFIG95_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x17C 23. "PADCONFIG95_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x17C 22. "PADCONFIG95_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x17C 21. "PADCONFIG95_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x17C 19.--20. "PADCONFIG95_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x17C 18. "PADCONFIG95_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x17C 17. "PADCONFIG95_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x17C 16. "PADCONFIG95_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x17C 15. "PADCONFIG95_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x17C 14. "PADCONFIG95_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x17C 11.--13. "PADCONFIG95_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x17C 8. "PADCONFIG95_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x17C 7. "PADCONFIG95_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x17C 0.--3. "PADCONFIG95_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x180 "CFG0_PADCONFIG96,"
bitfld.long 0x180 31. "PADCONFIG96_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x180 30. "PADCONFIG96_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x180 29. "PADCONFIG96_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x180 28. "PADCONFIG96_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x180 27. "PADCONFIG96_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x180 26. "PADCONFIG96_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x180 25. "PADCONFIG96_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x180 24. "PADCONFIG96_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x180 23. "PADCONFIG96_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x180 22. "PADCONFIG96_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x180 21. "PADCONFIG96_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x180 19.--20. "PADCONFIG96_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x180 18. "PADCONFIG96_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x180 17. "PADCONFIG96_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x180 16. "PADCONFIG96_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x180 15. "PADCONFIG96_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x180 14. "PADCONFIG96_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x180 11.--13. "PADCONFIG96_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x180 8. "PADCONFIG96_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x180 7. "PADCONFIG96_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x180 0.--3. "PADCONFIG96_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x184 "CFG0_PADCONFIG97,"
bitfld.long 0x184 31. "PADCONFIG97_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x184 30. "PADCONFIG97_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x184 29. "PADCONFIG97_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x184 28. "PADCONFIG97_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x184 27. "PADCONFIG97_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x184 26. "PADCONFIG97_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x184 25. "PADCONFIG97_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x184 24. "PADCONFIG97_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x184 23. "PADCONFIG97_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x184 22. "PADCONFIG97_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x184 21. "PADCONFIG97_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x184 19.--20. "PADCONFIG97_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x184 18. "PADCONFIG97_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x184 17. "PADCONFIG97_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x184 16. "PADCONFIG97_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x184 15. "PADCONFIG97_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x184 14. "PADCONFIG97_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x184 11.--13. "PADCONFIG97_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x184 8. "PADCONFIG97_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x184 7. "PADCONFIG97_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x184 0.--3. "PADCONFIG97_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x188 "CFG0_PADCONFIG98,"
bitfld.long 0x188 31. "PADCONFIG98_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x188 30. "PADCONFIG98_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x188 29. "PADCONFIG98_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x188 28. "PADCONFIG98_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x188 27. "PADCONFIG98_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x188 26. "PADCONFIG98_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x188 25. "PADCONFIG98_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x188 24. "PADCONFIG98_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x188 23. "PADCONFIG98_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x188 22. "PADCONFIG98_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x188 21. "PADCONFIG98_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x188 19.--20. "PADCONFIG98_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x188 18. "PADCONFIG98_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x188 17. "PADCONFIG98_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x188 16. "PADCONFIG98_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x188 15. "PADCONFIG98_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x188 14. "PADCONFIG98_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x188 11.--13. "PADCONFIG98_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x188 8. "PADCONFIG98_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x188 7. "PADCONFIG98_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x188 0.--3. "PADCONFIG98_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x18C "CFG0_PADCONFIG99,"
bitfld.long 0x18C 31. "PADCONFIG99_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x18C 30. "PADCONFIG99_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x18C 29. "PADCONFIG99_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x18C 28. "PADCONFIG99_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x18C 27. "PADCONFIG99_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x18C 26. "PADCONFIG99_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x18C 25. "PADCONFIG99_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x18C 24. "PADCONFIG99_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x18C 23. "PADCONFIG99_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x18C 22. "PADCONFIG99_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x18C 21. "PADCONFIG99_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x18C 19.--20. "PADCONFIG99_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x18C 18. "PADCONFIG99_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x18C 17. "PADCONFIG99_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x18C 16. "PADCONFIG99_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x18C 15. "PADCONFIG99_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x18C 14. "PADCONFIG99_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x18C 11.--13. "PADCONFIG99_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18C 8. "PADCONFIG99_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x18C 7. "PADCONFIG99_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x18C 0.--3. "PADCONFIG99_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x190 "CFG0_PADCONFIG100,"
bitfld.long 0x190 31. "PADCONFIG100_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x190 30. "PADCONFIG100_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x190 29. "PADCONFIG100_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x190 28. "PADCONFIG100_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x190 27. "PADCONFIG100_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x190 26. "PADCONFIG100_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x190 25. "PADCONFIG100_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x190 24. "PADCONFIG100_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x190 23. "PADCONFIG100_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x190 22. "PADCONFIG100_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x190 21. "PADCONFIG100_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x190 19.--20. "PADCONFIG100_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x190 18. "PADCONFIG100_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x190 17. "PADCONFIG100_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x190 16. "PADCONFIG100_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x190 15. "PADCONFIG100_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x190 14. "PADCONFIG100_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x190 11.--13. "PADCONFIG100_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x190 8. "PADCONFIG100_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x190 7. "PADCONFIG100_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x190 0.--3. "PADCONFIG100_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x194 "CFG0_PADCONFIG101,"
bitfld.long 0x194 31. "PADCONFIG101_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x194 30. "PADCONFIG101_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x194 29. "PADCONFIG101_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x194 28. "PADCONFIG101_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x194 27. "PADCONFIG101_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x194 26. "PADCONFIG101_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x194 25. "PADCONFIG101_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x194 24. "PADCONFIG101_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x194 23. "PADCONFIG101_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x194 22. "PADCONFIG101_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x194 21. "PADCONFIG101_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x194 19.--20. "PADCONFIG101_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x194 18. "PADCONFIG101_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x194 17. "PADCONFIG101_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x194 16. "PADCONFIG101_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x194 15. "PADCONFIG101_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x194 14. "PADCONFIG101_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x194 11.--13. "PADCONFIG101_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x194 8. "PADCONFIG101_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x194 7. "PADCONFIG101_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x194 0.--3. "PADCONFIG101_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x198 "CFG0_PADCONFIG102,"
bitfld.long 0x198 31. "PADCONFIG102_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x198 30. "PADCONFIG102_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x198 29. "PADCONFIG102_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x198 28. "PADCONFIG102_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x198 27. "PADCONFIG102_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x198 26. "PADCONFIG102_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x198 25. "PADCONFIG102_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x198 24. "PADCONFIG102_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x198 23. "PADCONFIG102_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x198 22. "PADCONFIG102_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x198 21. "PADCONFIG102_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x198 19.--20. "PADCONFIG102_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x198 18. "PADCONFIG102_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x198 17. "PADCONFIG102_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x198 16. "PADCONFIG102_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x198 15. "PADCONFIG102_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x198 14. "PADCONFIG102_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x198 11.--13. "PADCONFIG102_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x198 8. "PADCONFIG102_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x198 7. "PADCONFIG102_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x198 0.--3. "PADCONFIG102_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x19C "CFG0_PADCONFIG103,"
bitfld.long 0x19C 31. "PADCONFIG103_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x19C 30. "PADCONFIG103_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x19C 29. "PADCONFIG103_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x19C 28. "PADCONFIG103_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x19C 27. "PADCONFIG103_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x19C 26. "PADCONFIG103_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x19C 25. "PADCONFIG103_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x19C 24. "PADCONFIG103_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x19C 23. "PADCONFIG103_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x19C 22. "PADCONFIG103_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x19C 21. "PADCONFIG103_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x19C 19.--20. "PADCONFIG103_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x19C 18. "PADCONFIG103_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x19C 17. "PADCONFIG103_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x19C 16. "PADCONFIG103_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x19C 15. "PADCONFIG103_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x19C 14. "PADCONFIG103_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x19C 11.--13. "PADCONFIG103_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x19C 8. "PADCONFIG103_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x19C 7. "PADCONFIG103_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x19C 0.--3. "PADCONFIG103_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1A0 "CFG0_PADCONFIG104,"
bitfld.long 0x1A0 31. "PADCONFIG104_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1A0 30. "PADCONFIG104_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1A0 29. "PADCONFIG104_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1A0 28. "PADCONFIG104_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1A0 27. "PADCONFIG104_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1A0 26. "PADCONFIG104_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1A0 25. "PADCONFIG104_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1A0 24. "PADCONFIG104_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1A0 23. "PADCONFIG104_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1A0 22. "PADCONFIG104_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1A0 21. "PADCONFIG104_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1A0 19.--20. "PADCONFIG104_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1A0 18. "PADCONFIG104_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1A0 17. "PADCONFIG104_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1A0 16. "PADCONFIG104_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1A0 15. "PADCONFIG104_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x1A0 14. "PADCONFIG104_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1A0 11.--13. "PADCONFIG104_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1A0 8. "PADCONFIG104_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1A0 7. "PADCONFIG104_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1A0 0.--3. "PADCONFIG104_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1A4 "CFG0_PADCONFIG105,"
bitfld.long 0x1A4 31. "PADCONFIG105_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1A4 30. "PADCONFIG105_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1A4 29. "PADCONFIG105_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1A4 28. "PADCONFIG105_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1A4 27. "PADCONFIG105_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1A4 26. "PADCONFIG105_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1A4 25. "PADCONFIG105_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1A4 24. "PADCONFIG105_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x1A4 23. "PADCONFIG105_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x1A4 22. "PADCONFIG105_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x1A4 21. "PADCONFIG105_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1A4 19.--20. "PADCONFIG105_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x1A4 18. "PADCONFIG105_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1A4 17. "PADCONFIG105_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1A4 16. "PADCONFIG105_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1A4 15. "PADCONFIG105_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x1A4 14. "PADCONFIG105_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1A4 11.--13. "PADCONFIG105_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1A4 8. "PADCONFIG105_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1A4 7. "PADCONFIG105_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x1A4 0.--3. "PADCONFIG105_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1A8 "CFG0_PADCONFIG106,"
bitfld.long 0x1A8 31. "PADCONFIG106_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1A8 30. "PADCONFIG106_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1A8 29. "PADCONFIG106_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x1A8 28. "PADCONFIG106_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1A8 27. "PADCONFIG106_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1A8 26. "PADCONFIG106_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1A8 25. "PADCONFIG106_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x1A8 24. "PADCONFIG106_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x1A8 23. "PADCONFIG106_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x1A8 22. "PADCONFIG106_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x1A8 21. "PADCONFIG106_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1A8 19.--20. "PADCONFIG106_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1A8 18. "PADCONFIG106_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1A8 17. "PADCONFIG106_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1A8 16. "PADCONFIG106_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1A8 15. "PADCONFIG106_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x1A8 14. "PADCONFIG106_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1A8 11.--13. "PADCONFIG106_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1A8 8. "PADCONFIG106_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1A8 7. "PADCONFIG106_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1A8 0.--3. "PADCONFIG106_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1AC "CFG0_PADCONFIG107,"
bitfld.long 0x1AC 31. "PADCONFIG107_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1AC 30. "PADCONFIG107_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1AC 29. "PADCONFIG107_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1AC 28. "PADCONFIG107_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1AC 27. "PADCONFIG107_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1AC 26. "PADCONFIG107_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1AC 25. "PADCONFIG107_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1AC 24. "PADCONFIG107_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1AC 23. "PADCONFIG107_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1AC 22. "PADCONFIG107_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1AC 21. "PADCONFIG107_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1AC 19.--20. "PADCONFIG107_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1AC 18. "PADCONFIG107_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1AC 17. "PADCONFIG107_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1AC 16. "PADCONFIG107_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1AC 15. "PADCONFIG107_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1AC 14. "PADCONFIG107_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1AC 11.--13. "PADCONFIG107_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1AC 8. "PADCONFIG107_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1AC 7. "PADCONFIG107_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1AC 0.--3. "PADCONFIG107_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1B0 "CFG0_PADCONFIG108,"
bitfld.long 0x1B0 31. "PADCONFIG108_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1B0 30. "PADCONFIG108_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1B0 29. "PADCONFIG108_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1B0 28. "PADCONFIG108_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1B0 27. "PADCONFIG108_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1B0 26. "PADCONFIG108_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1B0 25. "PADCONFIG108_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1B0 24. "PADCONFIG108_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1B0 23. "PADCONFIG108_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1B0 22. "PADCONFIG108_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1B0 21. "PADCONFIG108_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1B0 19.--20. "PADCONFIG108_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1B0 18. "PADCONFIG108_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1B0 17. "PADCONFIG108_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1B0 16. "PADCONFIG108_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1B0 15. "PADCONFIG108_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1B0 14. "PADCONFIG108_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1B0 11.--13. "PADCONFIG108_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1B0 8. "PADCONFIG108_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1B0 7. "PADCONFIG108_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1B0 0.--3. "PADCONFIG108_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1B4 "CFG0_PADCONFIG109,"
bitfld.long 0x1B4 31. "PADCONFIG109_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1B4 30. "PADCONFIG109_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1B4 29. "PADCONFIG109_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1B4 28. "PADCONFIG109_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1B4 27. "PADCONFIG109_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1B4 26. "PADCONFIG109_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1B4 25. "PADCONFIG109_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1B4 24. "PADCONFIG109_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1B4 23. "PADCONFIG109_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1B4 22. "PADCONFIG109_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1B4 21. "PADCONFIG109_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1B4 19.--20. "PADCONFIG109_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1B4 18. "PADCONFIG109_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1B4 17. "PADCONFIG109_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1B4 16. "PADCONFIG109_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1B4 15. "PADCONFIG109_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1B4 14. "PADCONFIG109_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1B4 11.--13. "PADCONFIG109_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1B4 8. "PADCONFIG109_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1B4 7. "PADCONFIG109_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1B4 0.--3. "PADCONFIG109_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1B8 "CFG0_PADCONFIG110,"
bitfld.long 0x1B8 31. "PADCONFIG110_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1B8 30. "PADCONFIG110_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1B8 29. "PADCONFIG110_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1B8 28. "PADCONFIG110_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1B8 27. "PADCONFIG110_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1B8 26. "PADCONFIG110_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1B8 25. "PADCONFIG110_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1B8 24. "PADCONFIG110_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1B8 23. "PADCONFIG110_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1B8 22. "PADCONFIG110_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1B8 21. "PADCONFIG110_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1B8 19.--20. "PADCONFIG110_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1B8 18. "PADCONFIG110_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1B8 17. "PADCONFIG110_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1B8 16. "PADCONFIG110_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1B8 15. "PADCONFIG110_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1B8 14. "PADCONFIG110_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1B8 11.--13. "PADCONFIG110_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1B8 8. "PADCONFIG110_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1B8 7. "PADCONFIG110_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1B8 0.--3. "PADCONFIG110_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1BC "CFG0_PADCONFIG111,"
bitfld.long 0x1BC 31. "PADCONFIG111_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1BC 30. "PADCONFIG111_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1BC 29. "PADCONFIG111_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1BC 28. "PADCONFIG111_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1BC 27. "PADCONFIG111_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1BC 26. "PADCONFIG111_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1BC 25. "PADCONFIG111_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1BC 24. "PADCONFIG111_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1BC 23. "PADCONFIG111_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1BC 22. "PADCONFIG111_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1BC 21. "PADCONFIG111_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1BC 19.--20. "PADCONFIG111_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1BC 18. "PADCONFIG111_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1BC 17. "PADCONFIG111_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1BC 16. "PADCONFIG111_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1BC 15. "PADCONFIG111_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1BC 14. "PADCONFIG111_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1BC 11.--13. "PADCONFIG111_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1BC 8. "PADCONFIG111_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1BC 7. "PADCONFIG111_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1BC 0.--3. "PADCONFIG111_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C0 "CFG0_PADCONFIG112,"
bitfld.long 0x1C0 31. "PADCONFIG112_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C0 30. "PADCONFIG112_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C0 29. "PADCONFIG112_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1C0 28. "PADCONFIG112_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1C0 27. "PADCONFIG112_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C0 26. "PADCONFIG112_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1C0 25. "PADCONFIG112_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C0 24. "PADCONFIG112_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1C0 23. "PADCONFIG112_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1C0 22. "PADCONFIG112_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1C0 21. "PADCONFIG112_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1C0 19.--20. "PADCONFIG112_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1C0 18. "PADCONFIG112_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1C0 17. "PADCONFIG112_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1C0 16. "PADCONFIG112_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C0 15. "PADCONFIG112_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1C0 14. "PADCONFIG112_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C0 11.--13. "PADCONFIG112_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C0 8. "PADCONFIG112_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1C0 7. "PADCONFIG112_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1C0 0.--3. "PADCONFIG112_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C4 "CFG0_PADCONFIG113,"
bitfld.long 0x1C4 31. "PADCONFIG113_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C4 30. "PADCONFIG113_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C4 29. "PADCONFIG113_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1C4 28. "PADCONFIG113_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1C4 27. "PADCONFIG113_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C4 26. "PADCONFIG113_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1C4 25. "PADCONFIG113_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C4 24. "PADCONFIG113_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1C4 23. "PADCONFIG113_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1C4 22. "PADCONFIG113_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1C4 21. "PADCONFIG113_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1C4 19.--20. "PADCONFIG113_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1C4 18. "PADCONFIG113_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1C4 17. "PADCONFIG113_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1C4 16. "PADCONFIG113_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C4 15. "PADCONFIG113_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1C4 14. "PADCONFIG113_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C4 11.--13. "PADCONFIG113_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C4 8. "PADCONFIG113_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1C4 7. "PADCONFIG113_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1C4 0.--3. "PADCONFIG113_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C8 "CFG0_PADCONFIG114,"
bitfld.long 0x1C8 31. "PADCONFIG114_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C8 30. "PADCONFIG114_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C8 29. "PADCONFIG114_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1C8 28. "PADCONFIG114_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1C8 27. "PADCONFIG114_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C8 26. "PADCONFIG114_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1C8 25. "PADCONFIG114_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C8 24. "PADCONFIG114_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1C8 23. "PADCONFIG114_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1C8 22. "PADCONFIG114_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1C8 21. "PADCONFIG114_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1C8 19.--20. "PADCONFIG114_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1C8 18. "PADCONFIG114_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1C8 17. "PADCONFIG114_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1C8 16. "PADCONFIG114_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C8 15. "PADCONFIG114_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1C8 14. "PADCONFIG114_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C8 11.--13. "PADCONFIG114_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C8 8. "PADCONFIG114_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1C8 7. "PADCONFIG114_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1C8 0.--3. "PADCONFIG114_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1CC "CFG0_PADCONFIG115,"
bitfld.long 0x1CC 31. "PADCONFIG115_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1CC 30. "PADCONFIG115_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1CC 29. "PADCONFIG115_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1CC 28. "PADCONFIG115_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1CC 27. "PADCONFIG115_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1CC 26. "PADCONFIG115_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1CC 25. "PADCONFIG115_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1CC 24. "PADCONFIG115_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1CC 23. "PADCONFIG115_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1CC 22. "PADCONFIG115_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1CC 21. "PADCONFIG115_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1CC 19.--20. "PADCONFIG115_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1CC 18. "PADCONFIG115_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1CC 17. "PADCONFIG115_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1CC 16. "PADCONFIG115_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1CC 15. "PADCONFIG115_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1CC 14. "PADCONFIG115_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1CC 11.--13. "PADCONFIG115_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1CC 8. "PADCONFIG115_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1CC 7. "PADCONFIG115_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1CC 0.--3. "PADCONFIG115_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1D0 "CFG0_PADCONFIG116,"
bitfld.long 0x1D0 31. "PADCONFIG116_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1D0 30. "PADCONFIG116_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1D0 29. "PADCONFIG116_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1D0 28. "PADCONFIG116_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1D0 27. "PADCONFIG116_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1D0 26. "PADCONFIG116_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1D0 25. "PADCONFIG116_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1D0 24. "PADCONFIG116_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1D0 23. "PADCONFIG116_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1D0 22. "PADCONFIG116_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1D0 21. "PADCONFIG116_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1D0 19.--20. "PADCONFIG116_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1D0 18. "PADCONFIG116_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1D0 17. "PADCONFIG116_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1D0 16. "PADCONFIG116_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1D0 15. "PADCONFIG116_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1D0 14. "PADCONFIG116_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1D0 11.--13. "PADCONFIG116_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1D0 8. "PADCONFIG116_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1D0 7. "PADCONFIG116_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1D0 0.--3. "PADCONFIG116_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1D4 "CFG0_PADCONFIG117,"
bitfld.long 0x1D4 31. "PADCONFIG117_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1D4 30. "PADCONFIG117_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1D4 29. "PADCONFIG117_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1D4 28. "PADCONFIG117_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1D4 27. "PADCONFIG117_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1D4 26. "PADCONFIG117_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1D4 25. "PADCONFIG117_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1D4 24. "PADCONFIG117_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1D4 23. "PADCONFIG117_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1D4 22. "PADCONFIG117_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1D4 21. "PADCONFIG117_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1D4 19.--20. "PADCONFIG117_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1D4 18. "PADCONFIG117_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1D4 17. "PADCONFIG117_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1D4 16. "PADCONFIG117_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1D4 15. "PADCONFIG117_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1D4 14. "PADCONFIG117_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1D4 11.--13. "PADCONFIG117_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1D4 8. "PADCONFIG117_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1D4 7. "PADCONFIG117_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1D4 0.--3. "PADCONFIG117_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1D8 "CFG0_PADCONFIG118,"
bitfld.long 0x1D8 31. "PADCONFIG118_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1D8 30. "PADCONFIG118_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1D8 29. "PADCONFIG118_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1D8 28. "PADCONFIG118_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1D8 27. "PADCONFIG118_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1D8 26. "PADCONFIG118_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1D8 25. "PADCONFIG118_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1D8 24. "PADCONFIG118_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1D8 23. "PADCONFIG118_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1D8 22. "PADCONFIG118_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1D8 21. "PADCONFIG118_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1D8 19.--20. "PADCONFIG118_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1D8 18. "PADCONFIG118_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1D8 17. "PADCONFIG118_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1D8 16. "PADCONFIG118_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1D8 15. "PADCONFIG118_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1D8 14. "PADCONFIG118_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1D8 11.--13. "PADCONFIG118_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1D8 8. "PADCONFIG118_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1D8 7. "PADCONFIG118_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1D8 0.--3. "PADCONFIG118_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1DC "CFG0_PADCONFIG119,"
bitfld.long 0x1DC 31. "PADCONFIG119_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1DC 30. "PADCONFIG119_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1DC 29. "PADCONFIG119_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1DC 28. "PADCONFIG119_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1DC 27. "PADCONFIG119_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1DC 26. "PADCONFIG119_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1DC 25. "PADCONFIG119_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1DC 24. "PADCONFIG119_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1DC 23. "PADCONFIG119_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1DC 22. "PADCONFIG119_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1DC 21. "PADCONFIG119_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1DC 19.--20. "PADCONFIG119_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1DC 18. "PADCONFIG119_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1DC 17. "PADCONFIG119_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1DC 16. "PADCONFIG119_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1DC 15. "PADCONFIG119_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1DC 14. "PADCONFIG119_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1DC 11.--13. "PADCONFIG119_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1DC 8. "PADCONFIG119_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1DC 7. "PADCONFIG119_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1DC 0.--3. "PADCONFIG119_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1E0 "CFG0_PADCONFIG120,"
bitfld.long 0x1E0 31. "PADCONFIG120_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1E0 30. "PADCONFIG120_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1E0 29. "PADCONFIG120_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1E0 28. "PADCONFIG120_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1E0 27. "PADCONFIG120_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1E0 26. "PADCONFIG120_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1E0 25. "PADCONFIG120_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1E0 24. "PADCONFIG120_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1E0 23. "PADCONFIG120_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1E0 22. "PADCONFIG120_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1E0 21. "PADCONFIG120_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1E0 19.--20. "PADCONFIG120_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1E0 18. "PADCONFIG120_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1E0 17. "PADCONFIG120_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1E0 16. "PADCONFIG120_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1E0 15. "PADCONFIG120_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1E0 14. "PADCONFIG120_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1E0 11.--13. "PADCONFIG120_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1E0 8. "PADCONFIG120_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1E0 7. "PADCONFIG120_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1E0 0.--3. "PADCONFIG120_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1E4 "CFG0_PADCONFIG121,"
bitfld.long 0x1E4 31. "PADCONFIG121_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1E4 30. "PADCONFIG121_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1E4 29. "PADCONFIG121_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1E4 28. "PADCONFIG121_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1E4 27. "PADCONFIG121_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1E4 26. "PADCONFIG121_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1E4 25. "PADCONFIG121_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1E4 24. "PADCONFIG121_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1E4 23. "PADCONFIG121_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1E4 22. "PADCONFIG121_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1E4 21. "PADCONFIG121_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1E4 19.--20. "PADCONFIG121_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1E4 18. "PADCONFIG121_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1E4 17. "PADCONFIG121_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1E4 16. "PADCONFIG121_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1E4 15. "PADCONFIG121_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1E4 14. "PADCONFIG121_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1E4 11.--13. "PADCONFIG121_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1E4 8. "PADCONFIG121_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1E4 7. "PADCONFIG121_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1E4 0.--3. "PADCONFIG121_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1E8 "CFG0_PADCONFIG122,"
bitfld.long 0x1E8 31. "PADCONFIG122_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1E8 30. "PADCONFIG122_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1E8 29. "PADCONFIG122_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1E8 28. "PADCONFIG122_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1E8 27. "PADCONFIG122_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1E8 26. "PADCONFIG122_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1E8 25. "PADCONFIG122_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1E8 24. "PADCONFIG122_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1E8 23. "PADCONFIG122_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1E8 22. "PADCONFIG122_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1E8 21. "PADCONFIG122_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1E8 19.--20. "PADCONFIG122_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1E8 18. "PADCONFIG122_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1E8 17. "PADCONFIG122_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1E8 16. "PADCONFIG122_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1E8 15. "PADCONFIG122_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1E8 14. "PADCONFIG122_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1E8 11.--13. "PADCONFIG122_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1E8 8. "PADCONFIG122_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1E8 7. "PADCONFIG122_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1E8 0.--3. "PADCONFIG122_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1EC "CFG0_PADCONFIG123,"
bitfld.long 0x1EC 31. "PADCONFIG123_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1EC 30. "PADCONFIG123_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1EC 29. "PADCONFIG123_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1EC 28. "PADCONFIG123_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1EC 27. "PADCONFIG123_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1EC 26. "PADCONFIG123_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1EC 25. "PADCONFIG123_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1EC 24. "PADCONFIG123_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1EC 23. "PADCONFIG123_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1EC 22. "PADCONFIG123_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1EC 21. "PADCONFIG123_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1EC 19.--20. "PADCONFIG123_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1EC 18. "PADCONFIG123_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1EC 17. "PADCONFIG123_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1EC 16. "PADCONFIG123_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1EC 15. "PADCONFIG123_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1EC 14. "PADCONFIG123_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1EC 11.--13. "PADCONFIG123_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1EC 8. "PADCONFIG123_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1EC 7. "PADCONFIG123_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1EC 0.--3. "PADCONFIG123_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1F0 "CFG0_PADCONFIG124,"
bitfld.long 0x1F0 31. "PADCONFIG124_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1F0 30. "PADCONFIG124_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1F0 29. "PADCONFIG124_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1F0 28. "PADCONFIG124_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1F0 27. "PADCONFIG124_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1F0 26. "PADCONFIG124_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1F0 25. "PADCONFIG124_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1F0 24. "PADCONFIG124_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1F0 23. "PADCONFIG124_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1F0 22. "PADCONFIG124_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1F0 21. "PADCONFIG124_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1F0 19.--20. "PADCONFIG124_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1F0 18. "PADCONFIG124_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1F0 17. "PADCONFIG124_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1F0 16. "PADCONFIG124_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1F0 15. "PADCONFIG124_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1F0 14. "PADCONFIG124_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1F0 11.--13. "PADCONFIG124_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1F0 8. "PADCONFIG124_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1F0 7. "PADCONFIG124_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1F0 0.--3. "PADCONFIG124_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1F4 "CFG0_PADCONFIG125,"
bitfld.long 0x1F4 31. "PADCONFIG125_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1F4 30. "PADCONFIG125_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1F4 29. "PADCONFIG125_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1F4 28. "PADCONFIG125_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1F4 27. "PADCONFIG125_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1F4 26. "PADCONFIG125_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1F4 25. "PADCONFIG125_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1F4 24. "PADCONFIG125_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1F4 23. "PADCONFIG125_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1F4 22. "PADCONFIG125_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1F4 21. "PADCONFIG125_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1F4 19.--20. "PADCONFIG125_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1F4 18. "PADCONFIG125_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1F4 17. "PADCONFIG125_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1F4 16. "PADCONFIG125_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1F4 15. "PADCONFIG125_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1F4 14. "PADCONFIG125_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1F4 11.--13. "PADCONFIG125_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1F4 8. "PADCONFIG125_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1F4 7. "PADCONFIG125_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1F4 0.--3. "PADCONFIG125_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1F8 "CFG0_PADCONFIG126,"
bitfld.long 0x1F8 31. "PADCONFIG126_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1F8 30. "PADCONFIG126_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1F8 29. "PADCONFIG126_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1F8 28. "PADCONFIG126_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1F8 27. "PADCONFIG126_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1F8 26. "PADCONFIG126_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1F8 25. "PADCONFIG126_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1F8 24. "PADCONFIG126_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1F8 23. "PADCONFIG126_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1F8 22. "PADCONFIG126_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1F8 21. "PADCONFIG126_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1F8 19.--20. "PADCONFIG126_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1F8 18. "PADCONFIG126_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1F8 17. "PADCONFIG126_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1F8 16. "PADCONFIG126_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1F8 15. "PADCONFIG126_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1F8 14. "PADCONFIG126_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1F8 11.--13. "PADCONFIG126_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1F8 8. "PADCONFIG126_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1F8 7. "PADCONFIG126_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1F8 0.--3. "PADCONFIG126_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1FC "CFG0_PADCONFIG127,"
bitfld.long 0x1FC 31. "PADCONFIG127_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1FC 30. "PADCONFIG127_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1FC 29. "PADCONFIG127_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1FC 28. "PADCONFIG127_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1FC 27. "PADCONFIG127_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1FC 26. "PADCONFIG127_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1FC 25. "PADCONFIG127_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1FC 24. "PADCONFIG127_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1FC 23. "PADCONFIG127_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1FC 22. "PADCONFIG127_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1FC 21. "PADCONFIG127_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1FC 19.--20. "PADCONFIG127_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1FC 18. "PADCONFIG127_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1FC 17. "PADCONFIG127_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1FC 16. "PADCONFIG127_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1FC 15. "PADCONFIG127_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1FC 14. "PADCONFIG127_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1FC 11.--13. "PADCONFIG127_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1FC 8. "PADCONFIG127_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1FC 7. "PADCONFIG127_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1FC 0.--3. "PADCONFIG127_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x200 "CFG0_PADCONFIG128,"
bitfld.long 0x200 31. "PADCONFIG128_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x200 30. "PADCONFIG128_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x200 29. "PADCONFIG128_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x200 28. "PADCONFIG128_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x200 27. "PADCONFIG128_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x200 26. "PADCONFIG128_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x200 25. "PADCONFIG128_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x200 24. "PADCONFIG128_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x200 23. "PADCONFIG128_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x200 22. "PADCONFIG128_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x200 21. "PADCONFIG128_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x200 19.--20. "PADCONFIG128_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x200 18. "PADCONFIG128_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x200 17. "PADCONFIG128_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x200 16. "PADCONFIG128_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x200 15. "PADCONFIG128_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x200 14. "PADCONFIG128_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x200 11.--13. "PADCONFIG128_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x200 8. "PADCONFIG128_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x200 7. "PADCONFIG128_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x200 0.--3. "PADCONFIG128_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x204 "CFG0_PADCONFIG129,"
bitfld.long 0x204 31. "PADCONFIG129_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x204 30. "PADCONFIG129_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x204 29. "PADCONFIG129_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x204 28. "PADCONFIG129_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x204 27. "PADCONFIG129_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x204 26. "PADCONFIG129_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x204 25. "PADCONFIG129_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x204 24. "PADCONFIG129_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x204 23. "PADCONFIG129_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x204 22. "PADCONFIG129_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x204 21. "PADCONFIG129_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x204 19.--20. "PADCONFIG129_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x204 18. "PADCONFIG129_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x204 17. "PADCONFIG129_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x204 16. "PADCONFIG129_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x204 15. "PADCONFIG129_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x204 14. "PADCONFIG129_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x204 11.--13. "PADCONFIG129_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x204 8. "PADCONFIG129_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x204 7. "PADCONFIG129_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x204 0.--3. "PADCONFIG129_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x208 "CFG0_PADCONFIG130,"
bitfld.long 0x208 31. "PADCONFIG130_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x208 30. "PADCONFIG130_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x208 29. "PADCONFIG130_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x208 28. "PADCONFIG130_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x208 27. "PADCONFIG130_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x208 26. "PADCONFIG130_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x208 25. "PADCONFIG130_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x208 24. "PADCONFIG130_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x208 23. "PADCONFIG130_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x208 22. "PADCONFIG130_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x208 21. "PADCONFIG130_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x208 19.--20. "PADCONFIG130_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x208 18. "PADCONFIG130_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x208 17. "PADCONFIG130_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x208 16. "PADCONFIG130_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x208 15. "PADCONFIG130_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x208 14. "PADCONFIG130_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x208 11.--13. "PADCONFIG130_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x208 8. "PADCONFIG130_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x208 7. "PADCONFIG130_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x208 0.--3. "PADCONFIG130_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x20C "CFG0_PADCONFIG131,"
bitfld.long 0x20C 31. "PADCONFIG131_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x20C 30. "PADCONFIG131_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x20C 29. "PADCONFIG131_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x20C 28. "PADCONFIG131_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x20C 27. "PADCONFIG131_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x20C 26. "PADCONFIG131_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x20C 25. "PADCONFIG131_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x20C 24. "PADCONFIG131_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x20C 23. "PADCONFIG131_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x20C 22. "PADCONFIG131_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x20C 21. "PADCONFIG131_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x20C 19.--20. "PADCONFIG131_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x20C 18. "PADCONFIG131_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x20C 17. "PADCONFIG131_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x20C 16. "PADCONFIG131_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x20C 15. "PADCONFIG131_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x20C 14. "PADCONFIG131_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x20C 11.--13. "PADCONFIG131_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20C 8. "PADCONFIG131_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x20C 7. "PADCONFIG131_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x20C 0.--3. "PADCONFIG131_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x210 "CFG0_PADCONFIG132,"
bitfld.long 0x210 31. "PADCONFIG132_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x210 30. "PADCONFIG132_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x210 29. "PADCONFIG132_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x210 28. "PADCONFIG132_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x210 27. "PADCONFIG132_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x210 26. "PADCONFIG132_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x210 25. "PADCONFIG132_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x210 24. "PADCONFIG132_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x210 23. "PADCONFIG132_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x210 22. "PADCONFIG132_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x210 21. "PADCONFIG132_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x210 19.--20. "PADCONFIG132_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x210 18. "PADCONFIG132_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x210 17. "PADCONFIG132_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x210 16. "PADCONFIG132_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x210 15. "PADCONFIG132_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x210 14. "PADCONFIG132_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x210 11.--13. "PADCONFIG132_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x210 8. "PADCONFIG132_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x210 7. "PADCONFIG132_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x210 0.--3. "PADCONFIG132_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x214 "CFG0_PADCONFIG133,"
bitfld.long 0x214 31. "PADCONFIG133_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x214 30. "PADCONFIG133_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x214 29. "PADCONFIG133_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x214 28. "PADCONFIG133_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x214 27. "PADCONFIG133_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x214 26. "PADCONFIG133_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x214 25. "PADCONFIG133_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x214 24. "PADCONFIG133_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x214 23. "PADCONFIG133_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x214 22. "PADCONFIG133_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x214 21. "PADCONFIG133_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x214 19.--20. "PADCONFIG133_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x214 18. "PADCONFIG133_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x214 17. "PADCONFIG133_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x214 16. "PADCONFIG133_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x214 15. "PADCONFIG133_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x214 14. "PADCONFIG133_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x214 11.--13. "PADCONFIG133_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x214 8. "PADCONFIG133_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x214 7. "PADCONFIG133_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x214 0.--3. "PADCONFIG133_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x218 "CFG0_PADCONFIG134,"
bitfld.long 0x218 31. "PADCONFIG134_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x218 30. "PADCONFIG134_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x218 29. "PADCONFIG134_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x218 28. "PADCONFIG134_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x218 27. "PADCONFIG134_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x218 26. "PADCONFIG134_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x218 25. "PADCONFIG134_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x218 24. "PADCONFIG134_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x218 23. "PADCONFIG134_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x218 22. "PADCONFIG134_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x218 21. "PADCONFIG134_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x218 19.--20. "PADCONFIG134_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x218 18. "PADCONFIG134_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x218 17. "PADCONFIG134_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x218 16. "PADCONFIG134_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x218 15. "PADCONFIG134_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x218 14. "PADCONFIG134_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x218 11.--13. "PADCONFIG134_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x218 8. "PADCONFIG134_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x218 7. "PADCONFIG134_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x218 0.--3. "PADCONFIG134_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x21C "CFG0_PADCONFIG135,"
bitfld.long 0x21C 31. "PADCONFIG135_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x21C 30. "PADCONFIG135_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x21C 29. "PADCONFIG135_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x21C 28. "PADCONFIG135_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x21C 27. "PADCONFIG135_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x21C 26. "PADCONFIG135_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x21C 25. "PADCONFIG135_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x21C 24. "PADCONFIG135_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x21C 23. "PADCONFIG135_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x21C 22. "PADCONFIG135_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x21C 21. "PADCONFIG135_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x21C 19.--20. "PADCONFIG135_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x21C 18. "PADCONFIG135_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x21C 17. "PADCONFIG135_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x21C 16. "PADCONFIG135_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x21C 15. "PADCONFIG135_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x21C 14. "PADCONFIG135_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x21C 11.--13. "PADCONFIG135_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x21C 8. "PADCONFIG135_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x21C 7. "PADCONFIG135_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x21C 0.--3. "PADCONFIG135_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x220 "CFG0_PADCONFIG136,"
bitfld.long 0x220 31. "PADCONFIG136_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x220 30. "PADCONFIG136_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x220 29. "PADCONFIG136_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x220 28. "PADCONFIG136_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x220 27. "PADCONFIG136_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x220 26. "PADCONFIG136_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x220 25. "PADCONFIG136_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x220 24. "PADCONFIG136_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x220 23. "PADCONFIG136_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x220 22. "PADCONFIG136_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x220 21. "PADCONFIG136_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x220 19.--20. "PADCONFIG136_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x220 18. "PADCONFIG136_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x220 17. "PADCONFIG136_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x220 16. "PADCONFIG136_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x220 15. "PADCONFIG136_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x220 14. "PADCONFIG136_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x220 11.--13. "PADCONFIG136_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x220 8. "PADCONFIG136_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x220 7. "PADCONFIG136_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x220 0.--3. "PADCONFIG136_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x224 "CFG0_PADCONFIG137,"
bitfld.long 0x224 31. "PADCONFIG137_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x224 30. "PADCONFIG137_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x224 29. "PADCONFIG137_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x224 28. "PADCONFIG137_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x224 27. "PADCONFIG137_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x224 26. "PADCONFIG137_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x224 25. "PADCONFIG137_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x224 24. "PADCONFIG137_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x224 23. "PADCONFIG137_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x224 22. "PADCONFIG137_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x224 21. "PADCONFIG137_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x224 19.--20. "PADCONFIG137_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x224 18. "PADCONFIG137_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x224 17. "PADCONFIG137_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x224 16. "PADCONFIG137_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x224 15. "PADCONFIG137_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x224 14. "PADCONFIG137_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x224 11.--13. "PADCONFIG137_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x224 8. "PADCONFIG137_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x224 7. "PADCONFIG137_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x224 0.--3. "PADCONFIG137_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x228 "CFG0_PADCONFIG138,"
bitfld.long 0x228 31. "PADCONFIG138_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x228 30. "PADCONFIG138_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x228 29. "PADCONFIG138_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x228 28. "PADCONFIG138_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x228 27. "PADCONFIG138_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x228 26. "PADCONFIG138_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x228 25. "PADCONFIG138_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x228 24. "PADCONFIG138_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x228 23. "PADCONFIG138_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x228 22. "PADCONFIG138_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x228 21. "PADCONFIG138_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x228 19.--20. "PADCONFIG138_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x228 18. "PADCONFIG138_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x228 17. "PADCONFIG138_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x228 16. "PADCONFIG138_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x228 15. "PADCONFIG138_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x228 14. "PADCONFIG138_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x228 11.--13. "PADCONFIG138_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x228 8. "PADCONFIG138_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x228 7. "PADCONFIG138_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x228 0.--3. "PADCONFIG138_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x22C "CFG0_PADCONFIG139,"
bitfld.long 0x22C 31. "PADCONFIG139_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x22C 30. "PADCONFIG139_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x22C 29. "PADCONFIG139_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x22C 28. "PADCONFIG139_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x22C 27. "PADCONFIG139_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x22C 26. "PADCONFIG139_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x22C 25. "PADCONFIG139_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x22C 24. "PADCONFIG139_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x22C 23. "PADCONFIG139_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x22C 22. "PADCONFIG139_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x22C 21. "PADCONFIG139_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x22C 19.--20. "PADCONFIG139_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x22C 18. "PADCONFIG139_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x22C 17. "PADCONFIG139_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x22C 16. "PADCONFIG139_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x22C 15. "PADCONFIG139_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x22C 14. "PADCONFIG139_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x22C 11.--13. "PADCONFIG139_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x22C 8. "PADCONFIG139_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x22C 7. "PADCONFIG139_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x22C 0.--3. "PADCONFIG139_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x230 "CFG0_PADCONFIG140,"
bitfld.long 0x230 31. "PADCONFIG140_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x230 30. "PADCONFIG140_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x230 29. "PADCONFIG140_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x230 28. "PADCONFIG140_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x230 27. "PADCONFIG140_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x230 26. "PADCONFIG140_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x230 25. "PADCONFIG140_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x230 24. "PADCONFIG140_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x230 23. "PADCONFIG140_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x230 22. "PADCONFIG140_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x230 21. "PADCONFIG140_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x230 19.--20. "PADCONFIG140_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x230 18. "PADCONFIG140_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x230 17. "PADCONFIG140_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x230 16. "PADCONFIG140_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x230 15. "PADCONFIG140_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x230 14. "PADCONFIG140_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x230 11.--13. "PADCONFIG140_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x230 8. "PADCONFIG140_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x230 7. "PADCONFIG140_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x230 0.--3. "PADCONFIG140_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x234 "CFG0_PADCONFIG141,"
bitfld.long 0x234 31. "PADCONFIG141_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x234 30. "PADCONFIG141_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x234 29. "PADCONFIG141_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x234 28. "PADCONFIG141_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x234 27. "PADCONFIG141_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x234 26. "PADCONFIG141_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x234 25. "PADCONFIG141_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x234 24. "PADCONFIG141_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x234 23. "PADCONFIG141_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x234 22. "PADCONFIG141_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x234 21. "PADCONFIG141_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x234 19.--20. "PADCONFIG141_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x234 18. "PADCONFIG141_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x234 17. "PADCONFIG141_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x234 16. "PADCONFIG141_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x234 15. "PADCONFIG141_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x234 14. "PADCONFIG141_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x234 11.--13. "PADCONFIG141_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x234 8. "PADCONFIG141_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x234 7. "PADCONFIG141_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x234 0.--3. "PADCONFIG141_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x238 "CFG0_PADCONFIG142,"
bitfld.long 0x238 31. "PADCONFIG142_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x238 30. "PADCONFIG142_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x238 29. "PADCONFIG142_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x238 28. "PADCONFIG142_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x238 27. "PADCONFIG142_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x238 26. "PADCONFIG142_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x238 25. "PADCONFIG142_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x238 24. "PADCONFIG142_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x238 23. "PADCONFIG142_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x238 22. "PADCONFIG142_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x238 21. "PADCONFIG142_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x238 19.--20. "PADCONFIG142_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x238 18. "PADCONFIG142_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x238 17. "PADCONFIG142_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x238 16. "PADCONFIG142_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x238 15. "PADCONFIG142_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x238 14. "PADCONFIG142_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x238 11.--13. "PADCONFIG142_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x238 8. "PADCONFIG142_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x238 7. "PADCONFIG142_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x238 0.--3. "PADCONFIG142_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x23C "CFG0_PADCONFIG143,"
bitfld.long 0x23C 31. "PADCONFIG143_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x23C 30. "PADCONFIG143_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x23C 29. "PADCONFIG143_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x23C 28. "PADCONFIG143_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x23C 27. "PADCONFIG143_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x23C 26. "PADCONFIG143_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x23C 25. "PADCONFIG143_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x23C 24. "PADCONFIG143_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x23C 23. "PADCONFIG143_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x23C 22. "PADCONFIG143_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x23C 21. "PADCONFIG143_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x23C 19.--20. "PADCONFIG143_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x23C 18. "PADCONFIG143_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x23C 17. "PADCONFIG143_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x23C 16. "PADCONFIG143_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x23C 15. "PADCONFIG143_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x23C 14. "PADCONFIG143_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x23C 11.--13. "PADCONFIG143_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x23C 8. "PADCONFIG143_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x23C 7. "PADCONFIG143_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x23C 0.--3. "PADCONFIG143_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x240 "CFG0_PADCONFIG144,"
bitfld.long 0x240 31. "PADCONFIG144_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x240 30. "PADCONFIG144_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x240 29. "PADCONFIG144_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x240 28. "PADCONFIG144_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x240 27. "PADCONFIG144_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x240 26. "PADCONFIG144_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x240 25. "PADCONFIG144_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x240 24. "PADCONFIG144_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x240 23. "PADCONFIG144_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x240 22. "PADCONFIG144_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x240 21. "PADCONFIG144_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x240 19.--20. "PADCONFIG144_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x240 18. "PADCONFIG144_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x240 17. "PADCONFIG144_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x240 16. "PADCONFIG144_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x240 15. "PADCONFIG144_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x240 14. "PADCONFIG144_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x240 11.--13. "PADCONFIG144_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x240 8. "PADCONFIG144_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x240 7. "PADCONFIG144_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x240 0.--3. "PADCONFIG144_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x244 "CFG0_PADCONFIG145,"
bitfld.long 0x244 31. "PADCONFIG145_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x244 30. "PADCONFIG145_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x244 29. "PADCONFIG145_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x244 28. "PADCONFIG145_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x244 27. "PADCONFIG145_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x244 26. "PADCONFIG145_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x244 25. "PADCONFIG145_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x244 24. "PADCONFIG145_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x244 23. "PADCONFIG145_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x244 22. "PADCONFIG145_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x244 21. "PADCONFIG145_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x244 19.--20. "PADCONFIG145_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x244 18. "PADCONFIG145_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x244 17. "PADCONFIG145_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x244 16. "PADCONFIG145_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x244 15. "PADCONFIG145_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x244 14. "PADCONFIG145_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x244 11.--13. "PADCONFIG145_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x244 8. "PADCONFIG145_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x244 7. "PADCONFIG145_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x244 0.--3. "PADCONFIG145_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x248 "CFG0_PADCONFIG146,"
bitfld.long 0x248 31. "PADCONFIG146_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x248 30. "PADCONFIG146_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x248 29. "PADCONFIG146_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x248 28. "PADCONFIG146_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x248 27. "PADCONFIG146_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x248 26. "PADCONFIG146_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x248 25. "PADCONFIG146_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x248 24. "PADCONFIG146_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x248 23. "PADCONFIG146_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x248 22. "PADCONFIG146_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x248 21. "PADCONFIG146_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x248 19.--20. "PADCONFIG146_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x248 18. "PADCONFIG146_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x248 17. "PADCONFIG146_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x248 16. "PADCONFIG146_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x248 15. "PADCONFIG146_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x248 14. "PADCONFIG146_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x248 11.--13. "PADCONFIG146_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x248 8. "PADCONFIG146_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x248 7. "PADCONFIG146_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x248 0.--3. "PADCONFIG146_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x24C "CFG0_PADCONFIG147,"
bitfld.long 0x24C 31. "PADCONFIG147_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x24C 30. "PADCONFIG147_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x24C 29. "PADCONFIG147_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x24C 28. "PADCONFIG147_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x24C 27. "PADCONFIG147_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x24C 26. "PADCONFIG147_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x24C 25. "PADCONFIG147_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x24C 24. "PADCONFIG147_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x24C 23. "PADCONFIG147_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x24C 22. "PADCONFIG147_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x24C 21. "PADCONFIG147_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x24C 19.--20. "PADCONFIG147_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x24C 18. "PADCONFIG147_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x24C 17. "PADCONFIG147_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x24C 16. "PADCONFIG147_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x24C 15. "PADCONFIG147_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x24C 14. "PADCONFIG147_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x24C 11.--13. "PADCONFIG147_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x24C 8. "PADCONFIG147_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x24C 7. "PADCONFIG147_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x24C 0.--3. "PADCONFIG147_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x250 "CFG0_PADCONFIG148,"
bitfld.long 0x250 31. "PADCONFIG148_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x250 30. "PADCONFIG148_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x250 29. "PADCONFIG148_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x250 28. "PADCONFIG148_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x250 27. "PADCONFIG148_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x250 26. "PADCONFIG148_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x250 25. "PADCONFIG148_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x250 24. "PADCONFIG148_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x250 23. "PADCONFIG148_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x250 22. "PADCONFIG148_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x250 21. "PADCONFIG148_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x250 19.--20. "PADCONFIG148_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x250 18. "PADCONFIG148_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x250 17. "PADCONFIG148_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x250 16. "PADCONFIG148_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x250 15. "PADCONFIG148_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x250 14. "PADCONFIG148_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x250 11.--13. "PADCONFIG148_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x250 8. "PADCONFIG148_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x250 7. "PADCONFIG148_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x250 0.--3. "PADCONFIG148_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x254 "CFG0_PADCONFIG149,"
bitfld.long 0x254 31. "PADCONFIG149_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x254 30. "PADCONFIG149_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x254 29. "PADCONFIG149_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x254 28. "PADCONFIG149_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x254 27. "PADCONFIG149_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x254 26. "PADCONFIG149_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x254 25. "PADCONFIG149_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x254 24. "PADCONFIG149_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x254 23. "PADCONFIG149_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x254 22. "PADCONFIG149_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x254 21. "PADCONFIG149_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x254 19.--20. "PADCONFIG149_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x254 18. "PADCONFIG149_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x254 17. "PADCONFIG149_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x254 16. "PADCONFIG149_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x254 15. "PADCONFIG149_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x254 14. "PADCONFIG149_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x254 11.--13. "PADCONFIG149_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x254 8. "PADCONFIG149_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x254 7. "PADCONFIG149_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x254 0.--3. "PADCONFIG149_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x258 "CFG0_PADCONFIG150,"
bitfld.long 0x258 31. "PADCONFIG150_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x258 30. "PADCONFIG150_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x258 29. "PADCONFIG150_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x258 28. "PADCONFIG150_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x258 27. "PADCONFIG150_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x258 26. "PADCONFIG150_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x258 25. "PADCONFIG150_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x258 24. "PADCONFIG150_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x258 23. "PADCONFIG150_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x258 22. "PADCONFIG150_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x258 21. "PADCONFIG150_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x258 19.--20. "PADCONFIG150_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x258 18. "PADCONFIG150_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x258 17. "PADCONFIG150_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x258 16. "PADCONFIG150_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x258 15. "PADCONFIG150_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x258 14. "PADCONFIG150_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x258 11.--13. "PADCONFIG150_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x258 8. "PADCONFIG150_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x258 7. "PADCONFIG150_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x258 0.--3. "PADCONFIG150_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x25C "CFG0_PADCONFIG151,"
bitfld.long 0x25C 31. "PADCONFIG151_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x25C 30. "PADCONFIG151_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x25C 29. "PADCONFIG151_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x25C 28. "PADCONFIG151_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x25C 27. "PADCONFIG151_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x25C 26. "PADCONFIG151_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x25C 25. "PADCONFIG151_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x25C 24. "PADCONFIG151_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x25C 23. "PADCONFIG151_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x25C 22. "PADCONFIG151_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x25C 21. "PADCONFIG151_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x25C 19.--20. "PADCONFIG151_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x25C 18. "PADCONFIG151_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x25C 17. "PADCONFIG151_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x25C 16. "PADCONFIG151_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x25C 15. "PADCONFIG151_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x25C 14. "PADCONFIG151_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x25C 11.--13. "PADCONFIG151_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x25C 8. "PADCONFIG151_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x25C 7. "PADCONFIG151_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x25C 0.--3. "PADCONFIG151_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x260 "CFG0_PADCONFIG152,"
bitfld.long 0x260 31. "PADCONFIG152_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x260 30. "PADCONFIG152_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x260 29. "PADCONFIG152_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x260 28. "PADCONFIG152_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x260 27. "PADCONFIG152_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x260 26. "PADCONFIG152_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x260 25. "PADCONFIG152_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x260 24. "PADCONFIG152_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x260 23. "PADCONFIG152_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x260 22. "PADCONFIG152_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x260 21. "PADCONFIG152_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x260 19.--20. "PADCONFIG152_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x260 18. "PADCONFIG152_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x260 17. "PADCONFIG152_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x260 16. "PADCONFIG152_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x260 15. "PADCONFIG152_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x260 14. "PADCONFIG152_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x260 11.--13. "PADCONFIG152_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x260 8. "PADCONFIG152_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x260 7. "PADCONFIG152_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x260 0.--3. "PADCONFIG152_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x264 "CFG0_PADCONFIG153,"
bitfld.long 0x264 31. "PADCONFIG153_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x264 30. "PADCONFIG153_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x264 29. "PADCONFIG153_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x264 28. "PADCONFIG153_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x264 27. "PADCONFIG153_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x264 26. "PADCONFIG153_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x264 25. "PADCONFIG153_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x264 24. "PADCONFIG153_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x264 23. "PADCONFIG153_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x264 22. "PADCONFIG153_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x264 21. "PADCONFIG153_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x264 19.--20. "PADCONFIG153_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x264 18. "PADCONFIG153_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x264 17. "PADCONFIG153_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x264 16. "PADCONFIG153_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x264 15. "PADCONFIG153_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x264 14. "PADCONFIG153_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x264 11.--13. "PADCONFIG153_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x264 8. "PADCONFIG153_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x264 7. "PADCONFIG153_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x264 0.--3. "PADCONFIG153_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x268 "CFG0_PADCONFIG154,"
bitfld.long 0x268 31. "PADCONFIG154_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x268 30. "PADCONFIG154_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x268 29. "PADCONFIG154_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x268 28. "PADCONFIG154_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x268 27. "PADCONFIG154_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x268 26. "PADCONFIG154_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x268 25. "PADCONFIG154_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x268 24. "PADCONFIG154_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x268 23. "PADCONFIG154_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x268 22. "PADCONFIG154_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x268 21. "PADCONFIG154_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x268 19.--20. "PADCONFIG154_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x268 18. "PADCONFIG154_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x268 17. "PADCONFIG154_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x268 16. "PADCONFIG154_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x268 15. "PADCONFIG154_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x268 14. "PADCONFIG154_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x268 11.--13. "PADCONFIG154_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x268 8. "PADCONFIG154_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x268 7. "PADCONFIG154_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x268 0.--3. "PADCONFIG154_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x26C "CFG0_PADCONFIG155,"
bitfld.long 0x26C 31. "PADCONFIG155_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x26C 30. "PADCONFIG155_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x26C 29. "PADCONFIG155_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x26C 28. "PADCONFIG155_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x26C 27. "PADCONFIG155_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x26C 26. "PADCONFIG155_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x26C 25. "PADCONFIG155_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x26C 24. "PADCONFIG155_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x26C 23. "PADCONFIG155_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x26C 22. "PADCONFIG155_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x26C 21. "PADCONFIG155_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x26C 19.--20. "PADCONFIG155_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x26C 18. "PADCONFIG155_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x26C 17. "PADCONFIG155_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x26C 16. "PADCONFIG155_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x26C 15. "PADCONFIG155_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x26C 14. "PADCONFIG155_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x26C 11.--13. "PADCONFIG155_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x26C 8. "PADCONFIG155_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x26C 7. "PADCONFIG155_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x26C 0.--3. "PADCONFIG155_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x270 "CFG0_PADCONFIG156,"
bitfld.long 0x270 31. "PADCONFIG156_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x270 30. "PADCONFIG156_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x270 29. "PADCONFIG156_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x270 28. "PADCONFIG156_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x270 27. "PADCONFIG156_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x270 26. "PADCONFIG156_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x270 25. "PADCONFIG156_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x270 24. "PADCONFIG156_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x270 23. "PADCONFIG156_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x270 22. "PADCONFIG156_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x270 21. "PADCONFIG156_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x270 19.--20. "PADCONFIG156_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x270 18. "PADCONFIG156_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x270 17. "PADCONFIG156_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x270 16. "PADCONFIG156_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x270 15. "PADCONFIG156_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x270 14. "PADCONFIG156_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x270 11.--13. "PADCONFIG156_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x270 8. "PADCONFIG156_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x270 7. "PADCONFIG156_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x270 0.--3. "PADCONFIG156_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x274 "CFG0_PADCONFIG157,"
bitfld.long 0x274 31. "PADCONFIG157_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x274 30. "PADCONFIG157_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x274 29. "PADCONFIG157_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x274 28. "PADCONFIG157_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x274 27. "PADCONFIG157_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x274 26. "PADCONFIG157_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x274 25. "PADCONFIG157_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x274 24. "PADCONFIG157_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x274 23. "PADCONFIG157_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x274 22. "PADCONFIG157_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x274 21. "PADCONFIG157_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x274 19.--20. "PADCONFIG157_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x274 18. "PADCONFIG157_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x274 17. "PADCONFIG157_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x274 16. "PADCONFIG157_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x274 15. "PADCONFIG157_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x274 14. "PADCONFIG157_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x274 11.--13. "PADCONFIG157_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x274 8. "PADCONFIG157_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x274 7. "PADCONFIG157_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x274 0.--3. "PADCONFIG157_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x278 "CFG0_PADCONFIG158,"
bitfld.long 0x278 31. "PADCONFIG158_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x278 30. "PADCONFIG158_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x278 29. "PADCONFIG158_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x278 28. "PADCONFIG158_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x278 27. "PADCONFIG158_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x278 26. "PADCONFIG158_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x278 25. "PADCONFIG158_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x278 24. "PADCONFIG158_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x278 23. "PADCONFIG158_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x278 22. "PADCONFIG158_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x278 21. "PADCONFIG158_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x278 19.--20. "PADCONFIG158_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x278 18. "PADCONFIG158_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x278 17. "PADCONFIG158_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x278 16. "PADCONFIG158_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x278 15. "PADCONFIG158_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x278 14. "PADCONFIG158_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x278 11.--13. "PADCONFIG158_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x278 8. "PADCONFIG158_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x278 7. "PADCONFIG158_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x278 0.--3. "PADCONFIG158_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x27C "CFG0_PADCONFIG159,"
bitfld.long 0x27C 31. "PADCONFIG159_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x27C 30. "PADCONFIG159_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x27C 29. "PADCONFIG159_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x27C 28. "PADCONFIG159_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x27C 27. "PADCONFIG159_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x27C 26. "PADCONFIG159_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x27C 25. "PADCONFIG159_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x27C 24. "PADCONFIG159_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x27C 23. "PADCONFIG159_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x27C 22. "PADCONFIG159_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x27C 21. "PADCONFIG159_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x27C 19.--20. "PADCONFIG159_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x27C 18. "PADCONFIG159_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x27C 17. "PADCONFIG159_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x27C 16. "PADCONFIG159_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x27C 15. "PADCONFIG159_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x27C 14. "PADCONFIG159_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x27C 11.--13. "PADCONFIG159_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x27C 8. "PADCONFIG159_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x27C 7. "PADCONFIG159_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x27C 0.--3. "PADCONFIG159_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x280 "CFG0_PADCONFIG160,"
bitfld.long 0x280 31. "PADCONFIG160_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x280 30. "PADCONFIG160_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x280 29. "PADCONFIG160_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x280 28. "PADCONFIG160_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x280 27. "PADCONFIG160_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x280 26. "PADCONFIG160_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x280 25. "PADCONFIG160_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x280 24. "PADCONFIG160_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x280 23. "PADCONFIG160_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x280 22. "PADCONFIG160_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x280 21. "PADCONFIG160_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x280 19.--20. "PADCONFIG160_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x280 18. "PADCONFIG160_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x280 17. "PADCONFIG160_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x280 16. "PADCONFIG160_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x280 15. "PADCONFIG160_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x280 14. "PADCONFIG160_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x280 11.--13. "PADCONFIG160_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x280 8. "PADCONFIG160_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x280 7. "PADCONFIG160_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x280 0.--3. "PADCONFIG160_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x284 "CFG0_PADCONFIG161,"
bitfld.long 0x284 31. "PADCONFIG161_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x284 30. "PADCONFIG161_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x284 29. "PADCONFIG161_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x284 28. "PADCONFIG161_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x284 27. "PADCONFIG161_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x284 26. "PADCONFIG161_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x284 25. "PADCONFIG161_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x284 24. "PADCONFIG161_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x284 23. "PADCONFIG161_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x284 22. "PADCONFIG161_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x284 21. "PADCONFIG161_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x284 19.--20. "PADCONFIG161_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x284 18. "PADCONFIG161_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x284 17. "PADCONFIG161_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x284 16. "PADCONFIG161_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x284 15. "PADCONFIG161_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x284 14. "PADCONFIG161_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x284 11.--13. "PADCONFIG161_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x284 8. "PADCONFIG161_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x284 7. "PADCONFIG161_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x284 0.--3. "PADCONFIG161_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x288 "CFG0_PADCONFIG162,"
bitfld.long 0x288 31. "PADCONFIG162_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x288 30. "PADCONFIG162_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x288 29. "PADCONFIG162_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x288 28. "PADCONFIG162_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x288 27. "PADCONFIG162_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x288 26. "PADCONFIG162_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x288 25. "PADCONFIG162_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x288 24. "PADCONFIG162_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x288 23. "PADCONFIG162_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x288 22. "PADCONFIG162_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x288 21. "PADCONFIG162_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x288 19.--20. "PADCONFIG162_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x288 18. "PADCONFIG162_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x288 17. "PADCONFIG162_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x288 16. "PADCONFIG162_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x288 15. "PADCONFIG162_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x288 14. "PADCONFIG162_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x288 11.--13. "PADCONFIG162_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x288 8. "PADCONFIG162_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x288 7. "PADCONFIG162_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x288 0.--3. "PADCONFIG162_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x28C "CFG0_PADCONFIG163,"
bitfld.long 0x28C 31. "PADCONFIG163_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x28C 30. "PADCONFIG163_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x28C 29. "PADCONFIG163_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x28C 28. "PADCONFIG163_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x28C 27. "PADCONFIG163_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x28C 26. "PADCONFIG163_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x28C 25. "PADCONFIG163_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x28C 24. "PADCONFIG163_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x28C 23. "PADCONFIG163_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x28C 22. "PADCONFIG163_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x28C 21. "PADCONFIG163_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x28C 19.--20. "PADCONFIG163_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x28C 18. "PADCONFIG163_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x28C 17. "PADCONFIG163_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x28C 16. "PADCONFIG163_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x28C 15. "PADCONFIG163_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x28C 14. "PADCONFIG163_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x28C 11.--13. "PADCONFIG163_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28C 8. "PADCONFIG163_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x28C 7. "PADCONFIG163_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x28C 0.--3. "PADCONFIG163_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x290 "CFG0_PADCONFIG164,"
bitfld.long 0x290 31. "PADCONFIG164_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x290 30. "PADCONFIG164_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x290 29. "PADCONFIG164_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x290 28. "PADCONFIG164_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x290 27. "PADCONFIG164_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x290 26. "PADCONFIG164_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x290 25. "PADCONFIG164_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x290 24. "PADCONFIG164_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x290 23. "PADCONFIG164_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x290 22. "PADCONFIG164_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x290 21. "PADCONFIG164_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x290 19.--20. "PADCONFIG164_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x290 18. "PADCONFIG164_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x290 17. "PADCONFIG164_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x290 16. "PADCONFIG164_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x290 15. "PADCONFIG164_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x290 14. "PADCONFIG164_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x290 11.--13. "PADCONFIG164_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x290 8. "PADCONFIG164_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x290 7. "PADCONFIG164_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x290 0.--3. "PADCONFIG164_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x294 "CFG0_PADCONFIG165,"
bitfld.long 0x294 31. "PADCONFIG165_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x294 30. "PADCONFIG165_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x294 29. "PADCONFIG165_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x294 28. "PADCONFIG165_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x294 27. "PADCONFIG165_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x294 26. "PADCONFIG165_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x294 25. "PADCONFIG165_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x294 24. "PADCONFIG165_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x294 23. "PADCONFIG165_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x294 22. "PADCONFIG165_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x294 21. "PADCONFIG165_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x294 19.--20. "PADCONFIG165_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x294 18. "PADCONFIG165_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x294 17. "PADCONFIG165_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x294 16. "PADCONFIG165_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x294 15. "PADCONFIG165_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x294 14. "PADCONFIG165_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x294 11.--13. "PADCONFIG165_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x294 8. "PADCONFIG165_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x294 7. "PADCONFIG165_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x294 0.--3. "PADCONFIG165_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x298 "CFG0_PADCONFIG166,"
bitfld.long 0x298 31. "PADCONFIG166_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x298 30. "PADCONFIG166_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x298 29. "PADCONFIG166_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x298 28. "PADCONFIG166_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x298 27. "PADCONFIG166_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x298 26. "PADCONFIG166_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x298 25. "PADCONFIG166_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x298 24. "PADCONFIG166_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x298 23. "PADCONFIG166_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x298 22. "PADCONFIG166_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x298 21. "PADCONFIG166_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x298 19.--20. "PADCONFIG166_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x298 18. "PADCONFIG166_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x298 17. "PADCONFIG166_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x298 16. "PADCONFIG166_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x298 15. "PADCONFIG166_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x298 14. "PADCONFIG166_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x298 11.--13. "PADCONFIG166_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x298 8. "PADCONFIG166_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x298 7. "PADCONFIG166_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x298 0.--3. "PADCONFIG166_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x29C "CFG0_PADCONFIG167,"
bitfld.long 0x29C 31. "PADCONFIG167_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x29C 30. "PADCONFIG167_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x29C 29. "PADCONFIG167_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x29C 28. "PADCONFIG167_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x29C 27. "PADCONFIG167_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x29C 26. "PADCONFIG167_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x29C 25. "PADCONFIG167_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x29C 24. "PADCONFIG167_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x29C 23. "PADCONFIG167_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x29C 22. "PADCONFIG167_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x29C 21. "PADCONFIG167_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x29C 19.--20. "PADCONFIG167_DRV_STR,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x29C 18. "PADCONFIG167_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x29C 17. "PADCONFIG167_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x29C 16. "PADCONFIG167_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x29C 15. "PADCONFIG167_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x29C 14. "PADCONFIG167_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x29C 11.--13. "PADCONFIG167_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x29C 8. "PADCONFIG167_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x29C 7. "PADCONFIG167_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x29C 0.--3. "PADCONFIG167_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2A0 "CFG0_PADCONFIG168,"
bitfld.long 0x2A0 31. "PADCONFIG168_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x2A0 30. "PADCONFIG168_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x2A0 29. "PADCONFIG168_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x2A0 28. "PADCONFIG168_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x2A0 27. "PADCONFIG168_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x2A0 26. "PADCONFIG168_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2A0 25. "PADCONFIG168_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x2A0 24. "PADCONFIG168_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x2A0 23. "PADCONFIG168_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x2A0 22. "PADCONFIG168_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x2A0 21. "PADCONFIG168_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x2A0 19.--20. "PADCONFIG168_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x2A0 18. "PADCONFIG168_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x2A0 17. "PADCONFIG168_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x2A0 16. "PADCONFIG168_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x2A0 15. "PADCONFIG168_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x2A0 14. "PADCONFIG168_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x2A0 11.--13. "PADCONFIG168_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2A0 8. "PADCONFIG168_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x2A0 7. "PADCONFIG168_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x2A0 0.--3. "PADCONFIG168_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2A4 "CFG0_PADCONFIG169,"
bitfld.long 0x2A4 31. "PADCONFIG169_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x2A4 30. "PADCONFIG169_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x2A4 29. "PADCONFIG169_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x2A4 28. "PADCONFIG169_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x2A4 27. "PADCONFIG169_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x2A4 26. "PADCONFIG169_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2A4 25. "PADCONFIG169_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x2A4 24. "PADCONFIG169_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x2A4 23. "PADCONFIG169_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x2A4 22. "PADCONFIG169_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x2A4 21. "PADCONFIG169_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x2A4 19.--20. "PADCONFIG169_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x2A4 18. "PADCONFIG169_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x2A4 17. "PADCONFIG169_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x2A4 16. "PADCONFIG169_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x2A4 15. "PADCONFIG169_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x2A4 14. "PADCONFIG169_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x2A4 11.--13. "PADCONFIG169_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2A4 8. "PADCONFIG169_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x2A4 7. "PADCONFIG169_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x2A4 0.--3. "PADCONFIG169_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2A8 "CFG0_PADCONFIG170,"
bitfld.long 0x2A8 31. "PADCONFIG170_LOCK,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x2A8 30. "PADCONFIG170_WKUP_EVT,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x2A8 29. "PADCONFIG170_WKUP_EN,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x2A8 28. "PADCONFIG170_DS_PULLTYPE_SEL,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x2A8 27. "PADCONFIG170_DS_PULLUD_EN,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x2A8 26. "PADCONFIG170_DSOUT_VAL,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2A8 25. "PADCONFIG170_DSOUT_DIS,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x2A8 24. "PADCONFIG170_DS_EN,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x2A8 23. "PADCONFIG170_ISO_BYP,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x2A8 22. "PADCONFIG170_ISO_OVR,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x2A8 21. "PADCONFIG170_TX_DIS,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x2A8 19.--20. "PADCONFIG170_DRV_STR,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x2A8 18. "PADCONFIG170_RXACTIVE,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x2A8 17. "PADCONFIG170_PULLTYPESEL,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x2A8 16. "PADCONFIG170_PULLUDEN,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x2A8 15. "PADCONFIG170_FORCE_DS_EN,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x2A8 14. "PADCONFIG170_ST_EN,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x2A8 11.--13. "PADCONFIG170_DEBOUNCE_SEL,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2A8 8. "PADCONFIG170_WK_LVL_POL,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x2A8 7. "PADCONFIG170_WK_LVL_EN,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x2A8 0.--3. "PADCONFIG170_MUXMODE,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
group.long 0x5008++0x07
line.long 0x00 "CFG0_LOCK1_KICK0,"
line.long 0x04 "CFG0_LOCK1_KICK1,"
rgroup.long 0x5100++0x17
line.long 0x00 "CFG0_CLAIMREG_P1_R0_READONLY,"
line.long 0x04 "CFG0_CLAIMREG_P1_R1_READONLY,"
line.long 0x08 "CFG0_CLAIMREG_P1_R2_READONLY,"
line.long 0x0C "CFG0_CLAIMREG_P1_R3_READONLY,"
line.long 0x10 "CFG0_CLAIMREG_P1_R4_READONLY,"
line.long 0x14 "CFG0_CLAIMREG_P1_R5_READONLY,"
group.long 0x6000++0x2AB
line.long 0x00 "CFG0_PADCONFIG0_PROXY,"
bitfld.long 0x00 31. "PADCONFIG0_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x00 30. "PADCONFIG0_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x00 29. "PADCONFIG0_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x00 28. "PADCONFIG0_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x00 27. "PADCONFIG0_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x00 26. "PADCONFIG0_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x00 25. "PADCONFIG0_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x00 24. "PADCONFIG0_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x00 23. "PADCONFIG0_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x00 22. "PADCONFIG0_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x00 21. "PADCONFIG0_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x00 19.--20. "PADCONFIG0_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x00 18. "PADCONFIG0_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x00 17. "PADCONFIG0_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x00 16. "PADCONFIG0_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x00 15. "PADCONFIG0_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x00 14. "PADCONFIG0_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x00 11.--13. "PADCONFIG0_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8. "PADCONFIG0_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x00 7. "PADCONFIG0_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0.--3. "PADCONFIG0_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x04 "CFG0_PADCONFIG1_PROXY,"
bitfld.long 0x04 31. "PADCONFIG1_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x04 30. "PADCONFIG1_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x04 29. "PADCONFIG1_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x04 28. "PADCONFIG1_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x04 27. "PADCONFIG1_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x04 26. "PADCONFIG1_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x04 25. "PADCONFIG1_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x04 24. "PADCONFIG1_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x04 23. "PADCONFIG1_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x04 22. "PADCONFIG1_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x04 21. "PADCONFIG1_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x04 19.--20. "PADCONFIG1_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x04 18. "PADCONFIG1_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x04 17. "PADCONFIG1_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x04 16. "PADCONFIG1_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x04 15. "PADCONFIG1_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x04 14. "PADCONFIG1_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x04 11.--13. "PADCONFIG1_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 8. "PADCONFIG1_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x04 7. "PADCONFIG1_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x04 0.--3. "PADCONFIG1_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x08 "CFG0_PADCONFIG2_PROXY,"
bitfld.long 0x08 31. "PADCONFIG2_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x08 30. "PADCONFIG2_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x08 29. "PADCONFIG2_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x08 28. "PADCONFIG2_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x08 27. "PADCONFIG2_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x08 26. "PADCONFIG2_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x08 25. "PADCONFIG2_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x08 24. "PADCONFIG2_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x08 23. "PADCONFIG2_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x08 22. "PADCONFIG2_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x08 21. "PADCONFIG2_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x08 19.--20. "PADCONFIG2_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x08 18. "PADCONFIG2_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x08 17. "PADCONFIG2_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x08 16. "PADCONFIG2_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x08 15. "PADCONFIG2_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x08 14. "PADCONFIG2_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x08 11.--13. "PADCONFIG2_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 8. "PADCONFIG2_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x08 7. "PADCONFIG2_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x08 0.--3. "PADCONFIG2_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x0C "CFG0_PADCONFIG3_PROXY,"
bitfld.long 0x0C 31. "PADCONFIG3_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x0C 30. "PADCONFIG3_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x0C 29. "PADCONFIG3_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x0C 28. "PADCONFIG3_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x0C 27. "PADCONFIG3_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x0C 26. "PADCONFIG3_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x0C 25. "PADCONFIG3_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x0C 24. "PADCONFIG3_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x0C 23. "PADCONFIG3_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x0C 22. "PADCONFIG3_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x0C 21. "PADCONFIG3_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x0C 19.--20. "PADCONFIG3_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x0C 18. "PADCONFIG3_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x0C 17. "PADCONFIG3_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x0C 16. "PADCONFIG3_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x0C 15. "PADCONFIG3_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x0C 14. "PADCONFIG3_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x0C 11.--13. "PADCONFIG3_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 8. "PADCONFIG3_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x0C 7. "PADCONFIG3_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x0C 0.--3. "PADCONFIG3_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x10 "CFG0_PADCONFIG4_PROXY,"
bitfld.long 0x10 31. "PADCONFIG4_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x10 30. "PADCONFIG4_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x10 29. "PADCONFIG4_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x10 28. "PADCONFIG4_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x10 27. "PADCONFIG4_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x10 26. "PADCONFIG4_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x10 25. "PADCONFIG4_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x10 24. "PADCONFIG4_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x10 23. "PADCONFIG4_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x10 22. "PADCONFIG4_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x10 21. "PADCONFIG4_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x10 19.--20. "PADCONFIG4_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x10 18. "PADCONFIG4_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x10 17. "PADCONFIG4_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x10 16. "PADCONFIG4_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x10 15. "PADCONFIG4_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x10 14. "PADCONFIG4_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x10 11.--13. "PADCONFIG4_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 8. "PADCONFIG4_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x10 7. "PADCONFIG4_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x10 0.--3. "PADCONFIG4_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x14 "CFG0_PADCONFIG5_PROXY,"
bitfld.long 0x14 31. "PADCONFIG5_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x14 30. "PADCONFIG5_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x14 29. "PADCONFIG5_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x14 28. "PADCONFIG5_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x14 27. "PADCONFIG5_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x14 26. "PADCONFIG5_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x14 25. "PADCONFIG5_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x14 24. "PADCONFIG5_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x14 23. "PADCONFIG5_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x14 22. "PADCONFIG5_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x14 21. "PADCONFIG5_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x14 19.--20. "PADCONFIG5_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x14 18. "PADCONFIG5_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x14 17. "PADCONFIG5_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x14 16. "PADCONFIG5_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x14 15. "PADCONFIG5_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x14 14. "PADCONFIG5_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x14 11.--13. "PADCONFIG5_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 8. "PADCONFIG5_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x14 7. "PADCONFIG5_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x14 0.--3. "PADCONFIG5_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x18 "CFG0_PADCONFIG6_PROXY,"
bitfld.long 0x18 31. "PADCONFIG6_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x18 30. "PADCONFIG6_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x18 29. "PADCONFIG6_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x18 28. "PADCONFIG6_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x18 27. "PADCONFIG6_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x18 26. "PADCONFIG6_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x18 25. "PADCONFIG6_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x18 24. "PADCONFIG6_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x18 23. "PADCONFIG6_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x18 22. "PADCONFIG6_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x18 21. "PADCONFIG6_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x18 19.--20. "PADCONFIG6_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x18 18. "PADCONFIG6_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x18 17. "PADCONFIG6_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x18 16. "PADCONFIG6_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x18 15. "PADCONFIG6_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x18 14. "PADCONFIG6_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x18 11.--13. "PADCONFIG6_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 8. "PADCONFIG6_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x18 7. "PADCONFIG6_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x18 0.--3. "PADCONFIG6_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C "CFG0_PADCONFIG7_PROXY,"
bitfld.long 0x1C 31. "PADCONFIG7_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x1C 30. "PADCONFIG7_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x1C 29. "PADCONFIG7_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x1C 28. "PADCONFIG7_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x1C 27. "PADCONFIG7_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x1C 26. "PADCONFIG7_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x1C 25. "PADCONFIG7_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x1C 24. "PADCONFIG7_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x1C 23. "PADCONFIG7_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x1C 22. "PADCONFIG7_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x1C 21. "PADCONFIG7_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x1C 19.--20. "PADCONFIG7_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x1C 18. "PADCONFIG7_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x1C 17. "PADCONFIG7_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x1C 16. "PADCONFIG7_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x1C 15. "PADCONFIG7_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x1C 14. "PADCONFIG7_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x1C 11.--13. "PADCONFIG7_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1C 8. "PADCONFIG7_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x1C 7. "PADCONFIG7_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x1C 0.--3. "PADCONFIG7_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x20 "CFG0_PADCONFIG8_PROXY,"
bitfld.long 0x20 31. "PADCONFIG8_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x20 30. "PADCONFIG8_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x20 29. "PADCONFIG8_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x20 28. "PADCONFIG8_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x20 27. "PADCONFIG8_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x20 26. "PADCONFIG8_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x20 25. "PADCONFIG8_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x20 24. "PADCONFIG8_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x20 23. "PADCONFIG8_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x20 22. "PADCONFIG8_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x20 21. "PADCONFIG8_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x20 19.--20. "PADCONFIG8_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x20 18. "PADCONFIG8_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x20 17. "PADCONFIG8_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x20 16. "PADCONFIG8_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x20 15. "PADCONFIG8_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x20 14. "PADCONFIG8_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x20 11.--13. "PADCONFIG8_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x20 8. "PADCONFIG8_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x20 7. "PADCONFIG8_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x20 0.--3. "PADCONFIG8_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x24 "CFG0_PADCONFIG9_PROXY,"
bitfld.long 0x24 31. "PADCONFIG9_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x24 30. "PADCONFIG9_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x24 29. "PADCONFIG9_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x24 28. "PADCONFIG9_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x24 27. "PADCONFIG9_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x24 26. "PADCONFIG9_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x24 25. "PADCONFIG9_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x24 24. "PADCONFIG9_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x24 23. "PADCONFIG9_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x24 22. "PADCONFIG9_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x24 21. "PADCONFIG9_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x24 19.--20. "PADCONFIG9_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x24 18. "PADCONFIG9_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x24 17. "PADCONFIG9_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x24 16. "PADCONFIG9_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x24 15. "PADCONFIG9_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x24 14. "PADCONFIG9_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x24 11.--13. "PADCONFIG9_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 8. "PADCONFIG9_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x24 7. "PADCONFIG9_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x24 0.--3. "PADCONFIG9_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x28 "CFG0_PADCONFIG10_PROXY,"
bitfld.long 0x28 31. "PADCONFIG10_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x28 30. "PADCONFIG10_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x28 29. "PADCONFIG10_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x28 28. "PADCONFIG10_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x28 27. "PADCONFIG10_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x28 26. "PADCONFIG10_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x28 25. "PADCONFIG10_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x28 24. "PADCONFIG10_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x28 23. "PADCONFIG10_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x28 22. "PADCONFIG10_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x28 21. "PADCONFIG10_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x28 19.--20. "PADCONFIG10_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x28 18. "PADCONFIG10_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x28 17. "PADCONFIG10_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x28 16. "PADCONFIG10_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x28 15. "PADCONFIG10_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x28 14. "PADCONFIG10_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x28 11.--13. "PADCONFIG10_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x28 8. "PADCONFIG10_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x28 7. "PADCONFIG10_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x28 0.--3. "PADCONFIG10_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2C "CFG0_PADCONFIG11_PROXY,"
bitfld.long 0x2C 31. "PADCONFIG11_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x2C 30. "PADCONFIG11_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x2C 29. "PADCONFIG11_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x2C 28. "PADCONFIG11_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x2C 27. "PADCONFIG11_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x2C 26. "PADCONFIG11_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x2C 25. "PADCONFIG11_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x2C 24. "PADCONFIG11_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x2C 23. "PADCONFIG11_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x2C 22. "PADCONFIG11_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x2C 21. "PADCONFIG11_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x2C 19.--20. "PADCONFIG11_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x2C 18. "PADCONFIG11_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x2C 17. "PADCONFIG11_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x2C 16. "PADCONFIG11_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x2C 15. "PADCONFIG11_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x2C 14. "PADCONFIG11_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x2C 11.--13. "PADCONFIG11_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x2C 8. "PADCONFIG11_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x2C 7. "PADCONFIG11_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x2C 0.--3. "PADCONFIG11_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x30 "CFG0_PADCONFIG12_PROXY,"
bitfld.long 0x30 31. "PADCONFIG12_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x30 30. "PADCONFIG12_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x30 29. "PADCONFIG12_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x30 28. "PADCONFIG12_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x30 27. "PADCONFIG12_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x30 26. "PADCONFIG12_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x30 25. "PADCONFIG12_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x30 24. "PADCONFIG12_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x30 23. "PADCONFIG12_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x30 22. "PADCONFIG12_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x30 21. "PADCONFIG12_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x30 19.--20. "PADCONFIG12_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x30 18. "PADCONFIG12_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x30 17. "PADCONFIG12_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x30 16. "PADCONFIG12_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x30 15. "PADCONFIG12_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x30 14. "PADCONFIG12_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x30 11.--13. "PADCONFIG12_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x30 8. "PADCONFIG12_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x30 7. "PADCONFIG12_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x30 0.--3. "PADCONFIG12_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x34 "CFG0_PADCONFIG13_PROXY,"
bitfld.long 0x34 31. "PADCONFIG13_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x34 30. "PADCONFIG13_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x34 29. "PADCONFIG13_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x34 28. "PADCONFIG13_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x34 27. "PADCONFIG13_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x34 26. "PADCONFIG13_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x34 25. "PADCONFIG13_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x34 24. "PADCONFIG13_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x34 23. "PADCONFIG13_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x34 22. "PADCONFIG13_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x34 21. "PADCONFIG13_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x34 19.--20. "PADCONFIG13_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x34 18. "PADCONFIG13_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x34 17. "PADCONFIG13_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x34 16. "PADCONFIG13_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x34 15. "PADCONFIG13_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x34 14. "PADCONFIG13_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x34 11.--13. "PADCONFIG13_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 8. "PADCONFIG13_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x34 7. "PADCONFIG13_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x34 0.--3. "PADCONFIG13_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x38 "CFG0_PADCONFIG14_PROXY,"
bitfld.long 0x38 31. "PADCONFIG14_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x38 30. "PADCONFIG14_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x38 29. "PADCONFIG14_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x38 28. "PADCONFIG14_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x38 27. "PADCONFIG14_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x38 26. "PADCONFIG14_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x38 25. "PADCONFIG14_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x38 24. "PADCONFIG14_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x38 23. "PADCONFIG14_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x38 22. "PADCONFIG14_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x38 21. "PADCONFIG14_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x38 19.--20. "PADCONFIG14_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x38 18. "PADCONFIG14_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x38 17. "PADCONFIG14_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x38 16. "PADCONFIG14_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x38 15. "PADCONFIG14_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x38 14. "PADCONFIG14_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x38 11.--13. "PADCONFIG14_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 8. "PADCONFIG14_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x38 7. "PADCONFIG14_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x38 0.--3. "PADCONFIG14_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x3C "CFG0_PADCONFIG15_PROXY,"
bitfld.long 0x3C 31. "PADCONFIG15_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x3C 30. "PADCONFIG15_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x3C 29. "PADCONFIG15_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x3C 28. "PADCONFIG15_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x3C 27. "PADCONFIG15_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x3C 26. "PADCONFIG15_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x3C 25. "PADCONFIG15_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x3C 24. "PADCONFIG15_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x3C 23. "PADCONFIG15_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x3C 22. "PADCONFIG15_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x3C 21. "PADCONFIG15_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x3C 19.--20. "PADCONFIG15_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x3C 18. "PADCONFIG15_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x3C 17. "PADCONFIG15_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x3C 16. "PADCONFIG15_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x3C 15. "PADCONFIG15_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x3C 14. "PADCONFIG15_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x3C 11.--13. "PADCONFIG15_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x3C 8. "PADCONFIG15_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x3C 7. "PADCONFIG15_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x3C 0.--3. "PADCONFIG15_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x40 "CFG0_PADCONFIG16_PROXY,"
bitfld.long 0x40 31. "PADCONFIG16_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x40 30. "PADCONFIG16_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x40 29. "PADCONFIG16_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x40 28. "PADCONFIG16_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x40 27. "PADCONFIG16_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x40 26. "PADCONFIG16_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x40 25. "PADCONFIG16_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x40 24. "PADCONFIG16_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x40 23. "PADCONFIG16_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x40 22. "PADCONFIG16_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x40 21. "PADCONFIG16_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x40 19.--20. "PADCONFIG16_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x40 18. "PADCONFIG16_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x40 17. "PADCONFIG16_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x40 16. "PADCONFIG16_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x40 15. "PADCONFIG16_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x40 14. "PADCONFIG16_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x40 11.--13. "PADCONFIG16_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x40 8. "PADCONFIG16_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x40 7. "PADCONFIG16_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x40 0.--3. "PADCONFIG16_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x44 "CFG0_PADCONFIG17_PROXY,"
bitfld.long 0x44 31. "PADCONFIG17_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x44 30. "PADCONFIG17_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x44 29. "PADCONFIG17_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x44 28. "PADCONFIG17_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x44 27. "PADCONFIG17_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x44 26. "PADCONFIG17_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x44 25. "PADCONFIG17_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x44 24. "PADCONFIG17_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x44 23. "PADCONFIG17_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x44 22. "PADCONFIG17_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x44 21. "PADCONFIG17_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x44 19.--20. "PADCONFIG17_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x44 18. "PADCONFIG17_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x44 17. "PADCONFIG17_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x44 16. "PADCONFIG17_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x44 15. "PADCONFIG17_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x44 14. "PADCONFIG17_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x44 11.--13. "PADCONFIG17_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x44 8. "PADCONFIG17_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x44 7. "PADCONFIG17_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x44 0.--3. "PADCONFIG17_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x48 "CFG0_PADCONFIG18_PROXY,"
bitfld.long 0x48 31. "PADCONFIG18_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x48 30. "PADCONFIG18_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x48 29. "PADCONFIG18_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x48 28. "PADCONFIG18_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x48 27. "PADCONFIG18_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x48 26. "PADCONFIG18_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x48 25. "PADCONFIG18_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x48 24. "PADCONFIG18_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x48 23. "PADCONFIG18_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x48 22. "PADCONFIG18_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x48 21. "PADCONFIG18_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x48 19.--20. "PADCONFIG18_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x48 18. "PADCONFIG18_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x48 17. "PADCONFIG18_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x48 16. "PADCONFIG18_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x48 15. "PADCONFIG18_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x48 14. "PADCONFIG18_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x48 11.--13. "PADCONFIG18_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x48 8. "PADCONFIG18_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x48 7. "PADCONFIG18_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x48 0.--3. "PADCONFIG18_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x4C "CFG0_PADCONFIG19_PROXY,"
bitfld.long 0x4C 31. "PADCONFIG19_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x4C 30. "PADCONFIG19_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x4C 29. "PADCONFIG19_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x4C 28. "PADCONFIG19_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x4C 27. "PADCONFIG19_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x4C 26. "PADCONFIG19_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x4C 25. "PADCONFIG19_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x4C 24. "PADCONFIG19_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x4C 23. "PADCONFIG19_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x4C 22. "PADCONFIG19_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x4C 21. "PADCONFIG19_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x4C 19.--20. "PADCONFIG19_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x4C 18. "PADCONFIG19_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x4C 17. "PADCONFIG19_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x4C 16. "PADCONFIG19_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x4C 15. "PADCONFIG19_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x4C 14. "PADCONFIG19_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x4C 11.--13. "PADCONFIG19_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4C 8. "PADCONFIG19_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x4C 7. "PADCONFIG19_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x4C 0.--3. "PADCONFIG19_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x50 "CFG0_PADCONFIG20_PROXY,"
bitfld.long 0x50 31. "PADCONFIG20_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x50 30. "PADCONFIG20_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x50 29. "PADCONFIG20_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x50 28. "PADCONFIG20_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x50 27. "PADCONFIG20_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x50 26. "PADCONFIG20_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x50 25. "PADCONFIG20_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x50 24. "PADCONFIG20_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x50 23. "PADCONFIG20_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x50 22. "PADCONFIG20_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x50 21. "PADCONFIG20_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x50 19.--20. "PADCONFIG20_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x50 18. "PADCONFIG20_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x50 17. "PADCONFIG20_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x50 16. "PADCONFIG20_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x50 15. "PADCONFIG20_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x50 14. "PADCONFIG20_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x50 11.--13. "PADCONFIG20_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x50 8. "PADCONFIG20_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x50 7. "PADCONFIG20_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x50 0.--3. "PADCONFIG20_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x54 "CFG0_PADCONFIG21_PROXY,"
bitfld.long 0x54 31. "PADCONFIG21_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x54 30. "PADCONFIG21_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x54 29. "PADCONFIG21_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x54 28. "PADCONFIG21_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x54 27. "PADCONFIG21_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x54 26. "PADCONFIG21_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x54 25. "PADCONFIG21_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x54 24. "PADCONFIG21_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x54 23. "PADCONFIG21_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x54 22. "PADCONFIG21_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x54 21. "PADCONFIG21_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x54 19.--20. "PADCONFIG21_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x54 18. "PADCONFIG21_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x54 17. "PADCONFIG21_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x54 16. "PADCONFIG21_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x54 15. "PADCONFIG21_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x54 14. "PADCONFIG21_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x54 11.--13. "PADCONFIG21_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x54 8. "PADCONFIG21_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x54 7. "PADCONFIG21_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x54 0.--3. "PADCONFIG21_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x58 "CFG0_PADCONFIG22_PROXY,"
bitfld.long 0x58 31. "PADCONFIG22_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x58 30. "PADCONFIG22_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x58 29. "PADCONFIG22_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x58 28. "PADCONFIG22_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x58 27. "PADCONFIG22_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x58 26. "PADCONFIG22_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x58 25. "PADCONFIG22_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x58 24. "PADCONFIG22_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x58 23. "PADCONFIG22_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x58 22. "PADCONFIG22_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x58 21. "PADCONFIG22_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x58 19.--20. "PADCONFIG22_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x58 18. "PADCONFIG22_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x58 17. "PADCONFIG22_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x58 16. "PADCONFIG22_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x58 15. "PADCONFIG22_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x58 14. "PADCONFIG22_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x58 11.--13. "PADCONFIG22_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x58 8. "PADCONFIG22_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x58 7. "PADCONFIG22_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x58 0.--3. "PADCONFIG22_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x5C "CFG0_PADCONFIG23_PROXY,"
bitfld.long 0x5C 31. "PADCONFIG23_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x5C 30. "PADCONFIG23_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x5C 29. "PADCONFIG23_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x5C 28. "PADCONFIG23_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x5C 27. "PADCONFIG23_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x5C 26. "PADCONFIG23_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x5C 25. "PADCONFIG23_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x5C 24. "PADCONFIG23_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x5C 23. "PADCONFIG23_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x5C 22. "PADCONFIG23_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x5C 21. "PADCONFIG23_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x5C 19.--20. "PADCONFIG23_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x5C 18. "PADCONFIG23_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x5C 17. "PADCONFIG23_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x5C 16. "PADCONFIG23_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x5C 15. "PADCONFIG23_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x5C 14. "PADCONFIG23_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x5C 11.--13. "PADCONFIG23_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x5C 8. "PADCONFIG23_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x5C 7. "PADCONFIG23_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x5C 0.--3. "PADCONFIG23_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x60 "CFG0_PADCONFIG24_PROXY,"
bitfld.long 0x60 31. "PADCONFIG24_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x60 30. "PADCONFIG24_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x60 29. "PADCONFIG24_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x60 28. "PADCONFIG24_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x60 27. "PADCONFIG24_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x60 26. "PADCONFIG24_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x60 25. "PADCONFIG24_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x60 24. "PADCONFIG24_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x60 23. "PADCONFIG24_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x60 22. "PADCONFIG24_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x60 21. "PADCONFIG24_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x60 19.--20. "PADCONFIG24_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x60 18. "PADCONFIG24_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x60 17. "PADCONFIG24_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x60 16. "PADCONFIG24_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x60 15. "PADCONFIG24_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x60 14. "PADCONFIG24_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x60 11.--13. "PADCONFIG24_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x60 8. "PADCONFIG24_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x60 7. "PADCONFIG24_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x60 0.--3. "PADCONFIG24_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x64 "CFG0_PADCONFIG25_PROXY,"
bitfld.long 0x64 31. "PADCONFIG25_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x64 30. "PADCONFIG25_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x64 29. "PADCONFIG25_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x64 28. "PADCONFIG25_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x64 27. "PADCONFIG25_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x64 26. "PADCONFIG25_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x64 25. "PADCONFIG25_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x64 24. "PADCONFIG25_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x64 23. "PADCONFIG25_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x64 22. "PADCONFIG25_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x64 21. "PADCONFIG25_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x64 19.--20. "PADCONFIG25_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x64 18. "PADCONFIG25_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x64 17. "PADCONFIG25_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x64 16. "PADCONFIG25_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x64 15. "PADCONFIG25_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x64 14. "PADCONFIG25_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x64 11.--13. "PADCONFIG25_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x64 8. "PADCONFIG25_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x64 7. "PADCONFIG25_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x64 0.--3. "PADCONFIG25_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x68 "CFG0_PADCONFIG26_PROXY,"
bitfld.long 0x68 31. "PADCONFIG26_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x68 30. "PADCONFIG26_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x68 29. "PADCONFIG26_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x68 28. "PADCONFIG26_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x68 27. "PADCONFIG26_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x68 26. "PADCONFIG26_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x68 25. "PADCONFIG26_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x68 24. "PADCONFIG26_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x68 23. "PADCONFIG26_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x68 22. "PADCONFIG26_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x68 21. "PADCONFIG26_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x68 19.--20. "PADCONFIG26_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x68 18. "PADCONFIG26_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x68 17. "PADCONFIG26_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x68 16. "PADCONFIG26_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x68 15. "PADCONFIG26_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x68 14. "PADCONFIG26_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x68 11.--13. "PADCONFIG26_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x68 8. "PADCONFIG26_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x68 7. "PADCONFIG26_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x68 0.--3. "PADCONFIG26_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x6C "CFG0_PADCONFIG27_PROXY,"
bitfld.long 0x6C 31. "PADCONFIG27_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x6C 30. "PADCONFIG27_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x6C 29. "PADCONFIG27_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x6C 28. "PADCONFIG27_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x6C 27. "PADCONFIG27_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x6C 26. "PADCONFIG27_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x6C 25. "PADCONFIG27_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x6C 24. "PADCONFIG27_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x6C 23. "PADCONFIG27_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x6C 22. "PADCONFIG27_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x6C 21. "PADCONFIG27_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x6C 19.--20. "PADCONFIG27_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x6C 18. "PADCONFIG27_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x6C 17. "PADCONFIG27_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x6C 16. "PADCONFIG27_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x6C 15. "PADCONFIG27_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x6C 14. "PADCONFIG27_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x6C 11.--13. "PADCONFIG27_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x6C 8. "PADCONFIG27_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x6C 7. "PADCONFIG27_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x6C 0.--3. "PADCONFIG27_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x70 "CFG0_PADCONFIG28_PROXY,"
bitfld.long 0x70 31. "PADCONFIG28_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x70 30. "PADCONFIG28_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x70 29. "PADCONFIG28_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x70 28. "PADCONFIG28_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x70 27. "PADCONFIG28_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x70 26. "PADCONFIG28_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x70 25. "PADCONFIG28_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x70 24. "PADCONFIG28_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x70 23. "PADCONFIG28_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x70 22. "PADCONFIG28_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x70 21. "PADCONFIG28_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x70 19.--20. "PADCONFIG28_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x70 18. "PADCONFIG28_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x70 17. "PADCONFIG28_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x70 16. "PADCONFIG28_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x70 15. "PADCONFIG28_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x70 14. "PADCONFIG28_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x70 11.--13. "PADCONFIG28_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x70 8. "PADCONFIG28_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x70 7. "PADCONFIG28_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x70 0.--3. "PADCONFIG28_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x74 "CFG0_PADCONFIG29_PROXY,"
bitfld.long 0x74 31. "PADCONFIG29_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x74 30. "PADCONFIG29_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x74 29. "PADCONFIG29_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x74 28. "PADCONFIG29_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x74 27. "PADCONFIG29_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x74 26. "PADCONFIG29_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x74 25. "PADCONFIG29_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x74 24. "PADCONFIG29_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x74 23. "PADCONFIG29_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x74 22. "PADCONFIG29_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x74 21. "PADCONFIG29_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x74 19.--20. "PADCONFIG29_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x74 18. "PADCONFIG29_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x74 17. "PADCONFIG29_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x74 16. "PADCONFIG29_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x74 15. "PADCONFIG29_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x74 14. "PADCONFIG29_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x74 11.--13. "PADCONFIG29_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x74 8. "PADCONFIG29_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x74 7. "PADCONFIG29_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x74 0.--3. "PADCONFIG29_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x78 "CFG0_PADCONFIG30_PROXY,"
bitfld.long 0x78 31. "PADCONFIG30_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x78 30. "PADCONFIG30_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x78 29. "PADCONFIG30_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x78 28. "PADCONFIG30_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x78 27. "PADCONFIG30_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x78 26. "PADCONFIG30_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x78 25. "PADCONFIG30_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x78 24. "PADCONFIG30_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x78 23. "PADCONFIG30_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x78 22. "PADCONFIG30_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x78 21. "PADCONFIG30_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x78 19.--20. "PADCONFIG30_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x78 18. "PADCONFIG30_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x78 17. "PADCONFIG30_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x78 16. "PADCONFIG30_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x78 15. "PADCONFIG30_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x78 14. "PADCONFIG30_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x78 11.--13. "PADCONFIG30_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x78 8. "PADCONFIG30_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x78 7. "PADCONFIG30_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x78 0.--3. "PADCONFIG30_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x7C "CFG0_PADCONFIG31_PROXY,"
bitfld.long 0x7C 31. "PADCONFIG31_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x7C 30. "PADCONFIG31_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x7C 29. "PADCONFIG31_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x7C 28. "PADCONFIG31_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x7C 27. "PADCONFIG31_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x7C 26. "PADCONFIG31_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x7C 25. "PADCONFIG31_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x7C 24. "PADCONFIG31_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x7C 23. "PADCONFIG31_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x7C 22. "PADCONFIG31_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x7C 21. "PADCONFIG31_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x7C 19.--20. "PADCONFIG31_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x7C 18. "PADCONFIG31_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x7C 17. "PADCONFIG31_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x7C 16. "PADCONFIG31_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x7C 15. "PADCONFIG31_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x7C 14. "PADCONFIG31_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x7C 11.--13. "PADCONFIG31_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x7C 8. "PADCONFIG31_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x7C 7. "PADCONFIG31_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x7C 0.--3. "PADCONFIG31_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x80 "CFG0_PADCONFIG32_PROXY,"
bitfld.long 0x80 31. "PADCONFIG32_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x80 30. "PADCONFIG32_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x80 29. "PADCONFIG32_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x80 28. "PADCONFIG32_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x80 27. "PADCONFIG32_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x80 26. "PADCONFIG32_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x80 25. "PADCONFIG32_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x80 24. "PADCONFIG32_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x80 23. "PADCONFIG32_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x80 22. "PADCONFIG32_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x80 21. "PADCONFIG32_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x80 19.--20. "PADCONFIG32_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x80 18. "PADCONFIG32_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x80 17. "PADCONFIG32_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x80 16. "PADCONFIG32_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x80 15. "PADCONFIG32_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x80 14. "PADCONFIG32_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x80 11.--13. "PADCONFIG32_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x80 8. "PADCONFIG32_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x80 7. "PADCONFIG32_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x80 0.--3. "PADCONFIG32_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x84 "CFG0_PADCONFIG33_PROXY,"
bitfld.long 0x84 31. "PADCONFIG33_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x84 30. "PADCONFIG33_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x84 29. "PADCONFIG33_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x84 28. "PADCONFIG33_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x84 27. "PADCONFIG33_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x84 26. "PADCONFIG33_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x84 25. "PADCONFIG33_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x84 24. "PADCONFIG33_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x84 23. "PADCONFIG33_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x84 22. "PADCONFIG33_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x84 21. "PADCONFIG33_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x84 19.--20. "PADCONFIG33_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x84 18. "PADCONFIG33_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x84 17. "PADCONFIG33_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x84 16. "PADCONFIG33_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x84 15. "PADCONFIG33_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x84 14. "PADCONFIG33_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x84 11.--13. "PADCONFIG33_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x84 8. "PADCONFIG33_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x84 7. "PADCONFIG33_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x84 0.--3. "PADCONFIG33_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x88 "CFG0_PADCONFIG34_PROXY,"
bitfld.long 0x88 31. "PADCONFIG34_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x88 30. "PADCONFIG34_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x88 29. "PADCONFIG34_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x88 28. "PADCONFIG34_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x88 27. "PADCONFIG34_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x88 26. "PADCONFIG34_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x88 25. "PADCONFIG34_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x88 24. "PADCONFIG34_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x88 23. "PADCONFIG34_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x88 22. "PADCONFIG34_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x88 21. "PADCONFIG34_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x88 19.--20. "PADCONFIG34_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x88 18. "PADCONFIG34_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x88 17. "PADCONFIG34_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x88 16. "PADCONFIG34_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x88 15. "PADCONFIG34_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x88 14. "PADCONFIG34_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x88 11.--13. "PADCONFIG34_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x88 8. "PADCONFIG34_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x88 7. "PADCONFIG34_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x88 0.--3. "PADCONFIG34_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x8C "CFG0_PADCONFIG35_PROXY,"
bitfld.long 0x8C 31. "PADCONFIG35_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x8C 30. "PADCONFIG35_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x8C 29. "PADCONFIG35_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x8C 28. "PADCONFIG35_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x8C 27. "PADCONFIG35_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x8C 26. "PADCONFIG35_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x8C 25. "PADCONFIG35_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x8C 24. "PADCONFIG35_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x8C 23. "PADCONFIG35_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x8C 22. "PADCONFIG35_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x8C 21. "PADCONFIG35_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x8C 19.--20. "PADCONFIG35_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x8C 18. "PADCONFIG35_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x8C 17. "PADCONFIG35_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x8C 16. "PADCONFIG35_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x8C 15. "PADCONFIG35_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x8C 14. "PADCONFIG35_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x8C 11.--13. "PADCONFIG35_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8C 8. "PADCONFIG35_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x8C 7. "PADCONFIG35_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x8C 0.--3. "PADCONFIG35_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x90 "CFG0_PADCONFIG36_PROXY,"
bitfld.long 0x90 31. "PADCONFIG36_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x90 30. "PADCONFIG36_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x90 29. "PADCONFIG36_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x90 28. "PADCONFIG36_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x90 27. "PADCONFIG36_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x90 26. "PADCONFIG36_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x90 25. "PADCONFIG36_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x90 24. "PADCONFIG36_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x90 23. "PADCONFIG36_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x90 22. "PADCONFIG36_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x90 21. "PADCONFIG36_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x90 19.--20. "PADCONFIG36_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x90 18. "PADCONFIG36_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x90 17. "PADCONFIG36_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x90 16. "PADCONFIG36_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x90 15. "PADCONFIG36_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x90 14. "PADCONFIG36_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x90 11.--13. "PADCONFIG36_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x90 8. "PADCONFIG36_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x90 7. "PADCONFIG36_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x90 0.--3. "PADCONFIG36_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x94 "CFG0_PADCONFIG37_PROXY,"
bitfld.long 0x94 31. "PADCONFIG37_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x94 30. "PADCONFIG37_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x94 29. "PADCONFIG37_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x94 28. "PADCONFIG37_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x94 27. "PADCONFIG37_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x94 26. "PADCONFIG37_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x94 25. "PADCONFIG37_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x94 24. "PADCONFIG37_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x94 23. "PADCONFIG37_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x94 22. "PADCONFIG37_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x94 21. "PADCONFIG37_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x94 19.--20. "PADCONFIG37_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x94 18. "PADCONFIG37_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x94 17. "PADCONFIG37_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x94 16. "PADCONFIG37_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x94 15. "PADCONFIG37_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x94 14. "PADCONFIG37_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x94 11.--13. "PADCONFIG37_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x94 8. "PADCONFIG37_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x94 7. "PADCONFIG37_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x94 0.--3. "PADCONFIG37_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x98 "CFG0_PADCONFIG38_PROXY,"
bitfld.long 0x98 31. "PADCONFIG38_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x98 30. "PADCONFIG38_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x98 29. "PADCONFIG38_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x98 28. "PADCONFIG38_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x98 27. "PADCONFIG38_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x98 26. "PADCONFIG38_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x98 25. "PADCONFIG38_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x98 24. "PADCONFIG38_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x98 23. "PADCONFIG38_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x98 22. "PADCONFIG38_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x98 21. "PADCONFIG38_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x98 19.--20. "PADCONFIG38_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x98 18. "PADCONFIG38_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x98 17. "PADCONFIG38_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x98 16. "PADCONFIG38_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x98 15. "PADCONFIG38_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x98 14. "PADCONFIG38_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x98 11.--13. "PADCONFIG38_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x98 8. "PADCONFIG38_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x98 7. "PADCONFIG38_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x98 0.--3. "PADCONFIG38_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x9C "CFG0_PADCONFIG39_PROXY,"
bitfld.long 0x9C 31. "PADCONFIG39_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x9C 30. "PADCONFIG39_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x9C 29. "PADCONFIG39_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x9C 28. "PADCONFIG39_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x9C 27. "PADCONFIG39_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x9C 26. "PADCONFIG39_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x9C 25. "PADCONFIG39_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x9C 24. "PADCONFIG39_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x9C 23. "PADCONFIG39_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x9C 22. "PADCONFIG39_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x9C 21. "PADCONFIG39_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x9C 19.--20. "PADCONFIG39_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x9C 18. "PADCONFIG39_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x9C 17. "PADCONFIG39_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x9C 16. "PADCONFIG39_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x9C 15. "PADCONFIG39_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x9C 14. "PADCONFIG39_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x9C 11.--13. "PADCONFIG39_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x9C 8. "PADCONFIG39_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x9C 7. "PADCONFIG39_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x9C 0.--3. "PADCONFIG39_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xA0 "CFG0_PADCONFIG40_PROXY,"
bitfld.long 0xA0 31. "PADCONFIG40_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xA0 30. "PADCONFIG40_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xA0 29. "PADCONFIG40_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xA0 28. "PADCONFIG40_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xA0 27. "PADCONFIG40_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xA0 26. "PADCONFIG40_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xA0 25. "PADCONFIG40_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xA0 24. "PADCONFIG40_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xA0 23. "PADCONFIG40_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xA0 22. "PADCONFIG40_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xA0 21. "PADCONFIG40_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xA0 19.--20. "PADCONFIG40_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xA0 18. "PADCONFIG40_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xA0 17. "PADCONFIG40_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xA0 16. "PADCONFIG40_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xA0 15. "PADCONFIG40_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xA0 14. "PADCONFIG40_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xA0 11.--13. "PADCONFIG40_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xA0 8. "PADCONFIG40_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xA0 7. "PADCONFIG40_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xA0 0.--3. "PADCONFIG40_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xA4 "CFG0_PADCONFIG41_PROXY,"
bitfld.long 0xA4 31. "PADCONFIG41_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xA4 30. "PADCONFIG41_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xA4 29. "PADCONFIG41_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xA4 28. "PADCONFIG41_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xA4 27. "PADCONFIG41_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xA4 26. "PADCONFIG41_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xA4 25. "PADCONFIG41_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xA4 24. "PADCONFIG41_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xA4 23. "PADCONFIG41_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xA4 22. "PADCONFIG41_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xA4 21. "PADCONFIG41_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xA4 19.--20. "PADCONFIG41_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xA4 18. "PADCONFIG41_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xA4 17. "PADCONFIG41_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xA4 16. "PADCONFIG41_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xA4 15. "PADCONFIG41_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xA4 14. "PADCONFIG41_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xA4 11.--13. "PADCONFIG41_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xA4 8. "PADCONFIG41_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xA4 7. "PADCONFIG41_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xA4 0.--3. "PADCONFIG41_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xA8 "CFG0_PADCONFIG42_PROXY,"
bitfld.long 0xA8 31. "PADCONFIG42_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xA8 30. "PADCONFIG42_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xA8 29. "PADCONFIG42_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xA8 28. "PADCONFIG42_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xA8 27. "PADCONFIG42_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xA8 26. "PADCONFIG42_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xA8 25. "PADCONFIG42_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xA8 24. "PADCONFIG42_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xA8 23. "PADCONFIG42_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xA8 22. "PADCONFIG42_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xA8 21. "PADCONFIG42_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xA8 19.--20. "PADCONFIG42_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xA8 18. "PADCONFIG42_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xA8 17. "PADCONFIG42_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xA8 16. "PADCONFIG42_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xA8 15. "PADCONFIG42_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xA8 14. "PADCONFIG42_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xA8 11.--13. "PADCONFIG42_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xA8 8. "PADCONFIG42_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xA8 7. "PADCONFIG42_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xA8 0.--3. "PADCONFIG42_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xAC "CFG0_PADCONFIG43_PROXY,"
bitfld.long 0xAC 31. "PADCONFIG43_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xAC 30. "PADCONFIG43_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xAC 29. "PADCONFIG43_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xAC 28. "PADCONFIG43_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xAC 27. "PADCONFIG43_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xAC 26. "PADCONFIG43_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xAC 25. "PADCONFIG43_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xAC 24. "PADCONFIG43_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xAC 23. "PADCONFIG43_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xAC 22. "PADCONFIG43_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xAC 21. "PADCONFIG43_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xAC 19.--20. "PADCONFIG43_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xAC 18. "PADCONFIG43_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xAC 17. "PADCONFIG43_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xAC 16. "PADCONFIG43_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xAC 15. "PADCONFIG43_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xAC 14. "PADCONFIG43_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xAC 11.--13. "PADCONFIG43_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xAC 8. "PADCONFIG43_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xAC 7. "PADCONFIG43_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xAC 0.--3. "PADCONFIG43_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xB0 "CFG0_PADCONFIG44_PROXY,"
bitfld.long 0xB0 31. "PADCONFIG44_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xB0 30. "PADCONFIG44_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xB0 29. "PADCONFIG44_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xB0 28. "PADCONFIG44_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xB0 27. "PADCONFIG44_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xB0 26. "PADCONFIG44_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xB0 25. "PADCONFIG44_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xB0 24. "PADCONFIG44_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xB0 23. "PADCONFIG44_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xB0 22. "PADCONFIG44_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xB0 21. "PADCONFIG44_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xB0 19.--20. "PADCONFIG44_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xB0 18. "PADCONFIG44_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xB0 17. "PADCONFIG44_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xB0 16. "PADCONFIG44_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xB0 15. "PADCONFIG44_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xB0 14. "PADCONFIG44_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xB0 11.--13. "PADCONFIG44_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xB0 8. "PADCONFIG44_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xB0 7. "PADCONFIG44_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xB0 0.--3. "PADCONFIG44_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xB4 "CFG0_PADCONFIG45_PROXY,"
bitfld.long 0xB4 31. "PADCONFIG45_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xB4 30. "PADCONFIG45_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xB4 29. "PADCONFIG45_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xB4 28. "PADCONFIG45_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xB4 27. "PADCONFIG45_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xB4 26. "PADCONFIG45_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xB4 25. "PADCONFIG45_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xB4 24. "PADCONFIG45_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xB4 23. "PADCONFIG45_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xB4 22. "PADCONFIG45_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xB4 21. "PADCONFIG45_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xB4 19.--20. "PADCONFIG45_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xB4 18. "PADCONFIG45_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xB4 17. "PADCONFIG45_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xB4 16. "PADCONFIG45_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xB4 15. "PADCONFIG45_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xB4 14. "PADCONFIG45_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xB4 11.--13. "PADCONFIG45_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xB4 8. "PADCONFIG45_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xB4 7. "PADCONFIG45_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xB4 0.--3. "PADCONFIG45_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xB8 "CFG0_PADCONFIG46_PROXY,"
bitfld.long 0xB8 31. "PADCONFIG46_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xB8 30. "PADCONFIG46_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xB8 29. "PADCONFIG46_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xB8 28. "PADCONFIG46_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xB8 27. "PADCONFIG46_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xB8 26. "PADCONFIG46_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xB8 25. "PADCONFIG46_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xB8 24. "PADCONFIG46_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xB8 23. "PADCONFIG46_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xB8 22. "PADCONFIG46_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xB8 21. "PADCONFIG46_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xB8 19.--20. "PADCONFIG46_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xB8 18. "PADCONFIG46_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xB8 17. "PADCONFIG46_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xB8 16. "PADCONFIG46_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xB8 15. "PADCONFIG46_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xB8 14. "PADCONFIG46_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xB8 11.--13. "PADCONFIG46_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xB8 8. "PADCONFIG46_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xB8 7. "PADCONFIG46_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xB8 0.--3. "PADCONFIG46_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xBC "CFG0_PADCONFIG47_PROXY,"
bitfld.long 0xBC 31. "PADCONFIG47_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xBC 30. "PADCONFIG47_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xBC 29. "PADCONFIG47_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xBC 28. "PADCONFIG47_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xBC 27. "PADCONFIG47_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xBC 26. "PADCONFIG47_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xBC 25. "PADCONFIG47_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xBC 24. "PADCONFIG47_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xBC 23. "PADCONFIG47_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xBC 22. "PADCONFIG47_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xBC 21. "PADCONFIG47_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xBC 19.--20. "PADCONFIG47_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xBC 18. "PADCONFIG47_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xBC 17. "PADCONFIG47_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xBC 16. "PADCONFIG47_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xBC 15. "PADCONFIG47_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xBC 14. "PADCONFIG47_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xBC 11.--13. "PADCONFIG47_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xBC 8. "PADCONFIG47_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xBC 7. "PADCONFIG47_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xBC 0.--3. "PADCONFIG47_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xC0 "CFG0_PADCONFIG48_PROXY,"
bitfld.long 0xC0 31. "PADCONFIG48_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xC0 30. "PADCONFIG48_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xC0 29. "PADCONFIG48_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xC0 28. "PADCONFIG48_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xC0 27. "PADCONFIG48_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xC0 26. "PADCONFIG48_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xC0 25. "PADCONFIG48_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xC0 24. "PADCONFIG48_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xC0 23. "PADCONFIG48_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xC0 22. "PADCONFIG48_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xC0 21. "PADCONFIG48_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xC0 19.--20. "PADCONFIG48_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xC0 18. "PADCONFIG48_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xC0 17. "PADCONFIG48_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xC0 16. "PADCONFIG48_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xC0 15. "PADCONFIG48_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xC0 14. "PADCONFIG48_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xC0 11.--13. "PADCONFIG48_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC0 8. "PADCONFIG48_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xC0 7. "PADCONFIG48_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xC0 0.--3. "PADCONFIG48_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xC4 "CFG0_PADCONFIG49_PROXY,"
bitfld.long 0xC4 31. "PADCONFIG49_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xC4 30. "PADCONFIG49_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xC4 29. "PADCONFIG49_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xC4 28. "PADCONFIG49_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xC4 27. "PADCONFIG49_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xC4 26. "PADCONFIG49_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xC4 25. "PADCONFIG49_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xC4 24. "PADCONFIG49_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xC4 23. "PADCONFIG49_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xC4 22. "PADCONFIG49_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xC4 21. "PADCONFIG49_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xC4 19.--20. "PADCONFIG49_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xC4 18. "PADCONFIG49_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xC4 17. "PADCONFIG49_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xC4 16. "PADCONFIG49_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xC4 15. "PADCONFIG49_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xC4 14. "PADCONFIG49_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xC4 11.--13. "PADCONFIG49_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC4 8. "PADCONFIG49_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xC4 7. "PADCONFIG49_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xC4 0.--3. "PADCONFIG49_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xC8 "CFG0_PADCONFIG50_PROXY,"
bitfld.long 0xC8 31. "PADCONFIG50_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xC8 30. "PADCONFIG50_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xC8 29. "PADCONFIG50_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xC8 28. "PADCONFIG50_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xC8 27. "PADCONFIG50_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xC8 26. "PADCONFIG50_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xC8 25. "PADCONFIG50_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xC8 24. "PADCONFIG50_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xC8 23. "PADCONFIG50_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xC8 22. "PADCONFIG50_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xC8 21. "PADCONFIG50_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xC8 19.--20. "PADCONFIG50_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xC8 18. "PADCONFIG50_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xC8 17. "PADCONFIG50_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xC8 16. "PADCONFIG50_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xC8 15. "PADCONFIG50_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xC8 14. "PADCONFIG50_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xC8 11.--13. "PADCONFIG50_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC8 8. "PADCONFIG50_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xC8 7. "PADCONFIG50_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xC8 0.--3. "PADCONFIG50_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xCC "CFG0_PADCONFIG51_PROXY,"
bitfld.long 0xCC 31. "PADCONFIG51_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xCC 30. "PADCONFIG51_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xCC 29. "PADCONFIG51_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xCC 28. "PADCONFIG51_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xCC 27. "PADCONFIG51_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xCC 26. "PADCONFIG51_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xCC 25. "PADCONFIG51_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xCC 24. "PADCONFIG51_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xCC 23. "PADCONFIG51_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xCC 22. "PADCONFIG51_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xCC 21. "PADCONFIG51_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xCC 19.--20. "PADCONFIG51_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xCC 18. "PADCONFIG51_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xCC 17. "PADCONFIG51_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xCC 16. "PADCONFIG51_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xCC 15. "PADCONFIG51_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xCC 14. "PADCONFIG51_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xCC 11.--13. "PADCONFIG51_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xCC 8. "PADCONFIG51_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xCC 7. "PADCONFIG51_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xCC 0.--3. "PADCONFIG51_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xD0 "CFG0_PADCONFIG52_PROXY,"
bitfld.long 0xD0 31. "PADCONFIG52_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xD0 30. "PADCONFIG52_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xD0 29. "PADCONFIG52_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xD0 28. "PADCONFIG52_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xD0 27. "PADCONFIG52_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xD0 26. "PADCONFIG52_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xD0 25. "PADCONFIG52_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xD0 24. "PADCONFIG52_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xD0 23. "PADCONFIG52_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xD0 22. "PADCONFIG52_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xD0 21. "PADCONFIG52_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xD0 19.--20. "PADCONFIG52_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xD0 18. "PADCONFIG52_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xD0 17. "PADCONFIG52_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xD0 16. "PADCONFIG52_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xD0 15. "PADCONFIG52_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xD0 14. "PADCONFIG52_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xD0 11.--13. "PADCONFIG52_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xD0 8. "PADCONFIG52_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xD0 7. "PADCONFIG52_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xD0 0.--3. "PADCONFIG52_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xD4 "CFG0_PADCONFIG53_PROXY,"
bitfld.long 0xD4 31. "PADCONFIG53_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xD4 30. "PADCONFIG53_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xD4 29. "PADCONFIG53_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xD4 28. "PADCONFIG53_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xD4 27. "PADCONFIG53_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xD4 26. "PADCONFIG53_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xD4 25. "PADCONFIG53_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xD4 24. "PADCONFIG53_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xD4 23. "PADCONFIG53_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xD4 22. "PADCONFIG53_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0xD4 21. "PADCONFIG53_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xD4 19.--20. "PADCONFIG53_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xD4 18. "PADCONFIG53_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xD4 17. "PADCONFIG53_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xD4 16. "PADCONFIG53_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xD4 15. "PADCONFIG53_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xD4 14. "PADCONFIG53_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xD4 11.--13. "PADCONFIG53_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xD4 8. "PADCONFIG53_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xD4 7. "PADCONFIG53_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xD4 0.--3. "PADCONFIG53_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xD8 "CFG0_PADCONFIG54_PROXY,"
bitfld.long 0xD8 31. "PADCONFIG54_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xD8 30. "PADCONFIG54_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xD8 29. "PADCONFIG54_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xD8 28. "PADCONFIG54_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xD8 27. "PADCONFIG54_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xD8 26. "PADCONFIG54_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xD8 25. "PADCONFIG54_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xD8 24. "PADCONFIG54_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xD8 23. "PADCONFIG54_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xD8 22. "PADCONFIG54_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xD8 21. "PADCONFIG54_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xD8 19.--20. "PADCONFIG54_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xD8 18. "PADCONFIG54_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xD8 17. "PADCONFIG54_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xD8 16. "PADCONFIG54_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xD8 15. "PADCONFIG54_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xD8 14. "PADCONFIG54_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xD8 11.--13. "PADCONFIG54_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xD8 8. "PADCONFIG54_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xD8 7. "PADCONFIG54_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xD8 0.--3. "PADCONFIG54_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xDC "CFG0_PADCONFIG55_PROXY,"
bitfld.long 0xDC 31. "PADCONFIG55_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xDC 30. "PADCONFIG55_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0xDC 29. "PADCONFIG55_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0xDC 28. "PADCONFIG55_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0xDC 27. "PADCONFIG55_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xDC 26. "PADCONFIG55_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0xDC 25. "PADCONFIG55_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xDC 24. "PADCONFIG55_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0xDC 23. "PADCONFIG55_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0xDC 22. "PADCONFIG55_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xDC 21. "PADCONFIG55_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0xDC 19.--20. "PADCONFIG55_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xDC 18. "PADCONFIG55_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xDC 17. "PADCONFIG55_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xDC 16. "PADCONFIG55_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xDC 15. "PADCONFIG55_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0xDC 14. "PADCONFIG55_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xDC 11.--13. "PADCONFIG55_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xDC 8. "PADCONFIG55_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xDC 7. "PADCONFIG55_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xDC 0.--3. "PADCONFIG55_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xE0 "CFG0_PADCONFIG56_PROXY,"
bitfld.long 0xE0 31. "PADCONFIG56_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xE0 30. "PADCONFIG56_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xE0 29. "PADCONFIG56_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xE0 28. "PADCONFIG56_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xE0 27. "PADCONFIG56_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0xE0 26. "PADCONFIG56_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xE0 25. "PADCONFIG56_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xE0 24. "PADCONFIG56_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xE0 23. "PADCONFIG56_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xE0 22. "PADCONFIG56_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xE0 21. "PADCONFIG56_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xE0 19.--20. "PADCONFIG56_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0xE0 18. "PADCONFIG56_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xE0 17. "PADCONFIG56_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xE0 16. "PADCONFIG56_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xE0 15. "PADCONFIG56_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xE0 14. "PADCONFIG56_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xE0 11.--13. "PADCONFIG56_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xE0 8. "PADCONFIG56_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xE0 7. "PADCONFIG56_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0xE0 0.--3. "PADCONFIG56_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xE4 "CFG0_PADCONFIG57_PROXY,"
bitfld.long 0xE4 31. "PADCONFIG57_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0xE4 30. "PADCONFIG57_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xE4 29. "PADCONFIG57_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xE4 28. "PADCONFIG57_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xE4 27. "PADCONFIG57_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xE4 26. "PADCONFIG57_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xE4 25. "PADCONFIG57_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xE4 24. "PADCONFIG57_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xE4 23. "PADCONFIG57_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xE4 22. "PADCONFIG57_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xE4 21. "PADCONFIG57_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xE4 19.--20. "PADCONFIG57_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xE4 18. "PADCONFIG57_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xE4 17. "PADCONFIG57_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xE4 16. "PADCONFIG57_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xE4 15. "PADCONFIG57_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xE4 14. "PADCONFIG57_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xE4 11.--13. "PADCONFIG57_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE4 8. "PADCONFIG57_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xE4 7. "PADCONFIG57_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xE4 0.--3. "PADCONFIG57_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xE8 "CFG0_PADCONFIG58_PROXY,"
bitfld.long 0xE8 31. "PADCONFIG58_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xE8 30. "PADCONFIG58_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xE8 29. "PADCONFIG58_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xE8 28. "PADCONFIG58_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xE8 27. "PADCONFIG58_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xE8 26. "PADCONFIG58_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xE8 25. "PADCONFIG58_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xE8 24. "PADCONFIG58_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xE8 23. "PADCONFIG58_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xE8 22. "PADCONFIG58_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xE8 21. "PADCONFIG58_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xE8 19.--20. "PADCONFIG58_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xE8 18. "PADCONFIG58_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xE8 17. "PADCONFIG58_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xE8 16. "PADCONFIG58_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xE8 15. "PADCONFIG58_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xE8 14. "PADCONFIG58_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0xE8 11.--13. "PADCONFIG58_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0xE8 8. "PADCONFIG58_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0xE8 7. "PADCONFIG58_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xE8 0.--3. "PADCONFIG58_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xEC "CFG0_PADCONFIG59_PROXY,"
bitfld.long 0xEC 31. "PADCONFIG59_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xEC 30. "PADCONFIG59_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xEC 29. "PADCONFIG59_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xEC 28. "PADCONFIG59_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xEC 27. "PADCONFIG59_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xEC 26. "PADCONFIG59_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xEC 25. "PADCONFIG59_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0xEC 24. "PADCONFIG59_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xEC 23. "PADCONFIG59_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xEC 22. "PADCONFIG59_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xEC 21. "PADCONFIG59_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xEC 19.--20. "PADCONFIG59_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xEC 18. "PADCONFIG59_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0xEC 17. "PADCONFIG59_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0xEC 16. "PADCONFIG59_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0xEC 15. "PADCONFIG59_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xEC 14. "PADCONFIG59_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xEC 11.--13. "PADCONFIG59_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xEC 8. "PADCONFIG59_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xEC 7. "PADCONFIG59_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xEC 0.--3. "PADCONFIG59_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xF0 "CFG0_PADCONFIG60_PROXY,"
bitfld.long 0xF0 31. "PADCONFIG60_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xF0 30. "PADCONFIG60_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xF0 29. "PADCONFIG60_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xF0 28. "PADCONFIG60_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xF0 27. "PADCONFIG60_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xF0 26. "PADCONFIG60_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xF0 25. "PADCONFIG60_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xF0 24. "PADCONFIG60_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xF0 23. "PADCONFIG60_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xF0 22. "PADCONFIG60_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xF0 21. "PADCONFIG60_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xF0 19.--20. "PADCONFIG60_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xF0 18. "PADCONFIG60_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xF0 17. "PADCONFIG60_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xF0 16. "PADCONFIG60_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xF0 15. "PADCONFIG60_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xF0 14. "PADCONFIG60_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xF0 11.--13. "PADCONFIG60_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF0 8. "PADCONFIG60_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xF0 7. "PADCONFIG60_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xF0 0.--3. "PADCONFIG60_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xF4 "CFG0_PADCONFIG61_PROXY,"
bitfld.long 0xF4 31. "PADCONFIG61_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xF4 30. "PADCONFIG61_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xF4 29. "PADCONFIG61_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xF4 28. "PADCONFIG61_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xF4 27. "PADCONFIG61_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xF4 26. "PADCONFIG61_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xF4 25. "PADCONFIG61_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xF4 24. "PADCONFIG61_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xF4 23. "PADCONFIG61_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xF4 22. "PADCONFIG61_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xF4 21. "PADCONFIG61_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xF4 19.--20. "PADCONFIG61_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xF4 18. "PADCONFIG61_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xF4 17. "PADCONFIG61_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xF4 16. "PADCONFIG61_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xF4 15. "PADCONFIG61_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xF4 14. "PADCONFIG61_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xF4 11.--13. "PADCONFIG61_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF4 8. "PADCONFIG61_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xF4 7. "PADCONFIG61_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xF4 0.--3. "PADCONFIG61_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xF8 "CFG0_PADCONFIG62_PROXY,"
bitfld.long 0xF8 31. "PADCONFIG62_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xF8 30. "PADCONFIG62_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xF8 29. "PADCONFIG62_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xF8 28. "PADCONFIG62_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xF8 27. "PADCONFIG62_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xF8 26. "PADCONFIG62_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xF8 25. "PADCONFIG62_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xF8 24. "PADCONFIG62_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xF8 23. "PADCONFIG62_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xF8 22. "PADCONFIG62_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xF8 21. "PADCONFIG62_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xF8 19.--20. "PADCONFIG62_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xF8 18. "PADCONFIG62_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xF8 17. "PADCONFIG62_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xF8 16. "PADCONFIG62_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xF8 15. "PADCONFIG62_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xF8 14. "PADCONFIG62_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xF8 11.--13. "PADCONFIG62_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF8 8. "PADCONFIG62_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xF8 7. "PADCONFIG62_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xF8 0.--3. "PADCONFIG62_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0xFC "CFG0_PADCONFIG63_PROXY,"
bitfld.long 0xFC 31. "PADCONFIG63_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0xFC 30. "PADCONFIG63_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0xFC 29. "PADCONFIG63_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0xFC 28. "PADCONFIG63_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0xFC 27. "PADCONFIG63_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0xFC 26. "PADCONFIG63_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0xFC 25. "PADCONFIG63_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0xFC 24. "PADCONFIG63_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0xFC 23. "PADCONFIG63_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0xFC 22. "PADCONFIG63_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0xFC 21. "PADCONFIG63_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0xFC 19.--20. "PADCONFIG63_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0xFC 18. "PADCONFIG63_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0xFC 17. "PADCONFIG63_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0xFC 16. "PADCONFIG63_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0xFC 15. "PADCONFIG63_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0xFC 14. "PADCONFIG63_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0xFC 11.--13. "PADCONFIG63_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xFC 8. "PADCONFIG63_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0xFC 7. "PADCONFIG63_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0xFC 0.--3. "PADCONFIG63_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x100 "CFG0_PADCONFIG64_PROXY,"
bitfld.long 0x100 31. "PADCONFIG64_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x100 30. "PADCONFIG64_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x100 29. "PADCONFIG64_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x100 28. "PADCONFIG64_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x100 27. "PADCONFIG64_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x100 26. "PADCONFIG64_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x100 25. "PADCONFIG64_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x100 24. "PADCONFIG64_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x100 23. "PADCONFIG64_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x100 22. "PADCONFIG64_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x100 21. "PADCONFIG64_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x100 19.--20. "PADCONFIG64_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x100 18. "PADCONFIG64_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x100 17. "PADCONFIG64_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x100 16. "PADCONFIG64_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x100 15. "PADCONFIG64_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x100 14. "PADCONFIG64_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x100 11.--13. "PADCONFIG64_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x100 8. "PADCONFIG64_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x100 7. "PADCONFIG64_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x100 0.--3. "PADCONFIG64_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x104 "CFG0_PADCONFIG65_PROXY,"
bitfld.long 0x104 31. "PADCONFIG65_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x104 30. "PADCONFIG65_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x104 29. "PADCONFIG65_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x104 28. "PADCONFIG65_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x104 27. "PADCONFIG65_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x104 26. "PADCONFIG65_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x104 25. "PADCONFIG65_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x104 24. "PADCONFIG65_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x104 23. "PADCONFIG65_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x104 22. "PADCONFIG65_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x104 21. "PADCONFIG65_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x104 19.--20. "PADCONFIG65_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x104 18. "PADCONFIG65_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x104 17. "PADCONFIG65_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x104 16. "PADCONFIG65_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x104 15. "PADCONFIG65_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x104 14. "PADCONFIG65_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x104 11.--13. "PADCONFIG65_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x104 8. "PADCONFIG65_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x104 7. "PADCONFIG65_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x104 0.--3. "PADCONFIG65_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x108 "CFG0_PADCONFIG66_PROXY,"
bitfld.long 0x108 31. "PADCONFIG66_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x108 30. "PADCONFIG66_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x108 29. "PADCONFIG66_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x108 28. "PADCONFIG66_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x108 27. "PADCONFIG66_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x108 26. "PADCONFIG66_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x108 25. "PADCONFIG66_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x108 24. "PADCONFIG66_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x108 23. "PADCONFIG66_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x108 22. "PADCONFIG66_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x108 21. "PADCONFIG66_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x108 19.--20. "PADCONFIG66_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x108 18. "PADCONFIG66_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x108 17. "PADCONFIG66_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x108 16. "PADCONFIG66_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x108 15. "PADCONFIG66_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x108 14. "PADCONFIG66_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x108 11.--13. "PADCONFIG66_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x108 8. "PADCONFIG66_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x108 7. "PADCONFIG66_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x108 0.--3. "PADCONFIG66_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x10C "CFG0_PADCONFIG67_PROXY,"
bitfld.long 0x10C 31. "PADCONFIG67_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x10C 30. "PADCONFIG67_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x10C 29. "PADCONFIG67_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x10C 28. "PADCONFIG67_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x10C 27. "PADCONFIG67_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x10C 26. "PADCONFIG67_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x10C 25. "PADCONFIG67_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x10C 24. "PADCONFIG67_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x10C 23. "PADCONFIG67_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x10C 22. "PADCONFIG67_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x10C 21. "PADCONFIG67_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x10C 19.--20. "PADCONFIG67_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x10C 18. "PADCONFIG67_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x10C 17. "PADCONFIG67_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x10C 16. "PADCONFIG67_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x10C 15. "PADCONFIG67_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x10C 14. "PADCONFIG67_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x10C 11.--13. "PADCONFIG67_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10C 8. "PADCONFIG67_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x10C 7. "PADCONFIG67_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x10C 0.--3. "PADCONFIG67_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x110 "CFG0_PADCONFIG68_PROXY,"
bitfld.long 0x110 31. "PADCONFIG68_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x110 30. "PADCONFIG68_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x110 29. "PADCONFIG68_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x110 28. "PADCONFIG68_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x110 27. "PADCONFIG68_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x110 26. "PADCONFIG68_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x110 25. "PADCONFIG68_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x110 24. "PADCONFIG68_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x110 23. "PADCONFIG68_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x110 22. "PADCONFIG68_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x110 21. "PADCONFIG68_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x110 19.--20. "PADCONFIG68_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x110 18. "PADCONFIG68_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x110 17. "PADCONFIG68_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x110 16. "PADCONFIG68_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x110 15. "PADCONFIG68_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x110 14. "PADCONFIG68_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x110 11.--13. "PADCONFIG68_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x110 8. "PADCONFIG68_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x110 7. "PADCONFIG68_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x110 0.--3. "PADCONFIG68_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x114 "CFG0_PADCONFIG69_PROXY,"
bitfld.long 0x114 31. "PADCONFIG69_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x114 30. "PADCONFIG69_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x114 29. "PADCONFIG69_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x114 28. "PADCONFIG69_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x114 27. "PADCONFIG69_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x114 26. "PADCONFIG69_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x114 25. "PADCONFIG69_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x114 24. "PADCONFIG69_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x114 23. "PADCONFIG69_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x114 22. "PADCONFIG69_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x114 21. "PADCONFIG69_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x114 19.--20. "PADCONFIG69_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x114 18. "PADCONFIG69_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x114 17. "PADCONFIG69_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x114 16. "PADCONFIG69_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x114 15. "PADCONFIG69_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x114 14. "PADCONFIG69_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x114 11.--13. "PADCONFIG69_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x114 8. "PADCONFIG69_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x114 7. "PADCONFIG69_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x114 0.--3. "PADCONFIG69_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x118 "CFG0_PADCONFIG70_PROXY,"
bitfld.long 0x118 31. "PADCONFIG70_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x118 30. "PADCONFIG70_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x118 29. "PADCONFIG70_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x118 28. "PADCONFIG70_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x118 27. "PADCONFIG70_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x118 26. "PADCONFIG70_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x118 25. "PADCONFIG70_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x118 24. "PADCONFIG70_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x118 23. "PADCONFIG70_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x118 22. "PADCONFIG70_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x118 21. "PADCONFIG70_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x118 19.--20. "PADCONFIG70_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x118 18. "PADCONFIG70_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x118 17. "PADCONFIG70_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x118 16. "PADCONFIG70_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x118 15. "PADCONFIG70_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x118 14. "PADCONFIG70_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x118 11.--13. "PADCONFIG70_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x118 8. "PADCONFIG70_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x118 7. "PADCONFIG70_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x118 0.--3. "PADCONFIG70_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x11C "CFG0_PADCONFIG71_PROXY,"
bitfld.long 0x11C 31. "PADCONFIG71_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x11C 30. "PADCONFIG71_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x11C 29. "PADCONFIG71_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x11C 28. "PADCONFIG71_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x11C 27. "PADCONFIG71_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x11C 26. "PADCONFIG71_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x11C 25. "PADCONFIG71_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x11C 24. "PADCONFIG71_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x11C 23. "PADCONFIG71_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x11C 22. "PADCONFIG71_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x11C 21. "PADCONFIG71_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x11C 19.--20. "PADCONFIG71_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x11C 18. "PADCONFIG71_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x11C 17. "PADCONFIG71_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x11C 16. "PADCONFIG71_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x11C 15. "PADCONFIG71_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x11C 14. "PADCONFIG71_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x11C 11.--13. "PADCONFIG71_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x11C 8. "PADCONFIG71_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x11C 7. "PADCONFIG71_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x11C 0.--3. "PADCONFIG71_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x120 "CFG0_PADCONFIG72_PROXY,"
bitfld.long 0x120 31. "PADCONFIG72_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x120 30. "PADCONFIG72_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x120 29. "PADCONFIG72_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x120 28. "PADCONFIG72_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x120 27. "PADCONFIG72_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x120 26. "PADCONFIG72_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x120 25. "PADCONFIG72_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x120 24. "PADCONFIG72_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x120 23. "PADCONFIG72_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x120 22. "PADCONFIG72_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x120 21. "PADCONFIG72_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x120 19.--20. "PADCONFIG72_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x120 18. "PADCONFIG72_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x120 17. "PADCONFIG72_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x120 16. "PADCONFIG72_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x120 15. "PADCONFIG72_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x120 14. "PADCONFIG72_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x120 11.--13. "PADCONFIG72_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x120 8. "PADCONFIG72_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x120 7. "PADCONFIG72_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x120 0.--3. "PADCONFIG72_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x124 "CFG0_PADCONFIG73_PROXY,"
bitfld.long 0x124 31. "PADCONFIG73_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x124 30. "PADCONFIG73_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x124 29. "PADCONFIG73_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x124 28. "PADCONFIG73_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x124 27. "PADCONFIG73_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x124 26. "PADCONFIG73_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x124 25. "PADCONFIG73_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x124 24. "PADCONFIG73_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x124 23. "PADCONFIG73_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x124 22. "PADCONFIG73_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x124 21. "PADCONFIG73_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x124 19.--20. "PADCONFIG73_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x124 18. "PADCONFIG73_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x124 17. "PADCONFIG73_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x124 16. "PADCONFIG73_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x124 15. "PADCONFIG73_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x124 14. "PADCONFIG73_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x124 11.--13. "PADCONFIG73_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x124 8. "PADCONFIG73_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x124 7. "PADCONFIG73_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x124 0.--3. "PADCONFIG73_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x128 "CFG0_PADCONFIG74_PROXY,"
bitfld.long 0x128 31. "PADCONFIG74_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x128 30. "PADCONFIG74_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x128 29. "PADCONFIG74_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x128 28. "PADCONFIG74_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x128 27. "PADCONFIG74_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x128 26. "PADCONFIG74_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x128 25. "PADCONFIG74_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x128 24. "PADCONFIG74_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x128 23. "PADCONFIG74_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x128 22. "PADCONFIG74_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x128 21. "PADCONFIG74_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x128 19.--20. "PADCONFIG74_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x128 18. "PADCONFIG74_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x128 17. "PADCONFIG74_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x128 16. "PADCONFIG74_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x128 15. "PADCONFIG74_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x128 14. "PADCONFIG74_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x128 11.--13. "PADCONFIG74_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x128 8. "PADCONFIG74_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x128 7. "PADCONFIG74_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x128 0.--3. "PADCONFIG74_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x12C "CFG0_PADCONFIG75_PROXY,"
bitfld.long 0x12C 31. "PADCONFIG75_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x12C 30. "PADCONFIG75_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x12C 29. "PADCONFIG75_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x12C 28. "PADCONFIG75_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x12C 27. "PADCONFIG75_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x12C 26. "PADCONFIG75_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x12C 25. "PADCONFIG75_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x12C 24. "PADCONFIG75_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x12C 23. "PADCONFIG75_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x12C 22. "PADCONFIG75_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x12C 21. "PADCONFIG75_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x12C 19.--20. "PADCONFIG75_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x12C 18. "PADCONFIG75_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x12C 17. "PADCONFIG75_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x12C 16. "PADCONFIG75_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x12C 15. "PADCONFIG75_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x12C 14. "PADCONFIG75_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x12C 11.--13. "PADCONFIG75_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x12C 8. "PADCONFIG75_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x12C 7. "PADCONFIG75_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x12C 0.--3. "PADCONFIG75_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x130 "CFG0_PADCONFIG76_PROXY,"
bitfld.long 0x130 31. "PADCONFIG76_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x130 30. "PADCONFIG76_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x130 29. "PADCONFIG76_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x130 28. "PADCONFIG76_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x130 27. "PADCONFIG76_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x130 26. "PADCONFIG76_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x130 25. "PADCONFIG76_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x130 24. "PADCONFIG76_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x130 23. "PADCONFIG76_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x130 22. "PADCONFIG76_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x130 21. "PADCONFIG76_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x130 19.--20. "PADCONFIG76_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x130 18. "PADCONFIG76_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x130 17. "PADCONFIG76_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x130 16. "PADCONFIG76_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x130 15. "PADCONFIG76_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x130 14. "PADCONFIG76_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x130 11.--13. "PADCONFIG76_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x130 8. "PADCONFIG76_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x130 7. "PADCONFIG76_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x130 0.--3. "PADCONFIG76_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x134 "CFG0_PADCONFIG77_PROXY,"
bitfld.long 0x134 31. "PADCONFIG77_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x134 30. "PADCONFIG77_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x134 29. "PADCONFIG77_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x134 28. "PADCONFIG77_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x134 27. "PADCONFIG77_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x134 26. "PADCONFIG77_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x134 25. "PADCONFIG77_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x134 24. "PADCONFIG77_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x134 23. "PADCONFIG77_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x134 22. "PADCONFIG77_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x134 21. "PADCONFIG77_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x134 19.--20. "PADCONFIG77_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x134 18. "PADCONFIG77_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x134 17. "PADCONFIG77_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x134 16. "PADCONFIG77_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x134 15. "PADCONFIG77_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x134 14. "PADCONFIG77_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x134 11.--13. "PADCONFIG77_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x134 8. "PADCONFIG77_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x134 7. "PADCONFIG77_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x134 0.--3. "PADCONFIG77_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x138 "CFG0_PADCONFIG78_PROXY,"
bitfld.long 0x138 31. "PADCONFIG78_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x138 30. "PADCONFIG78_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x138 29. "PADCONFIG78_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x138 28. "PADCONFIG78_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x138 27. "PADCONFIG78_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x138 26. "PADCONFIG78_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x138 25. "PADCONFIG78_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x138 24. "PADCONFIG78_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x138 23. "PADCONFIG78_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x138 22. "PADCONFIG78_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x138 21. "PADCONFIG78_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x138 19.--20. "PADCONFIG78_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x138 18. "PADCONFIG78_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x138 17. "PADCONFIG78_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x138 16. "PADCONFIG78_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x138 15. "PADCONFIG78_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x138 14. "PADCONFIG78_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x138 11.--13. "PADCONFIG78_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x138 8. "PADCONFIG78_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x138 7. "PADCONFIG78_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x138 0.--3. "PADCONFIG78_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x13C "CFG0_PADCONFIG79_PROXY,"
bitfld.long 0x13C 31. "PADCONFIG79_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x13C 30. "PADCONFIG79_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x13C 29. "PADCONFIG79_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x13C 28. "PADCONFIG79_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x13C 27. "PADCONFIG79_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x13C 26. "PADCONFIG79_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x13C 25. "PADCONFIG79_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x13C 24. "PADCONFIG79_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x13C 23. "PADCONFIG79_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x13C 22. "PADCONFIG79_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x13C 21. "PADCONFIG79_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x13C 19.--20. "PADCONFIG79_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x13C 18. "PADCONFIG79_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x13C 17. "PADCONFIG79_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x13C 16. "PADCONFIG79_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x13C 15. "PADCONFIG79_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x13C 14. "PADCONFIG79_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x13C 11.--13. "PADCONFIG79_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x13C 8. "PADCONFIG79_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x13C 7. "PADCONFIG79_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x13C 0.--3. "PADCONFIG79_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x140 "CFG0_PADCONFIG80_PROXY,"
bitfld.long 0x140 31. "PADCONFIG80_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x140 30. "PADCONFIG80_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x140 29. "PADCONFIG80_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x140 28. "PADCONFIG80_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x140 27. "PADCONFIG80_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x140 26. "PADCONFIG80_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x140 25. "PADCONFIG80_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x140 24. "PADCONFIG80_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x140 23. "PADCONFIG80_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x140 22. "PADCONFIG80_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x140 21. "PADCONFIG80_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x140 19.--20. "PADCONFIG80_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x140 18. "PADCONFIG80_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x140 17. "PADCONFIG80_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x140 16. "PADCONFIG80_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x140 15. "PADCONFIG80_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x140 14. "PADCONFIG80_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x140 11.--13. "PADCONFIG80_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 8. "PADCONFIG80_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x140 7. "PADCONFIG80_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x140 0.--3. "PADCONFIG80_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x144 "CFG0_PADCONFIG81_PROXY,"
bitfld.long 0x144 31. "PADCONFIG81_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x144 30. "PADCONFIG81_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x144 29. "PADCONFIG81_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x144 28. "PADCONFIG81_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x144 27. "PADCONFIG81_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x144 26. "PADCONFIG81_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x144 25. "PADCONFIG81_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x144 24. "PADCONFIG81_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x144 23. "PADCONFIG81_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x144 22. "PADCONFIG81_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x144 21. "PADCONFIG81_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x144 19.--20. "PADCONFIG81_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x144 18. "PADCONFIG81_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x144 17. "PADCONFIG81_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x144 16. "PADCONFIG81_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x144 15. "PADCONFIG81_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x144 14. "PADCONFIG81_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x144 11.--13. "PADCONFIG81_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 8. "PADCONFIG81_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x144 7. "PADCONFIG81_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x144 0.--3. "PADCONFIG81_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x148 "CFG0_PADCONFIG82_PROXY,"
bitfld.long 0x148 31. "PADCONFIG82_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x148 30. "PADCONFIG82_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x148 29. "PADCONFIG82_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x148 28. "PADCONFIG82_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x148 27. "PADCONFIG82_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x148 26. "PADCONFIG82_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x148 25. "PADCONFIG82_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x148 24. "PADCONFIG82_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x148 23. "PADCONFIG82_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x148 22. "PADCONFIG82_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x148 21. "PADCONFIG82_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x148 19.--20. "PADCONFIG82_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x148 18. "PADCONFIG82_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x148 17. "PADCONFIG82_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x148 16. "PADCONFIG82_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x148 15. "PADCONFIG82_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x148 14. "PADCONFIG82_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x148 11.--13. "PADCONFIG82_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x148 8. "PADCONFIG82_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x148 7. "PADCONFIG82_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x148 0.--3. "PADCONFIG82_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x14C "CFG0_PADCONFIG83_PROXY,"
bitfld.long 0x14C 31. "PADCONFIG83_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x14C 30. "PADCONFIG83_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x14C 29. "PADCONFIG83_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x14C 28. "PADCONFIG83_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x14C 27. "PADCONFIG83_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x14C 26. "PADCONFIG83_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x14C 25. "PADCONFIG83_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x14C 24. "PADCONFIG83_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x14C 23. "PADCONFIG83_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x14C 22. "PADCONFIG83_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x14C 21. "PADCONFIG83_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x14C 19.--20. "PADCONFIG83_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x14C 18. "PADCONFIG83_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x14C 17. "PADCONFIG83_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x14C 16. "PADCONFIG83_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x14C 15. "PADCONFIG83_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x14C 14. "PADCONFIG83_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x14C 11.--13. "PADCONFIG83_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14C 8. "PADCONFIG83_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x14C 7. "PADCONFIG83_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x14C 0.--3. "PADCONFIG83_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x150 "CFG0_PADCONFIG84_PROXY,"
bitfld.long 0x150 31. "PADCONFIG84_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x150 30. "PADCONFIG84_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x150 29. "PADCONFIG84_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x150 28. "PADCONFIG84_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x150 27. "PADCONFIG84_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x150 26. "PADCONFIG84_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x150 25. "PADCONFIG84_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x150 24. "PADCONFIG84_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x150 23. "PADCONFIG84_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x150 22. "PADCONFIG84_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x150 21. "PADCONFIG84_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x150 19.--20. "PADCONFIG84_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x150 18. "PADCONFIG84_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x150 17. "PADCONFIG84_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x150 16. "PADCONFIG84_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x150 15. "PADCONFIG84_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x150 14. "PADCONFIG84_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x150 11.--13. "PADCONFIG84_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x150 8. "PADCONFIG84_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x150 7. "PADCONFIG84_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x150 0.--3. "PADCONFIG84_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x154 "CFG0_PADCONFIG85_PROXY,"
bitfld.long 0x154 31. "PADCONFIG85_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x154 30. "PADCONFIG85_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x154 29. "PADCONFIG85_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x154 28. "PADCONFIG85_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x154 27. "PADCONFIG85_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x154 26. "PADCONFIG85_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x154 25. "PADCONFIG85_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x154 24. "PADCONFIG85_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x154 23. "PADCONFIG85_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x154 22. "PADCONFIG85_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x154 21. "PADCONFIG85_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x154 19.--20. "PADCONFIG85_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x154 18. "PADCONFIG85_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x154 17. "PADCONFIG85_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x154 16. "PADCONFIG85_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x154 15. "PADCONFIG85_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x154 14. "PADCONFIG85_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x154 11.--13. "PADCONFIG85_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x154 8. "PADCONFIG85_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x154 7. "PADCONFIG85_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x154 0.--3. "PADCONFIG85_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x158 "CFG0_PADCONFIG86_PROXY,"
bitfld.long 0x158 31. "PADCONFIG86_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x158 30. "PADCONFIG86_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x158 29. "PADCONFIG86_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x158 28. "PADCONFIG86_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x158 27. "PADCONFIG86_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x158 26. "PADCONFIG86_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x158 25. "PADCONFIG86_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x158 24. "PADCONFIG86_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x158 23. "PADCONFIG86_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x158 22. "PADCONFIG86_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x158 21. "PADCONFIG86_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x158 19.--20. "PADCONFIG86_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x158 18. "PADCONFIG86_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x158 17. "PADCONFIG86_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x158 16. "PADCONFIG86_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x158 15. "PADCONFIG86_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x158 14. "PADCONFIG86_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x158 11.--13. "PADCONFIG86_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x158 8. "PADCONFIG86_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x158 7. "PADCONFIG86_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x158 0.--3. "PADCONFIG86_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x15C "CFG0_PADCONFIG87_PROXY,"
bitfld.long 0x15C 31. "PADCONFIG87_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x15C 30. "PADCONFIG87_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x15C 29. "PADCONFIG87_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x15C 28. "PADCONFIG87_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x15C 27. "PADCONFIG87_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x15C 26. "PADCONFIG87_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x15C 25. "PADCONFIG87_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x15C 24. "PADCONFIG87_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x15C 23. "PADCONFIG87_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x15C 22. "PADCONFIG87_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x15C 21. "PADCONFIG87_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x15C 19.--20. "PADCONFIG87_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x15C 18. "PADCONFIG87_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x15C 17. "PADCONFIG87_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x15C 16. "PADCONFIG87_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x15C 15. "PADCONFIG87_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x15C 14. "PADCONFIG87_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x15C 11.--13. "PADCONFIG87_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x15C 8. "PADCONFIG87_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x15C 7. "PADCONFIG87_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x15C 0.--3. "PADCONFIG87_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x160 "CFG0_PADCONFIG88_PROXY,"
bitfld.long 0x160 31. "PADCONFIG88_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x160 30. "PADCONFIG88_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x160 29. "PADCONFIG88_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x160 28. "PADCONFIG88_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x160 27. "PADCONFIG88_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x160 26. "PADCONFIG88_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x160 25. "PADCONFIG88_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x160 24. "PADCONFIG88_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x160 23. "PADCONFIG88_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x160 22. "PADCONFIG88_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x160 21. "PADCONFIG88_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x160 19.--20. "PADCONFIG88_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x160 18. "PADCONFIG88_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x160 17. "PADCONFIG88_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x160 16. "PADCONFIG88_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x160 15. "PADCONFIG88_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x160 14. "PADCONFIG88_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x160 11.--13. "PADCONFIG88_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x160 8. "PADCONFIG88_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x160 7. "PADCONFIG88_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x160 0.--3. "PADCONFIG88_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x164 "CFG0_PADCONFIG89_PROXY,"
bitfld.long 0x164 31. "PADCONFIG89_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x164 30. "PADCONFIG89_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x164 29. "PADCONFIG89_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x164 28. "PADCONFIG89_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x164 27. "PADCONFIG89_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x164 26. "PADCONFIG89_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x164 25. "PADCONFIG89_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x164 24. "PADCONFIG89_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x164 23. "PADCONFIG89_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x164 22. "PADCONFIG89_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x164 21. "PADCONFIG89_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x164 19.--20. "PADCONFIG89_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x164 18. "PADCONFIG89_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x164 17. "PADCONFIG89_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x164 16. "PADCONFIG89_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x164 15. "PADCONFIG89_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x164 14. "PADCONFIG89_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x164 11.--13. "PADCONFIG89_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x164 8. "PADCONFIG89_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x164 7. "PADCONFIG89_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x164 0.--3. "PADCONFIG89_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x168 "CFG0_PADCONFIG90_PROXY,"
bitfld.long 0x168 31. "PADCONFIG90_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x168 30. "PADCONFIG90_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x168 29. "PADCONFIG90_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x168 28. "PADCONFIG90_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x168 27. "PADCONFIG90_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x168 26. "PADCONFIG90_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x168 25. "PADCONFIG90_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x168 24. "PADCONFIG90_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x168 23. "PADCONFIG90_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x168 22. "PADCONFIG90_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x168 21. "PADCONFIG90_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x168 19.--20. "PADCONFIG90_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x168 18. "PADCONFIG90_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x168 17. "PADCONFIG90_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x168 16. "PADCONFIG90_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x168 15. "PADCONFIG90_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x168 14. "PADCONFIG90_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x168 11.--13. "PADCONFIG90_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x168 8. "PADCONFIG90_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x168 7. "PADCONFIG90_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x168 0.--3. "PADCONFIG90_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x16C "CFG0_PADCONFIG91_PROXY,"
bitfld.long 0x16C 31. "PADCONFIG91_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x16C 30. "PADCONFIG91_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x16C 29. "PADCONFIG91_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x16C 28. "PADCONFIG91_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x16C 27. "PADCONFIG91_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x16C 26. "PADCONFIG91_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x16C 25. "PADCONFIG91_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x16C 24. "PADCONFIG91_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x16C 23. "PADCONFIG91_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x16C 22. "PADCONFIG91_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x16C 21. "PADCONFIG91_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x16C 19.--20. "PADCONFIG91_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x16C 18. "PADCONFIG91_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x16C 17. "PADCONFIG91_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x16C 16. "PADCONFIG91_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x16C 15. "PADCONFIG91_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x16C 14. "PADCONFIG91_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x16C 11.--13. "PADCONFIG91_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x16C 8. "PADCONFIG91_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x16C 7. "PADCONFIG91_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x16C 0.--3. "PADCONFIG91_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x170 "CFG0_PADCONFIG92_PROXY,"
bitfld.long 0x170 31. "PADCONFIG92_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x170 30. "PADCONFIG92_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x170 29. "PADCONFIG92_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x170 28. "PADCONFIG92_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x170 27. "PADCONFIG92_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x170 26. "PADCONFIG92_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x170 25. "PADCONFIG92_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x170 24. "PADCONFIG92_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x170 23. "PADCONFIG92_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x170 22. "PADCONFIG92_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x170 21. "PADCONFIG92_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x170 19.--20. "PADCONFIG92_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x170 18. "PADCONFIG92_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x170 17. "PADCONFIG92_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x170 16. "PADCONFIG92_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x170 15. "PADCONFIG92_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x170 14. "PADCONFIG92_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x170 11.--13. "PADCONFIG92_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x170 8. "PADCONFIG92_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x170 7. "PADCONFIG92_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x170 0.--3. "PADCONFIG92_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x174 "CFG0_PADCONFIG93_PROXY,"
bitfld.long 0x174 31. "PADCONFIG93_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x174 30. "PADCONFIG93_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x174 29. "PADCONFIG93_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x174 28. "PADCONFIG93_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x174 27. "PADCONFIG93_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x174 26. "PADCONFIG93_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x174 25. "PADCONFIG93_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x174 24. "PADCONFIG93_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x174 23. "PADCONFIG93_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x174 22. "PADCONFIG93_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x174 21. "PADCONFIG93_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x174 19.--20. "PADCONFIG93_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x174 18. "PADCONFIG93_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x174 17. "PADCONFIG93_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x174 16. "PADCONFIG93_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x174 15. "PADCONFIG93_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x174 14. "PADCONFIG93_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x174 11.--13. "PADCONFIG93_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x174 8. "PADCONFIG93_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x174 7. "PADCONFIG93_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x174 0.--3. "PADCONFIG93_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x178 "CFG0_PADCONFIG94_PROXY,"
bitfld.long 0x178 31. "PADCONFIG94_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x178 30. "PADCONFIG94_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x178 29. "PADCONFIG94_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x178 28. "PADCONFIG94_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x178 27. "PADCONFIG94_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x178 26. "PADCONFIG94_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x178 25. "PADCONFIG94_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x178 24. "PADCONFIG94_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x178 23. "PADCONFIG94_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x178 22. "PADCONFIG94_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x178 21. "PADCONFIG94_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x178 19.--20. "PADCONFIG94_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x178 18. "PADCONFIG94_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x178 17. "PADCONFIG94_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x178 16. "PADCONFIG94_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x178 15. "PADCONFIG94_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x178 14. "PADCONFIG94_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x178 11.--13. "PADCONFIG94_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x178 8. "PADCONFIG94_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x178 7. "PADCONFIG94_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x178 0.--3. "PADCONFIG94_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x17C "CFG0_PADCONFIG95_PROXY,"
bitfld.long 0x17C 31. "PADCONFIG95_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x17C 30. "PADCONFIG95_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x17C 29. "PADCONFIG95_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x17C 28. "PADCONFIG95_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x17C 27. "PADCONFIG95_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x17C 26. "PADCONFIG95_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x17C 25. "PADCONFIG95_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x17C 24. "PADCONFIG95_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x17C 23. "PADCONFIG95_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x17C 22. "PADCONFIG95_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x17C 21. "PADCONFIG95_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x17C 19.--20. "PADCONFIG95_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x17C 18. "PADCONFIG95_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x17C 17. "PADCONFIG95_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x17C 16. "PADCONFIG95_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x17C 15. "PADCONFIG95_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x17C 14. "PADCONFIG95_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x17C 11.--13. "PADCONFIG95_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x17C 8. "PADCONFIG95_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x17C 7. "PADCONFIG95_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x17C 0.--3. "PADCONFIG95_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x180 "CFG0_PADCONFIG96_PROXY,"
bitfld.long 0x180 31. "PADCONFIG96_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x180 30. "PADCONFIG96_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x180 29. "PADCONFIG96_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x180 28. "PADCONFIG96_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x180 27. "PADCONFIG96_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x180 26. "PADCONFIG96_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x180 25. "PADCONFIG96_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x180 24. "PADCONFIG96_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x180 23. "PADCONFIG96_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x180 22. "PADCONFIG96_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x180 21. "PADCONFIG96_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x180 19.--20. "PADCONFIG96_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x180 18. "PADCONFIG96_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x180 17. "PADCONFIG96_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x180 16. "PADCONFIG96_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x180 15. "PADCONFIG96_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x180 14. "PADCONFIG96_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x180 11.--13. "PADCONFIG96_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x180 8. "PADCONFIG96_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x180 7. "PADCONFIG96_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x180 0.--3. "PADCONFIG96_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x184 "CFG0_PADCONFIG97_PROXY,"
bitfld.long 0x184 31. "PADCONFIG97_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x184 30. "PADCONFIG97_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x184 29. "PADCONFIG97_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x184 28. "PADCONFIG97_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x184 27. "PADCONFIG97_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x184 26. "PADCONFIG97_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x184 25. "PADCONFIG97_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x184 24. "PADCONFIG97_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x184 23. "PADCONFIG97_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x184 22. "PADCONFIG97_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x184 21. "PADCONFIG97_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x184 19.--20. "PADCONFIG97_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x184 18. "PADCONFIG97_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x184 17. "PADCONFIG97_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x184 16. "PADCONFIG97_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x184 15. "PADCONFIG97_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x184 14. "PADCONFIG97_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x184 11.--13. "PADCONFIG97_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x184 8. "PADCONFIG97_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x184 7. "PADCONFIG97_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x184 0.--3. "PADCONFIG97_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x188 "CFG0_PADCONFIG98_PROXY,"
bitfld.long 0x188 31. "PADCONFIG98_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x188 30. "PADCONFIG98_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x188 29. "PADCONFIG98_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x188 28. "PADCONFIG98_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x188 27. "PADCONFIG98_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x188 26. "PADCONFIG98_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x188 25. "PADCONFIG98_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x188 24. "PADCONFIG98_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x188 23. "PADCONFIG98_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x188 22. "PADCONFIG98_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x188 21. "PADCONFIG98_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x188 19.--20. "PADCONFIG98_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x188 18. "PADCONFIG98_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x188 17. "PADCONFIG98_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x188 16. "PADCONFIG98_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x188 15. "PADCONFIG98_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x188 14. "PADCONFIG98_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x188 11.--13. "PADCONFIG98_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x188 8. "PADCONFIG98_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x188 7. "PADCONFIG98_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x188 0.--3. "PADCONFIG98_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x18C "CFG0_PADCONFIG99_PROXY,"
bitfld.long 0x18C 31. "PADCONFIG99_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x18C 30. "PADCONFIG99_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x18C 29. "PADCONFIG99_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x18C 28. "PADCONFIG99_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x18C 27. "PADCONFIG99_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x18C 26. "PADCONFIG99_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x18C 25. "PADCONFIG99_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x18C 24. "PADCONFIG99_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x18C 23. "PADCONFIG99_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x18C 22. "PADCONFIG99_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x18C 21. "PADCONFIG99_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x18C 19.--20. "PADCONFIG99_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x18C 18. "PADCONFIG99_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x18C 17. "PADCONFIG99_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x18C 16. "PADCONFIG99_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x18C 15. "PADCONFIG99_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x18C 14. "PADCONFIG99_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x18C 11.--13. "PADCONFIG99_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18C 8. "PADCONFIG99_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x18C 7. "PADCONFIG99_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x18C 0.--3. "PADCONFIG99_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x190 "CFG0_PADCONFIG100_PROXY,"
bitfld.long 0x190 31. "PADCONFIG100_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x190 30. "PADCONFIG100_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x190 29. "PADCONFIG100_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x190 28. "PADCONFIG100_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x190 27. "PADCONFIG100_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x190 26. "PADCONFIG100_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x190 25. "PADCONFIG100_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x190 24. "PADCONFIG100_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x190 23. "PADCONFIG100_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x190 22. "PADCONFIG100_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x190 21. "PADCONFIG100_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x190 19.--20. "PADCONFIG100_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x190 18. "PADCONFIG100_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x190 17. "PADCONFIG100_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x190 16. "PADCONFIG100_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x190 15. "PADCONFIG100_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x190 14. "PADCONFIG100_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x190 11.--13. "PADCONFIG100_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x190 8. "PADCONFIG100_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x190 7. "PADCONFIG100_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x190 0.--3. "PADCONFIG100_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x194 "CFG0_PADCONFIG101_PROXY,"
bitfld.long 0x194 31. "PADCONFIG101_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x194 30. "PADCONFIG101_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x194 29. "PADCONFIG101_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x194 28. "PADCONFIG101_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x194 27. "PADCONFIG101_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x194 26. "PADCONFIG101_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x194 25. "PADCONFIG101_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x194 24. "PADCONFIG101_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x194 23. "PADCONFIG101_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x194 22. "PADCONFIG101_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x194 21. "PADCONFIG101_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x194 19.--20. "PADCONFIG101_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x194 18. "PADCONFIG101_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x194 17. "PADCONFIG101_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x194 16. "PADCONFIG101_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x194 15. "PADCONFIG101_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x194 14. "PADCONFIG101_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x194 11.--13. "PADCONFIG101_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x194 8. "PADCONFIG101_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x194 7. "PADCONFIG101_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x194 0.--3. "PADCONFIG101_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x198 "CFG0_PADCONFIG102_PROXY,"
bitfld.long 0x198 31. "PADCONFIG102_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x198 30. "PADCONFIG102_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x198 29. "PADCONFIG102_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x198 28. "PADCONFIG102_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x198 27. "PADCONFIG102_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x198 26. "PADCONFIG102_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x198 25. "PADCONFIG102_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x198 24. "PADCONFIG102_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x198 23. "PADCONFIG102_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x198 22. "PADCONFIG102_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x198 21. "PADCONFIG102_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x198 19.--20. "PADCONFIG102_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x198 18. "PADCONFIG102_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x198 17. "PADCONFIG102_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x198 16. "PADCONFIG102_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x198 15. "PADCONFIG102_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x198 14. "PADCONFIG102_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x198 11.--13. "PADCONFIG102_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x198 8. "PADCONFIG102_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x198 7. "PADCONFIG102_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x198 0.--3. "PADCONFIG102_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x19C "CFG0_PADCONFIG103_PROXY,"
bitfld.long 0x19C 31. "PADCONFIG103_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x19C 30. "PADCONFIG103_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x19C 29. "PADCONFIG103_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x19C 28. "PADCONFIG103_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x19C 27. "PADCONFIG103_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x19C 26. "PADCONFIG103_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x19C 25. "PADCONFIG103_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x19C 24. "PADCONFIG103_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x19C 23. "PADCONFIG103_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x19C 22. "PADCONFIG103_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x19C 21. "PADCONFIG103_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x19C 19.--20. "PADCONFIG103_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x19C 18. "PADCONFIG103_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x19C 17. "PADCONFIG103_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x19C 16. "PADCONFIG103_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x19C 15. "PADCONFIG103_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x19C 14. "PADCONFIG103_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x19C 11.--13. "PADCONFIG103_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x19C 8. "PADCONFIG103_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x19C 7. "PADCONFIG103_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x19C 0.--3. "PADCONFIG103_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1A0 "CFG0_PADCONFIG104_PROXY,"
bitfld.long 0x1A0 31. "PADCONFIG104_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x1A0 30. "PADCONFIG104_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x1A0 29. "PADCONFIG104_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x1A0 28. "PADCONFIG104_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x1A0 27. "PADCONFIG104_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x1A0 26. "PADCONFIG104_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x1A0 25. "PADCONFIG104_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x1A0 24. "PADCONFIG104_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x1A0 23. "PADCONFIG104_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x1A0 22. "PADCONFIG104_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x1A0 21. "PADCONFIG104_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x1A0 19.--20. "PADCONFIG104_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x1A0 18. "PADCONFIG104_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x1A0 17. "PADCONFIG104_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x1A0 16. "PADCONFIG104_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x1A0 15. "PADCONFIG104_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x1A0 14. "PADCONFIG104_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x1A0 11.--13. "PADCONFIG104_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1A0 8. "PADCONFIG104_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x1A0 7. "PADCONFIG104_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x1A0 0.--3. "PADCONFIG104_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1A4 "CFG0_PADCONFIG105_PROXY,"
bitfld.long 0x1A4 31. "PADCONFIG105_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x1A4 30. "PADCONFIG105_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x1A4 29. "PADCONFIG105_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x1A4 28. "PADCONFIG105_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x1A4 27. "PADCONFIG105_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x1A4 26. "PADCONFIG105_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x1A4 25. "PADCONFIG105_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x1A4 24. "PADCONFIG105_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x1A4 23. "PADCONFIG105_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x1A4 22. "PADCONFIG105_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1A4 21. "PADCONFIG105_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1A4 19.--20. "PADCONFIG105_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1A4 18. "PADCONFIG105_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1A4 17. "PADCONFIG105_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1A4 16. "PADCONFIG105_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1A4 15. "PADCONFIG105_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1A4 14. "PADCONFIG105_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1A4 11.--13. "PADCONFIG105_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1A4 8. "PADCONFIG105_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1A4 7. "PADCONFIG105_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1A4 0.--3. "PADCONFIG105_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1A8 "CFG0_PADCONFIG106_PROXY,"
bitfld.long 0x1A8 31. "PADCONFIG106_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1A8 30. "PADCONFIG106_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1A8 29. "PADCONFIG106_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1A8 28. "PADCONFIG106_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1A8 27. "PADCONFIG106_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1A8 26. "PADCONFIG106_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1A8 25. "PADCONFIG106_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1A8 24. "PADCONFIG106_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1A8 23. "PADCONFIG106_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1A8 22. "PADCONFIG106_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1A8 21. "PADCONFIG106_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1A8 19.--20. "PADCONFIG106_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1A8 18. "PADCONFIG106_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1A8 17. "PADCONFIG106_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1A8 16. "PADCONFIG106_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1A8 15. "PADCONFIG106_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1A8 14. "PADCONFIG106_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1A8 11.--13. "PADCONFIG106_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1A8 8. "PADCONFIG106_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1A8 7. "PADCONFIG106_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1A8 0.--3. "PADCONFIG106_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1AC "CFG0_PADCONFIG107_PROXY,"
bitfld.long 0x1AC 31. "PADCONFIG107_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1AC 30. "PADCONFIG107_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1AC 29. "PADCONFIG107_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1AC 28. "PADCONFIG107_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1AC 27. "PADCONFIG107_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1AC 26. "PADCONFIG107_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1AC 25. "PADCONFIG107_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1AC 24. "PADCONFIG107_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1AC 23. "PADCONFIG107_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1AC 22. "PADCONFIG107_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1AC 21. "PADCONFIG107_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1AC 19.--20. "PADCONFIG107_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1AC 18. "PADCONFIG107_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1AC 17. "PADCONFIG107_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1AC 16. "PADCONFIG107_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1AC 15. "PADCONFIG107_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1AC 14. "PADCONFIG107_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1AC 11.--13. "PADCONFIG107_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1AC 8. "PADCONFIG107_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1AC 7. "PADCONFIG107_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1AC 0.--3. "PADCONFIG107_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1B0 "CFG0_PADCONFIG108_PROXY,"
bitfld.long 0x1B0 31. "PADCONFIG108_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1B0 30. "PADCONFIG108_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1B0 29. "PADCONFIG108_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1B0 28. "PADCONFIG108_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1B0 27. "PADCONFIG108_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1B0 26. "PADCONFIG108_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1B0 25. "PADCONFIG108_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1B0 24. "PADCONFIG108_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1B0 23. "PADCONFIG108_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1B0 22. "PADCONFIG108_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1B0 21. "PADCONFIG108_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1B0 19.--20. "PADCONFIG108_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1B0 18. "PADCONFIG108_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1B0 17. "PADCONFIG108_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1B0 16. "PADCONFIG108_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1B0 15. "PADCONFIG108_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1B0 14. "PADCONFIG108_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1B0 11.--13. "PADCONFIG108_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1B0 8. "PADCONFIG108_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1B0 7. "PADCONFIG108_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1B0 0.--3. "PADCONFIG108_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1B4 "CFG0_PADCONFIG109_PROXY,"
bitfld.long 0x1B4 31. "PADCONFIG109_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1B4 30. "PADCONFIG109_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1B4 29. "PADCONFIG109_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1B4 28. "PADCONFIG109_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1B4 27. "PADCONFIG109_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1B4 26. "PADCONFIG109_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1B4 25. "PADCONFIG109_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1B4 24. "PADCONFIG109_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1B4 23. "PADCONFIG109_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1B4 22. "PADCONFIG109_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1B4 21. "PADCONFIG109_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1B4 19.--20. "PADCONFIG109_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1B4 18. "PADCONFIG109_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1B4 17. "PADCONFIG109_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1B4 16. "PADCONFIG109_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1B4 15. "PADCONFIG109_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1B4 14. "PADCONFIG109_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1B4 11.--13. "PADCONFIG109_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1B4 8. "PADCONFIG109_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1B4 7. "PADCONFIG109_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1B4 0.--3. "PADCONFIG109_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1B8 "CFG0_PADCONFIG110_PROXY,"
bitfld.long 0x1B8 31. "PADCONFIG110_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1B8 30. "PADCONFIG110_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1B8 29. "PADCONFIG110_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1B8 28. "PADCONFIG110_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1B8 27. "PADCONFIG110_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1B8 26. "PADCONFIG110_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1B8 25. "PADCONFIG110_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1B8 24. "PADCONFIG110_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1B8 23. "PADCONFIG110_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1B8 22. "PADCONFIG110_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1B8 21. "PADCONFIG110_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1B8 19.--20. "PADCONFIG110_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1B8 18. "PADCONFIG110_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1B8 17. "PADCONFIG110_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1B8 16. "PADCONFIG110_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1B8 15. "PADCONFIG110_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1B8 14. "PADCONFIG110_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1B8 11.--13. "PADCONFIG110_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1B8 8. "PADCONFIG110_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1B8 7. "PADCONFIG110_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1B8 0.--3. "PADCONFIG110_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1BC "CFG0_PADCONFIG111_PROXY,"
bitfld.long 0x1BC 31. "PADCONFIG111_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1BC 30. "PADCONFIG111_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1BC 29. "PADCONFIG111_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1BC 28. "PADCONFIG111_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1BC 27. "PADCONFIG111_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1BC 26. "PADCONFIG111_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x1BC 25. "PADCONFIG111_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1BC 24. "PADCONFIG111_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1BC 23. "PADCONFIG111_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1BC 22. "PADCONFIG111_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x1BC 21. "PADCONFIG111_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1BC 19.--20. "PADCONFIG111_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1BC 18. "PADCONFIG111_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1BC 17. "PADCONFIG111_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1BC 16. "PADCONFIG111_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1BC 15. "PADCONFIG111_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1BC 14. "PADCONFIG111_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1BC 11.--13. "PADCONFIG111_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1BC 8. "PADCONFIG111_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1BC 7. "PADCONFIG111_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1BC 0.--3. "PADCONFIG111_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C0 "CFG0_PADCONFIG112_PROXY,"
bitfld.long 0x1C0 31. "PADCONFIG112_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C0 30. "PADCONFIG112_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C0 29. "PADCONFIG112_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1C0 28. "PADCONFIG112_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1C0 27. "PADCONFIG112_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C0 26. "PADCONFIG112_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1C0 25. "PADCONFIG112_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C0 24. "PADCONFIG112_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1C0 23. "PADCONFIG112_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1C0 22. "PADCONFIG112_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1C0 21. "PADCONFIG112_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1C0 19.--20. "PADCONFIG112_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1C0 18. "PADCONFIG112_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1C0 17. "PADCONFIG112_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1C0 16. "PADCONFIG112_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C0 15. "PADCONFIG112_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1C0 14. "PADCONFIG112_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C0 11.--13. "PADCONFIG112_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C0 8. "PADCONFIG112_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1C0 7. "PADCONFIG112_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1C0 0.--3. "PADCONFIG112_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C4 "CFG0_PADCONFIG113_PROXY,"
bitfld.long 0x1C4 31. "PADCONFIG113_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C4 30. "PADCONFIG113_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C4 29. "PADCONFIG113_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1C4 28. "PADCONFIG113_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1C4 27. "PADCONFIG113_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C4 26. "PADCONFIG113_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1C4 25. "PADCONFIG113_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C4 24. "PADCONFIG113_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1C4 23. "PADCONFIG113_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1C4 22. "PADCONFIG113_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1C4 21. "PADCONFIG113_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1C4 19.--20. "PADCONFIG113_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1C4 18. "PADCONFIG113_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1C4 17. "PADCONFIG113_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1C4 16. "PADCONFIG113_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C4 15. "PADCONFIG113_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1C4 14. "PADCONFIG113_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C4 11.--13. "PADCONFIG113_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C4 8. "PADCONFIG113_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1C4 7. "PADCONFIG113_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1C4 0.--3. "PADCONFIG113_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1C8 "CFG0_PADCONFIG114_PROXY,"
bitfld.long 0x1C8 31. "PADCONFIG114_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1C8 30. "PADCONFIG114_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1C8 29. "PADCONFIG114_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1C8 28. "PADCONFIG114_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1C8 27. "PADCONFIG114_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1C8 26. "PADCONFIG114_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1C8 25. "PADCONFIG114_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1C8 24. "PADCONFIG114_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1C8 23. "PADCONFIG114_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1C8 22. "PADCONFIG114_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1C8 21. "PADCONFIG114_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1C8 19.--20. "PADCONFIG114_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1C8 18. "PADCONFIG114_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1C8 17. "PADCONFIG114_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1C8 16. "PADCONFIG114_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1C8 15. "PADCONFIG114_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1C8 14. "PADCONFIG114_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1C8 11.--13. "PADCONFIG114_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1C8 8. "PADCONFIG114_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1C8 7. "PADCONFIG114_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1C8 0.--3. "PADCONFIG114_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1CC "CFG0_PADCONFIG115_PROXY,"
bitfld.long 0x1CC 31. "PADCONFIG115_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1CC 30. "PADCONFIG115_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1CC 29. "PADCONFIG115_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1CC 28. "PADCONFIG115_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1CC 27. "PADCONFIG115_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1CC 26. "PADCONFIG115_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1CC 25. "PADCONFIG115_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1CC 24. "PADCONFIG115_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1CC 23. "PADCONFIG115_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1CC 22. "PADCONFIG115_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1CC 21. "PADCONFIG115_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1CC 19.--20. "PADCONFIG115_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1CC 18. "PADCONFIG115_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1CC 17. "PADCONFIG115_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1CC 16. "PADCONFIG115_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1CC 15. "PADCONFIG115_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1CC 14. "PADCONFIG115_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1CC 11.--13. "PADCONFIG115_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1CC 8. "PADCONFIG115_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1CC 7. "PADCONFIG115_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1CC 0.--3. "PADCONFIG115_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1D0 "CFG0_PADCONFIG116_PROXY,"
bitfld.long 0x1D0 31. "PADCONFIG116_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1D0 30. "PADCONFIG116_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1D0 29. "PADCONFIG116_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1D0 28. "PADCONFIG116_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1D0 27. "PADCONFIG116_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1D0 26. "PADCONFIG116_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1D0 25. "PADCONFIG116_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1D0 24. "PADCONFIG116_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1D0 23. "PADCONFIG116_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1D0 22. "PADCONFIG116_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1D0 21. "PADCONFIG116_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1D0 19.--20. "PADCONFIG116_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1D0 18. "PADCONFIG116_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1D0 17. "PADCONFIG116_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1D0 16. "PADCONFIG116_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1D0 15. "PADCONFIG116_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1D0 14. "PADCONFIG116_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1D0 11.--13. "PADCONFIG116_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1D0 8. "PADCONFIG116_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1D0 7. "PADCONFIG116_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1D0 0.--3. "PADCONFIG116_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1D4 "CFG0_PADCONFIG117_PROXY,"
bitfld.long 0x1D4 31. "PADCONFIG117_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1D4 30. "PADCONFIG117_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1D4 29. "PADCONFIG117_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1D4 28. "PADCONFIG117_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1D4 27. "PADCONFIG117_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1D4 26. "PADCONFIG117_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1D4 25. "PADCONFIG117_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1D4 24. "PADCONFIG117_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1D4 23. "PADCONFIG117_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1D4 22. "PADCONFIG117_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1D4 21. "PADCONFIG117_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1D4 19.--20. "PADCONFIG117_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1D4 18. "PADCONFIG117_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1D4 17. "PADCONFIG117_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1D4 16. "PADCONFIG117_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1D4 15. "PADCONFIG117_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1D4 14. "PADCONFIG117_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1D4 11.--13. "PADCONFIG117_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1D4 8. "PADCONFIG117_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1D4 7. "PADCONFIG117_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1D4 0.--3. "PADCONFIG117_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1D8 "CFG0_PADCONFIG118_PROXY,"
bitfld.long 0x1D8 31. "PADCONFIG118_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1D8 30. "PADCONFIG118_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1D8 29. "PADCONFIG118_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1D8 28. "PADCONFIG118_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1D8 27. "PADCONFIG118_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1D8 26. "PADCONFIG118_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1D8 25. "PADCONFIG118_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1D8 24. "PADCONFIG118_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1D8 23. "PADCONFIG118_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1D8 22. "PADCONFIG118_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1D8 21. "PADCONFIG118_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1D8 19.--20. "PADCONFIG118_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1D8 18. "PADCONFIG118_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1D8 17. "PADCONFIG118_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1D8 16. "PADCONFIG118_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1D8 15. "PADCONFIG118_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1D8 14. "PADCONFIG118_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1D8 11.--13. "PADCONFIG118_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1D8 8. "PADCONFIG118_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1D8 7. "PADCONFIG118_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1D8 0.--3. "PADCONFIG118_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1DC "CFG0_PADCONFIG119_PROXY,"
bitfld.long 0x1DC 31. "PADCONFIG119_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1DC 30. "PADCONFIG119_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1DC 29. "PADCONFIG119_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1DC 28. "PADCONFIG119_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1DC 27. "PADCONFIG119_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1DC 26. "PADCONFIG119_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1DC 25. "PADCONFIG119_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1DC 24. "PADCONFIG119_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1DC 23. "PADCONFIG119_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1DC 22. "PADCONFIG119_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1DC 21. "PADCONFIG119_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1DC 19.--20. "PADCONFIG119_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1DC 18. "PADCONFIG119_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1DC 17. "PADCONFIG119_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1DC 16. "PADCONFIG119_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1DC 15. "PADCONFIG119_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1DC 14. "PADCONFIG119_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1DC 11.--13. "PADCONFIG119_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1DC 8. "PADCONFIG119_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1DC 7. "PADCONFIG119_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1DC 0.--3. "PADCONFIG119_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1E0 "CFG0_PADCONFIG120_PROXY,"
bitfld.long 0x1E0 31. "PADCONFIG120_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1E0 30. "PADCONFIG120_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1E0 29. "PADCONFIG120_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1E0 28. "PADCONFIG120_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1E0 27. "PADCONFIG120_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1E0 26. "PADCONFIG120_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1E0 25. "PADCONFIG120_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1E0 24. "PADCONFIG120_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1E0 23. "PADCONFIG120_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1E0 22. "PADCONFIG120_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1E0 21. "PADCONFIG120_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1E0 19.--20. "PADCONFIG120_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1E0 18. "PADCONFIG120_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1E0 17. "PADCONFIG120_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1E0 16. "PADCONFIG120_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1E0 15. "PADCONFIG120_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1E0 14. "PADCONFIG120_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1E0 11.--13. "PADCONFIG120_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1E0 8. "PADCONFIG120_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1E0 7. "PADCONFIG120_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1E0 0.--3. "PADCONFIG120_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1E4 "CFG0_PADCONFIG121_PROXY,"
bitfld.long 0x1E4 31. "PADCONFIG121_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1E4 30. "PADCONFIG121_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1E4 29. "PADCONFIG121_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1E4 28. "PADCONFIG121_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1E4 27. "PADCONFIG121_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1E4 26. "PADCONFIG121_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1E4 25. "PADCONFIG121_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1E4 24. "PADCONFIG121_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1E4 23. "PADCONFIG121_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1E4 22. "PADCONFIG121_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1E4 21. "PADCONFIG121_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1E4 19.--20. "PADCONFIG121_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1E4 18. "PADCONFIG121_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1E4 17. "PADCONFIG121_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1E4 16. "PADCONFIG121_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1E4 15. "PADCONFIG121_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1E4 14. "PADCONFIG121_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1E4 11.--13. "PADCONFIG121_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1E4 8. "PADCONFIG121_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1E4 7. "PADCONFIG121_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1E4 0.--3. "PADCONFIG121_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1E8 "CFG0_PADCONFIG122_PROXY,"
bitfld.long 0x1E8 31. "PADCONFIG122_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1E8 30. "PADCONFIG122_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1E8 29. "PADCONFIG122_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1E8 28. "PADCONFIG122_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1E8 27. "PADCONFIG122_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1E8 26. "PADCONFIG122_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1E8 25. "PADCONFIG122_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1E8 24. "PADCONFIG122_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1E8 23. "PADCONFIG122_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1E8 22. "PADCONFIG122_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1E8 21. "PADCONFIG122_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1E8 19.--20. "PADCONFIG122_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1E8 18. "PADCONFIG122_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1E8 17. "PADCONFIG122_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1E8 16. "PADCONFIG122_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1E8 15. "PADCONFIG122_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1E8 14. "PADCONFIG122_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1E8 11.--13. "PADCONFIG122_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1E8 8. "PADCONFIG122_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1E8 7. "PADCONFIG122_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1E8 0.--3. "PADCONFIG122_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1EC "CFG0_PADCONFIG123_PROXY,"
bitfld.long 0x1EC 31. "PADCONFIG123_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1EC 30. "PADCONFIG123_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1EC 29. "PADCONFIG123_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1EC 28. "PADCONFIG123_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1EC 27. "PADCONFIG123_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1EC 26. "PADCONFIG123_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1EC 25. "PADCONFIG123_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1EC 24. "PADCONFIG123_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1EC 23. "PADCONFIG123_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1EC 22. "PADCONFIG123_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1EC 21. "PADCONFIG123_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1EC 19.--20. "PADCONFIG123_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1EC 18. "PADCONFIG123_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1EC 17. "PADCONFIG123_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1EC 16. "PADCONFIG123_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1EC 15. "PADCONFIG123_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1EC 14. "PADCONFIG123_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1EC 11.--13. "PADCONFIG123_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1EC 8. "PADCONFIG123_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1EC 7. "PADCONFIG123_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1EC 0.--3. "PADCONFIG123_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1F0 "CFG0_PADCONFIG124_PROXY,"
bitfld.long 0x1F0 31. "PADCONFIG124_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1F0 30. "PADCONFIG124_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1F0 29. "PADCONFIG124_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1F0 28. "PADCONFIG124_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1F0 27. "PADCONFIG124_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1F0 26. "PADCONFIG124_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1F0 25. "PADCONFIG124_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1F0 24. "PADCONFIG124_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1F0 23. "PADCONFIG124_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1F0 22. "PADCONFIG124_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1F0 21. "PADCONFIG124_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1F0 19.--20. "PADCONFIG124_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1F0 18. "PADCONFIG124_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1F0 17. "PADCONFIG124_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1F0 16. "PADCONFIG124_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1F0 15. "PADCONFIG124_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1F0 14. "PADCONFIG124_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1F0 11.--13. "PADCONFIG124_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1F0 8. "PADCONFIG124_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1F0 7. "PADCONFIG124_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1F0 0.--3. "PADCONFIG124_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1F4 "CFG0_PADCONFIG125_PROXY,"
bitfld.long 0x1F4 31. "PADCONFIG125_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1F4 30. "PADCONFIG125_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1F4 29. "PADCONFIG125_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1F4 28. "PADCONFIG125_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1F4 27. "PADCONFIG125_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1F4 26. "PADCONFIG125_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1F4 25. "PADCONFIG125_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1F4 24. "PADCONFIG125_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1F4 23. "PADCONFIG125_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
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bitfld.long 0x1F4 22. "PADCONFIG125_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
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bitfld.long 0x1F4 21. "PADCONFIG125_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x1F4 19.--20. "PADCONFIG125_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x1F4 18. "PADCONFIG125_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x1F4 17. "PADCONFIG125_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1F4 16. "PADCONFIG125_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1F4 15. "PADCONFIG125_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1F4 14. "PADCONFIG125_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1F4 11.--13. "PADCONFIG125_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1F4 8. "PADCONFIG125_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x1F4 7. "PADCONFIG125_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x1F4 0.--3. "PADCONFIG125_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1F8 "CFG0_PADCONFIG126_PROXY,"
bitfld.long 0x1F8 31. "PADCONFIG126_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1F8 30. "PADCONFIG126_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1F8 29. "PADCONFIG126_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x1F8 28. "PADCONFIG126_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1F8 27. "PADCONFIG126_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1F8 26. "PADCONFIG126_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x1F8 25. "PADCONFIG126_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x1F8 24. "PADCONFIG126_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x1F8 23. "PADCONFIG126_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x1F8 22. "PADCONFIG126_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x1F8 21. "PADCONFIG126_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x1F8 19.--20. "PADCONFIG126_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x1F8 18. "PADCONFIG126_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x1F8 17. "PADCONFIG126_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x1F8 16. "PADCONFIG126_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1F8 15. "PADCONFIG126_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1F8 14. "PADCONFIG126_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1F8 11.--13. "PADCONFIG126_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1F8 8. "PADCONFIG126_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x1F8 7. "PADCONFIG126_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x1F8 0.--3. "PADCONFIG126_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x1FC "CFG0_PADCONFIG127_PROXY,"
bitfld.long 0x1FC 31. "PADCONFIG127_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x1FC 30. "PADCONFIG127_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x1FC 29. "PADCONFIG127_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x1FC 28. "PADCONFIG127_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x1FC 27. "PADCONFIG127_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x1FC 26. "PADCONFIG127_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x1FC 25. "PADCONFIG127_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x1FC 24. "PADCONFIG127_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x1FC 23. "PADCONFIG127_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x1FC 22. "PADCONFIG127_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x1FC 21. "PADCONFIG127_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x1FC 19.--20. "PADCONFIG127_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x1FC 18. "PADCONFIG127_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x1FC 17. "PADCONFIG127_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x1FC 16. "PADCONFIG127_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x1FC 15. "PADCONFIG127_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x1FC 14. "PADCONFIG127_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x1FC 11.--13. "PADCONFIG127_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1FC 8. "PADCONFIG127_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x1FC 7. "PADCONFIG127_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x1FC 0.--3. "PADCONFIG127_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x200 "CFG0_PADCONFIG128_PROXY,"
bitfld.long 0x200 31. "PADCONFIG128_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x200 30. "PADCONFIG128_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x200 29. "PADCONFIG128_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x200 28. "PADCONFIG128_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x200 27. "PADCONFIG128_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x200 26. "PADCONFIG128_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x200 25. "PADCONFIG128_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x200 24. "PADCONFIG128_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x200 23. "PADCONFIG128_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x200 22. "PADCONFIG128_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x200 21. "PADCONFIG128_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x200 19.--20. "PADCONFIG128_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x200 18. "PADCONFIG128_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x200 17. "PADCONFIG128_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x200 16. "PADCONFIG128_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x200 15. "PADCONFIG128_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x200 14. "PADCONFIG128_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x200 11.--13. "PADCONFIG128_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x200 8. "PADCONFIG128_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x200 7. "PADCONFIG128_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x200 0.--3. "PADCONFIG128_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x204 "CFG0_PADCONFIG129_PROXY,"
bitfld.long 0x204 31. "PADCONFIG129_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x204 30. "PADCONFIG129_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x204 29. "PADCONFIG129_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x204 28. "PADCONFIG129_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x204 27. "PADCONFIG129_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x204 26. "PADCONFIG129_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x204 25. "PADCONFIG129_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x204 24. "PADCONFIG129_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x204 23. "PADCONFIG129_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x204 22. "PADCONFIG129_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x204 21. "PADCONFIG129_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x204 19.--20. "PADCONFIG129_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x204 18. "PADCONFIG129_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x204 17. "PADCONFIG129_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x204 16. "PADCONFIG129_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x204 15. "PADCONFIG129_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x204 14. "PADCONFIG129_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x204 11.--13. "PADCONFIG129_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x204 8. "PADCONFIG129_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x204 7. "PADCONFIG129_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x204 0.--3. "PADCONFIG129_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x208 "CFG0_PADCONFIG130_PROXY,"
bitfld.long 0x208 31. "PADCONFIG130_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x208 30. "PADCONFIG130_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x208 29. "PADCONFIG130_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x208 28. "PADCONFIG130_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x208 27. "PADCONFIG130_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x208 26. "PADCONFIG130_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x208 25. "PADCONFIG130_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x208 24. "PADCONFIG130_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x208 23. "PADCONFIG130_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x208 22. "PADCONFIG130_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x208 21. "PADCONFIG130_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x208 19.--20. "PADCONFIG130_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x208 18. "PADCONFIG130_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x208 17. "PADCONFIG130_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x208 16. "PADCONFIG130_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x208 15. "PADCONFIG130_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x208 14. "PADCONFIG130_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x208 11.--13. "PADCONFIG130_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x208 8. "PADCONFIG130_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x208 7. "PADCONFIG130_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x208 0.--3. "PADCONFIG130_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x20C "CFG0_PADCONFIG131_PROXY,"
bitfld.long 0x20C 31. "PADCONFIG131_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x20C 30. "PADCONFIG131_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x20C 29. "PADCONFIG131_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x20C 28. "PADCONFIG131_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x20C 27. "PADCONFIG131_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x20C 26. "PADCONFIG131_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x20C 25. "PADCONFIG131_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x20C 24. "PADCONFIG131_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x20C 23. "PADCONFIG131_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x20C 22. "PADCONFIG131_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x20C 21. "PADCONFIG131_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x20C 19.--20. "PADCONFIG131_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x20C 18. "PADCONFIG131_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x20C 17. "PADCONFIG131_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x20C 16. "PADCONFIG131_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x20C 15. "PADCONFIG131_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x20C 14. "PADCONFIG131_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x20C 11.--13. "PADCONFIG131_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20C 8. "PADCONFIG131_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x20C 7. "PADCONFIG131_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x20C 0.--3. "PADCONFIG131_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x210 "CFG0_PADCONFIG132_PROXY,"
bitfld.long 0x210 31. "PADCONFIG132_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x210 30. "PADCONFIG132_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x210 29. "PADCONFIG132_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x210 28. "PADCONFIG132_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x210 27. "PADCONFIG132_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x210 26. "PADCONFIG132_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x210 25. "PADCONFIG132_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x210 24. "PADCONFIG132_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x210 23. "PADCONFIG132_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x210 22. "PADCONFIG132_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x210 21. "PADCONFIG132_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x210 19.--20. "PADCONFIG132_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x210 18. "PADCONFIG132_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x210 17. "PADCONFIG132_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x210 16. "PADCONFIG132_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x210 15. "PADCONFIG132_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x210 14. "PADCONFIG132_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x210 11.--13. "PADCONFIG132_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x210 8. "PADCONFIG132_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x210 7. "PADCONFIG132_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x210 0.--3. "PADCONFIG132_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x214 "CFG0_PADCONFIG133_PROXY,"
bitfld.long 0x214 31. "PADCONFIG133_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x214 30. "PADCONFIG133_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x214 29. "PADCONFIG133_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x214 28. "PADCONFIG133_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x214 27. "PADCONFIG133_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x214 26. "PADCONFIG133_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x214 25. "PADCONFIG133_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x214 24. "PADCONFIG133_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x214 23. "PADCONFIG133_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x214 22. "PADCONFIG133_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x214 21. "PADCONFIG133_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x214 19.--20. "PADCONFIG133_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x214 18. "PADCONFIG133_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x214 17. "PADCONFIG133_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x214 16. "PADCONFIG133_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x214 15. "PADCONFIG133_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x214 14. "PADCONFIG133_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x214 11.--13. "PADCONFIG133_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x214 8. "PADCONFIG133_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x214 7. "PADCONFIG133_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x214 0.--3. "PADCONFIG133_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x218 "CFG0_PADCONFIG134_PROXY,"
bitfld.long 0x218 31. "PADCONFIG134_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x218 30. "PADCONFIG134_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x218 29. "PADCONFIG134_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x218 28. "PADCONFIG134_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x218 27. "PADCONFIG134_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x218 26. "PADCONFIG134_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x218 25. "PADCONFIG134_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x218 24. "PADCONFIG134_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x218 23. "PADCONFIG134_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x218 22. "PADCONFIG134_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x218 21. "PADCONFIG134_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x218 19.--20. "PADCONFIG134_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x218 18. "PADCONFIG134_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x218 17. "PADCONFIG134_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x218 16. "PADCONFIG134_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x218 15. "PADCONFIG134_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x218 14. "PADCONFIG134_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x218 11.--13. "PADCONFIG134_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x218 8. "PADCONFIG134_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x218 7. "PADCONFIG134_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x218 0.--3. "PADCONFIG134_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x21C "CFG0_PADCONFIG135_PROXY,"
bitfld.long 0x21C 31. "PADCONFIG135_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x21C 30. "PADCONFIG135_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x21C 29. "PADCONFIG135_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x21C 28. "PADCONFIG135_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x21C 27. "PADCONFIG135_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x21C 26. "PADCONFIG135_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x21C 25. "PADCONFIG135_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x21C 24. "PADCONFIG135_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x21C 23. "PADCONFIG135_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x21C 22. "PADCONFIG135_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x21C 21. "PADCONFIG135_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x21C 19.--20. "PADCONFIG135_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x21C 18. "PADCONFIG135_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x21C 17. "PADCONFIG135_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x21C 16. "PADCONFIG135_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x21C 15. "PADCONFIG135_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x21C 14. "PADCONFIG135_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x21C 11.--13. "PADCONFIG135_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x21C 8. "PADCONFIG135_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x21C 7. "PADCONFIG135_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x21C 0.--3. "PADCONFIG135_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x220 "CFG0_PADCONFIG136_PROXY,"
bitfld.long 0x220 31. "PADCONFIG136_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x220 30. "PADCONFIG136_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x220 29. "PADCONFIG136_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x220 28. "PADCONFIG136_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x220 27. "PADCONFIG136_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x220 26. "PADCONFIG136_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x220 25. "PADCONFIG136_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x220 24. "PADCONFIG136_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x220 23. "PADCONFIG136_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x220 22. "PADCONFIG136_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x220 21. "PADCONFIG136_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x220 19.--20. "PADCONFIG136_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x220 18. "PADCONFIG136_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x220 17. "PADCONFIG136_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x220 16. "PADCONFIG136_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x220 15. "PADCONFIG136_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x220 14. "PADCONFIG136_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x220 11.--13. "PADCONFIG136_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x220 8. "PADCONFIG136_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x220 7. "PADCONFIG136_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x220 0.--3. "PADCONFIG136_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x224 "CFG0_PADCONFIG137_PROXY,"
bitfld.long 0x224 31. "PADCONFIG137_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x224 30. "PADCONFIG137_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x224 29. "PADCONFIG137_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x224 28. "PADCONFIG137_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x224 27. "PADCONFIG137_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x224 26. "PADCONFIG137_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x224 25. "PADCONFIG137_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x224 24. "PADCONFIG137_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x224 23. "PADCONFIG137_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x224 22. "PADCONFIG137_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x224 21. "PADCONFIG137_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x224 19.--20. "PADCONFIG137_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x224 18. "PADCONFIG137_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x224 17. "PADCONFIG137_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x224 16. "PADCONFIG137_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x224 15. "PADCONFIG137_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x224 14. "PADCONFIG137_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x224 11.--13. "PADCONFIG137_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x224 8. "PADCONFIG137_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x224 7. "PADCONFIG137_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x224 0.--3. "PADCONFIG137_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x228 "CFG0_PADCONFIG138_PROXY,"
bitfld.long 0x228 31. "PADCONFIG138_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x228 30. "PADCONFIG138_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x228 29. "PADCONFIG138_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x228 28. "PADCONFIG138_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x228 27. "PADCONFIG138_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x228 26. "PADCONFIG138_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x228 25. "PADCONFIG138_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x228 24. "PADCONFIG138_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x228 23. "PADCONFIG138_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x228 22. "PADCONFIG138_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x228 21. "PADCONFIG138_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x228 19.--20. "PADCONFIG138_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x228 18. "PADCONFIG138_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x228 17. "PADCONFIG138_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x228 16. "PADCONFIG138_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x228 15. "PADCONFIG138_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x228 14. "PADCONFIG138_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x228 11.--13. "PADCONFIG138_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x228 8. "PADCONFIG138_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x228 7. "PADCONFIG138_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x228 0.--3. "PADCONFIG138_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x22C "CFG0_PADCONFIG139_PROXY,"
bitfld.long 0x22C 31. "PADCONFIG139_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x22C 30. "PADCONFIG139_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x22C 29. "PADCONFIG139_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x22C 28. "PADCONFIG139_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x22C 27. "PADCONFIG139_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x22C 26. "PADCONFIG139_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x22C 25. "PADCONFIG139_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x22C 24. "PADCONFIG139_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x22C 23. "PADCONFIG139_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x22C 22. "PADCONFIG139_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x22C 21. "PADCONFIG139_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x22C 19.--20. "PADCONFIG139_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x22C 18. "PADCONFIG139_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x22C 17. "PADCONFIG139_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x22C 16. "PADCONFIG139_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x22C 15. "PADCONFIG139_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x22C 14. "PADCONFIG139_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x22C 11.--13. "PADCONFIG139_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x22C 8. "PADCONFIG139_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x22C 7. "PADCONFIG139_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x22C 0.--3. "PADCONFIG139_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x230 "CFG0_PADCONFIG140_PROXY,"
bitfld.long 0x230 31. "PADCONFIG140_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x230 30. "PADCONFIG140_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x230 29. "PADCONFIG140_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x230 28. "PADCONFIG140_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x230 27. "PADCONFIG140_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x230 26. "PADCONFIG140_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
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bitfld.long 0x230 25. "PADCONFIG140_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x230 24. "PADCONFIG140_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x230 23. "PADCONFIG140_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x230 22. "PADCONFIG140_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x230 21. "PADCONFIG140_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x230 19.--20. "PADCONFIG140_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
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bitfld.long 0x230 18. "PADCONFIG140_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x230 17. "PADCONFIG140_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x230 16. "PADCONFIG140_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x230 15. "PADCONFIG140_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x230 14. "PADCONFIG140_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x230 11.--13. "PADCONFIG140_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x230 8. "PADCONFIG140_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x230 7. "PADCONFIG140_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x230 0.--3. "PADCONFIG140_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x234 "CFG0_PADCONFIG141_PROXY,"
bitfld.long 0x234 31. "PADCONFIG141_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x234 30. "PADCONFIG141_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
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bitfld.long 0x234 29. "PADCONFIG141_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x234 28. "PADCONFIG141_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
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bitfld.long 0x234 27. "PADCONFIG141_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x234 26. "PADCONFIG141_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x234 25. "PADCONFIG141_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x234 24. "PADCONFIG141_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
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bitfld.long 0x234 23. "PADCONFIG141_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x234 22. "PADCONFIG141_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x234 21. "PADCONFIG141_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
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bitfld.long 0x234 19.--20. "PADCONFIG141_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x234 18. "PADCONFIG141_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x234 17. "PADCONFIG141_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x234 16. "PADCONFIG141_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
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bitfld.long 0x234 15. "PADCONFIG141_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
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bitfld.long 0x234 14. "PADCONFIG141_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
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bitfld.long 0x234 11.--13. "PADCONFIG141_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
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bitfld.long 0x234 8. "PADCONFIG141_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x234 7. "PADCONFIG141_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
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bitfld.long 0x234 0.--3. "PADCONFIG141_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x238 "CFG0_PADCONFIG142_PROXY,"
bitfld.long 0x238 31. "PADCONFIG142_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x238 30. "PADCONFIG142_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x238 29. "PADCONFIG142_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
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bitfld.long 0x238 28. "PADCONFIG142_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x238 27. "PADCONFIG142_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
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bitfld.long 0x238 26. "PADCONFIG142_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x238 25. "PADCONFIG142_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x238 24. "PADCONFIG142_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x238 23. "PADCONFIG142_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x238 22. "PADCONFIG142_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x238 21. "PADCONFIG142_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x238 19.--20. "PADCONFIG142_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x238 18. "PADCONFIG142_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
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bitfld.long 0x238 17. "PADCONFIG142_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
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bitfld.long 0x238 16. "PADCONFIG142_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x238 15. "PADCONFIG142_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x238 14. "PADCONFIG142_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x238 11.--13. "PADCONFIG142_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x238 8. "PADCONFIG142_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
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bitfld.long 0x238 7. "PADCONFIG142_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x238 0.--3. "PADCONFIG142_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x23C "CFG0_PADCONFIG143_PROXY,"
bitfld.long 0x23C 31. "PADCONFIG143_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
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bitfld.long 0x23C 30. "PADCONFIG143_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x23C 29. "PADCONFIG143_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x23C 28. "PADCONFIG143_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x23C 27. "PADCONFIG143_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x23C 26. "PADCONFIG143_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x23C 25. "PADCONFIG143_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
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bitfld.long 0x23C 24. "PADCONFIG143_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x23C 23. "PADCONFIG143_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x23C 22. "PADCONFIG143_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x23C 21. "PADCONFIG143_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x23C 19.--20. "PADCONFIG143_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x23C 18. "PADCONFIG143_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x23C 17. "PADCONFIG143_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x23C 16. "PADCONFIG143_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x23C 15. "PADCONFIG143_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x23C 14. "PADCONFIG143_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x23C 11.--13. "PADCONFIG143_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x23C 8. "PADCONFIG143_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x23C 7. "PADCONFIG143_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x23C 0.--3. "PADCONFIG143_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x240 "CFG0_PADCONFIG144_PROXY,"
bitfld.long 0x240 31. "PADCONFIG144_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x240 30. "PADCONFIG144_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x240 29. "PADCONFIG144_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x240 28. "PADCONFIG144_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x240 27. "PADCONFIG144_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x240 26. "PADCONFIG144_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x240 25. "PADCONFIG144_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x240 24. "PADCONFIG144_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x240 23. "PADCONFIG144_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x240 22. "PADCONFIG144_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x240 21. "PADCONFIG144_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x240 19.--20. "PADCONFIG144_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x240 18. "PADCONFIG144_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x240 17. "PADCONFIG144_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x240 16. "PADCONFIG144_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x240 15. "PADCONFIG144_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x240 14. "PADCONFIG144_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x240 11.--13. "PADCONFIG144_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x240 8. "PADCONFIG144_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x240 7. "PADCONFIG144_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x240 0.--3. "PADCONFIG144_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x244 "CFG0_PADCONFIG145_PROXY,"
bitfld.long 0x244 31. "PADCONFIG145_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x244 30. "PADCONFIG145_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x244 29. "PADCONFIG145_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x244 28. "PADCONFIG145_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x244 27. "PADCONFIG145_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x244 26. "PADCONFIG145_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x244 25. "PADCONFIG145_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x244 24. "PADCONFIG145_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x244 23. "PADCONFIG145_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x244 22. "PADCONFIG145_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x244 21. "PADCONFIG145_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x244 19.--20. "PADCONFIG145_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x244 18. "PADCONFIG145_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x244 17. "PADCONFIG145_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x244 16. "PADCONFIG145_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x244 15. "PADCONFIG145_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x244 14. "PADCONFIG145_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x244 11.--13. "PADCONFIG145_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x244 8. "PADCONFIG145_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x244 7. "PADCONFIG145_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x244 0.--3. "PADCONFIG145_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x248 "CFG0_PADCONFIG146_PROXY,"
bitfld.long 0x248 31. "PADCONFIG146_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x248 30. "PADCONFIG146_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x248 29. "PADCONFIG146_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x248 28. "PADCONFIG146_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x248 27. "PADCONFIG146_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x248 26. "PADCONFIG146_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x248 25. "PADCONFIG146_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x248 24. "PADCONFIG146_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x248 23. "PADCONFIG146_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x248 22. "PADCONFIG146_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x248 21. "PADCONFIG146_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x248 19.--20. "PADCONFIG146_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x248 18. "PADCONFIG146_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x248 17. "PADCONFIG146_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x248 16. "PADCONFIG146_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x248 15. "PADCONFIG146_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x248 14. "PADCONFIG146_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x248 11.--13. "PADCONFIG146_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x248 8. "PADCONFIG146_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x248 7. "PADCONFIG146_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x248 0.--3. "PADCONFIG146_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x24C "CFG0_PADCONFIG147_PROXY,"
bitfld.long 0x24C 31. "PADCONFIG147_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x24C 30. "PADCONFIG147_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x24C 29. "PADCONFIG147_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x24C 28. "PADCONFIG147_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x24C 27. "PADCONFIG147_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x24C 26. "PADCONFIG147_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x24C 25. "PADCONFIG147_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x24C 24. "PADCONFIG147_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x24C 23. "PADCONFIG147_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x24C 22. "PADCONFIG147_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x24C 21. "PADCONFIG147_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x24C 19.--20. "PADCONFIG147_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x24C 18. "PADCONFIG147_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x24C 17. "PADCONFIG147_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x24C 16. "PADCONFIG147_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x24C 15. "PADCONFIG147_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x24C 14. "PADCONFIG147_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x24C 11.--13. "PADCONFIG147_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x24C 8. "PADCONFIG147_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x24C 7. "PADCONFIG147_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x24C 0.--3. "PADCONFIG147_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x250 "CFG0_PADCONFIG148_PROXY,"
bitfld.long 0x250 31. "PADCONFIG148_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x250 30. "PADCONFIG148_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x250 29. "PADCONFIG148_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x250 28. "PADCONFIG148_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x250 27. "PADCONFIG148_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x250 26. "PADCONFIG148_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x250 25. "PADCONFIG148_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x250 24. "PADCONFIG148_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x250 23. "PADCONFIG148_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x250 22. "PADCONFIG148_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x250 21. "PADCONFIG148_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x250 19.--20. "PADCONFIG148_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x250 18. "PADCONFIG148_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x250 17. "PADCONFIG148_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x250 16. "PADCONFIG148_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x250 15. "PADCONFIG148_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x250 14. "PADCONFIG148_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x250 11.--13. "PADCONFIG148_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x250 8. "PADCONFIG148_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x250 7. "PADCONFIG148_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x250 0.--3. "PADCONFIG148_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x254 "CFG0_PADCONFIG149_PROXY,"
bitfld.long 0x254 31. "PADCONFIG149_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x254 30. "PADCONFIG149_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x254 29. "PADCONFIG149_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x254 28. "PADCONFIG149_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x254 27. "PADCONFIG149_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x254 26. "PADCONFIG149_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x254 25. "PADCONFIG149_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x254 24. "PADCONFIG149_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x254 23. "PADCONFIG149_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x254 22. "PADCONFIG149_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x254 21. "PADCONFIG149_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x254 19.--20. "PADCONFIG149_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x254 18. "PADCONFIG149_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x254 17. "PADCONFIG149_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x254 16. "PADCONFIG149_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x254 15. "PADCONFIG149_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x254 14. "PADCONFIG149_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x254 11.--13. "PADCONFIG149_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x254 8. "PADCONFIG149_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x254 7. "PADCONFIG149_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x254 0.--3. "PADCONFIG149_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x258 "CFG0_PADCONFIG150_PROXY,"
bitfld.long 0x258 31. "PADCONFIG150_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x258 30. "PADCONFIG150_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x258 29. "PADCONFIG150_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x258 28. "PADCONFIG150_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x258 27. "PADCONFIG150_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x258 26. "PADCONFIG150_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x258 25. "PADCONFIG150_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x258 24. "PADCONFIG150_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x258 23. "PADCONFIG150_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x258 22. "PADCONFIG150_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x258 21. "PADCONFIG150_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x258 19.--20. "PADCONFIG150_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x258 18. "PADCONFIG150_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x258 17. "PADCONFIG150_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x258 16. "PADCONFIG150_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x258 15. "PADCONFIG150_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x258 14. "PADCONFIG150_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x258 11.--13. "PADCONFIG150_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x258 8. "PADCONFIG150_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x258 7. "PADCONFIG150_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x258 0.--3. "PADCONFIG150_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x25C "CFG0_PADCONFIG151_PROXY,"
bitfld.long 0x25C 31. "PADCONFIG151_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x25C 30. "PADCONFIG151_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x25C 29. "PADCONFIG151_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x25C 28. "PADCONFIG151_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x25C 27. "PADCONFIG151_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x25C 26. "PADCONFIG151_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x25C 25. "PADCONFIG151_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x25C 24. "PADCONFIG151_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x25C 23. "PADCONFIG151_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x25C 22. "PADCONFIG151_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x25C 21. "PADCONFIG151_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x25C 19.--20. "PADCONFIG151_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x25C 18. "PADCONFIG151_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x25C 17. "PADCONFIG151_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x25C 16. "PADCONFIG151_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x25C 15. "PADCONFIG151_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x25C 14. "PADCONFIG151_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x25C 11.--13. "PADCONFIG151_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x25C 8. "PADCONFIG151_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x25C 7. "PADCONFIG151_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x25C 0.--3. "PADCONFIG151_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x260 "CFG0_PADCONFIG152_PROXY,"
bitfld.long 0x260 31. "PADCONFIG152_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x260 30. "PADCONFIG152_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x260 29. "PADCONFIG152_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x260 28. "PADCONFIG152_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x260 27. "PADCONFIG152_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x260 26. "PADCONFIG152_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x260 25. "PADCONFIG152_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x260 24. "PADCONFIG152_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x260 23. "PADCONFIG152_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x260 22. "PADCONFIG152_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x260 21. "PADCONFIG152_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x260 19.--20. "PADCONFIG152_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x260 18. "PADCONFIG152_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x260 17. "PADCONFIG152_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x260 16. "PADCONFIG152_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x260 15. "PADCONFIG152_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x260 14. "PADCONFIG152_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x260 11.--13. "PADCONFIG152_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x260 8. "PADCONFIG152_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x260 7. "PADCONFIG152_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x260 0.--3. "PADCONFIG152_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x264 "CFG0_PADCONFIG153_PROXY,"
bitfld.long 0x264 31. "PADCONFIG153_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x264 30. "PADCONFIG153_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x264 29. "PADCONFIG153_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x264 28. "PADCONFIG153_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x264 27. "PADCONFIG153_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x264 26. "PADCONFIG153_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x264 25. "PADCONFIG153_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x264 24. "PADCONFIG153_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x264 23. "PADCONFIG153_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x264 22. "PADCONFIG153_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x264 21. "PADCONFIG153_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x264 19.--20. "PADCONFIG153_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x264 18. "PADCONFIG153_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x264 17. "PADCONFIG153_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x264 16. "PADCONFIG153_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x264 15. "PADCONFIG153_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x264 14. "PADCONFIG153_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x264 11.--13. "PADCONFIG153_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x264 8. "PADCONFIG153_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x264 7. "PADCONFIG153_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x264 0.--3. "PADCONFIG153_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x268 "CFG0_PADCONFIG154_PROXY,"
bitfld.long 0x268 31. "PADCONFIG154_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x268 30. "PADCONFIG154_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x268 29. "PADCONFIG154_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x268 28. "PADCONFIG154_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x268 27. "PADCONFIG154_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x268 26. "PADCONFIG154_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x268 25. "PADCONFIG154_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x268 24. "PADCONFIG154_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x268 23. "PADCONFIG154_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x268 22. "PADCONFIG154_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x268 21. "PADCONFIG154_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x268 19.--20. "PADCONFIG154_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x268 18. "PADCONFIG154_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x268 17. "PADCONFIG154_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x268 16. "PADCONFIG154_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x268 15. "PADCONFIG154_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x268 14. "PADCONFIG154_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x268 11.--13. "PADCONFIG154_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x268 8. "PADCONFIG154_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x268 7. "PADCONFIG154_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x268 0.--3. "PADCONFIG154_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x26C "CFG0_PADCONFIG155_PROXY,"
bitfld.long 0x26C 31. "PADCONFIG155_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x26C 30. "PADCONFIG155_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x26C 29. "PADCONFIG155_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x26C 28. "PADCONFIG155_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x26C 27. "PADCONFIG155_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x26C 26. "PADCONFIG155_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x26C 25. "PADCONFIG155_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x26C 24. "PADCONFIG155_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x26C 23. "PADCONFIG155_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x26C 22. "PADCONFIG155_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x26C 21. "PADCONFIG155_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x26C 19.--20. "PADCONFIG155_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x26C 18. "PADCONFIG155_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x26C 17. "PADCONFIG155_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x26C 16. "PADCONFIG155_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x26C 15. "PADCONFIG155_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x26C 14. "PADCONFIG155_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x26C 11.--13. "PADCONFIG155_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x26C 8. "PADCONFIG155_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x26C 7. "PADCONFIG155_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x26C 0.--3. "PADCONFIG155_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x270 "CFG0_PADCONFIG156_PROXY,"
bitfld.long 0x270 31. "PADCONFIG156_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x270 30. "PADCONFIG156_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x270 29. "PADCONFIG156_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x270 28. "PADCONFIG156_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x270 27. "PADCONFIG156_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x270 26. "PADCONFIG156_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x270 25. "PADCONFIG156_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x270 24. "PADCONFIG156_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x270 23. "PADCONFIG156_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x270 22. "PADCONFIG156_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x270 21. "PADCONFIG156_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x270 19.--20. "PADCONFIG156_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x270 18. "PADCONFIG156_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x270 17. "PADCONFIG156_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x270 16. "PADCONFIG156_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x270 15. "PADCONFIG156_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x270 14. "PADCONFIG156_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x270 11.--13. "PADCONFIG156_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x270 8. "PADCONFIG156_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x270 7. "PADCONFIG156_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x270 0.--3. "PADCONFIG156_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x274 "CFG0_PADCONFIG157_PROXY,"
bitfld.long 0x274 31. "PADCONFIG157_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x274 30. "PADCONFIG157_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x274 29. "PADCONFIG157_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x274 28. "PADCONFIG157_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x274 27. "PADCONFIG157_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x274 26. "PADCONFIG157_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x274 25. "PADCONFIG157_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x274 24. "PADCONFIG157_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x274 23. "PADCONFIG157_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x274 22. "PADCONFIG157_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x274 21. "PADCONFIG157_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x274 19.--20. "PADCONFIG157_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x274 18. "PADCONFIG157_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x274 17. "PADCONFIG157_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x274 16. "PADCONFIG157_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x274 15. "PADCONFIG157_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x274 14. "PADCONFIG157_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x274 11.--13. "PADCONFIG157_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x274 8. "PADCONFIG157_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x274 7. "PADCONFIG157_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x274 0.--3. "PADCONFIG157_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x278 "CFG0_PADCONFIG158_PROXY,"
bitfld.long 0x278 31. "PADCONFIG158_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x278 30. "PADCONFIG158_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x278 29. "PADCONFIG158_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x278 28. "PADCONFIG158_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x278 27. "PADCONFIG158_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x278 26. "PADCONFIG158_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x278 25. "PADCONFIG158_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x278 24. "PADCONFIG158_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x278 23. "PADCONFIG158_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x278 22. "PADCONFIG158_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x278 21. "PADCONFIG158_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x278 19.--20. "PADCONFIG158_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x278 18. "PADCONFIG158_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x278 17. "PADCONFIG158_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x278 16. "PADCONFIG158_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x278 15. "PADCONFIG158_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x278 14. "PADCONFIG158_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x278 11.--13. "PADCONFIG158_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x278 8. "PADCONFIG158_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x278 7. "PADCONFIG158_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x278 0.--3. "PADCONFIG158_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x27C "CFG0_PADCONFIG159_PROXY,"
bitfld.long 0x27C 31. "PADCONFIG159_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x27C 30. "PADCONFIG159_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x27C 29. "PADCONFIG159_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x27C 28. "PADCONFIG159_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x27C 27. "PADCONFIG159_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x27C 26. "PADCONFIG159_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x27C 25. "PADCONFIG159_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x27C 24. "PADCONFIG159_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x27C 23. "PADCONFIG159_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x27C 22. "PADCONFIG159_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x27C 21. "PADCONFIG159_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x27C 19.--20. "PADCONFIG159_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x27C 18. "PADCONFIG159_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x27C 17. "PADCONFIG159_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x27C 16. "PADCONFIG159_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x27C 15. "PADCONFIG159_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x27C 14. "PADCONFIG159_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x27C 11.--13. "PADCONFIG159_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x27C 8. "PADCONFIG159_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x27C 7. "PADCONFIG159_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x27C 0.--3. "PADCONFIG159_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x280 "CFG0_PADCONFIG160_PROXY,"
bitfld.long 0x280 31. "PADCONFIG160_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x280 30. "PADCONFIG160_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x280 29. "PADCONFIG160_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x280 28. "PADCONFIG160_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x280 27. "PADCONFIG160_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x280 26. "PADCONFIG160_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x280 25. "PADCONFIG160_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x280 24. "PADCONFIG160_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x280 23. "PADCONFIG160_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x280 22. "PADCONFIG160_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x280 21. "PADCONFIG160_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x280 19.--20. "PADCONFIG160_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x280 18. "PADCONFIG160_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x280 17. "PADCONFIG160_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x280 16. "PADCONFIG160_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x280 15. "PADCONFIG160_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x280 14. "PADCONFIG160_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x280 11.--13. "PADCONFIG160_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x280 8. "PADCONFIG160_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x280 7. "PADCONFIG160_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x280 0.--3. "PADCONFIG160_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x284 "CFG0_PADCONFIG161_PROXY,"
bitfld.long 0x284 31. "PADCONFIG161_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x284 30. "PADCONFIG161_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x284 29. "PADCONFIG161_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x284 28. "PADCONFIG161_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x284 27. "PADCONFIG161_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x284 26. "PADCONFIG161_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x284 25. "PADCONFIG161_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x284 24. "PADCONFIG161_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x284 23. "PADCONFIG161_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x284 22. "PADCONFIG161_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x284 21. "PADCONFIG161_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x284 19.--20. "PADCONFIG161_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x284 18. "PADCONFIG161_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x284 17. "PADCONFIG161_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x284 16. "PADCONFIG161_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x284 15. "PADCONFIG161_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x284 14. "PADCONFIG161_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x284 11.--13. "PADCONFIG161_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x284 8. "PADCONFIG161_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x284 7. "PADCONFIG161_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x284 0.--3. "PADCONFIG161_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x288 "CFG0_PADCONFIG162_PROXY,"
bitfld.long 0x288 31. "PADCONFIG162_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x288 30. "PADCONFIG162_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x288 29. "PADCONFIG162_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x288 28. "PADCONFIG162_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x288 27. "PADCONFIG162_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x288 26. "PADCONFIG162_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x288 25. "PADCONFIG162_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x288 24. "PADCONFIG162_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x288 23. "PADCONFIG162_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x288 22. "PADCONFIG162_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x288 21. "PADCONFIG162_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x288 19.--20. "PADCONFIG162_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x288 18. "PADCONFIG162_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x288 17. "PADCONFIG162_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x288 16. "PADCONFIG162_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x288 15. "PADCONFIG162_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x288 14. "PADCONFIG162_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x288 11.--13. "PADCONFIG162_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x288 8. "PADCONFIG162_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x288 7. "PADCONFIG162_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x288 0.--3. "PADCONFIG162_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x28C "CFG0_PADCONFIG163_PROXY,"
bitfld.long 0x28C 31. "PADCONFIG163_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x28C 30. "PADCONFIG163_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x28C 29. "PADCONFIG163_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x28C 28. "PADCONFIG163_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x28C 27. "PADCONFIG163_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x28C 26. "PADCONFIG163_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x28C 25. "PADCONFIG163_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x28C 24. "PADCONFIG163_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x28C 23. "PADCONFIG163_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x28C 22. "PADCONFIG163_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x28C 21. "PADCONFIG163_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x28C 19.--20. "PADCONFIG163_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x28C 18. "PADCONFIG163_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x28C 17. "PADCONFIG163_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x28C 16. "PADCONFIG163_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x28C 15. "PADCONFIG163_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x28C 14. "PADCONFIG163_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x28C 11.--13. "PADCONFIG163_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28C 8. "PADCONFIG163_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x28C 7. "PADCONFIG163_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x28C 0.--3. "PADCONFIG163_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x290 "CFG0_PADCONFIG164_PROXY,"
bitfld.long 0x290 31. "PADCONFIG164_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x290 30. "PADCONFIG164_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x290 29. "PADCONFIG164_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x290 28. "PADCONFIG164_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x290 27. "PADCONFIG164_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x290 26. "PADCONFIG164_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x290 25. "PADCONFIG164_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x290 24. "PADCONFIG164_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x290 23. "PADCONFIG164_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x290 22. "PADCONFIG164_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x290 21. "PADCONFIG164_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x290 19.--20. "PADCONFIG164_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x290 18. "PADCONFIG164_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x290 17. "PADCONFIG164_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x290 16. "PADCONFIG164_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x290 15. "PADCONFIG164_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x290 14. "PADCONFIG164_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x290 11.--13. "PADCONFIG164_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x290 8. "PADCONFIG164_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x290 7. "PADCONFIG164_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x290 0.--3. "PADCONFIG164_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x294 "CFG0_PADCONFIG165_PROXY,"
bitfld.long 0x294 31. "PADCONFIG165_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x294 30. "PADCONFIG165_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x294 29. "PADCONFIG165_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x294 28. "PADCONFIG165_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x294 27. "PADCONFIG165_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x294 26. "PADCONFIG165_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x294 25. "PADCONFIG165_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x294 24. "PADCONFIG165_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x294 23. "PADCONFIG165_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x294 22. "PADCONFIG165_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x294 21. "PADCONFIG165_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x294 19.--20. "PADCONFIG165_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x294 18. "PADCONFIG165_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x294 17. "PADCONFIG165_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x294 16. "PADCONFIG165_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x294 15. "PADCONFIG165_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x294 14. "PADCONFIG165_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x294 11.--13. "PADCONFIG165_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x294 8. "PADCONFIG165_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x294 7. "PADCONFIG165_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x294 0.--3. "PADCONFIG165_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x298 "CFG0_PADCONFIG166_PROXY,"
bitfld.long 0x298 31. "PADCONFIG166_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x298 30. "PADCONFIG166_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x298 29. "PADCONFIG166_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x298 28. "PADCONFIG166_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x298 27. "PADCONFIG166_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x298 26. "PADCONFIG166_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x298 25. "PADCONFIG166_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x298 24. "PADCONFIG166_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x298 23. "PADCONFIG166_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x298 22. "PADCONFIG166_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x298 21. "PADCONFIG166_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x298 19.--20. "PADCONFIG166_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x298 18. "PADCONFIG166_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x298 17. "PADCONFIG166_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x298 16. "PADCONFIG166_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x298 15. "PADCONFIG166_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x298 14. "PADCONFIG166_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x298 11.--13. "PADCONFIG166_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x298 8. "PADCONFIG166_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x298 7. "PADCONFIG166_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x298 0.--3. "PADCONFIG166_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x29C "CFG0_PADCONFIG167_PROXY,"
bitfld.long 0x29C 31. "PADCONFIG167_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x29C 30. "PADCONFIG167_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x29C 29. "PADCONFIG167_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x29C 28. "PADCONFIG167_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x29C 27. "PADCONFIG167_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x29C 26. "PADCONFIG167_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x29C 25. "PADCONFIG167_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x29C 24. "PADCONFIG167_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x29C 23. "PADCONFIG167_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x29C 22. "PADCONFIG167_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x29C 21. "PADCONFIG167_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x29C 19.--20. "PADCONFIG167_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x29C 18. "PADCONFIG167_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x29C 17. "PADCONFIG167_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x29C 16. "PADCONFIG167_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x29C 15. "PADCONFIG167_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x29C 14. "PADCONFIG167_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x29C 11.--13. "PADCONFIG167_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x29C 8. "PADCONFIG167_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x29C 7. "PADCONFIG167_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x29C 0.--3. "PADCONFIG167_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2A0 "CFG0_PADCONFIG168_PROXY,"
bitfld.long 0x2A0 31. "PADCONFIG168_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x2A0 30. "PADCONFIG168_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x2A0 29. "PADCONFIG168_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x2A0 28. "PADCONFIG168_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x2A0 27. "PADCONFIG168_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x2A0 26. "PADCONFIG168_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2A0 25. "PADCONFIG168_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x2A0 24. "PADCONFIG168_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x2A0 23. "PADCONFIG168_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x2A0 22. "PADCONFIG168_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x2A0 21. "PADCONFIG168_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x2A0 19.--20. "PADCONFIG168_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x2A0 18. "PADCONFIG168_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x2A0 17. "PADCONFIG168_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x2A0 16. "PADCONFIG168_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x2A0 15. "PADCONFIG168_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x2A0 14. "PADCONFIG168_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x2A0 11.--13. "PADCONFIG168_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2A0 8. "PADCONFIG168_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x2A0 7. "PADCONFIG168_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x2A0 0.--3. "PADCONFIG168_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2A4 "CFG0_PADCONFIG169_PROXY,"
bitfld.long 0x2A4 31. "PADCONFIG169_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x2A4 30. "PADCONFIG169_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x2A4 29. "PADCONFIG169_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x2A4 28. "PADCONFIG169_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x2A4 27. "PADCONFIG169_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x2A4 26. "PADCONFIG169_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2A4 25. "PADCONFIG169_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x2A4 24. "PADCONFIG169_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x2A4 23. "PADCONFIG169_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x2A4 22. "PADCONFIG169_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x2A4 21. "PADCONFIG169_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x2A4 19.--20. "PADCONFIG169_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x2A4 18. "PADCONFIG169_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x2A4 17. "PADCONFIG169_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x2A4 16. "PADCONFIG169_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x2A4 15. "PADCONFIG169_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x2A4 14. "PADCONFIG169_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x2A4 11.--13. "PADCONFIG169_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2A4 8. "PADCONFIG169_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x2A4 7. "PADCONFIG169_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x2A4 0.--3. "PADCONFIG169_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
line.long 0x2A8 "CFG0_PADCONFIG170_PROXY,"
bitfld.long 0x2A8 31. "PADCONFIG170_LOCK_PROXY,Lock" "Padconfig register is unlocked,Padconfig register is locked from further writes"
newline
bitfld.long 0x2A8 30. "PADCONFIG170_WKUP_EVT_PROXY,Wakeup event status" "No wake event on pin,Wake event occurred on pin"
newline
bitfld.long 0x2A8 29. "PADCONFIG170_WKUP_EN_PROXY,Wakeup enable" "Wakeup operation disabled,Wakeup operation enabled"
newline
bitfld.long 0x2A8 28. "PADCONFIG170_DS_PULLTYPE_SEL_PROXY,Deep Sleep pull-up/down selection" "Offmode pulldown selected,Offmode pullup selected"
newline
bitfld.long 0x2A8 27. "PADCONFIG170_DS_PULLUD_EN_PROXY,Deep Sleep pull-up/down enable (active low)" "Pullup / pulldown is enabled,Pullup / pulldown is disabled"
newline
bitfld.long 0x2A8 26. "PADCONFIG170_DSOUT_VAL_PROXY,Deep Sleep output value" "Output value is 0,Output value is 1"
newline
bitfld.long 0x2A8 25. "PADCONFIG170_DSOUT_DIS_PROXY,Deep Sleep output disable" "Output enabled,Output disabled"
newline
bitfld.long 0x2A8 24. "PADCONFIG170_DS_EN_PROXY,Deep Sleep override control" "IO keeps its previous state when Deep Sleep mode..,IO state is forced to OFF mode value when Deep.."
newline
bitfld.long 0x2A8 23. "PADCONFIG170_ISO_BYP_PROXY,Isolation Bypass" "IO isolation is preserved,IO isolation is bypassed"
newline
bitfld.long 0x2A8 22. "PADCONFIG170_ISO_OVR_PROXY,Isolation Override" "IO isolation is preserved,IO isolation is overridden"
newline
bitfld.long 0x2A8 21. "PADCONFIG170_TX_DIS_PROXY,Driver Disable" "Driver is enabled,Driver is disabled"
newline
bitfld.long 0x2A8 19.--20. "PADCONFIG170_DRV_STR_PROXY,Drive Strength Control" "0,1,2,3"
newline
bitfld.long 0x2A8 18. "PADCONFIG170_RXACTIVE_PROXY,Input enable for the Pad" "Receiver disabled,Receiver enabled"
newline
bitfld.long 0x2A8 17. "PADCONFIG170_PULLTYPESEL_PROXY,Pad Pullup / Pulldown type selection" "Pulldown selected,Pullup selected"
newline
bitfld.long 0x2A8 16. "PADCONFIG170_PULLUDEN_PROXY,Pad Pullup / Pulldown enable" "Pullup / Pulldown enabled,Pullup / Pulldown disabled"
newline
bitfld.long 0x2A8 15. "PADCONFIG170_FORCE_DS_EN_PROXY,Enable pad Deep Sleep controls by overriding DMSC gating" "Deep Sleep pad controls are gated by the DMSC,Activate Deep Sleep pad controls (override DMSC.."
newline
bitfld.long 0x2A8 14. "PADCONFIG170_ST_EN_PROXY,Receiver Schmitt Trigger enable" "Schmitt trigger input disabled,Schmitt trigger input enabled"
newline
bitfld.long 0x2A8 11.--13. "PADCONFIG170_DEBOUNCE_SEL_PROXY,Selects the debouce period for the pad" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2A8 8. "PADCONFIG170_WK_LVL_POL_PROXY,Level Sensitive Wakeup Polarity This bit is not relevant unless wk_lvl_en is set to 1'b1" "Low,High"
newline
bitfld.long 0x2A8 7. "PADCONFIG170_WK_LVL_EN_PROXY,Level Sensitive Wakeup Enable" "Disabled,Enabled"
newline
bitfld.long 0x2A8 0.--3. "PADCONFIG170_MUXMODE_PROXY,Pad functional signal mux selection Field values (others are reserved)" "Mux Mode 0,Mux Mode 1,Mux Mode 2,Mux Mode 3,Mux Mode 4,Mux Mode 5,Mux Mode 6,Mux Mode 7,Mux Mode 8,Mux Mode 9,Mux Mode 10,Mux Mode 11,Mux Mode 12,Mux Mode 13,Mux Mode 14,Mux Mode 15"
group.long 0x7008++0x07
line.long 0x00 "CFG0_LOCK1_KICK0_PROXY,"
line.long 0x04 "CFG0_LOCK1_KICK1_PROXY,"
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x7100)++0x03
line.long 0x00 "CFG0_CLAIMREG_P1_R$1,"
repeat.end
tree.end
repeat 7. (list 0. 1. 2. 3. 4. 5. 6. )(list ad:0x2800000 ad:0x2810000 ad:0x2820000 ad:0x2830000 ad:0x2840000 ad:0x2850000 ad:0x2860000 )
tree "UART$1"
base $2
group.long 0x00++0x03
line.long 0x00 "MEM_DLL,Divisor Latches Low Register"
hexmask.long.byte 0x00 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value"
rgroup.long 0x00++0x03
line.long 0x00 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "RHR,Receive holding register"
group.long 0x00++0x07
line.long 0x00 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER"
line.long 0x04 "MEM_DLH,Divisor Latches High Register"
hexmask.long.byte 0x04 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value"
group.long 0x04++0x03
line.long 0x00 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt"
bitfld.long 0x00 6.--7. "NOT_USED2," "0,1,2,3"
newline
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x00 4. "NOT_USED1," "0,1"
newline
bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x03
line.long 0x00 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt"
bitfld.long 0x00 7. "EOF_IT," "0,1"
newline
bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x00 4. "STS_FIFO_TRIG_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
newline
bitfld.long 0x00 2. "LAST_RX_BYTE_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x07
line.long 0x00 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 7. "CTS_IT," "0,1"
newline
bitfld.long 0x00 6. "RTS_IT," "0,1"
newline
bitfld.long 0x00 5. "XOFF_IT," "0,1"
newline
bitfld.long 0x00 4. "SLEEP_MODE," "0,1"
newline
bitfld.long 0x00 3. "MODEM_STS_IT," "0,1"
newline
bitfld.long 0x00 2. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
line.long 0x04 "MEM_EFR,Enhanced Feature Register"
bitfld.long 0x04 7. "AUTO_CTS_EN,Auto-CTS enable bit" "Normal operation,Auto-CTS flow control is enabled i.e"
newline
bitfld.long 0x04 6. "AUTO_RTS_EN,Auto-RTS enable bit" "Normal operation,Auto- RTS flow control is enabled i.e"
newline
bitfld.long 0x04 5. "SPECIAL_CHAR_DETECT," "0,1"
newline
bitfld.long 0x04 4. "ENHANCED_EN,Enhanced functions write enable bit" "Disables writing to IER bits 4-7 FCR bits 4-5..,Enables writing to IER bits 4-7 FCR bits 4-5 and.."
newline
bitfld.long 0x04 0.--3. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "MEM_FCR,Notes: Bits 4 and 5 can only be written to when EFR[4] = 1 Bits 0 to 3 can be changed only when the baud clock is not running (DLL and DLH set to 0) See Table 31 for FCR[5:4] setting restriction when SCR[6]=1 See Table 32 for FCR[7:6] setting.."
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] =" "8 characters,16 characters,56 characters,60 characters If SCR[7] = 0 and.."
newline
bitfld.long 0x00 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] =" "8 spaces,16 spaces,32 spaces,56 spaces If SCR[6] = 0.."
newline
bitfld.long 0x00 3. "DMA_MODE,This register is considered if SCR[0] = 0" "0,1"
newline
bitfld.long 0x00 2. "TX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x00 1. "RX_FIFO_CLEAR," "0,1"
newline
bitfld.long 0x00 0. "FIFO_EN," "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner"
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner"
bitfld.long 0x00 7. "EOF_IT," "0,1"
newline
bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
newline
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
newline
bitfld.long 0x00 4. "STS_FIFO_IT," "0,1"
newline
bitfld.long 0x00 3. "RX_OE_IT," "0,1"
newline
bitfld.long 0x00 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
newline
bitfld.long 0x00 1. "THR_IT," "0,1"
newline
bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x0B
line.long 0x00 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
newline
bitfld.long 0x00 1.--5. "IT_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0. "IT_PENDING," "0,1"
line.long 0x04 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception.Note: As soon as LCR[6] is set to 1. the TX line is forced to 0 and remains in this state as long as LCR[6] = 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "DIV_EN," "0,1"
newline
bitfld.long 0x04 6. "BREAK_EN,Break control bit" "0,1"
newline
bitfld.long 0x04 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]" "0,1"
newline
bitfld.long 0x04 4. "PARITY_TYPE1," "0,1"
newline
bitfld.long 0x04 3. "PARITY_EN," "0,1"
newline
bitfld.long 0x04 2. "NB_STOP,Specifies the number of stop bits" "0,1"
newline
bitfld.long 0x04 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3"
line.long 0x08 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x08 7. "RESERVED," "0,1"
newline
bitfld.long 0x08 6. "TCR_TLR," "0,1"
newline
bitfld.long 0x08 5. "XON_EN," "0,1"
newline
bitfld.long 0x08 4. "LOOPBACK_EN," "0,1"
newline
bitfld.long 0x08 3. "CD_STS_CH," "0,1"
newline
bitfld.long 0x08 2. "RI_STS_CH," "0,1"
newline
bitfld.long 0x08 1. "RTS,In loop back controls MSR[4]" "0,1"
newline
bitfld.long 0x08 0. "DTR," "0,1"
group.long 0x10++0x07
line.long 0x00 "MEM_XON1_ADDR1,XON1/ADDR1 Register"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes"
line.long 0x04 "MEM_LSR_CIR,"
bitfld.long 0x04 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x04 6. "RESERVED," "0,1"
newline
bitfld.long 0x04 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR)" "0,1"
newline
bitfld.long 0x04 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "MEM_LSR_IRDA,"
bitfld.long 0x00 7. "THR_EMPTY," "0,1"
newline
bitfld.long 0x00 6. "STS_FIFO_FULL," "0,1"
newline
bitfld.long 0x00 5. "RX_LAST_BYTE," "0,1"
newline
bitfld.long 0x00 4. "FRAME_TOO_LONG," "0,1"
newline
bitfld.long 0x00 3. "ABORT," "0,1"
newline
bitfld.long 0x00 2. "CRC," "0,1"
newline
bitfld.long 0x00 1. "STS_FIFO_E," "0,1"
newline
bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "MEM_LSR_UART,"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 7. "RX_FIFO_STS," "0,1"
newline
bitfld.long 0x00 6. "TX_SR_E," "0,1"
newline
bitfld.long 0x00 5. "TX_FIFO_E," "0,1"
newline
bitfld.long 0x00 4. "RX_BI," "0,1"
newline
bitfld.long 0x00 3. "RX_FE," "0,1"
newline
bitfld.long 0x00 2. "RX_PE," "0,1"
newline
bitfld.long 0x00 1. "RX_OE," "0,1"
newline
bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x07
line.long 0x00 "MEM_XON2_ADDR2,XON2/ADDR2 Register"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes"
line.long 0x04 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "NCD_STS,This bit is the complement of the DCD* input" "0,1"
newline
bitfld.long 0x04 6. "NRI_STS,This bit is the complement of the RI* input" "0,1"
newline
bitfld.long 0x04 5. "NDSR_STS,This bit is the complement of the DSR* input" "0,1"
newline
bitfld.long 0x04 4. "NCTS_STS,This bit is the complement of the CTS* input" "0,1"
newline
bitfld.long 0x04 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed" "0,1"
newline
bitfld.long 0x04 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high" "0,1"
newline
bitfld.long 0x04 1. "DSR_STS," "0,1"
newline
bitfld.long 0x04 0. "CTS_STS," "0,1"
group.long 0x18++0x03
line.long 0x00 "MEM_TCR,Transmission Control Register"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x07
line.long 0x00 "MEM_XOFF1,XOFF1 Register"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes"
line.long 0x04 "MEM_SPR,This read/write register does not control the module in anyway"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x04 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x03
line.long 0x00 "MEM_TLR,Trigger Level Register"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x0F
line.long 0x00 "MEM_XOFF2,XOFF2 Register"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes"
line.long 0x04 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR)"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "FRAME_END_MODE,IrDA mode only" "0,1"
newline
bitfld.long 0x04 6. "SIP_MODE,MIR/FIR modes only" "0,1"
newline
bitfld.long 0x04 5. "SCT,Store and control the transmission" "0,1"
newline
bitfld.long 0x04 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1"
newline
bitfld.long 0x04 3. "IR_SLEEP," "0,1"
newline
bitfld.long 0x04 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7"
line.long 0x08 "MEM_MDR2,IR-IrDA and IR-CIR modes only.MDR2[0] describes the status of the interrupt in IIR[5]"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x08 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1"
newline
bitfld.long 0x08 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block" "0,1"
newline
bitfld.long 0x08 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition" "0,1,2,3"
newline
bitfld.long 0x08 3. "UART_PULSE,UART mode only" "0,1"
newline
bitfld.long 0x08 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode" "0,1,2,3"
newline
rbitfld.long 0x08 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is" "0,1"
line.long 0x0C "MEM_SFLSR,IrDA modes only.Reading this register effectively reads frame status information from the status FIFO (this register doesn't physically exist)"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0C 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 4. "OE_ERROR," "0,1"
newline
bitfld.long 0x0C 3. "FRAME_TOO_LONG_ERROR," "0,1"
newline
bitfld.long 0x0C 2. "ABORT_DETECT," "0,1"
newline
bitfld.long 0x0C 1. "CRC_ERROR," "0,1"
newline
bitfld.long 0x0C 0. "RESERVED0," "0,1"
group.long 0x28++0x07
line.long 0x00 "MEM_TXFLL,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes)"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
line.long 0x04 "MEM_RESUME,IR-IrDA and IR-CIR modes only.This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x04 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x07
line.long 0x00 "MEM_TXFLH,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes)"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "TXFLH,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "MEM_RXFLL,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x04 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x07
line.long 0x00 "MEM_SFREGL,IrDA modes only.The frame lengths of received frames are written into the status FIFO"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "SFREGL,LSB part of the frame length"
line.long 0x04 "MEM_RXFLH,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x04 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--3. "RXFLH,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x34++0x07
line.long 0x00 "MEM_SFREGH,IrDA modes only.The frame lengths of received frames are written into the status FIFO"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "SFREGH,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MEM_BLR,IrDA modes only.Note that BLR[6] is used to select whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR Mode"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "STS_FIFO_RESET,Status FIFO reset" "0,1"
newline
bitfld.long 0x04 6. "XBOF_TYPE,SIR xBOF select" "0,1"
newline
rbitfld.long 0x04 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x38++0x13
line.long 0x00 "MEM_UASR,UART Autobauding Status Register"
bitfld.long 0x00 6.--7. "PARITY_TYPE," "?,Parity space,Even Parity,Odd Parity"
newline
bitfld.long 0x00 5. "BIT_BY_CHAR," "0,1"
newline
bitfld.long 0x00 0.--4. "SPEED,Used to report the speed identified" "No speed identified,115200 bauds,57600 bauds,38400 bauds,28800 bauds,19200 bauds,14400 bauds,9600 bauds,4800 bauds,2400 bauds,1200 bauds,?..."
line.long 0x04 "MEM_ACREG,IR-IrDA and IR-CIR modes only"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "PULSE_TYPE,SIR pulse width select" "0,1"
newline
bitfld.long 0x04 6. "SD_MOD,Primary output used to configure transceivers" "0,1"
newline
bitfld.long 0x04 5. "DIS_IR_RX," "0,1"
newline
bitfld.long 0x04 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt" "0,1"
newline
bitfld.long 0x04 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission" "0,1"
newline
bitfld.long 0x04 2. "SCTX_EN,Store and controlled TX start" "0,1"
newline
bitfld.long 0x04 1. "ABORT_EN,Frame Abort" "0,1"
newline
bitfld.long 0x04 0. "EOT_EN,EOT [end of transmission] bit" "0,1"
line.long 0x08 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x08 7. "RX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x08 6. "TX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x08 5. "DSR_IT," "0,1"
newline
bitfld.long 0x08 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1"
newline
bitfld.long 0x08 3. "TX_EMPTY_CTL_IT," "0,1"
newline
bitfld.long 0x08 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3"
newline
bitfld.long 0x08 0. "DMA_MODE_CTL," "0,1"
line.long 0x0C "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0C 3.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 2. "DMA_COUNTER_RST," "0,1"
newline
rbitfld.long 0x0C 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1"
newline
rbitfld.long 0x0C 0. "TX_FIFO_FULL," "0,1"
line.long 0x10 "MEM_EBLR,IR-IrDA and IR-CIR modes only.In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,"
newline
abitfld.long 0x10 0.--7. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification" "0x00=feature disabled,0x01=generate RX_STOP interrupt after receiving..,0xFF=generate RX_STOP interrupt after receiving.."
rgroup.long 0x50++0x57
line.long 0x00 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module"
bitfld.long 0x00 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function revision number of module"
newline
bitfld.long 0x00 11.--15. "RTL,Rtl revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x04 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3"
newline
bitfld.long 0x04 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1"
newline
bitfld.long 0x04 1. "SOFTRESET,Software reset" "0,1"
newline
bitfld.long 0x04 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
line.long 0x08 "MEM_SYSS,"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x08 1.--7. 1. "RESERVED,"
newline
bitfld.long 0x08 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x0C "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0C 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
newline
bitfld.long 0x0C 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0C 5. "EVENT_5_RHR_INTERRUPT," "0,1"
newline
bitfld.long 0x0C 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 1. "EVENT_1_DSR_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x10 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x10 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]"
line.long 0x14 "MEM_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x14 0.--7. 1. "RXFIFO_LVL,"
line.long 0x18 "MEM_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x18 0.--7. 1. "TXFIFO_LVL,"
line.long 0x1C "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x1C 3.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 2. "RHR_IT_DIS," "0,1"
newline
bitfld.long 0x1C 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt" "0,1"
newline
bitfld.long 0x1C 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt" "0,1"
line.long 0x20 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x20 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x20 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1"
newline
bitfld.long 0x20 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1"
line.long 0x24 "MEM_FREQ_SEL,Sample per bit value selector"
hexmask.long.byte 0x24 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used"
line.long 0x28 "MEM_ABAUD_1ST_CHAR,Unused"
line.long 0x2C "MEM_BAUD_2ND_CHAR,Unused"
line.long 0x30 "MEM_MDR3,Mode definition register 3"
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED2,"
newline
bitfld.long 0x30 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
newline
bitfld.long 0x30 3. "DIR_POL,RS-485 External Transceiver Direction Polarity" "TX,TX"
newline
bitfld.long 0x30 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1"
newline
bitfld.long 0x30 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x30 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1"
line.long 0x34 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level.MDR3[2] SET_TX_DMA_THRESHOLD must be one and must be value + tx_trigger_level <= 64 (TX FIFO size).If not. 64-tx_trigger_level will be used w/o modifying the value of this register"
bitfld.long 0x34 0.--5. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "MEM_MDR4,Mode definition register 4"
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x38 7. "RESERVED," "0,1"
newline
bitfld.long 0x38 6. "MODE9,9-bit character length" "0,1"
newline
bitfld.long 0x38 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7"
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bitfld.long 0x38 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7"
line.long 0x3C "MEM_EFR2,Enhanced Features Register 2"
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED1,"
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bitfld.long 0x3C 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
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bitfld.long 0x3C 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
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bitfld.long 0x3C 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
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bitfld.long 0x3C 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
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bitfld.long 0x3C 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
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bitfld.long 0x3C 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1"
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bitfld.long 0x3C 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1"
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bitfld.long 0x3C 0. "ENDIAN,Endianness" "0,1"
line.long 0x40 "MEM_ECR,Enhanced Control register"
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED1,"
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rbitfld.long 0x40 6.--7. "RESERVED," "0,1,2,3"
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bitfld.long 0x40 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
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bitfld.long 0x40 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x40 3. "RX_EN,Enables/Disables the receiver" "0,1"
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bitfld.long 0x40 2. "TX_RST,Writing '1' resets the transmitter" "0,1"
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bitfld.long 0x40 1. "RX_RST,Writing '1' resets the receiver" "0,1"
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bitfld.long 0x40 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1"
line.long 0x44 "MEM_TIMEGUARD,Timeguard"
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,"
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hexmask.long.byte 0x44 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices"
line.long 0x48 "MEM_TIMEOUTL,Timeout lower byte"
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,"
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hexmask.long.byte 0x48 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0"
line.long 0x4C "MEM_TIMEOUTH,Timeout higher byte"
hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,"
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hexmask.long.byte 0x4C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0"
line.long 0x50 "MEM_SCCR,Smartcard (ISO7816) mode Control Register"
hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED1,"
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bitfld.long 0x50 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error" "0,1"
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bitfld.long 0x50 6. "INACK,Inhibit NACK when receiving even if an error is received" "0,1"
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rbitfld.long 0x50 3.--5. "RESERVED," "0,1,2,3,4,5,6,7"
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bitfld.long 0x50 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge" "0,1,2,3,4,5,6,7"
line.long 0x54 "MEM_ERHR,Extended Receive Holding Register"
hexmask.long.tbyte 0x54 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x54 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR"
group.long 0xA4++0x0F
line.long 0x00 "MEM_ETHR,Extended Transmit Holding Register"
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x00 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR"
line.long 0x04 "MEM_MAR,Multidrop Address Register"
hexmask.long.byte 0x04 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x08 "MEM_MMR,Multidrop Mask Register"
hexmask.long.byte 0x08 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0x0C "MEM_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0x0C 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
repeat.end
tree "VIM_CFG"
base ad:0x2FFF0000
rgroup.long 0x00++0x27
line.long 0x00 "R5FSS_VIM_PID,This register contains the major and minor revisions for the module"
line.long 0x04 "R5FSS_VIM_INFO,This contains information about the configuration of the R5FSS_VIM"
hexmask.long.word 0x04 0.--10. 1. "INTERRUPTS,Indicates the number of interrupts supported by the VIM"
line.long 0x08 "R5FSS_VIM_PRIIRQ,This register contains the number of the highest priority pending IRQ"
bitfld.long 0x08 31. "VALID,This field indicates if the NUM field of this register is valid" "0,1"
bitfld.long 0x08 16.--19. "PRI,This field indicates the priority of the pending IRQ interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x08 0.--9. 1. "NUM,This field indicates the interrupt number of the pending IRQ interrupt with the highest priority"
line.long 0x0C "R5FSS_VIM_PRIFIQ,This register contains the number of the highest priority pending FIQ"
bitfld.long 0x0C 31. "VALID,This field indicates if the NUM field of this register is valid" "0,1"
bitfld.long 0x0C 16.--19. "PRI,This field indicates the priority of the pending FIQ interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x0C 0.--9. 1. "NUM,This field indicates the interrupt number of the pending FIQ interrupt with the highest priority"
line.long 0x10 "R5FSS_VIM_IRQGSTS,This register indicates which groups of interrupts have pending. unmasked IRQ interrupts"
line.long 0x14 "R5FSS_VIM_FIQGSTS,This register indicates which groups of interrupts have pending. unmasked FIQ interrupts"
line.long 0x18 "R5FSS_VIM_IRQVEC,This register contains the 32-bit interrupt vector address of the currently pending IRQ"
hexmask.long 0x18 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (addresses must be 32-bit aligned) of the currently pending highest priority IRQ (as indicated by"
line.long 0x1C "R5FSS_VIM_FIQVEC,This register contains the 32-bit interrupt vector address of the currently pending FIQ"
hexmask.long 0x1C 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (addresses must be 32-bit aligned) of the currently pending highest priority FIQ (as indicated by"
line.long 0x20 "R5FSS_VIM_ACTIRQ,This register contains the number of the active IRQ"
bitfld.long 0x20 31. "VALID,This field indicates if the NUM field of this register is valid" "0,1"
bitfld.long 0x20 16.--19. "PRI,This field indicates the priority of the active IRQ interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x20 0.--9. 1. "NUM,This field indicates the interrupt number of the active IRQ interrupt"
line.long 0x24 "R5FSS_VIM_ACTFIQ,This register contains the number of the active FIQ"
bitfld.long 0x24 31. "VALID,This field indicates if the NUM field of this register is valid" "0,1"
bitfld.long 0x24 16.--19. "PRI,This field indicates the priority of the active FIQ interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x24 0.--9. 1. "NUM,This field indicates the interrupt number of the active FIQ interrupt"
group.long 0x30++0x03
line.long 0x00 "R5FSS_VIM_DEDVEC,This register contains the 32-bit interrupt vector address to be used as a default in case of a DED error in any of the vectors"
hexmask.long 0x00 2.--31. 1. "ADDR,This field contains the upper 30 bits of the 32-bit interrupt vector address (the address must be 32-bit aligned) of an interrupt to be used if an uncorrectable double-bit error (DED) is detected in any of the interrupt vector addresses"
group.long 0x400++0x1F
line.long 0x00 "R5FSS_VIM_RAW_j,This register indicates the raw status of the events in group M"
line.long 0x04 "R5FSS_VIM_STS_j,This register indicates the masked status of the events in group M"
line.long 0x08 "R5FSS_VIM_INTR_EN_SET_j,This register is used to enable the mask for the events in group M"
line.long 0x0C "R5FSS_VIM_INTR_EN_CLR_j,This register is used to disable the mask for the events in group M"
line.long 0x10 "R5FSS_VIM_IRQSTS_j,This register indicates the masked status of the events in Group M that are also mapped as IRQs"
line.long 0x14 "R5FSS_VIM_FIQSTS_j,This register indicates the masked status of the events in group M that are also mapped as FIQs"
line.long 0x18 "R5FSS_VIM_INTMAP_j,This register is used to map interrupts as IRQ or FIQ"
line.long 0x1C "R5FSS_VIM_INTTYPE_j,This register indicates whether an interrupt is a pulse or level source"
group.long 0x1000++0x03
line.long 0x00 "R5FSS_VIM_PRI_INT_j,This register is used to set the priority of interrupt Q"
bitfld.long 0x00 0.--3. "VAL,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2000++0x03
line.long 0x00 "R5FSS_VIM_VEC_INT_j,This register contains the vector address associated with interrupt Q"
hexmask.long 0x00 2.--31. 1. "VAL,These are the upper 30 bits of the 32-bit vector address associated with interrupt Q"
width 0x0B
tree.end
tree "WKUP_CBASS0_ERR"
base ad:0x2B400000
rgroup.long 0x00++0x07
line.long 0x00 "ERR_REGS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ERR_REGS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,The destination ID"
rgroup.long 0x24++0x17
line.long 0x00 "ERR_REGS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x00 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x00 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x04 "ERR_REGS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x04 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x04 16.--23. 1. "CODE,Code"
line.long 0x08 "ERR_REGS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x0C "ERR_REGS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x0C 0.--15. 1. "ADDR_H,Address upper 16 bits"
line.long 0x10 "ERR_REGS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x10 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x10 13. "WRITE," "0,1"
bitfld.long 0x10 12. "READ," "0,1"
bitfld.long 0x10 11. "DEBUG,Debug" "0,1"
bitfld.long 0x10 10. "CACHEABLE,Cacheable" "0,1"
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bitfld.long 0x10 9. "PRIV,Priv" "0,1"
bitfld.long 0x10 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x14 "ERR_REGS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x14 0.--9. 1. "BYTECNT,Byte count"
group.long 0x50++0x13
line.long 0x00 "ERR_REGS_err_intr_raw_stat,Global Interrupt Raw Status Register"
bitfld.long 0x00 0. "INTR,Level Interrupt status" "0,1"
line.long 0x04 "ERR_REGS_err_intr_enabled_stat,Global Interrupt Enabled Status Register"
bitfld.long 0x04 0. "ENABLED_INTR,Level Enabled Interrupt status" "0,1"
line.long 0x08 "ERR_REGS_err_intr_enable_set,Interrupt Enable Set Register"
bitfld.long 0x08 0. "INTR_ENABLE_SET,Interrupt Enable Set Register" "0,1"
line.long 0x0C "ERR_REGS_err_intr_enable_clr,Interrupt Enable Clear Register"
bitfld.long 0x0C 0. "INTR_ENABLE_CLR,Interrupt Enable Clear Register" "0,1"
line.long 0x10 "ERR_REGS_err_eoi,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
tree.end
tree "WKUP_I2C0_CFG"
base ad:0x2B200000
rgroup.long 0x00++0x07
line.long 0x00 "CFG_I2C_REVNB_LO,Revision Number register (Low)"
bitfld.long 0x00 11.--15. "RTL,RTL version This field changes on bug fix and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix or major feature change" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CFG_I2C_REVNB_HI,Revision Number register (High)"
bitfld.long 0x04 14.--15. "SCHEME,Used to distinguish between old Scheme and current Spare bit to encode future schemes" "0,1,2,3"
bitfld.long 0x04 12.--13. "RESERVED,Reads return 0x1" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. "FUNC,Function: Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "CFG_I2C_SYSC,System Configuration register"
bitfld.long 0x00 8.--9. "CLKACTIVITY,Clock Activity selection bits" "0,1,2,3"
bitfld.long 0x00 5.--7. "RESERVED,Reads return 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--4. "IDLEMODE,Idle Mode selection bits" "0,1,2,3"
bitfld.long 0x00 2. "ENAWAKEUP,Enable Wakeup control bit" "0,1"
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bitfld.long 0x00 1. "SRST,SoftReset bit" "0,1"
bitfld.long 0x00 0. "AUTOIDLE,Autoidle bit" "0,1"
group.long 0x20++0x2F
line.long 0x00 "CFG_I2C_EOI,End Of Interrupt number specification"
bitfld.long 0x00 0. "LINE_NUMBER,Software End Of Interrupt [EOI] control Write number of interrupt output" "0,1"
line.long 0x04 "CFG_I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
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bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x08 "CFG_I2C_IRQSTATUS,Per-event enabled interrupt status vector"
bitfld.long 0x08 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x08 14. "XDR,Transmit draining IRQ enabled status" "0,1"
bitfld.long 0x08 13. "RDR,Receive draining IRQ enabled status" "0,1"
rbitfld.long 0x08 12. "BB,Bus busy enabled statusWriting into this bit has no effect" "0,1"
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bitfld.long 0x08 11. "ROVR,Receive overrun enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 10. "XUDF,Transmit underflow enabled statusWriting into this bit has no effect" "0,1"
bitfld.long 0x08 9. "AAS,Address recognized as slave IRQ enabled status" "0,1"
bitfld.long 0x08 8. "BF,Bus Free IRQ enabled status" "0,1"
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bitfld.long 0x08 7. "AERR,Access Error IRQ enabled status" "0,1"
bitfld.long 0x08 6. "STC,Start Condition IRQ enabled status" "0,1"
bitfld.long 0x08 5. "GC,General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 4. "XRDY,Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x08 3. "RRDY,Receive data ready IRQ enabled status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 2. "ARDY,Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x08 1. "NACK,No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x08 0. "AL,Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
line.long 0x0C "CFG_I2C_IRQENABLE_SET,Per-event interrupt enable bit vector"
bitfld.long 0x0C 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x0C 14. "XDR_IE,Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x0C 13. "RDR_IE,Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x0C 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x0C 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x0C 9. "ASS_IE,Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x0C 8. "BF_IE,Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x0C 7. "AERR_IE,Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x0C 6. "STC_IE,Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x0C 5. "GC_IE,General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x0C 4. "XRDY_IE,Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x0C 3. "RRDY_IE,Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x0C 2. "ARDY_IE,Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x0C 1. "NACK_IE,No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x0C 0. "AL_IE,Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x10 "CFG_I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector"
bitfld.long 0x10 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x10 14. "XDR_IE,Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x10 13. "RDR_IE,Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x10 11. "ROVR,Receive overrun enable clear" "0,1"
newline
bitfld.long 0x10 10. "XUDF,Transmit underflow enable clear" "0,1"
bitfld.long 0x10 9. "ASS_IE,Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x10 8. "BF_IE,Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x10 7. "AERR_IE,Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x10 6. "STC_IE,Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x10 5. "GC_IE,General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x10 4. "XRDY_IE,Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x10 3. "RRDY_IE,Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x10 2. "ARDY_IE,Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x10 1. "NACK_IE,No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x10 0. "AL_IE,Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x14 "CFG_I2C_WE,I2C wakeup enable vector (legacy)"
bitfld.long 0x14 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x14 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x14 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x14 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x14 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x14 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x14 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x14 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x14 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x14 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x14 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x14 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x18 "CFG_I2C_DMARXENABLE_SET,Per-event DMA RX enable set"
bitfld.long 0x18 0. "DMARX_ENABLE_SET,Receive DMA channel enable set" "0,1"
line.long 0x1C "CFG_I2C_DMATXENABLE_SET,Per-event DMA TX enable set"
bitfld.long 0x1C 0. "DMATX_ENABLE_SET,Transmit DMA channel enable set" "0,1"
line.long 0x20 "CFG_I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear"
bitfld.long 0x20 0. "DMARX_ENABLE_CLEAR,Receive DMA channel enable clear" "0,1"
line.long 0x24 "CFG_I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear"
bitfld.long 0x24 0. "DMATX_ENABLE_CLEAR,Transmit DMA channel enable clear" "0,1"
line.long 0x28 "CFG_I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable"
bitfld.long 0x28 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x28 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x28 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x28 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x28 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x28 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x28 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x28 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x28 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x28 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x28 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x28 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
line.long 0x2C "CFG_I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable"
bitfld.long 0x2C 14. "XDR,Transmit Draining wakeup set" "0,1"
bitfld.long 0x2C 13. "RDR,Receive Draining wakeup set" "0,1"
bitfld.long 0x2C 11. "ROVR,Receive overrun wakeup set" "0,1"
bitfld.long 0x2C 10. "XUDF,Transmit underflow wakeup set" "0,1"
newline
bitfld.long 0x2C 9. "AAS,Address as slave IRQ wakeup set" "0,1"
bitfld.long 0x2C 8. "BF,Bus Free IRQ wakeup set" "0,1"
bitfld.long 0x2C 6. "STC,Start Condition IRQ wakeup set" "0,1"
bitfld.long 0x2C 5. "GC,General call IRQ wakeup set" "0,1"
newline
bitfld.long 0x2C 3. "DRDY,Receive/Transmit data ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 2. "ARDY,Register access ready IRQ wakeup set" "0,1"
bitfld.long 0x2C 1. "NACK,No acknowledgment IRQ wakeup set" "0,1"
bitfld.long 0x2C 0. "AL,Arbitration lost IRQ wakeup set" "0,1"
group.long 0x84++0x07
line.long 0x00 "CFG_I2C_IE,I2C interrupt enable vector (legacy)"
bitfld.long 0x00 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x00 14. "XDR_IE,Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR]" "0,1"
bitfld.long 0x00 13. "RDR_IE,Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR]" "0,1"
bitfld.long 0x00 11. "ROVR,Receive overrun enable set" "0,1"
newline
bitfld.long 0x00 10. "XUDF,Transmit underflow enable set" "0,1"
bitfld.long 0x00 9. "ASS_IE,Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS]" "0,1"
bitfld.long 0x00 8. "BF_IE,Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF]" "0,1"
bitfld.long 0x00 7. "AERR_IE,Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR]" "0,1"
newline
bitfld.long 0x00 6. "STC_IE,Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC]" "0,1"
bitfld.long 0x00 5. "GC_IE,General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC]" "0,1"
bitfld.long 0x00 4. "XRDY_IE,Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY]" "0,1"
bitfld.long 0x00 3. "RRDY_IE,Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]" "0,1"
newline
bitfld.long 0x00 2. "ARDY_IE,Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY]" "0,1"
bitfld.long 0x00 1. "NACK_IE,No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK]" "0,1"
bitfld.long 0x00 0. "AL_IE,Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL]" "0,1"
line.long 0x04 "CFG_I2C_STAT,I2C interrupt status vector (legacy)"
bitfld.long 0x04 15. "RESERVED,Write 0s for future compatibility Read returns 0" "0,1"
bitfld.long 0x04 14. "XDR,Transmit draining IRQ status" "0,1"
bitfld.long 0x04 13. "RDR,Receive draining IRQ status" "0,1"
rbitfld.long 0x04 12. "BB,Bus busy statusWriting into this bit has no effect" "0,1"
newline
bitfld.long 0x04 11. "ROVR,Receive overrun statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 10. "XUDF,Transmit underflow statusWriting into this bit has no effect" "0,1"
bitfld.long 0x04 9. "AAS,Address recognized as slave IRQ status" "0,1"
bitfld.long 0x04 8. "BF,Bus Free IRQ status" "0,1"
newline
bitfld.long 0x04 7. "AERR,Access Error IRQ status" "0,1"
bitfld.long 0x04 6. "STC,Start Condition IRQ status" "0,1"
bitfld.long 0x04 5. "GC,General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 4. "XRDY,Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
newline
bitfld.long 0x04 3. "RRDY,Receive data ready IRQ status Set to '1' by core when receiver mode a new data is able to be read When set to '1' by core an interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear" "0,1"
bitfld.long 0x04 1. "NACK,No acknowledgement IRQ status Bit is set when No Acknowledge has been received an interrupt is signaled to MPUSS Write '1' to clear this bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode an interrupt is signaled to MPUSS During reads it always returns 0" "0,1"
rgroup.long 0x90++0x0F
line.long 0x00 "CFG_I2C_SYSS,System Status register"
bitfld.long 0x00 0. "RDONE,Reset done bit" "0,1"
line.long 0x04 "CFG_I2C_BUF,Buffer Configuration register"
bitfld.long 0x04 15. "RDMA_EN,Receive DMA channel enable" "0,1"
bitfld.long 0x04 14. "RXFIFO_CLR,Receive FIFO clear" "0,1"
bitfld.long 0x04 8.--13. "RXTRSH,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 7. "XDMA_EN,Transmit DMA channel enable" "0,1"
newline
bitfld.long 0x04 6. "TXFIFO_CLR,Transmit FIFO clear" "0,1"
bitfld.long 0x04 0.--5. "TXTRSH,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "CFG_I2C_CNT,Data counter register"
hexmask.long.word 0x08 0.--15. 1. "DCOUNT,Data count"
line.long 0x0C "CFG_I2C_DATA,Data access register"
hexmask.long.byte 0x0C 0.--7. 1. "DATA,Transmit/Receive data FIFO endpoint"
group.long 0xA4++0x33
line.long 0x00 "CFG_I2C_CON,I2C configuration register"
bitfld.long 0x00 15. "I2C_EN,I2C module enable" "0,1"
bitfld.long 0x00 12.--13. "OPMODE,Operation mode selection" "0,1,2,3"
bitfld.long 0x00 11. "STB,Start byte mode [master mode only]" "0,1"
bitfld.long 0x00 10. "MST,Master/slave mode" "0,1"
newline
bitfld.long 0x00 9. "TRX,Transmitter/Receiver mode [master mode only]" "0,1"
bitfld.long 0x00 8. "XSA,Expand Slave address" "0,1"
bitfld.long 0x00 7. "XOA0,Expand Own address 0" "0,1"
bitfld.long 0x00 6. "XOA1,Expand Own address 1" "0,1"
newline
bitfld.long 0x00 5. "XOA2,Expand Own address 2" "0,1"
bitfld.long 0x00 4. "XOA3,Expand Own address 3" "0,1"
bitfld.long 0x00 1. "STP,Stop condition [master mode only]" "0,1"
bitfld.long 0x00 0. "STT,Start condition [master mode only]" "0,1"
line.long 0x04 "CFG_I2C_OA,Own address register"
bitfld.long 0x04 13.--15. "MCODE,Master Code" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 0.--9. 1. "OA,Own address"
line.long 0x08 "CFG_I2C_SA,Slave address register"
hexmask.long.word 0x08 0.--9. 1. "SA,Slave address"
line.long 0x0C "CFG_I2C_PSC,I2C Clock Prescaler Register"
abitfld.long 0x0C 0.--7. "PSC,Fast/Standard mode prescale sampling clock divider value" "0x00=Divide by 1,0x01=Divide by 2,0xFF=Divide by 256"
line.long 0x10 "CFG_I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x10 8.--15. 1. "HSSCLL,High Speed mode SCL low time"
hexmask.long.byte 0x10 0.--7. 1. "SCLL,Fast/Standard mode SCL low time"
line.long 0x14 "CFG_I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x14 8.--15. 1. "HSSCLH,High Speed mode SCL high time"
hexmask.long.byte 0x14 0.--7. 1. "SCLH,Fast/Standard mode SCL high time"
line.long 0x18 "CFG_I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x18 15. "ST_EN,System test enable" "0,1"
bitfld.long 0x18 14. "FREE,Free running mode [on breakpoint]" "0,1"
bitfld.long 0x18 12.--13. "TMODE,Test mode select" "0,1,2,3"
bitfld.long 0x18 11. "SSB,Set status bits" "0,1"
newline
rbitfld.long 0x18 8. "SCL_I_FUNC,SCL line input value [functional mode]" "0,1"
rbitfld.long 0x18 7. "SCL_O_FUNC,SCL line output value [functional mode]" "0,1"
rbitfld.long 0x18 6. "SDA_I_FUNC,SDA line input value [functional mode]" "0,1"
rbitfld.long 0x18 5. "SDA_O_FUNC,SDA line output value [functional mode]" "0,1"
newline
bitfld.long 0x18 4. "SCCB_E_O,SCCB_E line sense output value" "0,1"
rbitfld.long 0x18 3. "SCL_I,SCL line sense input value" "0,1"
bitfld.long 0x18 2. "SCL_O,SCL line drive output value" "0,1"
rbitfld.long 0x18 1. "SDA_I,SDA line sense input value" "0,1"
newline
bitfld.long 0x18 0. "SDA_O,SDA line drive output value" "0,1"
line.long 0x1C "CFG_I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x1C 14.--15. "FIFODEPTH,Internal FIFO buffers depth" "0,1,2,3"
bitfld.long 0x1C 8.--13. "RXSTAT,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x1C 0.--5. "TXSTAT,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "CFG_I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x20 0.--9. 1. "OA1,Own address 1"
line.long 0x24 "CFG_I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x24 0.--9. 1. "OA2,Own address 2"
line.long 0x28 "CFG_I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x28 0.--9. 1. "OA3,Own address 3"
line.long 0x2C "CFG_I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x2C 3. "OA3_ACT,Own Address 3 active" "0,1"
bitfld.long 0x2C 2. "OA2_ACT,Own Address 2 active" "0,1"
bitfld.long 0x2C 1. "OA1_ACT,Own Address 1 active" "0,1"
bitfld.long 0x2C 0. "OA0_ACT,Own Address 0 active" "0,1"
line.long 0x30 "CFG_I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x30 3. "OA3_EN,Enable I2C Clock Blocking for Own Address 3" "0,1"
bitfld.long 0x30 2. "OA2_EN,Enable I2C Clock Blocking for Own Address 2" "0,1"
bitfld.long 0x30 1. "OA1_EN,Enable I2C Clock Blocking for Own Address 1" "0,1"
bitfld.long 0x30 0. "OA0_EN,Enable I2C Clock Blocking for Own Address 0" "0,1"
tree.end
tree "WKUP_PBIST0"
base ad:0x2B500000
group.long 0x00++0x7F
line.long 0x00 "MEM_RF0L,"
line.long 0x04 "MEM_RF1L,"
line.long 0x08 "MEM_RF2L,"
line.long 0x0C "MEM_RF3L,"
line.long 0x10 "MEM_RF4L,"
line.long 0x14 "MEM_RF5L,"
line.long 0x18 "MEM_RF6L,"
line.long 0x1C "MEM_RF7L,"
line.long 0x20 "MEM_RF8L,"
line.long 0x24 "MEM_RF9L,"
line.long 0x28 "MEM_RF10L,"
line.long 0x2C "MEM_RF11L,"
line.long 0x30 "MEM_RF12L,"
line.long 0x34 "MEM_RF13L,"
line.long 0x38 "MEM_RF14L,"
line.long 0x3C "MEM_RF15L,"
line.long 0x40 "MEM_RF0U,"
line.long 0x44 "MEM_RF1U,"
line.long 0x48 "MEM_RF2U,"
line.long 0x4C "MEM_RF3U,"
line.long 0x50 "MEM_RF4U,"
line.long 0x54 "MEM_RF5U,"
line.long 0x58 "MEM_RF6U,"
line.long 0x5C "MEM_RF7U,"
line.long 0x60 "MEM_RF8U,"
line.long 0x64 "MEM_RF9U,"
line.long 0x68 "MEM_RF10U,"
line.long 0x6C "MEM_RF11U,"
line.long 0x70 "MEM_RF12U,"
line.long 0x74 "MEM_RF13U,"
line.long 0x78 "MEM_RF14U,"
line.long 0x7C "MEM_RF15U,"
group.long 0x100++0x27
line.long 0x00 "MEM_A0,"
hexmask.long.word 0x00 0.--15. 1. "A0,Variable Address Register 0 (A0)"
line.long 0x04 "MEM_A1,"
hexmask.long.word 0x04 0.--15. 1. "A1,Variable Address Register 1 (A1)"
line.long 0x08 "MEM_A2,"
hexmask.long.word 0x08 0.--15. 1. "A2,Variable Address Register 2 (A2)"
line.long 0x0C "MEM_A3,"
hexmask.long.word 0x0C 0.--15. 1. "A3,Variable Address Register 3 (A3)"
line.long 0x10 "MEM_L0,"
hexmask.long.word 0x10 0.--15. 1. "L0,Variable Loop Count Register 0 (L0)"
line.long 0x14 "MEM_L1,"
hexmask.long.word 0x14 0.--15. 1. "L1,Variable Loop Count Register 1 (L1)"
line.long 0x18 "MEM_L2,"
hexmask.long.word 0x18 0.--15. 1. "L2,Variable Loop Count Register 2 (L2)"
line.long 0x1C "MEM_L3,"
hexmask.long.word 0x1C 0.--15. 1. "L3,Variable Loop Count Register 3 (L3)"
line.long 0x20 "MEM_D,"
hexmask.long.word 0x20 16.--31. 1. "D1,DD1 Data Register Upper 16 (D1)"
hexmask.long.word 0x20 0.--15. 1. "D0,DD0 Data Register Lower 16 (D0)"
line.long 0x24 "MEM_E,"
hexmask.long.word 0x24 16.--31. 1. "E1,EE1 Data Register Upper 16 (E1)"
hexmask.long.word 0x24 0.--15. 1. "E0,EE0 Data Register Lower 16 (E0)"
group.long 0x130++0x3F
line.long 0x00 "MEM_CA0,"
hexmask.long.word 0x00 0.--15. 1. "CA0,Constant Address Register 0 (CA0)"
line.long 0x04 "MEM_CA1,"
hexmask.long.word 0x04 0.--15. 1. "CA1,Constant Address Register 1 (CA1)"
line.long 0x08 "MEM_CA2,"
hexmask.long.word 0x08 0.--15. 1. "CA2,Constant Address Register 2 (CA2)"
line.long 0x0C "MEM_CA3,"
hexmask.long.word 0x0C 0.--15. 1. "CA3,Constant Address Register 3 (CA3)"
line.long 0x10 "MEM_CL0,"
hexmask.long.word 0x10 0.--15. 1. "CL0,Constant Loop Count Register 0 (CL0)"
line.long 0x14 "MEM_CL1,"
hexmask.long.word 0x14 0.--15. 1. "CL1,Constant Loop Count Register 1 (CL1)"
line.long 0x18 "MEM_CL2,"
hexmask.long.word 0x18 0.--15. 1. "CL2,Constant Loop Count Register 2 (CL2)"
line.long 0x1C "MEM_CL3,"
hexmask.long.word 0x1C 0.--15. 1. "CL3,Constant Loop Count Register 3 (CL3)"
line.long 0x20 "MEM_I0,"
hexmask.long.word 0x20 0.--15. 1. "I0,Constant Increment Register 0 (I0)"
line.long 0x24 "MEM_I1,"
hexmask.long.word 0x24 0.--15. 1. "I0,Constant Increment Register 1 (I1)"
line.long 0x28 "MEM_I2,"
hexmask.long.word 0x28 0.--15. 1. "I0,Constant Increment Register 2 (I2)"
line.long 0x2C "MEM_I3,"
hexmask.long.word 0x2C 0.--15. 1. "I0,Constant Increment Register 3 (I3)"
line.long 0x30 "MEM_RAMT,"
hexmask.long.byte 0x30 24.--31. 1. "RGS,RAM Group Select RGS"
hexmask.long.byte 0x30 16.--23. 1. "RDS,Return Data select RDS"
hexmask.long.byte 0x30 8.--15. 1. "DWR,Data Width Register DWR"
bitfld.long 0x30 2.--5. "PLS,Pipeline Latency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 0.--1. "RLS,RAM Latency Select" "0,1,2,3"
line.long 0x34 "MEM_DLR,"
hexmask.long.byte 0x34 16.--23. 1. "BRP,Datalogger 2 (BRP)"
bitfld.long 0x34 10. "DLR1_RTM,Retention testing mode" "0,1"
bitfld.long 0x34 9. "DLR1_GNG,GO / NO-GO testing mode" "0,1"
bitfld.long 0x34 8. "DLR1_MISR,MISR testing mode (mainly for ROM testing)" "0,1"
bitfld.long 0x34 7. "DLR0_TSM,Time stamp mode" "0,1"
bitfld.long 0x34 6. "DLR0_CFMM,Column Fail Masking mode" "0,1"
newline
bitfld.long 0x34 5. "DLR0_ECAM,Emulation cache access mode" "0,1"
bitfld.long 0x34 4. "DLR0_CAM,Config access mode" "0,1"
bitfld.long 0x34 3. "DLR0_TCK,TCK Gated mode" "0,1"
bitfld.long 0x34 2. "DLR0_ROM,ROM-based testing mode" "0,1"
bitfld.long 0x34 1. "DLR0_IDDQ,IDDQ testing mode" "0,1"
bitfld.long 0x34 0. "DLR0_DCM,Distributed Compare mode" "0,1"
line.long 0x38 "MEM_CMS,"
bitfld.long 0x38 0.--3. "CMS,Clock Mux Select (CMS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "MEM_STR,"
bitfld.long 0x3C 4. "CHK,Check MISR mode" "0,1"
bitfld.long 0x3C 3. "STEP,Step / Step for emulation mode" "0,1"
bitfld.long 0x3C 2. "STOP,Stop" "0,1"
bitfld.long 0x3C 1. "RES,Resume / Emulation read" "0,1"
bitfld.long 0x3C 0. "START,Start / Time Stamp mode restart" "0,1"
group.quad 0x170++0x07
line.quad 0x00 "MEM_SCR,"
hexmask.quad.byte 0x00 56.--63. 1. "SCR7,Address Scrambling Register 7"
hexmask.quad.byte 0x00 48.--55. 1. "SCR6,Address Scrambling Register 6"
hexmask.quad.byte 0x00 40.--47. 1. "SCR5,Address Scrambling Register 5"
hexmask.quad.byte 0x00 32.--39. 1. "SCR4,Address Scrambling Register 4"
hexmask.quad.byte 0x00 24.--31. 1. "SCR3,Address Scrambling Register 3"
hexmask.quad.byte 0x00 16.--23. 1. "SCR2,Address Scrambling Register 2"
newline
hexmask.quad.byte 0x00 8.--15. 1. "SCR1,Address Scrambling Register 1"
hexmask.quad.byte 0x00 0.--7. 1. "SCR0,Address Scrambling Register 0"
group.long 0x178++0x13
line.long 0x00 "MEM_CSR,"
hexmask.long.byte 0x00 24.--31. 1. "CSR3,Chip Select 3 (CSR3)"
hexmask.long.byte 0x00 16.--23. 1. "CSR2,Chip Select 2 (CSR2)"
hexmask.long.byte 0x00 8.--15. 1. "CSR1,Chip Select 1(CSR1)"
hexmask.long.byte 0x00 0.--7. 1. "CSR0,Chip Select 0 (CSR0)"
line.long 0x04 "MEM_FDLY,"
hexmask.long.byte 0x04 0.--7. 1. "FDLY,Fail Delay (FDLY)"
line.long 0x08 "MEM_PACT,"
bitfld.long 0x08 0. "PACT,PBIST Activate (PACT)" "0,1"
line.long 0x0C "MEM_PID,"
bitfld.long 0x0C 0.--4. "PID,PBIST ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "MEM_OVER,"
bitfld.long 0x10 3. "ALGO,PBIST Override Algorithm Override" "0,1"
bitfld.long 0x10 2. "MM,PBIST Override Multiple Memory" "0,1"
bitfld.long 0x10 1. "READ,PBIST Override READ Override" "0,1"
bitfld.long 0x10 0. "RINFO,PBIST Override RINFO Override" "0,1"
rgroup.quad 0x190++0x17
line.quad 0x00 "MEM_FSRF,"
bitfld.quad 0x00 32. "FRSF1,Fail Status Fail - Port 1 (FSRF1)" "0,1"
bitfld.quad 0x00 0. "FRSF0,Fail Status Fail - Port 0 (FSRF0)" "0,1"
line.quad 0x08 "MEM_FSRC,"
bitfld.quad 0x08 32.--35. "FSRC1,Fail Status Count - Port 1 (FSRC1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x08 0.--3. "FSRC0,Fail Status Count - Port 0 (FSRC0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.quad 0x10 "MEM_FSRA,"
hexmask.quad.word 0x10 32.--47. 1. "FSRA1,Fail Status Address - Port 1 (FSRA1)"
hexmask.quad.word 0x10 0.--15. 1. "FSRA0,Fail Status Address - Port 0 (FSRA0)"
rgroup.long 0x1A8++0x03
line.long 0x00 "MEM_FSRDL0,"
rgroup.long 0x1B0++0x17
line.long 0x00 "MEM_FSRDL1,"
line.long 0x04 "MEM_MARGIN_MODE,"
bitfld.long 0x04 2.--3. "PBIST_DFT_READ,pbist_dft_read[1:0]" "0,1,2,3"
bitfld.long 0x04 0.--1. "PBIST_DFT_WRITE,pbist_dft_write[1:0]" "0,1,2,3"
line.long 0x08 "MEM_WRENZ,"
bitfld.long 0x08 0.--1. "WRENZ,pbist_ram_wrenz[1:0]" "0,1,2,3"
line.long 0x0C "MEM_PAGE_PGS,"
bitfld.long 0x0C 0.--1. "PGS,pbist_ram_pgs[1:0]" "0,1,2,3"
line.long 0x10 "MEM_ROM,"
bitfld.long 0x10 0.--1. "ROM,ROM Mask (ROM)" "0,1,2,3"
line.long 0x14 "MEM_ALGO,"
hexmask.long.byte 0x14 24.--31. 1. "ALGO_3,ROM Algorithm Mask 3 (ALGO 3)"
hexmask.long.byte 0x14 16.--23. 1. "ALGO_2,ROM Algorithm Mask 2 (ALGO 2)"
hexmask.long.byte 0x14 8.--15. 1. "ALGO_1,ROM Algorithm Mask 1 (ALGO 1)"
hexmask.long.byte 0x14 0.--7. 1. "ALGO_0,ROM Algorithm Mask 0 (ALGO 0)"
group.quad 0x1C8++0x07
line.quad 0x00 "MEM_RINFO,"
hexmask.quad.byte 0x00 56.--63. 1. "U3,RAM Info Mask Upper 3 (RINFOU3)"
hexmask.quad.byte 0x00 48.--55. 1. "U2,RAM Info Mask Upper 2 (RINFOU2)"
hexmask.quad.byte 0x00 40.--47. 1. "U1,RAM Info Mask Upper 1 (RINFOU1)"
hexmask.quad.byte 0x00 32.--39. 1. "U0,RAM Info Mask Upper 0 (RINFOU0)"
hexmask.quad.byte 0x00 24.--31. 1. "L3,RAM Info Mask Lower 3 (RINFOL3)"
hexmask.quad.byte 0x00 16.--23. 1. "L2,RAM Info Mask Lower 2 (RINFOL2)"
newline
hexmask.quad.byte 0x00 8.--15. 1. "L1,RAM Info Mask Lower 1 (RINFOL1)"
hexmask.quad.byte 0x00 0.--7. 1. "L0,RAM Info Mask Lower 0 (RINFOL0)"
tree.end
tree "WKUP_RTI0_CFG"
base ad:0x2B000000
group.long 0x00++0x1B
line.long 0x00 "CFG_GCTRL,"
bitfld.long 0x00 16.--19. "NTUSEL,These bits determine which NTU input signal is used as external timebase" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
bitfld.long 0x00 15. "COS,This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting" "stop counters in debug mode,continue counting in debug mode"
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bitfld.long 0x00 1. "CNT1EN,The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1)" "stop counters,start counters"
bitfld.long 0x00 0. "CNT0EN,The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters"
line.long 0x04 "CFG_TBCTRL,"
bitfld.long 0x04 1. "INC,This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
bitfld.long 0x04 0. "TBEXT,The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "CFG_CAPCTRL,"
bitfld.long 0x08 1. "CAPCNTR1,This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
bitfld.long 0x08 0. "CAPCNTR0,This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "CFG_COMPCTRL,"
bitfld.long 0x0C 12. "COMPSEL3,This bit determines the counter with which the compare value hold in compare register 3 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 8. "COMPSEL2,This bit determines the counter with which the compare value hold in compare register 2 is compared" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 4. "COMPSEL1,This bit determines the counter with which the compare value hold in compare register 1 is compared" "enable compare with FRC 0,enable compare with FRC 1"
bitfld.long 0x0C 0. "COMPSEL0,This bit determines the counter with which the compare value hold in compare register 0 is compared" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "CFG_FRC0,"
line.long 0x14 "CFG_UC0,"
line.long 0x18 "CFG_CPUC0,"
rgroup.long 0x20++0x07
line.long 0x00 "CFG_CAFRC0,"
line.long 0x04 "CFG_CAUC0,"
group.long 0x30++0x0B
line.long 0x00 "CFG_FRC1,"
line.long 0x04 "CFG_UC1,"
line.long 0x08 "CFG_CPUC1,"
rgroup.long 0x40++0x07
line.long 0x00 "CFG_CAFRC1,"
line.long 0x04 "CFG_CAUC1,"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x08 0x10 0x18 )
group.long ($2+0x50)++0x03
line.long 0x00 "CFG_COMP$1,"
repeat.end
group.long 0x54++0x03
line.long 0x00 "CFG_UDCP0,"
group.long 0x5C++0x03
line.long 0x00 "CFG_UDCP1,"
group.long 0x64++0x03
line.long 0x00 "CFG_UDCP2,"
group.long 0x6C++0x0B
line.long 0x00 "CFG_UDCP3,"
line.long 0x04 "CFG_TBLCOMP,"
line.long 0x08 "CFG_TBHCOMP,"
group.long 0x80++0x0B
line.long 0x00 "CFG_SETINT,"
bitfld.long 0x00 18. "SETOVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 17. "SETOVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 16. "SETTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 11. "SETDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 3. "SETINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 2. "SETINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 1. "SETINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 0. "SETINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "CFG_CLEARINT,"
bitfld.long 0x04 18. "CLEAROVL1INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 17. "CLEAROVL0INT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 16. "CLEARTBINT,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 11. "CLEARDMA3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 3. "CLEARINT3,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 2. "CLEARINT2,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 1. "CLEARINT1,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 0. "CLEARINT0,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "CFG_INTFLAG,"
bitfld.long 0x08 18. "OVL1INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 17. "OVL0INT,User and privilege mode (read): determines if an interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 3. "INT3,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,User and privilege mode (read): determines if a interrupt is pending" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "CFG_DWDCTRL,"
line.long 0x04 "CFG_DWDPRLD,"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value"
line.long 0x08 "CFG_WDSTATUS,"
bitfld.long 0x08 5. "DWWD,This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 4. "END,This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 3. "START,This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 2. "KEYST,This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 1. "DWDST,status flag and is maintained for compatibility reasons" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 0. "AWDST,User and priviledge mode (read)" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "CFG_WDKEY,"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,User and privilege mode reads are indeterminate"
line.long 0x10 "CFG_DWDCNTR,"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,The value of the DWDCNTR after a system reset is 0x002D_FFFF"
line.long 0x14 "CFG_WWDRXNCTRL,"
bitfld.long 0x14 0.--3. "WWDRXN,User and privilege mode (read) privileged mode (write)" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "CFG_WWDSIZECTRL,"
line.long 0x1C "CFG_INTCLRENABLE,"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,Enables the auto-clear functionality on the compare 3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,Enables the auto-clear functionality on the compare 2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,Enables the auto-clear functionality on the compare 1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,Enables the auto-clear functionality on the compare 0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "CFG_COMP0CLR,"
line.long 0x24 "CFG_COMP1CLR,"
line.long 0x28 "CFG_COMP2CLR,"
line.long 0x2C "CFG_COMP3CLR,"
tree.end
tree "WKUP_TIMER0_CFG"
base ad:0x2B100000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
newline
bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
newline
bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
newline
bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "WKUP_TIMER1_CFG"
base ad:0x2B110000
rgroup.long 0x00++0x03
line.long 0x00 "CFG_TIDR,"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "CFG_TIOCP_CFG,This register controls the various parameters of the OCP interface"
bitfld.long 0x00 2.--3. "IDLEMODE,Idle Mode" "0,1,2,3"
bitfld.long 0x00 1. "EMUFREE,Emulation Mode" "0,1"
bitfld.long 0x00 0. "SOFTRESET,Software reset" "0,1"
group.long 0x20++0x4F
line.long 0x00 "CFG_IRQ_EOI,Allows the generation of further pulses on the interrupt line. if an new interrupt event is pending. when using the pulsed output"
bitfld.long 0x00 0. "LINE_NUMBER,Idle Mode" "0,1"
line.long 0x04 "CFG_IRQSTATUS_RAW,Component interrupt request status.Check the corresponding secondary status register"
bitfld.long 0x04 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x04 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x04 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x08 "CFG_IRQSTATUS,Component interrupt request status.Check the corresponding secondary status register.Enabled status isn't set unless event is enabled.Write 1 to clear the status after interrupt has been serviced;raw status gets cleared. i.e"
bitfld.long 0x08 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x08 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x08 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x0C "CFG_IRQSTATUS_SET,Component interrupt request enableWrite 1 to set;enable interrupt"
bitfld.long 0x0C 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x0C 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x0C 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x10 "CFG_IRQSTATUS_CLR,Component interrupt request enable.Write 1 to clear; disable interrupt.Readout equal to corresponding _SET register"
bitfld.long 0x10 2. "TCAR_IT_FLAG,Capture Interrupt" "0,1"
bitfld.long 0x10 1. "OVF_IT_FLAG,Overflow Interrupt" "0,1"
bitfld.long 0x10 0. "MAT_IT_FLAG,Match Interrupt" "0,1"
line.long 0x14 "CFG_IRQWAKEEN,Wakeup-enabled events taking place when module is idle shall generate an asynchronous wakeup"
bitfld.long 0x14 2. "MAT_WUP_ENA,Match Wakeup Enable" "0,1"
bitfld.long 0x14 1. "OVF_WUP_ENA,Overflow Wakeup Enable" "0,1"
bitfld.long 0x14 0. "TCAR_WUP_ENA,Capture Wakeup Enable" "0,1"
line.long 0x18 "CFG_TCLR,This register controls optional features specific to the timer functionality"
bitfld.long 0x18 14. "GPO_CFG,This field drives directly the timer_gpocfg port" "0,1"
bitfld.long 0x18 13. "CAPT_MODE,Capture mode select bit; First/second" "0,1"
bitfld.long 0x18 12. "PT,Pulse or Toggle select bit" "0,1"
bitfld.long 0x18 10.--11. "TRG,Trigger Output Mode" "0,1,2,3"
bitfld.long 0x18 8.--9. "TCM,Transition Capture Mode" "0,1,2,3"
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bitfld.long 0x18 7. "SCPWM,Pulse Width Modulation output pin default value" "0,1"
bitfld.long 0x18 6. "CE,Compare Enable" "0,1"
bitfld.long 0x18 5. "PRE,Prescaler Enable" "0,1"
bitfld.long 0x18 2.--4. "PTV,Trigger Output Mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 1. "AR,Auto-reload mode" "0,1"
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bitfld.long 0x18 0. "ST,Start/Stop timer control" "0,1"
line.long 0x1C "CFG_TCRR,This register holds the value of the internal counter"
line.long 0x20 "CFG_TLDR,This register holds the timer's load value"
line.long 0x24 "CFG_TTGR,This register triggers a counter reload of timer by writing any value in it"
line.long 0x28 "CFG_TWPS,This register contains the write posting bits for all writ-able functional registers"
bitfld.long 0x28 9. "W_PEND_TOWR,Write pending for register TOWR" "0,1"
bitfld.long 0x28 8. "W_PEND_TOCR,Write pending for register TOCR" "0,1"
bitfld.long 0x28 7. "W_PEND_TCVR,Write pending for register TCVR" "0,1"
bitfld.long 0x28 6. "W_PEND_TNIR,Write pending for register TNIR" "0,1"
bitfld.long 0x28 5. "W_PEND_TPIR,Write pending for register TPIR" "0,1"
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bitfld.long 0x28 4. "W_PEND_TMAR,Write pending for register TMAR" "0,1"
bitfld.long 0x28 3. "W_PEND_TTGR,Write pending for register TTGR" "0,1"
bitfld.long 0x28 2. "W_PEND_TLDR,Write pending for register TLDR" "0,1"
bitfld.long 0x28 1. "W_PEND_TCRR,Write pending for register TCRR" "0,1"
bitfld.long 0x28 0. "W_PEND_TCLR,Write pending for register TCLR" "0,1"
line.long 0x2C "CFG_TMAR,This register holds the match value to be compared with the counter's value"
line.long 0x30 "CFG_TCAR1,This register holds the value of the first counter register capture"
line.long 0x34 "CFG_TSICR,Timer Synchronous Interface Control Register"
bitfld.long 0x34 4. "READ_AFTER_IDLE,Select if the synchronization mechanism used for first TCRR read operation after IDLE state is active" "0,1"
bitfld.long 0x34 3. "READ_MODE,Select posted/non-posted mode for read operation" "0,1"
bitfld.long 0x34 2. "POSTED,Reset value of POSTED depends on hardware integration module at design time" "0,1"
bitfld.long 0x34 1. "SFT,This bit reset all the functional part of teh module" "0,1"
line.long 0x38 "CFG_TCAR2,This register holds the value of the second counter register capture"
line.long 0x3C "CFG_TPIR,This register is used for 1ms tick generation.The TPIR register holds the value of the positive increment"
line.long 0x40 "CFG_TNIR,This register is used for 1ms tick generation"
line.long 0x44 "CFG_TCVR,This register is used for 1ms tick generation.The TCVR register defines whether next value loaded in TCRR will be the sub-period value or the over-period value"
line.long 0x48 "CFG_TOCR,This register is used to mask the tick interrupt for a selected number of ticks"
hexmask.long.tbyte 0x48 0.--23. 1. "OVF_COUNTER_VALUE,The number of overflow events"
line.long 0x4C "CFG_TOWR,This register holds the number of masked overflow interrupts"
hexmask.long.tbyte 0x4C 0.--23. 1. "OVF_WRAPPING_VALUE,The number of masked interrupts"
tree.end
tree "WKUP_UART0"
base ad:0x2B300000
group.long 0x00++0x03
line.long 0x00 "MEM_DLL,Divisor Latches Low Register"
hexmask.long.byte 0x00 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value"
rgroup.long 0x00++0x03
line.long 0x00 "MEM_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
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hexmask.long.byte 0x00 0.--7. 1. "RHR,Receive holding register"
group.long 0x00++0x07
line.long 0x00 "MEM_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
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hexmask.long.byte 0x00 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER"
line.long 0x04 "MEM_DLH,Divisor Latches High Register"
hexmask.long.byte 0x04 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value"
group.long 0x04++0x03
line.long 0x00 "MEM_IER_CIR,The interrupt enable register (IER) can be programmed to enable/disable any interrupt"
bitfld.long 0x00 6.--7. "NOT_USED2," "0,1,2,3"
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bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
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bitfld.long 0x00 4. "NOT_USED1," "0,1"
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bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
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bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
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bitfld.long 0x00 1. "THR_IT," "0,1"
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bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x03
line.long 0x00 "MEM_IER_IRDA,The interrupt enable register (IER) can be programmed to enable/disable any interrupt"
bitfld.long 0x00 7. "EOF_IT," "0,1"
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bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
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bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
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bitfld.long 0x00 4. "STS_FIFO_TRIG_IT," "0,1"
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bitfld.long 0x00 3. "RX_OVERRUN_IT," "0,1"
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bitfld.long 0x00 2. "LAST_RX_BYTE_IT," "0,1"
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bitfld.long 0x00 1. "THR_IT," "0,1"
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bitfld.long 0x00 0. "RHR_IT," "0,1"
group.long 0x04++0x07
line.long 0x00 "MEM_IER_UART,The interrupt enable register (IER) can be programmed to enable/disable any interrupt"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
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bitfld.long 0x00 7. "CTS_IT," "0,1"
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bitfld.long 0x00 6. "RTS_IT," "0,1"
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bitfld.long 0x00 5. "XOFF_IT," "0,1"
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bitfld.long 0x00 4. "SLEEP_MODE," "0,1"
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bitfld.long 0x00 3. "MODEM_STS_IT," "0,1"
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bitfld.long 0x00 2. "LINE_STS_IT," "0,1"
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bitfld.long 0x00 1. "THR_IT," "0,1"
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bitfld.long 0x00 0. "RHR_IT," "0,1"
line.long 0x04 "MEM_EFR,Enhanced Feature Register"
bitfld.long 0x04 7. "AUTO_CTS_EN,Auto-CTS enable bit" "Normal operation,Auto-CTS flow control is enabled i.e"
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bitfld.long 0x04 6. "AUTO_RTS_EN,Auto-RTS enable bit" "Normal operation,Auto- RTS flow control is enabled i.e"
newline
bitfld.long 0x04 5. "SPECIAL_CHAR_DETECT," "0,1"
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bitfld.long 0x04 4. "ENHANCED_EN,Enhanced functions write enable bit" "Disables writing to IER bits 4-7 FCR bits 4-5..,Enables writing to IER bits 4-7 FCR bits 4-5 and.."
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bitfld.long 0x04 0.--3. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "MEM_FCR,Notes: Bits 4 and 5 can only be written to when EFR[4] = 1 Bits 0 to 3 can be changed only when the baud clock is not running (DLL and DLH set to 0) See Table 31 for FCR[5:4] setting restriction when SCR[6]=1 See Table 32 for FCR[7:6] setting.."
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
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bitfld.long 0x00 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO: If SCR[7] = 0 and TLR[7:4] =" "8 characters,16 characters,56 characters,60 characters If SCR[7] = 0 and.."
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bitfld.long 0x00 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO: If SCR[6] = 0 and TLR[3:0] =" "8 spaces,16 spaces,32 spaces,56 spaces If SCR[6] = 0.."
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bitfld.long 0x00 3. "DMA_MODE,This register is considered if SCR[0] = 0" "0,1"
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bitfld.long 0x00 2. "TX_FIFO_CLEAR," "0,1"
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bitfld.long 0x00 1. "RX_FIFO_CLEAR," "0,1"
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bitfld.long 0x00 0. "FIFO_EN," "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "MEM_IIR_CIR,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner"
bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
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bitfld.long 0x00 3. "RX_OE_IT," "0,1"
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bitfld.long 0x00 2. "RX_STOP_IT," "0,1"
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bitfld.long 0x00 1. "THR_IT," "0,1"
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bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "MEM_IIR_IRDA,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner"
bitfld.long 0x00 7. "EOF_IT," "0,1"
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bitfld.long 0x00 6. "LINE_STS_IT," "0,1"
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bitfld.long 0x00 5. "TX_STATUS_IT," "0,1"
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bitfld.long 0x00 4. "STS_FIFO_IT," "0,1"
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bitfld.long 0x00 3. "RX_OE_IT," "0,1"
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bitfld.long 0x00 2. "RX_FIFO_LAST_BYTE_IT," "0,1"
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bitfld.long 0x00 1. "THR_IT," "0,1"
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bitfld.long 0x00 0. "RHR_IT," "0,1"
rgroup.long 0x08++0x0B
line.long 0x00 "MEM_IIR_UART,The IIR is a read-only register. which provides the source of the interrupt in a prioritized manner"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
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bitfld.long 0x00 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
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bitfld.long 0x00 1.--5. "IT_TYPE," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "IT_PENDING," "0,1"
line.long 0x04 "MEM_LCR,LCR[6:0] define parameters of the transmission and reception.Note: As soon as LCR[6] is set to 1. the TX line is forced to 0 and remains in this state as long as LCR[6] = 1"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
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bitfld.long 0x04 7. "DIV_EN," "0,1"
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bitfld.long 0x04 6. "BREAK_EN,Break control bit" "0,1"
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bitfld.long 0x04 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]" "0,1"
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bitfld.long 0x04 4. "PARITY_TYPE1," "0,1"
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bitfld.long 0x04 3. "PARITY_EN," "0,1"
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bitfld.long 0x04 2. "NB_STOP,Specifies the number of stop bits" "0,1"
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bitfld.long 0x04 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received" "0,1,2,3"
line.long 0x08 "MEM_MCR,MCR[3:0] controls the interface with the modem. data set or peripheral device that is emulating the modem"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
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rbitfld.long 0x08 7. "RESERVED," "0,1"
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bitfld.long 0x08 6. "TCR_TLR," "0,1"
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bitfld.long 0x08 5. "XON_EN," "0,1"
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bitfld.long 0x08 4. "LOOPBACK_EN," "0,1"
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bitfld.long 0x08 3. "CD_STS_CH," "0,1"
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bitfld.long 0x08 2. "RI_STS_CH," "0,1"
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bitfld.long 0x08 1. "RTS,In loop back controls MSR[4]" "0,1"
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bitfld.long 0x08 0. "DTR," "0,1"
group.long 0x10++0x07
line.long 0x00 "MEM_XON1_ADDR1,XON1/ADDR1 Register"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes"
line.long 0x04 "MEM_LSR_CIR,"
bitfld.long 0x04 7. "THR_EMPTY," "0,1"
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bitfld.long 0x04 6. "RESERVED," "0,1"
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bitfld.long 0x04 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR)" "0,1"
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bitfld.long 0x04 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "MEM_LSR_IRDA,"
bitfld.long 0x00 7. "THR_EMPTY," "0,1"
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bitfld.long 0x00 6. "STS_FIFO_FULL," "0,1"
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bitfld.long 0x00 5. "RX_LAST_BYTE," "0,1"
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bitfld.long 0x00 4. "FRAME_TOO_LONG," "0,1"
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bitfld.long 0x00 3. "ABORT," "0,1"
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bitfld.long 0x00 2. "CRC," "0,1"
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bitfld.long 0x00 1. "STS_FIFO_E," "0,1"
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bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "MEM_LSR_UART,"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 7. "RX_FIFO_STS," "0,1"
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bitfld.long 0x00 6. "TX_SR_E," "0,1"
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bitfld.long 0x00 5. "TX_FIFO_E," "0,1"
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bitfld.long 0x00 4. "RX_BI," "0,1"
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bitfld.long 0x00 3. "RX_FE," "0,1"
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bitfld.long 0x00 2. "RX_PE," "0,1"
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bitfld.long 0x00 1. "RX_OE," "0,1"
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bitfld.long 0x00 0. "RX_FIFO_E," "0,1"
group.long 0x14++0x07
line.long 0x00 "MEM_XON2_ADDR2,XON2/ADDR2 Register"
hexmask.long.byte 0x00 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes"
line.long 0x04 "MEM_MSR,This register provides information about the current state of the control lines from the modem. data set or peripheral device to the LH"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "NCD_STS,This bit is the complement of the DCD* input" "0,1"
newline
bitfld.long 0x04 6. "NRI_STS,This bit is the complement of the RI* input" "0,1"
newline
bitfld.long 0x04 5. "NDSR_STS,This bit is the complement of the DSR* input" "0,1"
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bitfld.long 0x04 4. "NCTS_STS,This bit is the complement of the CTS* input" "0,1"
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bitfld.long 0x04 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed" "0,1"
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bitfld.long 0x04 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high" "0,1"
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bitfld.long 0x04 1. "DSR_STS," "0,1"
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bitfld.long 0x04 0. "CTS_STS," "0,1"
group.long 0x18++0x03
line.long 0x00 "MEM_TCR,Transmission Control Register"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x07
line.long 0x00 "MEM_XOFF1,XOFF1 Register"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes"
line.long 0x04 "MEM_SPR,This read/write register does not control the module in anyway"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x04 0.--7. 1. "SPR_WORD,Scratchpad register"
group.long 0x1C++0x03
line.long 0x00 "MEM_TLR,Trigger Level Register"
bitfld.long 0x00 4.--7. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x0F
line.long 0x00 "MEM_XOFF2,XOFF2 Register"
hexmask.long.byte 0x00 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes"
line.long 0x04 "MEM_MDR1,The mode of operation can be programmed by writing to MDR1[2:0] and therefore the MDR1 must be programmed on start-up after configuration of the configuration registers (DLL. DLH. LCR)"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "FRAME_END_MODE,IrDA mode only" "0,1"
newline
bitfld.long 0x04 6. "SIP_MODE,MIR/FIR modes only" "0,1"
newline
bitfld.long 0x04 5. "SCT,Store and control the transmission" "0,1"
newline
bitfld.long 0x04 4. "SET_TXIR,Used to configure the infrared transceiver" "0,1"
newline
bitfld.long 0x04 3. "IR_SLEEP," "0,1"
newline
bitfld.long 0x04 0.--2. "MODE_SELECT," "0,1,2,3,4,5,6,7"
line.long 0x08 "MEM_MDR2,IR-IrDA and IR-CIR modes only.MDR2[0] describes the status of the interrupt in IIR[5]"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x08 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR]" "0,1"
newline
bitfld.long 0x08 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block" "0,1"
newline
bitfld.long 0x08 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition" "0,1,2,3"
newline
bitfld.long 0x08 3. "UART_PULSE,UART mode only" "0,1"
newline
bitfld.long 0x08 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode" "0,1,2,3"
newline
rbitfld.long 0x08 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is" "0,1"
line.long 0x0C "MEM_SFLSR,IrDA modes only.Reading this register effectively reads frame status information from the status FIFO (this register doesn't physically exist)"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0C 5.--7. "RESERVED5," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 4. "OE_ERROR," "0,1"
newline
bitfld.long 0x0C 3. "FRAME_TOO_LONG_ERROR," "0,1"
newline
bitfld.long 0x0C 2. "ABORT_DETECT," "0,1"
newline
bitfld.long 0x0C 1. "CRC_ERROR," "0,1"
newline
bitfld.long 0x0C 0. "RESERVED0," "0,1"
group.long 0x28++0x07
line.long 0x00 "MEM_TXFLL,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes)"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "TXFLL,LSB register used to specify the frame length"
line.long 0x04 "MEM_RESUME,IR-IrDA and IR-CIR modes only.This register is used to clear internal flags. which halt transmission/reception when an underrun/overrun error occurs"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x04 0.--7. 1. "RESUME,Dummy read to restart the TX or RX"
group.long 0x2C++0x07
line.long 0x00 "MEM_TXFLH,IrDA modes only.The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes)"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x00 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--4. "TXFLH,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "MEM_RXFLL,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x04 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception"
rgroup.long 0x30++0x07
line.long 0x00 "MEM_SFREGL,IrDA modes only.The frame lengths of received frames are written into the status FIFO"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x00 0.--7. 1. "SFREGL,LSB part of the frame length"
line.long 0x04 "MEM_RXFLH,IrDA modes only.The registers RXFLL and RXFLH hold the 12-bit receive maximum frame length"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x04 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--3. "RXFLH,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x34++0x07
line.long 0x00 "MEM_SFREGH,IrDA modes only.The frame lengths of received frames are written into the status FIFO"
hexmask.long.tbyte 0x00 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x00 4.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "SFREGH,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MEM_BLR,IrDA modes only.Note that BLR[6] is used to select whether 0xC0 or 0xFF start patterns are to be used. when multiple start flags are required in SIR Mode"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "STS_FIFO_RESET,Status FIFO reset" "0,1"
newline
bitfld.long 0x04 6. "XBOF_TYPE,SIR xBOF select" "0,1"
newline
rbitfld.long 0x04 0.--5. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x38++0x13
line.long 0x00 "MEM_UASR,UART Autobauding Status Register"
bitfld.long 0x00 6.--7. "PARITY_TYPE," "?,Parity space,Even Parity,Odd Parity"
newline
bitfld.long 0x00 5. "BIT_BY_CHAR," "0,1"
newline
bitfld.long 0x00 0.--4. "SPEED,Used to report the speed identified" "No speed identified,115200 bauds,57600 bauds,38400 bauds,28800 bauds,19200 bauds,14400 bauds,9600 bauds,4800 bauds,2400 bauds,1200 bauds,?..."
line.long 0x04 "MEM_ACREG,IR-IrDA and IR-CIR modes only"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x04 7. "PULSE_TYPE,SIR pulse width select" "0,1"
newline
bitfld.long 0x04 6. "SD_MOD,Primary output used to configure transceivers" "0,1"
newline
bitfld.long 0x04 5. "DIS_IR_RX," "0,1"
newline
bitfld.long 0x04 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt" "0,1"
newline
bitfld.long 0x04 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP] If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission" "0,1"
newline
bitfld.long 0x04 2. "SCTX_EN,Store and controlled TX start" "0,1"
newline
bitfld.long 0x04 1. "ABORT_EN,Frame Abort" "0,1"
newline
bitfld.long 0x04 0. "EOT_EN,EOT [end of transmission] bit" "0,1"
line.long 0x08 "MEM_SCR,Note: Bit 4 enables the wake-up interrupt. but this interrupt is not mapped into the IIR register"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x08 7. "RX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x08 6. "TX_TRIG_GRANU1," "0,1"
newline
bitfld.long 0x08 5. "DSR_IT," "0,1"
newline
bitfld.long 0x08 4. "RX_CTS_DSR_WAKE_UP_ENABLE," "0,1"
newline
bitfld.long 0x08 3. "TX_EMPTY_CTL_IT," "0,1"
newline
bitfld.long 0x08 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1" "0,1,2,3"
newline
bitfld.long 0x08 0. "DMA_MODE_CTL," "0,1"
line.long 0x0C "MEM_SSR,Note: Bit 1 is reset only when SCR[4] is reset to 0"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x0C 3.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 2. "DMA_COUNTER_RST," "0,1"
newline
rbitfld.long 0x0C 1. "RX_CTS_DSR_WAKE_UP_STS," "0,1"
newline
rbitfld.long 0x0C 0. "TX_FIFO_FULL," "0,1"
line.long 0x10 "MEM_EBLR,IR-IrDA and IR-CIR modes only.In IR-IrDA SIR operation. this register specifies the number of BOF + xBOFs to transmit"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,"
newline
abitfld.long 0x10 0.--7. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification" "0x00=feature disabled,0x01=generate RX_STOP interrupt after receiving..,0xFF=generate RX_STOP interrupt after receiving.."
rgroup.long 0x50++0x57
line.long 0x00 "MEM_MVR,The reset value is fixed by hardware and corresponds to the RTL revision of this module"
bitfld.long 0x00 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "RESERVED," "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function revision number of module"
newline
bitfld.long 0x00 11.--15. "RTL,Rtl revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major revision number of the module" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision number of the module" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor revision number of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MEM_SYSC,The auto idle bit controls a power saving technique to reduce the logic power consumption of the OCP interface"
hexmask.long.tbyte 0x04 8.--31. 1. "RESERVED,"
newline
rbitfld.long 0x04 5.--7. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROL REF: OCP DESIGN GUIDELINES VERSION 1.1" "0,1,2,3"
newline
bitfld.long 0x04 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL" "0,1"
newline
bitfld.long 0x04 1. "SOFTRESET,Software reset" "0,1"
newline
bitfld.long 0x04 0. "AUTOIDLE,Internal OCP clock gating strategy" "0,1"
line.long 0x08 "MEM_SYSS,"
hexmask.long.tbyte 0x08 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x08 1.--7. 1. "RESERVED,"
newline
bitfld.long 0x08 0. "RESETDONE,Internal Reset Monitoring" "0,1"
line.long 0x0C "MEM_WER,The UART wakeup enable register is used to mask and unmask a UART event that would subsequently notify the system"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED,"
newline
bitfld.long 0x0C 7. "EVENT_7_TX_WAKEUP_EN," "0,1"
newline
bitfld.long 0x0C 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT," "0,1"
newline
bitfld.long 0x0C 5. "EVENT_5_RHR_INTERRUPT," "0,1"
newline
bitfld.long 0x0C 4. "EVENT_4_RX_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 3. "EVENT_3_DCD_CD_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 2. "EVENT_2_RI_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 1. "EVENT_1_DSR_ACTIVITY," "0,1"
newline
bitfld.long 0x0C 0. "EVENT_0_CTS_ACTIVITY," "0,1"
line.long 0x10 "MEM_CFPS,Since the Consumer IR works at modulation rates of 30 56.8 KHz. the 48 MHz clock must be pre scaled before the clock can drive the IR logic"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x10 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]"
line.long 0x14 "MEM_RXFIFO_LVL,Level of the RX FIFO"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x14 0.--7. 1. "RXFIFO_LVL,"
line.long 0x18 "MEM_TXFIFO_LVL,Level of the TX FIFO"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED24,"
newline
hexmask.long.byte 0x18 0.--7. 1. "TXFIFO_LVL,"
line.long 0x1C "MEM_IER2,Enables RX/TX FIFOs empty corresponding interrupts"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x1C 3.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 2. "RHR_IT_DIS," "0,1"
newline
bitfld.long 0x1C 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt" "0,1"
newline
bitfld.long 0x1C 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt" "0,1"
line.long 0x20 "MEM_ISR2,Status of RX/TX FIFOs empty corresponding interrupts"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x20 2.--7. "RESERVED," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x20 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending" "0,1"
newline
bitfld.long 0x20 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending" "0,1"
line.long 0x24 "MEM_FREQ_SEL,Sample per bit value selector"
hexmask.long.byte 0x24 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used"
line.long 0x28 "MEM_ABAUD_1ST_CHAR,Unused"
line.long 0x2C "MEM_BAUD_2ND_CHAR,Unused"
line.long 0x30 "MEM_MDR3,Mode definition register 3"
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED2,"
newline
bitfld.long 0x30 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1"
newline
bitfld.long 0x30 3. "DIR_POL,RS-485 External Transceiver Direction Polarity" "TX,TX"
newline
bitfld.long 0x30 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1"
newline
bitfld.long 0x30 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1"
newline
bitfld.long 0x30 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation" "0,1"
line.long 0x34 "MEM_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level.MDR3[2] SET_TX_DMA_THRESHOLD must be one and must be value + tx_trigger_level <= 64 (TX FIFO size).If not. 64-tx_trigger_level will be used w/o modifying the value of this register"
bitfld.long 0x34 0.--5. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "MEM_MDR4,Mode definition register 4"
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x38 7. "RESERVED," "0,1"
newline
bitfld.long 0x38 6. "MODE9,9-bit character length" "0,1"
newline
bitfld.long 0x38 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 0.--2. "MODE,New modes [when set overrides MDR1 modes]" "0,1,2,3,4,5,6,7"
line.long 0x3C "MEM_EFR2,Enhanced Features Register 2"
hexmask.long.tbyte 0x3C 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0x3C 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1"
newline
bitfld.long 0x3C 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured" "0,1"
newline
bitfld.long 0x3C 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1"
newline
bitfld.long 0x3C 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1"
newline
bitfld.long 0x3C 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1"
newline
bitfld.long 0x3C 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1"
newline
bitfld.long 0x3C 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full" "0,1"
newline
bitfld.long 0x3C 0. "ENDIAN,Endianness" "0,1"
line.long 0x40 "MEM_ECR,Enhanced Control register"
hexmask.long.tbyte 0x40 8.--31. 1. "RESERVED1,"
newline
rbitfld.long 0x40 6.--7. "RESERVED," "0,1,2,3"
newline
bitfld.long 0x40 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1"
newline
bitfld.long 0x40 4. "TX_EN,Enables/Disables the transmitter" "0,1"
newline
bitfld.long 0x40 3. "RX_EN,Enables/Disables the receiver" "0,1"
newline
bitfld.long 0x40 2. "TX_RST,Writing '1' resets the transmitter" "0,1"
newline
bitfld.long 0x40 1. "RX_RST,Writing '1' resets the receiver" "0,1"
newline
bitfld.long 0x40 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1"
line.long 0x44 "MEM_TIMEGUARD,Timeguard"
hexmask.long.tbyte 0x44 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x44 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices"
line.long 0x48 "MEM_TIMEOUTL,Timeout lower byte"
hexmask.long.tbyte 0x48 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x48 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0"
line.long 0x4C "MEM_TIMEOUTH,Timeout higher byte"
hexmask.long.tbyte 0x4C 8.--31. 1. "RESERVED,"
newline
hexmask.long.byte 0x4C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0"
line.long 0x50 "MEM_SCCR,Smartcard (ISO7816) mode Control Register"
hexmask.long.tbyte 0x50 8.--31. 1. "RESERVED1,"
newline
bitfld.long 0x50 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error" "0,1"
newline
bitfld.long 0x50 6. "INACK,Inhibit NACK when receiving even if an error is received" "0,1"
newline
rbitfld.long 0x50 3.--5. "RESERVED," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x50 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge" "0,1,2,3,4,5,6,7"
line.long 0x54 "MEM_ERHR,Extended Receive Holding Register"
hexmask.long.tbyte 0x54 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x54 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR"
group.long 0xA4++0x0F
line.long 0x00 "MEM_ETHR,Extended Transmit Holding Register"
hexmask.long.tbyte 0x00 9.--31. 1. "RESERVED,"
newline
hexmask.long.word 0x00 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR"
line.long 0x04 "MEM_MAR,Multidrop Address Register"
hexmask.long.byte 0x04 0.--7. 1. "ADDRESS,Multidrop match address value"
line.long 0x08 "MEM_MMR,Multidrop Mask Register"
hexmask.long.byte 0x08 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching"
line.long 0x0C "MEM_MBR,Multidrop Broadcast Address Register"
hexmask.long.byte 0x0C 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching"
tree.end
endif
sif (cpuis("AM62*X-ICSS0"))
tree "ICSSM0_IEP0"
base ad:0x2E000
group.long 0x00++0x1F
line.long 0x00 "PR1_IEP0__SLV__REGS_global_cfg_reg,"
hexmask.long.word 0x00 8.--19. 1. "CMP_INC,"
bitfld.long 0x00 4.--7. "DEFAULT_INC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "CNT_ENABLE," "0,1"
line.long 0x04 "PR1_IEP0__SLV__REGS_global_status_reg,"
bitfld.long 0x04 0. "CNT_OVF," "0,1"
line.long 0x08 "PR1_IEP0__SLV__REGS_compen_reg,"
hexmask.long.tbyte 0x08 0.--22. 1. "COMPEN_CNT,"
line.long 0x0C "PR1_IEP0__SLV__REGS_slow_compen_reg,"
line.long 0x10 "PR1_IEP0__SLV__REGS_count_reg0,"
line.long 0x14 "PR1_IEP0__SLV__REGS_count_reg1,"
line.long 0x18 "PR1_IEP0__SLV__REGS_cap_cfg_reg,"
bitfld.long 0x18 18.--23. "EXT_CAP_EN," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x18 10.--17. 1. "CAP_ASYNC_EN,"
hexmask.long.word 0x18 0.--9. 1. "CAP_EN,"
line.long 0x1C "PR1_IEP0__SLV__REGS_cap_status_reg,"
hexmask.long.byte 0x1C 16.--23. 1. "CAP_RAW,"
hexmask.long.word 0x1C 0.--10. 1. "CAP_VALID,"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x20)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr0_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x28)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr1_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x30)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr2_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x38)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr3_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x40)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr4_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x48)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr5_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x50)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr6_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x58)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capf6_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x60)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr7_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x68)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capf7_reg$1,"
repeat.end
group.long 0x70++0x07
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp_cfg_reg,"
bitfld.long 0x00 17. "SHADOW_EN," "0,1"
hexmask.long.word 0x00 1.--16. 1. "CMP_EN,"
bitfld.long 0x00 0. "CMP0_RST_CNT_EN," "0,1"
line.long 0x04 "PR1_IEP0__SLV__REGS_cmp_status_reg,"
hexmask.long.word 0x04 0.--15. 1. "CMP_STATUS,"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x78)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp0_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x80)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp1_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x88)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp2_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x90)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp3_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x98)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp4_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xA0)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp5_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xA8)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp6_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xB0)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp7_reg$1,"
repeat.end
group.long 0xB8++0x07
line.long 0x00 "PR1_IEP0__SLV__REGS_rxipg0_reg,"
hexmask.long.word 0x00 16.--31. 1. "RX_MIN_IPG0,"
hexmask.long.word 0x00 0.--15. 1. "RX_IPG0,"
line.long 0x04 "PR1_IEP0__SLV__REGS_rxipg1_reg,"
hexmask.long.word 0x04 16.--31. 1. "RX_MIN_IPG1,"
hexmask.long.word 0x04 0.--15. 1. "RX_IPG1,"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xC0)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp8_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xC8)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp9_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xD0)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp10_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xD8)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp11_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xE0)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp12_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xE8)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp13_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xF0)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp14_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xF8)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_cmp15_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x100)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_count_reset_val_reg$1,"
repeat.end
group.long 0x108++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_pwm_reg,"
bitfld.long 0x00 3. "PWM3_HIT," "0,1"
bitfld.long 0x00 2. "PWM3_RST_CNT_EN," "0,1"
bitfld.long 0x00 1. "PWM0_HIT," "0,1"
bitfld.long 0x00 0. "PWM0_RST_CNT_EN," "0,1"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x10C)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr0_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x114)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr1_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x11C)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr2_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x124)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr3_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x12C)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr4_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x134)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr5_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x13C)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr6_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x144)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capf6_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x14C)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capr7_bi_reg$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x154)++0x03
line.long 0x00 "PR1_IEP0__SLV__REGS_capf7_bi_reg$1,"
repeat.end
group.long 0x180++0x1F
line.long 0x00 "PR1_IEP0__SLV__REGS_sync_ctrl_reg,"
bitfld.long 0x00 10. "SYNC1_OUT_NV_EN," "0,1"
bitfld.long 0x00 9. "SYNC0_OUT_NV_EN," "0,1"
bitfld.long 0x00 8. "SYNC1_IND_EN," "0,1"
bitfld.long 0x00 7. "SYNC1_CYCLIC_EN," "0,1"
bitfld.long 0x00 6. "SYNC1_ACK_EN," "0,1"
newline
bitfld.long 0x00 5. "SYNC0_CYCLIC_EN," "0,1"
bitfld.long 0x00 4. "SYNC0_ACK_EN," "0,1"
bitfld.long 0x00 2. "SYNC1_EN," "0,1"
bitfld.long 0x00 1. "SYNC0_EN," "0,1"
bitfld.long 0x00 0. "SYNC_EN," "0,1"
line.long 0x04 "PR1_IEP0__SLV__REGS_sync_first_stat_reg,"
bitfld.long 0x04 1. "FIRST_SYNC1," "0,1"
bitfld.long 0x04 0. "FIRST_SYNC0," "0,1"
line.long 0x08 "PR1_IEP0__SLV__REGS_sync0_stat_reg,"
bitfld.long 0x08 0. "SYNC0_PEND," "0,1"
line.long 0x0C "PR1_IEP0__SLV__REGS_sync1_stat_reg,"
bitfld.long 0x0C 0. "SYNC1_PEND," "0,1"
line.long 0x10 "PR1_IEP0__SLV__REGS_sync_pwidth_reg,"
line.long 0x14 "PR1_IEP0__SLV__REGS_sync0_period_reg,"
line.long 0x18 "PR1_IEP0__SLV__REGS_sync1_delay_reg,"
line.long 0x1C "PR1_IEP0__SLV__REGS_sync_start_reg,"
group.long 0x200++0x17
line.long 0x00 "PR1_IEP0__SLV__REGS_wd_prediv_reg,"
hexmask.long.word 0x00 0.--15. 1. "PRE_DIV,"
line.long 0x04 "PR1_IEP0__SLV__REGS_pdi_wd_tim_reg,"
hexmask.long.word 0x04 0.--15. 1. "PDI_WD_TIME,"
line.long 0x08 "PR1_IEP0__SLV__REGS_pd_wd_tim_reg,"
hexmask.long.word 0x08 0.--15. 1. "PD_WD_TIME,"
line.long 0x0C "PR1_IEP0__SLV__REGS_wd_status_reg,"
bitfld.long 0x0C 16. "PDI_WD_STAT," "0,1"
bitfld.long 0x0C 0. "PD_WD_STAT," "0,1"
line.long 0x10 "PR1_IEP0__SLV__REGS_wd_exp_cnt_reg,"
hexmask.long.byte 0x10 8.--15. 1. "PD_EXP_CNT,"
hexmask.long.byte 0x10 0.--7. 1. "PDI_EXP_CNT,"
line.long 0x14 "PR1_IEP0__SLV__REGS_wd_ctrl_reg,"
bitfld.long 0x14 16. "PDI_WD_EN," "0,1"
bitfld.long 0x14 0. "PD_WD_EN," "0,1"
group.long 0x300++0x1B
line.long 0x00 "PR1_IEP0__SLV__REGS_digio_ctrl_reg,"
bitfld.long 0x00 6.--7. "OUT_MODE," "0,1,2,3"
bitfld.long 0x00 4.--5. "IN_MODE," "0,1,2,3"
bitfld.long 0x00 3. "WD_MODE," "0,1"
rbitfld.long 0x00 2. "BIDI_MODE," "0,1"
bitfld.long 0x00 1. "OUTVALID_MODE," "0,1"
newline
rbitfld.long 0x00 0. "OUTVALID_POL," "0,1"
line.long 0x04 "PR1_IEP0__SLV__REGS_digio_status_reg,"
line.long 0x08 "PR1_IEP0__SLV__REGS_digio_data_in_reg,"
line.long 0x0C "PR1_IEP0__SLV__REGS_digio_data_in_raw_reg,"
line.long 0x10 "PR1_IEP0__SLV__REGS_digio_data_out_reg,"
line.long 0x14 "PR1_IEP0__SLV__REGS_digio_data_out_en_reg,"
line.long 0x18 "PR1_IEP0__SLV__REGS_digio_exp_reg,"
bitfld.long 0x18 13. "EOF_SEL," "0,1"
bitfld.long 0x18 12. "SOF_SEL," "0,1"
bitfld.long 0x18 8.--11. "SOF_DLY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 4.--7. "OUTVALID_DLY," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 2. "SW_OUTVALID," "0,1"
newline
bitfld.long 0x18 1. "OUTVALID_OVR_EN," "0,1"
bitfld.long 0x18 0. "SW_DATA_OUT_UP," "0,1"
tree.end
tree "ICSSM0_PR1_CFG_SLV"
base ad:0x26000
rgroup.long 0x00++0x1F
line.long 0x00 "PR1_CFG__SLV__REGS_pid_reg,"
line.long 0x04 "PR1_CFG__SLV__REGS_hwdis_reg,"
hexmask.long.byte 0x04 0.--7. 1. "HWDIS,HW Disable Observation"
line.long 0x08 "PR1_CFG__SLV__REGS_gpcfg0_reg,"
bitfld.long 0x08 26.--29. "PR1_PRU0_GP_MUX_SEL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x08 25. "PRU0_GPO_SH1_SEL," "0,1"
bitfld.long 0x08 20.--24. "PRU0_GPO_DIV1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 15.--19. "PRU0_GPO_DIV0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 14. "PRU0_GPO_MODE," "0,1"
bitfld.long 0x08 13. "PRU0_GPI_SB," "0,1"
newline
bitfld.long 0x08 8.--12. "PRU0_GPI_DIV1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 3.--7. "PRU0_GPI_DIV0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 2. "PRU0_GPI_CLK_MODE," "0,1"
newline
bitfld.long 0x08 0.--1. "PRU0_GPI_MODE," "0,1,2,3"
line.long 0x0C "PR1_CFG__SLV__REGS_gpcfg1_reg,"
bitfld.long 0x0C 26.--29. "PR1_PRU1_GP_MUX_SEL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x0C 25. "PRU1_GPO_SH1_SEL," "0,1"
bitfld.long 0x0C 20.--24. "PRU1_GPO_DIV1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 15.--19. "PRU1_GPO_DIV0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 14. "PRU1_GPO_MODE," "0,1"
bitfld.long 0x0C 13. "PRU1_GPI_SB," "0,1"
newline
bitfld.long 0x0C 8.--12. "PRU1_GPI_DIV1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 3.--7. "PRU1_GPI_DIV0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 2. "PRU1_GPI_CLK_MODE," "0,1"
newline
bitfld.long 0x0C 0.--1. "PRU1_GPI_MODE," "0,1,2,3"
line.long 0x10 "PR1_CFG__SLV__REGS_cgr_reg,"
bitfld.long 0x10 31. "ICSS_STOP_ACK," "0,1"
rbitfld.long 0x10 30. "ICSS_STOP_REQ," "0,1"
bitfld.long 0x10 29. "ICSS_PWR_IDLE," "0,1"
newline
bitfld.long 0x10 21. "BOTTOM_HALF_CLK_GATE_EN," "0,1"
bitfld.long 0x10 20. "TOP_HALF_CLK_GATE_EN," "0,1"
bitfld.long 0x10 19. "AUTO_SLICE1_CLK_GATE_EN," "0,1"
newline
bitfld.long 0x10 18. "AUTO_SLICE0_CLK_GATE_EN," "0,1"
bitfld.long 0x10 17. "IEP_CLK_EN," "0,1"
rbitfld.long 0x10 16. "IEP_CLK_STOP_ACK," "0,1"
newline
bitfld.long 0x10 15. "IEP_CLK_STOP_REQ," "0,1"
bitfld.long 0x10 14. "ECAP_CLK_EN," "0,1"
rbitfld.long 0x10 13. "ECAP_CLK_STOP_ACK," "0,1"
newline
bitfld.long 0x10 12. "ECAP_CLK_STOP_REQ," "0,1"
bitfld.long 0x10 11. "UART_CLK_EN," "0,1"
rbitfld.long 0x10 10. "UART_CLK_STOP_ACK," "0,1"
newline
bitfld.long 0x10 9. "UART_CLK_STOP_REQ," "0,1"
bitfld.long 0x10 8. "INTC_CLK_EN," "0,1"
rbitfld.long 0x10 7. "INTC_CLK_STOP_ACK," "0,1"
newline
bitfld.long 0x10 6. "INTC_CLK_STOP_REQ," "0,1"
line.long 0x14 "PR1_CFG__SLV__REGS_gpecfg0_reg,"
bitfld.long 0x14 17. "PRU0_GPO_SHIFT_CLK_DONE," "0,1"
bitfld.long 0x14 16. "PRU0_GPO_SHIFT_CLK_HIGH," "0,1"
hexmask.long.byte 0x14 8.--15. 1. "PRU0_GPO_SHIFT_CNT,"
newline
bitfld.long 0x14 6. "PRU0_GPO_SHIFT_GP_EN," "0,1"
bitfld.long 0x14 5. "PRU0_GPO_SHIFT_CLK_FREE," "0,1"
bitfld.long 0x14 4. "PRU0_GPO_SHIFT_SWAP," "0,1"
newline
bitfld.long 0x14 1. "PRU0_GPI_SHIFT_EN," "0,1"
bitfld.long 0x14 0. "PRU0_GPI_SB_P," "0,1"
line.long 0x18 "PR1_CFG__SLV__REGS_gpecfg1_reg,"
bitfld.long 0x18 17. "PRU1_GPO_SHIFT_CLK_DONE," "0,1"
bitfld.long 0x18 16. "PRU1_GPO_SHIFT_CLK_HIGH," "0,1"
hexmask.long.byte 0x18 8.--15. 1. "PRU1_GPO_SHIFT_CNT,"
newline
bitfld.long 0x18 6. "PRU1_GPO_SHIFT_GP_EN," "0,1"
bitfld.long 0x18 5. "PRU1_GPO_SHIFT_CLK_FREE," "0,1"
bitfld.long 0x18 4. "PRU1_GPO_SHIFT_SWAP," "0,1"
newline
bitfld.long 0x18 1. "PRU1_GPI_SHIFT_EN," "0,1"
bitfld.long 0x18 0. "PRU1_GPI_SB_P," "0,1"
line.long 0x1C "PR1_CFG__SLV__REGS_reset_iso_reg,"
bitfld.long 0x1C 2. "RESET_ISO_EDGE," "0,1"
bitfld.long 0x1C 1. "RESET_ISO_ACK," "0,1"
bitfld.long 0x1C 0. "RESET_ISO_REQ," "0,1"
group.long 0x2C++0x1B
line.long 0x00 "PR1_CFG__SLV__REGS_mii_rt_reg,"
bitfld.long 0x00 0. "MII_RT_EVENT_EN," "0,1"
line.long 0x04 "PR1_CFG__SLV__REGS_iepclk_reg,"
bitfld.long 0x04 1. "IEP1_SLV_EN," "0,1"
bitfld.long 0x04 0. "IEP_OCP_CLK_EN," "0,1"
line.long 0x08 "PR1_CFG__SLV__REGS_spp_reg,"
bitfld.long 0x08 3. "RTU_XFR_SHIFT_EN," "0,1"
bitfld.long 0x08 2. "XFR_BYTE_SHIFT_EN," "0,1"
bitfld.long 0x08 1. "XFR_SHIFT_EN," "0,1"
newline
bitfld.long 0x08 0. "PRU1_PAD_HP_EN," "0,1"
line.long 0x0C "PR1_CFG__SLV__REGS_spin_cfg_reg,"
bitfld.long 0x0C 0. "SPIN_CLOCK_TX_PRU_EN," "0,1"
line.long 0x10 "PR1_CFG__SLV__REGS_core_sync_reg,"
bitfld.long 0x10 0. "CORE_VBUSP_SYNC_EN," "0,1"
line.long 0x14 "PR1_CFG__SLV__REGS_sa_mx_reg,"
bitfld.long 0x14 16. "PWM_EFC_EN," "0,1"
bitfld.long 0x14 10.--11. "PWM3_REMAP_EN," "0,1,2,3"
bitfld.long 0x14 8.--9. "PWM0_REMAP_EN," "0,1,2,3"
newline
hexmask.long.byte 0x14 0.--7. 1. "SA_MUX_SEL,"
line.long 0x18 "PR1_CFG__SLV__REGS_pru0_sd_clk_div_reg,"
hexmask.long.byte 0x18 24.--31. 1. "PRU0_SD_MAN_REC_CLK_PERIOD,"
rbitfld.long 0x18 16. "PRU0_SD_MAN_CLK_CAL_DONE," "0,1"
rbitfld.long 0x18 15. "PRU0_SD_MAN_STATUS," "0,1"
newline
bitfld.long 0x18 11.--14. "PRU0_SD_CH_SEL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 10. "PRU0_SD_MAN_NV_DATA_EN," "0,1"
bitfld.long 0x18 9. "PRU0_SD_MAN_EN," "0,1"
newline
bitfld.long 0x18 8. "PRU0_SD_SHARE_EN," "0,1"
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 )
group.long ($2+0x48)++0x03
line.long 0x00 "PR1_CFG__SLV__REGS_pru0_sd_clk_sel_reg$1,"
bitfld.long 0x00 22. "PRU0_FD_ZERO_MAX_0," "0,1"
bitfld.long 0x00 17.--21. "PRU0_FD_ZERO_MAX_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "PRU0_FD_ZERO_MIN_0," "0,1"
newline
bitfld.long 0x00 11.--15. "PRU0_FD_ZERO_MIN_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--5. "PRU0_SD_ACC_SEL0," "0,1,2,3"
bitfld.long 0x00 2. "PRU0_SD_CLK_INV0," "0,1"
newline
bitfld.long 0x00 0.--1. "PRU0_SD_CLK_SEL0," "0,1,2,3"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 )
group.long ($2+0x4C)++0x03
line.long 0x00 "PR1_CFG__SLV__REGS_pru0_sd_sample_size_reg$1,"
bitfld.long 0x00 23. "PRU0_FD_EN_0," "0,1"
bitfld.long 0x00 22. "PRU0_FD_ONE_MAX_0," "0,1"
bitfld.long 0x00 17.--21. "PRU0_FD_ONE_MAX_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16. "PRU0_FD_ONE_MIN_0," "0,1"
bitfld.long 0x00 11.--15. "PRU0_FD_ONE_MIN_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "PRU0_FD_WINDOW_SIZE_0," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 0.--7. 1. "PRU0_SD_SAMPLE_SIZE0,"
repeat.end
group.long 0x90++0x03
line.long 0x00 "PR1_CFG__SLV__REGS_pru1_sd_clk_div_reg,"
hexmask.long.byte 0x00 24.--31. 1. "PRU1_SD_MAN_REC_CLK_PERIOD,"
rbitfld.long 0x00 16. "PRU1_SD_MAN_CLK_CAL_DONE," "0,1"
rbitfld.long 0x00 15. "PRU1_SD_MAN_STATUS," "0,1"
newline
bitfld.long 0x00 11.--14. "PRU1_SD_CH_SEL," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10. "PRU1_SD_MAN_NV_DATA_EN," "0,1"
bitfld.long 0x00 9. "PRU1_SD_MAN_EN," "0,1"
newline
bitfld.long 0x00 8. "PRU1_SD_SHARE_EN," "0,1"
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 )
group.long ($2+0x94)++0x03
line.long 0x00 "PR1_CFG__SLV__REGS_pru1_sd_clk_sel_reg$1,"
bitfld.long 0x00 22. "PRU1_FD_ZERO_MAX_0," "0,1"
bitfld.long 0x00 17.--21. "PRU1_FD_ZERO_MAX_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16. "PRU1_FD_ZERO_MIN_0," "0,1"
newline
bitfld.long 0x00 11.--15. "PRU1_FD_ZERO_MIN_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--5. "PRU1_SD_ACC_SEL0," "0,1,2,3"
bitfld.long 0x00 2. "PRU1_SD_CLK_INV0," "0,1"
newline
bitfld.long 0x00 0.--1. "PRU1_SD_CLK_SEL0," "0,1,2,3"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 )
group.long ($2+0x98)++0x03
line.long 0x00 "PR1_CFG__SLV__REGS_pru1_sd_sample_size_reg$1,"
bitfld.long 0x00 23. "PRU1_FD_EN_0," "0,1"
bitfld.long 0x00 22. "PRU1_FD_ONE_MAX_0," "0,1"
bitfld.long 0x00 17.--21. "PRU1_FD_ONE_MAX_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16. "PRU1_FD_ONE_MIN_0," "0,1"
bitfld.long 0x00 11.--15. "PRU1_FD_ONE_MIN_LIMIT_0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "PRU1_FD_WINDOW_SIZE_0," "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 0.--7. 1. "PRU1_SD_SAMPLE_SIZE0,"
repeat.end
group.long 0xE0++0x3F
line.long 0x00 "PR1_CFG__SLV__REGS_pru0_ed_rx_cfg_reg,"
hexmask.long.word 0x00 16.--31. 1. "PRU0_ED_RX_DIV_FACTOR,"
bitfld.long 0x00 15. "PRU0_ED_RX_DIV_FACTOR_FRAC," "0,1"
bitfld.long 0x00 4. "PRU0_ED_RX_CLK_SEL," "0,1"
newline
bitfld.long 0x00 3. "PRU0_ED_RX_SB_POL," "0,1"
bitfld.long 0x00 0.--2. "PRU0_ED_RX_SAMPLE_SIZE," "0,1,2,3,4,5,6,7"
line.long 0x04 "PR1_CFG__SLV__REGS_pru0_ed_tx_cfg_reg,"
hexmask.long.word 0x04 16.--31. 1. "PRU0_ED_TX_DIV_FACTOR,"
bitfld.long 0x04 15. "PRU0_ED_TX_DIV_FACTOR_FRAC," "0,1"
bitfld.long 0x04 11. "PRU0_ENDAT_SHARE_EN," "0,1"
newline
rbitfld.long 0x04 10. "PRU0_ENDAT2_CLK_SYNC," "0,1"
rbitfld.long 0x04 9. "PRU0_ENDAT1_CLK_SYNC," "0,1"
rbitfld.long 0x04 8. "PRU0_ENDAT0_CLK_SYNC," "0,1"
newline
rbitfld.long 0x04 7. "PRU0_ED_BUSY_2," "0,1"
rbitfld.long 0x04 6. "PRU0_ED_BUSY_1," "0,1"
rbitfld.long 0x04 5. "PRU0_ED_BUSY_0," "0,1"
newline
bitfld.long 0x04 4. "PRU0_ED_TX_CLK_SEL," "0,1"
line.long 0x08 "PR1_CFG__SLV__REGS_pru0_ed_ch0_cfg0_reg,"
bitfld.long 0x08 31. "PRU0_ED_TX_FIFO_SWAP_BITS0," "0,1"
bitfld.long 0x08 30. "PRU0_ED_SW_CLK_OUT0," "0,1"
bitfld.long 0x08 29. "PRU0_ED_CLK_OUT_OVR_EN0," "0,1"
newline
rbitfld.long 0x08 28. "PRU0_ED_RX_SNOOP0," "0,1"
hexmask.long.word 0x08 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE0,"
bitfld.long 0x08 11.--15. "PRU0_ED_TX_FRAME_SIZE0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x08 0.--10. 1. "PRU0_ED_TX_WDLY0,"
line.long 0x0C "PR1_CFG__SLV__REGS_pru0_ed_ch0_cfg1_reg,"
hexmask.long.word 0x0C 16.--31. 1. "PRU0_ED_RX_EN_COUNTER0,"
hexmask.long.word 0x0C 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER0,"
line.long 0x10 "PR1_CFG__SLV__REGS_pru0_ed_ch1_cfg0_reg,"
bitfld.long 0x10 31. "PRU0_ED_TX_FIFO_SWAP_BITS1," "0,1"
bitfld.long 0x10 30. "PRU0_ED_SW_CLK_OUT1," "0,1"
bitfld.long 0x10 29. "PRU0_ED_CLK_OUT_OVR_EN1," "0,1"
newline
rbitfld.long 0x10 28. "PRU0_ED_RX_SNOOP1," "0,1"
hexmask.long.word 0x10 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE1,"
bitfld.long 0x10 11.--15. "PRU0_ED_TX_FRAME_SIZE1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x10 0.--10. 1. "PRU0_ED_TX_WDLY1,"
line.long 0x14 "PR1_CFG__SLV__REGS_pru0_ed_ch1_cfg1_reg,"
hexmask.long.word 0x14 16.--31. 1. "PRU0_ED_RX_EN_COUNTER1,"
hexmask.long.word 0x14 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER1,"
line.long 0x18 "PR1_CFG__SLV__REGS_pru0_ed_ch2_cfg0_reg,"
bitfld.long 0x18 31. "PRU0_ED_TX_FIFO_SWAP_BITS2," "0,1"
bitfld.long 0x18 30. "PRU0_ED_SW_CLK_OUT2," "0,1"
bitfld.long 0x18 29. "PRU0_ED_CLK_OUT_OVR_EN2," "0,1"
newline
rbitfld.long 0x18 28. "PRU0_ED_RX_SNOOP2," "0,1"
hexmask.long.word 0x18 16.--27. 1. "PRU0_ED_RX_FRAME_SIZE2,"
bitfld.long 0x18 11.--15. "PRU0_ED_TX_FRAME_SIZE2," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x18 0.--10. 1. "PRU0_ED_TX_WDLY2,"
line.long 0x1C "PR1_CFG__SLV__REGS_pru0_ed_ch2_cfg1_reg,"
hexmask.long.word 0x1C 16.--31. 1. "PRU0_ED_RX_EN_COUNTER2,"
hexmask.long.word 0x1C 0.--15. 1. "PRU0_ED_TST_DELAY_COUNTER2,"
line.long 0x20 "PR1_CFG__SLV__REGS_pru1_ed_rx_cfg_reg,"
hexmask.long.word 0x20 16.--31. 1. "PRU1_ED_RX_DIV_FACTOR,"
bitfld.long 0x20 15. "PRU1_ED_RX_DIV_FACTOR_FRAC," "0,1"
bitfld.long 0x20 4. "PRU1_ED_RX_CLK_SEL," "0,1"
newline
bitfld.long 0x20 3. "PRU1_ED_RX_SB_POL," "0,1"
bitfld.long 0x20 0.--2. "PRU1_ED_RX_SAMPLE_SIZE," "0,1,2,3,4,5,6,7"
line.long 0x24 "PR1_CFG__SLV__REGS_pru1_ed_tx_cfg_reg,"
hexmask.long.word 0x24 16.--31. 1. "PRU1_ED_TX_DIV_FACTOR,"
bitfld.long 0x24 15. "PRU1_ED_TX_DIV_FACTOR_FRAC," "0,1"
bitfld.long 0x24 11. "PRU1_ENDAT_SHARE_EN," "0,1"
newline
rbitfld.long 0x24 10. "PRU1_ENDAT2_CLK_SYNC," "0,1"
rbitfld.long 0x24 9. "PRU1_ENDAT1_CLK_SYNC," "0,1"
rbitfld.long 0x24 8. "PRU1_ENDAT0_CLK_SYNC," "0,1"
newline
rbitfld.long 0x24 7. "PRU1_ED_BUSY_2," "0,1"
rbitfld.long 0x24 6. "PRU1_ED_BUSY_1," "0,1"
rbitfld.long 0x24 5. "PRU1_ED_BUSY_0," "0,1"
newline
bitfld.long 0x24 4. "PRU1_ED_TX_CLK_SEL," "0,1"
line.long 0x28 "PR1_CFG__SLV__REGS_pru1_ed_ch0_cfg0_reg,"
bitfld.long 0x28 31. "PRU1_ED_TX_FIFO_SWAP_BITS0," "0,1"
bitfld.long 0x28 30. "PRU1_ED_SW_CLK_OUT0," "0,1"
bitfld.long 0x28 29. "PRU1_ED_CLK_OUT_OVR_EN0," "0,1"
newline
rbitfld.long 0x28 28. "PRU1_ED_RX_SNOOP0," "0,1"
hexmask.long.word 0x28 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE0,"
bitfld.long 0x28 11.--15. "PRU1_ED_TX_FRAME_SIZE0," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x28 0.--10. 1. "PRU1_ED_TX_WDLY0,"
line.long 0x2C "PR1_CFG__SLV__REGS_pru1_ed_ch0_cfg1_reg,"
hexmask.long.word 0x2C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER0,"
hexmask.long.word 0x2C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER0,"
line.long 0x30 "PR1_CFG__SLV__REGS_pru1_ed_ch1_cfg0_reg,"
bitfld.long 0x30 31. "PRU1_ED_TX_FIFO_SWAP_BITS1," "0,1"
bitfld.long 0x30 30. "PRU1_ED_SW_CLK_OUT1," "0,1"
bitfld.long 0x30 29. "PRU1_ED_CLK_OUT_OVR_EN1," "0,1"
newline
rbitfld.long 0x30 28. "PRU1_ED_RX_SNOOP1," "0,1"
hexmask.long.word 0x30 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE1,"
bitfld.long 0x30 11.--15. "PRU1_ED_TX_FRAME_SIZE1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x30 0.--10. 1. "PRU1_ED_TX_WDLY1,"
line.long 0x34 "PR1_CFG__SLV__REGS_pru1_ed_ch1_cfg1_reg,"
hexmask.long.word 0x34 16.--31. 1. "PRU1_ED_RX_EN_COUNTER1,"
hexmask.long.word 0x34 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER1,"
line.long 0x38 "PR1_CFG__SLV__REGS_pru1_ed_ch2_cfg0_reg,"
bitfld.long 0x38 31. "PRU1_ED_TX_FIFO_SWAP_BITS2," "0,1"
bitfld.long 0x38 30. "PRU1_ED_SW_CLK_OUT2," "0,1"
bitfld.long 0x38 29. "PRU1_ED_CLK_OUT_OVR_EN2," "0,1"
newline
rbitfld.long 0x38 28. "PRU1_ED_RX_SNOOP2," "0,1"
hexmask.long.word 0x38 16.--27. 1. "PRU1_ED_RX_FRAME_SIZE2,"
bitfld.long 0x38 11.--15. "PRU1_ED_TX_FRAME_SIZE2," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x38 0.--10. 1. "PRU1_ED_TX_WDLY2,"
line.long 0x3C "PR1_CFG__SLV__REGS_pru1_ed_ch2_cfg1_reg,"
hexmask.long.word 0x3C 16.--31. 1. "PRU1_ED_RX_EN_COUNTER2,"
hexmask.long.word 0x3C 0.--15. 1. "PRU1_ED_TST_DELAY_COUNTER2,"
hgroup.long 0x124++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_rtu0_poke_en0_reg,"
hgroup.long 0x12C++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_rtu1_poke_en0_reg,"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x130)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_pwm$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
hgroup.long ($2+0x140)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_pwm0_$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
hgroup.long ($2+0x14C)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_pwm1_$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
hgroup.long ($2+0x158)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_pwm2_$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
hgroup.long ($2+0x164)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_pwm3_$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
hgroup.long ($2+0x170)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_spin_lock$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x08 0x10 0x18 )
hgroup.long ($2+0x178)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_pa_stat_pdsp_cfg$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x08 0x10 0x18 )
hgroup.long ($2+0x17C)++0x03
hide.long 0x00 "PR1_CFG__SLV__REGS_pa_stat_pdsp_stat$1,"
repeat.end
tree.end
tree "ICSSM0_PR1_ICSS_ECAP0_ECAP_SLV"
base ad:0x30000
group.long 0x00++0x17
line.long 0x00 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_TSCNT,TIME STAMP COUNTER REGISTER"
line.long 0x04 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CNTPHS,COUNTER PHASE CONTROL REGISTER"
line.long 0x08 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP1,CAPTURE-1 REGISTER"
line.long 0x0C "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP2,CAPTURE-2 REGISTER"
line.long 0x10 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP3,CAPTURE-3 REGISTER"
line.long 0x14 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_CAP4,CAPTURE-4 REGISTER"
group.long 0x28++0x0F
line.long 0x00 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_ECCTL2_ECCTL1,ECAP CONTROL REGISTER 1"
rbitfld.long 0x00 27.--31. "FILTER," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 26. "APWMPOL,APWM OUTPUT POLARITY SELECT:0OUTPUT IS ACTIVE HIGH [IE COMPARE VALUE DEFINES HIGH TIME]1OUTPUT IS ACTIVE LOW [IE COMPARE VALUE DEFINES LOW TIME]NOTE: THIS IS APPLICABLE ONLY IN APWM OPERATING MODE" "0,1"
bitfld.long 0x00 25. "CAP_APWM,CAP/APWM OPERATING MODE SELECT:0ECAP MODULE OPERATES IN CAPTURE MODETHIS MODE FORCES THE FOLLOWING CONFIGURATION:1] INHIBITS TSCNT RESETS VIA PRD_EQ EVENT2] INHIBITS SHADOW LOADS ON CAP1 &AMP" "0,1"
bitfld.long 0x00 24. "SWSYNC,SOFTWARE FORCED COUNTER [TSCNT] SYNCING:0WRITING A ZERO HAS NO EFFECT WILL ALWAYS RETURN A ZERO1WRITING A ONE WILL FORCE A TSCNT SHADOW LOAD OF CURRENT ECAP MODULE AND ANY ECAP MODULES DOWN-STREAM PROVIDING THE SYNCO_SEL BITS ARE 0 0 AFTER.." "0,1"
bitfld.long 0x00 22.--23. "SYNCO_SEL,SYNC-OUT SELECT:0 0SELECT SYNC-IN EVENT TO BE THE SYNC-OUT SIGNAL [PASS THROUGH]0 1SELECT PRD_EQ EVENT TO BE THE SYNC-OUT SIGNAL1 0DISABLE SYNC OUT SIGNAL1 1DISABLE SYNC OUT SIGNALNOTE: SELECTION PRD_EQ IS MEANINGFUL ONLY IN APWM MODE HOWEVER.." "0,1,2,3"
bitfld.long 0x00 21. "SYNCI_EN,COUNTER [TSCNT] SYNC-IN SELECT MODE:0DISABLE SYNC-IN OPTION1ENABLE COUNTER [TSCNT] TO BE LOADED FROM CNTPHS REGISTER UPON EITHER A SYNCI SIGNAL OR A S/W FORCE EVENT" "0,1"
newline
bitfld.long 0x00 20. "TSCNTSTP,COUNTER STOP [FREEZE] CONTROL:0COUNTER STOPPED1COUNTER FREE RUNNING" "0,1"
bitfld.long 0x00 19. "REARM_RESET,ONE-SHOT RE-ARMING IE WAIT FOR STOP TRIGGER:WRITING A ONE ARMS THE ONE-SHOT SEQUENCE IE:1] RESETS THE MOD4 COUNTER TO ZERO2] UN-FREEZES THE MOD4 COUNTER3] ENABLES CAPTURE REGISTER LOADSWRITING A ZERO HAS NO EFFECT ALWAYS RETURNS A 0NOTE: THE.." "0,1"
bitfld.long 0x00 17.--18. "STOPVALUE,STOP VALUE FOR ONE-SHOT MODE:THIS IS THE NUMBER [BETWEEN 1-4] OF CAPTURES ALLOWED TO OCCUR BEFORE THE CAP[1-4] REGISTERS ARE FROZEN IECAPTURE SEQUENCE IS STOPPED0 0STOP AFTER CAPTURE EVENT 10 1STOP AFTER CAPTURE EVENT 21 0STOP AFTER CAPTURE.." "0,1,2,3"
bitfld.long 0x00 16. "CONT_ONESHT,CONTINUOUS OR ONESHOT MODE CONTROL:[APPLICABLE ONLY IN CAPTURE MODE]0OPERATE IN CONTINUOUS MODE1OPERATE IN ONE-SHOT MODE" "0,1"
bitfld.long 0x00 15. "FREE,EMULATION CONTROL0 0 TSCNT COUNTER STOPS IMMEDIATELY ON EMULATION SUSPEND0 1 TSCNT COUNTER RUNS UNTIL = 01 X TSCNT COUNTER IS UNAFFECTED BY EMULATION SUSPEND [RUN FREE]" "0,1"
bitfld.long 0x00 14. "SOFT,EMULATION CONTROL0 0 TSCNT COUNTER STOPS IMMEDIATELY ON EMULATION SUSPEND0 1 TSCNT COUNTER RUNS UNTIL = 01 X TSCNT COUNTER IS UNAFFECTED BY EMULATION SUSPEND [RUN FREE]" "0,1"
newline
bitfld.long 0x00 9.--13. "EVTFLTPS,EVENT FILTER PRESCALE SELECT:0 0 0 0 0DIVIDE BY 1 [IE NO PRESCALE BY-PASS THE PRESCALER]0 0 0 0 1DIVIDE BY 20 0 0 1 0DIVIDE BY 40 0 0 1 1DIVIDE BY 60 0 1 0 0DIVIDE BY 80 0 1 0 1DIVIDE BY 10 1 1 1 1 0DIVIDE BY 601 1 1 1 1DIVIDE BY 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8. "CAPLDEN,ENABLE LOADING OF CAP1-4 REGISTERS ON A CAPTURE EVENT:0DISABLE CAP1-4 REGISTER LOADS AT CAPTURE EVENT TIME1ENABLE CAP1-4 REGISTER LOADS AT CAPTURE EVENT TIME" "0,1"
bitfld.long 0x00 7. "CTRRST4,COUNTER RESET ON CAPTURE EVENT 4:0DO NOT RESET COUNTER ON CAPTURE EVENT 4 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 4 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "0,1"
bitfld.long 0x00 6. "CAP4POL,CAPTURE EVENT 4 POLARITY SELECT:0CAPTURE EVENT 4 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 4 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
bitfld.long 0x00 5. "CTRRST3,COUNTER RESET ON CAPTURE EVENT 3:0DO NOT RESET COUNTER ON CAPTURE EVENT 3 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 3 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "0,1"
bitfld.long 0x00 4. "CAP3POL,CAPTURE EVENT 3 POLARITY SELECT:0CAPTURE EVENT 3 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 3 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
newline
bitfld.long 0x00 3. "CTRRST2,COUNTER RESET ON CAPTURE EVENT 2:0DO NOT RESET COUNTER ON CAPTURE EVENT 2 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 2 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "0,1"
bitfld.long 0x00 2. "CAP2POL,CAPTURE EVENT 2 POLARITY SELECT:0CAPTURE EVENT 2 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 2 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
bitfld.long 0x00 1. "CTRRST1,COUNTER RESET ON CAPTURE EVENT 1:0DO NOT RESET COUNTER ON CAPTURE EVENT 1 [ABSOLUTE TIME STAMP]1RESET COUNTER AFTER EVENT 1 TIME-STAMP HAS BEEN CAPTURED[USED IN DIFFERENCE MODE OPERATION]" "0,1"
bitfld.long 0x00 0. "CAP1POL,CAPTURE EVENT 1 POLARITY SELECT:0CAPTURE EVENT 1 TRIGGERED ON A RISING EDGE [FE]1CAPTURE EVENT 1 TRIGGERED ON A FALLING EDGE [FE]" "0,1"
line.long 0x04 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_ECFLG_ECEINT,ECAP INTERRUPT ENABLE REGISTER"
hexmask.long.byte 0x04 24.--31. 1. "FLAG_RESV0,"
rbitfld.long 0x04 23. "FLAG_CMPEQ,COMPARE EQUAL STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] REACHED THE COMPARE REGISTER VALUE [ACMP]READING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN APWM MODE" "0,1"
rbitfld.long 0x04 22. "FLAG_PRDEQ,PERIOD EQUAL STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] REACHED THE PERIOD REGISTER VALUE [APER] AND WAS RESETREADING A 0 INDICATES NO EVENT OCCURREDNOTES: THIS FLAG IS ONLY ACTIVE IN APWM MODE" "0,1"
rbitfld.long 0x04 21. "FLAG_CNTOVF,COUNTER OVERFLOW STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE COUNTER [TSCNT] HAS MADE THE TRANSITION FROM FFFFFFFF 00000000READING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ACTIVE IN CAP &AMP" "0,1"
rbitfld.long 0x04 20. "FLAG_CEVT4,CAPTURE EVENT 4 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE FOURTH EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
rbitfld.long 0x04 19. "FLAG_CEVT3,CAPTURE EVENT 3 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE THIRD EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
newline
rbitfld.long 0x04 18. "FLAG_CEVT2,CAPTURE EVENT 2 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE SECOND EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
rbitfld.long 0x04 17. "FLAG_CEVT1,CAPTURE EVENT 1 STATUS FLAG: READING A 1 ON THIS BIT INDICATES THE FIRST EVENT OCCURRED AT ECAPX PINREADING A 0 INDICATES NO EVENT OCCURREDNOTE: THIS FLAG IS ONLY ACTIVE IN CAP MODE" "0,1"
rbitfld.long 0x04 16. "FLAG_INT,GLOBAL INTERRUPT STATUS FLAG: READING A 1 ON THIS BIT INDICATES THAT AN INTERRUPT WAS GENERATED FROM ONE OF THE FOLLOWING EVENTSREADING A 0 INDICATES NO INTERRUPT GENERATED" "0,1"
hexmask.long.byte 0x04 8.--15. 1. "EN__RESV1,"
bitfld.long 0x04 7. "EN_CMPEQ,COMPARE EQUAL INTERRUPT ENABLE: 0DISABLED COMPARE EQUAL AS AN INTERRUPT SOURCE1ENABLE COMPARE EQUAL AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x04 6. "EN_PRDEQ,PERIOD EQUAL INTERRUPT ENABLE: 0DISABLED PERIOD EQUAL AS AN INTERRUPT SOURCE1ENABLE PERIOD EQUAL AS AN INTERRUPT SOURCE" "0,1"
newline
bitfld.long 0x04 5. "EN_CNTOVF,COUNTER OVERFLOW INTERRUPT ENABLE: 0DISABLED COUNTER OVERFLOW AS AN INTERRUPT SOURCE1ENABLE COUNTER OVERFLOW AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x04 4. "EN_CEVT4,CAPTURE EVENT 4 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x04 3. "EN_CEVT3,CAPTURE EVENT 3 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x04 2. "EN_CEVT2,CAPTURE EVENT 2 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
bitfld.long 0x04 1. "EN_CEVT1,CAPTURE EVENT 1 INTERRUPT ENABLE: 0DISABLED CAPTURE EVENT 1 AS AN INTERRUPT SOURCE1ENABLE CAPTURE EVENT 1 AS AN INTERRUPT SOURCE" "0,1"
rbitfld.long 0x04 0. "EN_RESV0," "0,1"
line.long 0x08 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_ECCLR,ECAP INTERRUPT CLEAR REGISTER"
hexmask.long.byte 0x08 8.--15. 1. "_RESV0,"
bitfld.long 0x08 7. "CMPEQ,COMPARE EQUAL STATUS FLAG: WRITING A 1 WILL CLEAR THE CMPEQ FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
bitfld.long 0x08 6. "PRDEQ,PERIOD EQUAL STATUS FLAG: WRITING A 1 WILL CLEAR THE PRDEQ FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
bitfld.long 0x08 5. "CNTOVF,COUNTER OVERFLOW STATUS FLAG: WRITING A 1 WILL CLEAR THE CNTOVF FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
bitfld.long 0x08 4. "CEVT4,CAPTURE EVENT 4 STATUS FLAG: WRITING A 1 WILL CLEAR THE CEVT3 FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
bitfld.long 0x08 3. "CEVT3,CAPTURE EVENT 3 STATUS FLAG: WRITING A 1 WILL CLEAR THE CEVT3 FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
newline
bitfld.long 0x08 2. "CEVT2,CAPTURE EVENT 2 STATUS FLAG: WRITING A 1 WILL CLEAR THE CEVT2 FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
bitfld.long 0x08 1. "CEVT1,CAPTURE EVENT 1 STATUS FLAG: WRITING A 1 WILL CLEAR THE CEVT1 FLAG CONDITIONWRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
bitfld.long 0x08 0. "INT,GLOBAL INTERRUPT CLEAR FLAG: WRITING A 1 WILL CLEAR THE INT FLAG AND ENABLE FURTHER INTERRUPTS TO BE GENERATED IF ANY OF THE EVENT FLAGS ARE SET TO 1WRITING A 0 WILL HAVE NO EFFECTALWAYS READS BACK A 0" "0,1"
line.long 0x0C "PR1_ICSS_ECAP0__ECAP_SLV__REGS_ECFRC,ECAP INTERRUPT FORCING REGISTER"
hexmask.long.byte 0x0C 8.--15. 1. "_RESV1,"
bitfld.long 0x0C 7. "CMPEQ,FORCE COMPARE EQUAL: WRITING A 1 TO THIS BIT WILL SET THE CMPEQ FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0" "0,1"
bitfld.long 0x0C 6. "PRDEQ,FORCE PERIOD EQUAL: WRITING A 1 TO THIS BIT WILL SET THE PRDEQ FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0" "0,1"
bitfld.long 0x0C 5. "CNTOVF,FORCE COUNTER OVERFLOW: WRITING A 1 TO THIS BIT WILL SET THE CNTOVF FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0" "0,1"
bitfld.long 0x0C 4. "CEVT4,FORCE CAPTURE EVENT" "0,1"
bitfld.long 0x0C 3. "CEVT3,FORCE CAPTURE EVENT" "0,1"
newline
bitfld.long 0x0C 2. "CEVT2,FORCE CAPTURE EVENT" "0,1"
bitfld.long 0x0C 1. "CEVT1,FORCE CAPTURE EVENT" "0,1"
rbitfld.long 0x0C 0. "_RESV0," "0,1"
rgroup.long 0x5C++0x03
line.long 0x00 "PR1_ICSS_ECAP0__ECAP_SLV__REGS_PID,ECAP PERIPHERAL ID REGISTER"
tree.end
tree "ICSSM0_PR1_ICSS_INTC_INTC_SLV"
base ad:0x20000
rgroup.long 0x00++0x07
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_REVISION_REG,"
bitfld.long 0x00 30.--31. "REV_SCHEME,Scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "REV_MODULE,Module ID"
bitfld.long 0x00 11.--15. "REV_RTL,RTL revisions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REV_MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "REV_CUSTOM,Custom revision" "0,1,2,3"
bitfld.long 0x00 0.--5. "REV_MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_CONTROL_REG,"
bitfld.long 0x04 4. "PRIORITY_HOLD_MODE,Priority Holding Mode" "0,1"
bitfld.long 0x04 2.--3. "NEST_MODE,Nesting Mode" "0,1,2,3"
bitfld.long 0x04 1. "WAKEUP_MODE,Wakeup mode enable" "0,1"
group.long 0x10++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_GLOBAL_ENABLE_HINT_REG,"
bitfld.long 0x00 0. "ENABLE_HINT_ANY,Global Enable for all Host Ints" "0,1"
group.long 0x1C++0x13
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_GLB_NEST_LEVEL_REG,"
bitfld.long 0x00 31. "GLB_NEST_AUTO_OVR,Global Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "GLB_NEST_LEVEL,Global Nesting Level"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_STATUS_SET_INDEX_REG,"
hexmask.long.word 0x04 0.--9. 1. "STATUS_SET_INDEX,Status Set Index Register (write index to set status of)"
line.long 0x08 "PR1_ICSS_INTC__INTC_SLV__REGS_STATUS_CLR_INDEX_REG,"
hexmask.long.word 0x08 0.--9. 1. "STATUS_CLR_INDEX,Status Clear Index Register (write index to clear status of)"
line.long 0x0C "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_SET_INDEX_REG,"
hexmask.long.word 0x0C 0.--9. 1. "ENABLE_SET_INDEX,Enable Set Index Register (write index to set enable of)"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_INDEX_REG,"
hexmask.long.word 0x10 0.--9. 1. "ENABLE_CLR_INDEX,Enable Clear Index Register (write index to clear enable of)"
group.long 0x34++0x07
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_ENABLE_SET_INDEX_REG,"
hexmask.long.word 0x00 0.--9. 1. "HINT_ENABLE_SET_INDEX,Enable set for Host Interrupts"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_ENABLE_CLR_INDEX_REG,"
hexmask.long.word 0x04 0.--9. 1. "HINT_ENABLE_CLR_INDEX,Enable clear for Host Interrupts"
rgroup.long 0x80++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_GLB_PRI_INTR_REG,"
bitfld.long 0x00 31. "GLB_NONE,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "GLB_PRI_INTR,Prioritized Interrupt"
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x200)++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_RAW_STATUS_REG$1,"
bitfld.long 0x00 31. "RAW_STATUS_31,Raw Status (write 1 to set) for intr_in[31]" "0,1"
bitfld.long 0x00 30. "RAW_STATUS_30,Raw Status (write 1 to set) for intr_in[30]" "0,1"
bitfld.long 0x00 29. "RAW_STATUS_29,Raw Status (write 1 to set) for intr_in[29]" "0,1"
newline
bitfld.long 0x00 28. "RAW_STATUS_28,Raw Status (write 1 to set) for intr_in[28]" "0,1"
bitfld.long 0x00 27. "RAW_STATUS_27,Raw Status (write 1 to set) for intr_in[27]" "0,1"
bitfld.long 0x00 26. "RAW_STATUS_26,Raw Status (write 1 to set) for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "RAW_STATUS_25,Raw Status (write 1 to set) for intr_in[25]" "0,1"
bitfld.long 0x00 24. "RAW_STATUS_24,Raw Status (write 1 to set) for intr_in[24]" "0,1"
bitfld.long 0x00 23. "RAW_STATUS_23,Raw Status (write 1 to set) for intr_in[23]" "0,1"
newline
bitfld.long 0x00 22. "RAW_STATUS_22,Raw Status (write 1 to set) for intr_in[22]" "0,1"
bitfld.long 0x00 21. "RAW_STATUS_21,Raw Status (write 1 to set) for intr_in[21]" "0,1"
bitfld.long 0x00 20. "RAW_STATUS_20,Raw Status (write 1 to set) for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "RAW_STATUS_19,Raw Status (write 1 to set) for intr_in[19]" "0,1"
bitfld.long 0x00 18. "RAW_STATUS_18,Raw Status (write 1 to set) for intr_in[18]" "0,1"
bitfld.long 0x00 17. "RAW_STATUS_17,Raw Status (write 1 to set) for intr_in[17]" "0,1"
newline
bitfld.long 0x00 16. "RAW_STATUS_16,Raw Status (write 1 to set) for intr_in[16]" "0,1"
bitfld.long 0x00 15. "RAW_STATUS_15,Raw Status (write 1 to set) for intr_in[15]" "0,1"
bitfld.long 0x00 14. "RAW_STATUS_14,Raw Status (write 1 to set) for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "RAW_STATUS_13,Raw Status (write 1 to set) for intr_in[13]" "0,1"
bitfld.long 0x00 12. "RAW_STATUS_12,Raw Status (write 1 to set) for intr_in[12]" "0,1"
bitfld.long 0x00 11. "RAW_STATUS_11,Raw Status (write 1 to set) for intr_in[11]" "0,1"
newline
bitfld.long 0x00 10. "RAW_STATUS_10,Raw Status (write 1 to set) for intr_in[10]" "0,1"
bitfld.long 0x00 9. "RAW_STATUS_9,Raw Status (write 1 to set) for intr_in[9]" "0,1"
bitfld.long 0x00 8. "RAW_STATUS_8,Raw Status (write 1 to set) for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "RAW_STATUS_7,Raw Status (write 1 to set) for intr_in[7]" "0,1"
bitfld.long 0x00 6. "RAW_STATUS_6,Raw Status (write 1 to set) for intr_in[6]" "0,1"
bitfld.long 0x00 5. "RAW_STATUS_5,Raw Status (write 1 to set) for intr_in[5]" "0,1"
newline
bitfld.long 0x00 4. "RAW_STATUS_4,Raw Status (write 1 to set) for intr_in[4]" "0,1"
bitfld.long 0x00 3. "RAW_STATUS_3,Raw Status (write 1 to set) for intr_in[3]" "0,1"
bitfld.long 0x00 2. "RAW_STATUS_2,Raw Status (write 1 to set) for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "RAW_STATUS_1,Raw Status (write 1 to set) for intr_in[1]" "0,1"
bitfld.long 0x00 0. "RAW_STATUS_0,Raw Status (write 1 to set) for intr_in[0]" "0,1"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x280)++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_ENA_STATUS_REG$1,"
bitfld.long 0x00 31. "ENA_STATUS_31,Enabled Status for intr_in[31]" "0,1"
bitfld.long 0x00 30. "ENA_STATUS_30,Enabled Status for intr_in[30]" "0,1"
bitfld.long 0x00 29. "ENA_STATUS_29,Enabled Status for intr_in[29]" "0,1"
newline
bitfld.long 0x00 28. "ENA_STATUS_28,Enabled Status for intr_in[28]" "0,1"
bitfld.long 0x00 27. "ENA_STATUS_27,Enabled Status for intr_in[27]" "0,1"
bitfld.long 0x00 26. "ENA_STATUS_26,Enabled Status for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "ENA_STATUS_25,Enabled Status for intr_in[25]" "0,1"
bitfld.long 0x00 24. "ENA_STATUS_24,Enabled Status for intr_in[24]" "0,1"
bitfld.long 0x00 23. "ENA_STATUS_23,Enabled Status for intr_in[23]" "0,1"
newline
bitfld.long 0x00 22. "ENA_STATUS_22,Enabled Status for intr_in[22]" "0,1"
bitfld.long 0x00 21. "ENA_STATUS_21,Enabled Status for intr_in[21]" "0,1"
bitfld.long 0x00 20. "ENA_STATUS_20,Enabled Status for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENA_STATUS_19,Enabled Status for intr_in[19]" "0,1"
bitfld.long 0x00 18. "ENA_STATUS_18,Enabled Status for intr_in[18]" "0,1"
bitfld.long 0x00 17. "ENA_STATUS_17,Enabled Status for intr_in[17]" "0,1"
newline
bitfld.long 0x00 16. "ENA_STATUS_16,Enabled Status for intr_in[16]" "0,1"
bitfld.long 0x00 15. "ENA_STATUS_15,Enabled Status for intr_in[15]" "0,1"
bitfld.long 0x00 14. "ENA_STATUS_14,Enabled Status for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "ENA_STATUS_13,Enabled Status for intr_in[13]" "0,1"
bitfld.long 0x00 12. "ENA_STATUS_12,Enabled Status for intr_in[12]" "0,1"
bitfld.long 0x00 11. "ENA_STATUS_11,Enabled Status for intr_in[11]" "0,1"
newline
bitfld.long 0x00 10. "ENA_STATUS_10,Enabled Status for intr_in[10]" "0,1"
bitfld.long 0x00 9. "ENA_STATUS_9,Enabled Status for intr_in[9]" "0,1"
bitfld.long 0x00 8. "ENA_STATUS_8,Enabled Status for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENA_STATUS_7,Enabled Status for intr_in[7]" "0,1"
bitfld.long 0x00 6. "ENA_STATUS_6,Enabled Status for intr_in[6]" "0,1"
bitfld.long 0x00 5. "ENA_STATUS_5,Enabled Status for intr_in[5]" "0,1"
newline
bitfld.long 0x00 4. "ENA_STATUS_4,Enabled Status for intr_in[4]" "0,1"
bitfld.long 0x00 3. "ENA_STATUS_3,Enabled Status for intr_in[3]" "0,1"
bitfld.long 0x00 2. "ENA_STATUS_2,Enabled Status for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "ENA_STATUS_1,Enabled Status for intr_in[1]" "0,1"
bitfld.long 0x00 0. "ENA_STATUS_0,Enabled Status for intr_in[0]" "0,1"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x300)++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_REG$1,"
bitfld.long 0x00 31. "ENABLE_31,Enable (set) for intr_in[31]" "0,1"
bitfld.long 0x00 30. "ENABLE_30,Enable (set) for intr_in[30]" "0,1"
bitfld.long 0x00 29. "ENABLE_29,Enable (set) for intr_in[29]" "0,1"
newline
bitfld.long 0x00 28. "ENABLE_28,Enable (set) for intr_in[28]" "0,1"
bitfld.long 0x00 27. "ENABLE_27,Enable (set) for intr_in[27]" "0,1"
bitfld.long 0x00 26. "ENABLE_26,Enable (set) for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_25,Enable (set) for intr_in[25]" "0,1"
bitfld.long 0x00 24. "ENABLE_24,Enable (set) for intr_in[24]" "0,1"
bitfld.long 0x00 23. "ENABLE_23,Enable (set) for intr_in[23]" "0,1"
newline
bitfld.long 0x00 22. "ENABLE_22,Enable (set) for intr_in[22]" "0,1"
bitfld.long 0x00 21. "ENABLE_21,Enable (set) for intr_in[21]" "0,1"
bitfld.long 0x00 20. "ENABLE_20,Enable (set) for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_19,Enable (set) for intr_in[19]" "0,1"
bitfld.long 0x00 18. "ENABLE_18,Enable (set) for intr_in[18]" "0,1"
bitfld.long 0x00 17. "ENABLE_17,Enable (set) for intr_in[17]" "0,1"
newline
bitfld.long 0x00 16. "ENABLE_16,Enable (set) for intr_in[16]" "0,1"
bitfld.long 0x00 15. "ENABLE_15,Enable (set) for intr_in[15]" "0,1"
bitfld.long 0x00 14. "ENABLE_14,Enable (set) for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_13,Enable (set) for intr_in[13]" "0,1"
bitfld.long 0x00 12. "ENABLE_12,Enable (set) for intr_in[12]" "0,1"
bitfld.long 0x00 11. "ENABLE_11,Enable (set) for intr_in[11]" "0,1"
newline
bitfld.long 0x00 10. "ENABLE_10,Enable (set) for intr_in[10]" "0,1"
bitfld.long 0x00 9. "ENABLE_9,Enable (set) for intr_in[9]" "0,1"
bitfld.long 0x00 8. "ENABLE_8,Enable (set) for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_7,Enable (set) for intr_in[7]" "0,1"
bitfld.long 0x00 6. "ENABLE_6,Enable (set) for intr_in[6]" "0,1"
bitfld.long 0x00 5. "ENABLE_5,Enable (set) for intr_in[5]" "0,1"
newline
bitfld.long 0x00 4. "ENABLE_4,Enable (set) for intr_in[4]" "0,1"
bitfld.long 0x00 3. "ENABLE_3,Enable (set) for intr_in[3]" "0,1"
bitfld.long 0x00 2. "ENABLE_2,Enable (set) for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_1,Enable (set) for intr_in[1]" "0,1"
bitfld.long 0x00 0. "ENABLE_0,Enable (set) for intr_in[0]" "0,1"
repeat.end
group.long 0x380++0x07
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG0,"
bitfld.long 0x00 31. "ENABLE_31_CLR,Enable clear for intr_in[31]" "0,1"
bitfld.long 0x00 30. "ENABLE_30_CLR,Enable clear for intr_in[30]" "0,1"
bitfld.long 0x00 29. "ENABLE_29_CLR,Enable clear for intr_in[29]" "0,1"
newline
bitfld.long 0x00 28. "ENABLE_28_CLR,Enable clear for intr_in[28]" "0,1"
bitfld.long 0x00 27. "ENABLE_27_CLR,Enable clear for intr_in[27]" "0,1"
bitfld.long 0x00 26. "ENABLE_26_CLR,Enable clear for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "ENABLE_25_CLR,Enable clear for intr_in[25]" "0,1"
bitfld.long 0x00 24. "ENABLE_24_CLR,Enable clear for intr_in[24]" "0,1"
bitfld.long 0x00 23. "ENABLE_23_CLR,Enable clear for intr_in[23]" "0,1"
newline
bitfld.long 0x00 22. "ENABLE_22_CLR,Enable clear for intr_in[22]" "0,1"
bitfld.long 0x00 21. "ENABLE_21_CLR,Enable clear for intr_in[21]" "0,1"
bitfld.long 0x00 20. "ENABLE_20_CLR,Enable clear for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "ENABLE_19_CLR,Enable clear for intr_in[19]" "0,1"
bitfld.long 0x00 18. "ENABLE_18_CLR,Enable clear for intr_in[18]" "0,1"
bitfld.long 0x00 17. "ENABLE_17_CLR,Enable clear for intr_in[17]" "0,1"
newline
bitfld.long 0x00 16. "ENABLE_16_CLR,Enable clear for intr_in[16]" "0,1"
bitfld.long 0x00 15. "ENABLE_15_CLR,Enable clear for intr_in[15]" "0,1"
bitfld.long 0x00 14. "ENABLE_14_CLR,Enable clear for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "ENABLE_13_CLR,Enable clear for intr_in[13]" "0,1"
bitfld.long 0x00 12. "ENABLE_12_CLR,Enable clear for intr_in[12]" "0,1"
bitfld.long 0x00 11. "ENABLE_11_CLR,Enable clear for intr_in[11]" "0,1"
newline
bitfld.long 0x00 10. "ENABLE_10_CLR,Enable clear for intr_in[10]" "0,1"
bitfld.long 0x00 9. "ENABLE_9_CLR,Enable clear for intr_in[9]" "0,1"
bitfld.long 0x00 8. "ENABLE_8_CLR,Enable clear for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "ENABLE_7_CLR,Enable clear for intr_in[7]" "0,1"
bitfld.long 0x00 6. "ENABLE_6_CLR,Enable clear for intr_in[6]" "0,1"
bitfld.long 0x00 5. "ENABLE_5_CLR,Enable clear for intr_in[5]" "0,1"
newline
bitfld.long 0x00 4. "ENABLE_4_CLR,Enable clear for intr_in[4]" "0,1"
bitfld.long 0x00 3. "ENABLE_3_CLR,Enable clear for intr_in[3]" "0,1"
bitfld.long 0x00 2. "ENABLE_2_CLR,Enable clear for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "ENABLE_1_CLR,Enable clear for intr_in[1]" "0,1"
bitfld.long 0x00 0. "ENABLE_0_CLR,Enable clear for intr_in[0]" "0,1"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_CLR_REG1,"
bitfld.long 0x04 31. "ENABLE_63_CLR,Enable clear for intr_in[63]" "0,1"
bitfld.long 0x04 30. "ENABLE_62_CLR,Enable clear for intr_in[62]" "0,1"
bitfld.long 0x04 29. "ENABLE_61_CLR,Enable clear for intr_in[61]" "0,1"
newline
bitfld.long 0x04 28. "ENABLE_60_CLR,Enable clear for intr_in[60]" "0,1"
bitfld.long 0x04 27. "ENABLE_59_CLR,Enable clear for intr_in[59]" "0,1"
bitfld.long 0x04 26. "ENABLE_58_CLR,Enable clear for intr_in[58]" "0,1"
newline
bitfld.long 0x04 25. "ENABLE_57_CLR,Enable clear for intr_in[57]" "0,1"
bitfld.long 0x04 24. "ENABLE_56_CLR,Enable clear for intr_in[56]" "0,1"
bitfld.long 0x04 23. "ENABLE_55_CLR,Enable clear for intr_in[55]" "0,1"
newline
bitfld.long 0x04 22. "ENABLE_54_CLR,Enable clear for intr_in[54]" "0,1"
bitfld.long 0x04 21. "ENABLE_53_CLR,Enable clear for intr_in[53]" "0,1"
bitfld.long 0x04 20. "ENABLE_52_CLR,Enable clear for intr_in[52]" "0,1"
newline
bitfld.long 0x04 19. "ENABLE_51_CLR,Enable clear for intr_in[51]" "0,1"
bitfld.long 0x04 18. "ENABLE_50_CLR,Enable clear for intr_in[50]" "0,1"
bitfld.long 0x04 17. "ENABLE_49_CLR,Enable clear for intr_in[49]" "0,1"
newline
bitfld.long 0x04 16. "ENABLE_48_CLR,Enable clear for intr_in[48]" "0,1"
bitfld.long 0x04 15. "ENABLE_47_CLR,Enable clear for intr_in[47]" "0,1"
bitfld.long 0x04 14. "ENABLE_46_CLR,Enable clear for intr_in[46]" "0,1"
newline
bitfld.long 0x04 13. "ENABLE_45_CLR,Enable clear for intr_in[45]" "0,1"
bitfld.long 0x04 12. "ENABLE_44_CLR,Enable clear for intr_in[44]" "0,1"
bitfld.long 0x04 11. "ENABLE_43_CLR,Enable clear for intr_in[43]" "0,1"
newline
bitfld.long 0x04 10. "ENABLE_42_CLR,Enable clear for intr_in[42]" "0,1"
bitfld.long 0x04 9. "ENABLE_41_CLR,Enable clear for intr_in[41]" "0,1"
bitfld.long 0x04 8. "ENABLE_40_CLR,Enable clear for intr_in[40]" "0,1"
newline
bitfld.long 0x04 7. "ENABLE_39_CLR,Enable clear for intr_in[39]" "0,1"
bitfld.long 0x04 6. "ENABLE_38_CLR,Enable clear for intr_in[38]" "0,1"
bitfld.long 0x04 5. "ENABLE_37_CLR,Enable clear for intr_in[37]" "0,1"
newline
bitfld.long 0x04 4. "ENABLE_36_CLR,Enable clear for intr_in[36]" "0,1"
bitfld.long 0x04 3. "ENABLE_35_CLR,Enable clear for intr_in[35]" "0,1"
bitfld.long 0x04 2. "ENABLE_34_CLR,Enable clear for intr_in[34]" "0,1"
newline
bitfld.long 0x04 1. "ENABLE_33_CLR,Enable clear for intr_in[33]" "0,1"
bitfld.long 0x04 0. "ENABLE_32_CLR,Enable clear for intr_in[32]" "0,1"
group.long 0x400++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG0,"
bitfld.long 0x00 24.--27. "CH_MAP_3,Interrupt Channel Map for intr_in[3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "CH_MAP_2,Interrupt Channel Map for intr_in[2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "CH_MAP_1,Interrupt Channel Map for intr_in[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "CH_MAP_0,Interrupt Channel Map for intr_in[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 15. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
group.long ($2+0x404)++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_CH_MAP_REG$1,"
bitfld.long 0x00 24.--27. "CH_MAP_7,Interrupt Channel Map for intr_in[7]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "CH_MAP_6,Interrupt Channel Map for intr_in[6]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "CH_MAP_5,Interrupt Channel Map for intr_in[5]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "CH_MAP_4,Interrupt Channel Map for intr_in[4]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0x800)++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG$1,"
bitfld.long 0x00 24.--27. "HINT_MAP_3,Host Interrupt Map for Channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "HINT_MAP_2,Host Interrupt Map for Channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "HINT_MAP_1,Host Interrupt Map for Channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "HINT_MAP_0,Host Interrupt Map for Channel 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
group.long 0x808++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_HINT_MAP_REG2,"
bitfld.long 0x00 8.--11. "HINT_MAP_9,Host Interrupt Map for Channel 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "HINT_MAP_8,Host Interrupt Map for Channel 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x900++0x27
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG0,"
bitfld.long 0x00 31. "NONE_HINT_0,No interrupt pending flag" "0,1"
hexmask.long.word 0x00 0.--9. 1. "PRI_HINT_0,Host Int 0 Prioritized Interrupt"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG1,"
bitfld.long 0x04 31. "NONE_HINT_1,No interrupt pending flag" "0,1"
hexmask.long.word 0x04 0.--9. 1. "PRI_HINT_1,Host Int 1 Prioritized Interrupt"
line.long 0x08 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG2,"
bitfld.long 0x08 31. "NONE_HINT_2,No interrupt pending flag" "0,1"
hexmask.long.word 0x08 0.--9. 1. "PRI_HINT_2,Host Int 2 Prioritized Interrupt"
line.long 0x0C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG3,"
bitfld.long 0x0C 31. "NONE_HINT_3,No interrupt pending flag" "0,1"
hexmask.long.word 0x0C 0.--9. 1. "PRI_HINT_3,Host Int 3 Prioritized Interrupt"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG4,"
bitfld.long 0x10 31. "NONE_HINT_4,No interrupt pending flag" "0,1"
hexmask.long.word 0x10 0.--9. 1. "PRI_HINT_4,Host Int 4 Prioritized Interrupt"
line.long 0x14 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG5,"
bitfld.long 0x14 31. "NONE_HINT_5,No interrupt pending flag" "0,1"
hexmask.long.word 0x14 0.--9. 1. "PRI_HINT_5,Host Int 5 Prioritized Interrupt"
line.long 0x18 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG6,"
bitfld.long 0x18 31. "NONE_HINT_6,No interrupt pending flag" "0,1"
hexmask.long.word 0x18 0.--9. 1. "PRI_HINT_6,Host Int 6 Prioritized Interrupt"
line.long 0x1C "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG7,"
bitfld.long 0x1C 31. "NONE_HINT_7,No interrupt pending flag" "0,1"
hexmask.long.word 0x1C 0.--9. 1. "PRI_HINT_7,Host Int 7 Prioritized Interrupt"
line.long 0x20 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG8,"
bitfld.long 0x20 31. "NONE_HINT_8,No interrupt pending flag" "0,1"
hexmask.long.word 0x20 0.--9. 1. "PRI_HINT_8,Host Int 8 Prioritized Interrupt"
line.long 0x24 "PR1_ICSS_INTC__INTC_SLV__REGS_PRI_HINT_REG9,"
bitfld.long 0x24 31. "NONE_HINT_9,No interrupt pending flag" "0,1"
hexmask.long.word 0x24 0.--9. 1. "PRI_HINT_9,Host Int 9 Prioritized Interrupt"
group.long 0xD00++0x07
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG0,"
bitfld.long 0x00 31. "POLARITY_31,Polarity for intr_in[31]" "0,1"
bitfld.long 0x00 30. "POLARITY_30,Polarity for intr_in[30]" "0,1"
bitfld.long 0x00 29. "POLARITY_29,Polarity for intr_in[29]" "0,1"
newline
bitfld.long 0x00 28. "POLARITY_28,Polarity for intr_in[28]" "0,1"
bitfld.long 0x00 27. "POLARITY_27,Polarity for intr_in[27]" "0,1"
bitfld.long 0x00 26. "POLARITY_26,Polarity for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "POLARITY_25,Polarity for intr_in[25]" "0,1"
bitfld.long 0x00 24. "POLARITY_24,Polarity for intr_in[24]" "0,1"
bitfld.long 0x00 23. "POLARITY_23,Polarity for intr_in[23]" "0,1"
newline
bitfld.long 0x00 22. "POLARITY_22,Polarity for intr_in[22]" "0,1"
bitfld.long 0x00 21. "POLARITY_21,Polarity for intr_in[21]" "0,1"
bitfld.long 0x00 20. "POLARITY_20,Polarity for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "POLARITY_19,Polarity for intr_in[19]" "0,1"
bitfld.long 0x00 18. "POLARITY_18,Polarity for intr_in[18]" "0,1"
bitfld.long 0x00 17. "POLARITY_17,Polarity for intr_in[17]" "0,1"
newline
bitfld.long 0x00 16. "POLARITY_16,Polarity for intr_in[16]" "0,1"
bitfld.long 0x00 15. "POLARITY_15,Polarity for intr_in[15]" "0,1"
bitfld.long 0x00 14. "POLARITY_14,Polarity for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "POLARITY_13,Polarity for intr_in[13]" "0,1"
bitfld.long 0x00 12. "POLARITY_12,Polarity for intr_in[12]" "0,1"
bitfld.long 0x00 11. "POLARITY_11,Polarity for intr_in[11]" "0,1"
newline
bitfld.long 0x00 10. "POLARITY_10,Polarity for intr_in[10]" "0,1"
bitfld.long 0x00 9. "POLARITY_9,Polarity for intr_in[9]" "0,1"
bitfld.long 0x00 8. "POLARITY_8,Polarity for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "POLARITY_7,Polarity for intr_in[7]" "0,1"
bitfld.long 0x00 6. "POLARITY_6,Polarity for intr_in[6]" "0,1"
bitfld.long 0x00 5. "POLARITY_5,Polarity for intr_in[5]" "0,1"
newline
bitfld.long 0x00 4. "POLARITY_4,Polarity for intr_in[4]" "0,1"
bitfld.long 0x00 3. "POLARITY_3,Polarity for intr_in[3]" "0,1"
bitfld.long 0x00 2. "POLARITY_2,Polarity for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "POLARITY_1,Polarity for intr_in[1]" "0,1"
bitfld.long 0x00 0. "POLARITY_0,Polarity for intr_in[0]" "0,1"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_POLARITY_REG1,"
bitfld.long 0x04 31. "POLARITY_63,Polarity for intr_in[63]" "0,1"
bitfld.long 0x04 30. "POLARITY_62,Polarity for intr_in[62]" "0,1"
bitfld.long 0x04 29. "POLARITY_61,Polarity for intr_in[61]" "0,1"
newline
bitfld.long 0x04 28. "POLARITY_60,Polarity for intr_in[60]" "0,1"
bitfld.long 0x04 27. "POLARITY_59,Polarity for intr_in[59]" "0,1"
bitfld.long 0x04 26. "POLARITY_58,Polarity for intr_in[58]" "0,1"
newline
bitfld.long 0x04 25. "POLARITY_57,Polarity for intr_in[57]" "0,1"
bitfld.long 0x04 24. "POLARITY_56,Polarity for intr_in[56]" "0,1"
bitfld.long 0x04 23. "POLARITY_55,Polarity for intr_in[55]" "0,1"
newline
bitfld.long 0x04 22. "POLARITY_54,Polarity for intr_in[54]" "0,1"
bitfld.long 0x04 21. "POLARITY_53,Polarity for intr_in[53]" "0,1"
bitfld.long 0x04 20. "POLARITY_52,Polarity for intr_in[52]" "0,1"
newline
bitfld.long 0x04 19. "POLARITY_51,Polarity for intr_in[51]" "0,1"
bitfld.long 0x04 18. "POLARITY_50,Polarity for intr_in[50]" "0,1"
bitfld.long 0x04 17. "POLARITY_49,Polarity for intr_in[49]" "0,1"
newline
bitfld.long 0x04 16. "POLARITY_48,Polarity for intr_in[48]" "0,1"
bitfld.long 0x04 15. "POLARITY_47,Polarity for intr_in[47]" "0,1"
bitfld.long 0x04 14. "POLARITY_46,Polarity for intr_in[46]" "0,1"
newline
bitfld.long 0x04 13. "POLARITY_45,Polarity for intr_in[45]" "0,1"
bitfld.long 0x04 12. "POLARITY_44,Polarity for intr_in[44]" "0,1"
bitfld.long 0x04 11. "POLARITY_43,Polarity for intr_in[43]" "0,1"
newline
bitfld.long 0x04 10. "POLARITY_42,Polarity for intr_in[42]" "0,1"
bitfld.long 0x04 9. "POLARITY_41,Polarity for intr_in[41]" "0,1"
bitfld.long 0x04 8. "POLARITY_40,Polarity for intr_in[40]" "0,1"
newline
bitfld.long 0x04 7. "POLARITY_39,Polarity for intr_in[39]" "0,1"
bitfld.long 0x04 6. "POLARITY_38,Polarity for intr_in[38]" "0,1"
bitfld.long 0x04 5. "POLARITY_37,Polarity for intr_in[37]" "0,1"
newline
bitfld.long 0x04 4. "POLARITY_36,Polarity for intr_in[36]" "0,1"
bitfld.long 0x04 3. "POLARITY_35,Polarity for intr_in[35]" "0,1"
bitfld.long 0x04 2. "POLARITY_34,Polarity for intr_in[34]" "0,1"
newline
bitfld.long 0x04 1. "POLARITY_33,Polarity for intr_in[33]" "0,1"
bitfld.long 0x04 0. "POLARITY_32,Polarity for intr_in[32]" "0,1"
group.long 0xD80++0x07
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG0,"
bitfld.long 0x00 31. "TYPE_31,Type for intr_in[31]" "0,1"
bitfld.long 0x00 30. "TYPE_30,Type for intr_in[30]" "0,1"
bitfld.long 0x00 29. "TYPE_29,Type for intr_in[29]" "0,1"
newline
bitfld.long 0x00 28. "TYPE_28,Type for intr_in[28]" "0,1"
bitfld.long 0x00 27. "TYPE_27,Type for intr_in[27]" "0,1"
bitfld.long 0x00 26. "TYPE_26,Type for intr_in[26]" "0,1"
newline
bitfld.long 0x00 25. "TYPE_25,Type for intr_in[25]" "0,1"
bitfld.long 0x00 24. "TYPE_24,Type for intr_in[24]" "0,1"
bitfld.long 0x00 23. "TYPE_23,Type for intr_in[23]" "0,1"
newline
bitfld.long 0x00 22. "TYPE_22,Type for intr_in[22]" "0,1"
bitfld.long 0x00 21. "TYPE_21,Type for intr_in[21]" "0,1"
bitfld.long 0x00 20. "TYPE_20,Type for intr_in[20]" "0,1"
newline
bitfld.long 0x00 19. "TYPE_19,Type for intr_in[19]" "0,1"
bitfld.long 0x00 18. "TYPE_18,Type for intr_in[18]" "0,1"
bitfld.long 0x00 17. "TYPE_17,Type for intr_in[17]" "0,1"
newline
bitfld.long 0x00 16. "TYPE_16,Type for intr_in[16]" "0,1"
bitfld.long 0x00 15. "TYPE_15,Type for intr_in[15]" "0,1"
bitfld.long 0x00 14. "TYPE_14,Type for intr_in[14]" "0,1"
newline
bitfld.long 0x00 13. "TYPE_13,Type for intr_in[13]" "0,1"
bitfld.long 0x00 12. "TYPE_12,Type for intr_in[12]" "0,1"
bitfld.long 0x00 11. "TYPE_11,Type for intr_in[11]" "0,1"
newline
bitfld.long 0x00 10. "TYPE_10,Type for intr_in[10]" "0,1"
bitfld.long 0x00 9. "TYPE_9,Type for intr_in[9]" "0,1"
bitfld.long 0x00 8. "TYPE_8,Type for intr_in[8]" "0,1"
newline
bitfld.long 0x00 7. "TYPE_7,Type for intr_in[7]" "0,1"
bitfld.long 0x00 6. "TYPE_6,Type for intr_in[6]" "0,1"
bitfld.long 0x00 5. "TYPE_5,Type for intr_in[5]" "0,1"
newline
bitfld.long 0x00 4. "TYPE_4,Type for intr_in[4]" "0,1"
bitfld.long 0x00 3. "TYPE_3,Type for intr_in[3]" "0,1"
bitfld.long 0x00 2. "TYPE_2,Type for intr_in[2]" "0,1"
newline
bitfld.long 0x00 1. "TYPE_1,Type for intr_in[1]" "0,1"
bitfld.long 0x00 0. "TYPE_0,Type for intr_in[0]" "0,1"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_TYPE_REG1,"
bitfld.long 0x04 31. "TYPE_63,Type for intr_in[63]" "0,1"
bitfld.long 0x04 30. "TYPE_62,Type for intr_in[62]" "0,1"
bitfld.long 0x04 29. "TYPE_61,Type for intr_in[61]" "0,1"
newline
bitfld.long 0x04 28. "TYPE_60,Type for intr_in[60]" "0,1"
bitfld.long 0x04 27. "TYPE_59,Type for intr_in[59]" "0,1"
bitfld.long 0x04 26. "TYPE_58,Type for intr_in[58]" "0,1"
newline
bitfld.long 0x04 25. "TYPE_57,Type for intr_in[57]" "0,1"
bitfld.long 0x04 24. "TYPE_56,Type for intr_in[56]" "0,1"
bitfld.long 0x04 23. "TYPE_55,Type for intr_in[55]" "0,1"
newline
bitfld.long 0x04 22. "TYPE_54,Type for intr_in[54]" "0,1"
bitfld.long 0x04 21. "TYPE_53,Type for intr_in[53]" "0,1"
bitfld.long 0x04 20. "TYPE_52,Type for intr_in[52]" "0,1"
newline
bitfld.long 0x04 19. "TYPE_51,Type for intr_in[51]" "0,1"
bitfld.long 0x04 18. "TYPE_50,Type for intr_in[50]" "0,1"
bitfld.long 0x04 17. "TYPE_49,Type for intr_in[49]" "0,1"
newline
bitfld.long 0x04 16. "TYPE_48,Type for intr_in[48]" "0,1"
bitfld.long 0x04 15. "TYPE_47,Type for intr_in[47]" "0,1"
bitfld.long 0x04 14. "TYPE_46,Type for intr_in[46]" "0,1"
newline
bitfld.long 0x04 13. "TYPE_45,Type for intr_in[45]" "0,1"
bitfld.long 0x04 12. "TYPE_44,Type for intr_in[44]" "0,1"
bitfld.long 0x04 11. "TYPE_43,Type for intr_in[43]" "0,1"
newline
bitfld.long 0x04 10. "TYPE_42,Type for intr_in[42]" "0,1"
bitfld.long 0x04 9. "TYPE_41,Type for intr_in[41]" "0,1"
bitfld.long 0x04 8. "TYPE_40,Type for intr_in[40]" "0,1"
newline
bitfld.long 0x04 7. "TYPE_39,Type for intr_in[39]" "0,1"
bitfld.long 0x04 6. "TYPE_38,Type for intr_in[38]" "0,1"
bitfld.long 0x04 5. "TYPE_37,Type for intr_in[37]" "0,1"
newline
bitfld.long 0x04 4. "TYPE_36,Type for intr_in[36]" "0,1"
bitfld.long 0x04 3. "TYPE_35,Type for intr_in[35]" "0,1"
bitfld.long 0x04 2. "TYPE_34,Type for intr_in[34]" "0,1"
newline
bitfld.long 0x04 1. "TYPE_33,Type for intr_in[33]" "0,1"
bitfld.long 0x04 0. "TYPE_32,Type for intr_in[32]" "0,1"
group.long 0x1100++0x27
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG0,"
bitfld.long 0x00 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x00 0.--8. 1. "NEST_HINT_0,Host Int 0 Nesting Level"
line.long 0x04 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG1,"
bitfld.long 0x04 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x04 0.--8. 1. "NEST_HINT_1,Host Int 1 Nesting Level"
line.long 0x08 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG2,"
bitfld.long 0x08 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x08 0.--8. 1. "NEST_HINT_2,Host Int 2 Nesting Level"
line.long 0x0C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG3,"
bitfld.long 0x0C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x0C 0.--8. 1. "NEST_HINT_3,Host Int 3 Nesting Level"
line.long 0x10 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG4,"
bitfld.long 0x10 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x10 0.--8. 1. "NEST_HINT_4,Host Int 4 Nesting Level"
line.long 0x14 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG5,"
bitfld.long 0x14 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x14 0.--8. 1. "NEST_HINT_5,Host Int 5 Nesting Level"
line.long 0x18 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG6,"
bitfld.long 0x18 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x18 0.--8. 1. "NEST_HINT_6,Host Int 6 Nesting Level"
line.long 0x1C "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG7,"
bitfld.long 0x1C 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x1C 0.--8. 1. "NEST_HINT_7,Host Int 7 Nesting Level"
line.long 0x20 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG8,"
bitfld.long 0x20 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x20 0.--8. 1. "NEST_HINT_8,Host Int 8 Nesting Level"
line.long 0x24 "PR1_ICSS_INTC__INTC_SLV__REGS_NEST_LEVEL_REG9,"
bitfld.long 0x24 31. "NEST_AUTO_OVR,Nesting Level Override Automatic" "0,1"
hexmask.long.word 0x24 0.--8. 1. "NEST_HINT_9,Host Int 9 Nesting Level"
group.long 0x1500++0x03
line.long 0x00 "PR1_ICSS_INTC__INTC_SLV__REGS_ENABLE_HINT_REG0,"
bitfld.long 0x00 9. "ENABLE_HINT_9,Enable for Host Int 9" "0,1"
bitfld.long 0x00 8. "ENABLE_HINT_8,Enable for Host Int 8" "0,1"
bitfld.long 0x00 7. "ENABLE_HINT_7,Enable for Host Int 7" "0,1"
newline
bitfld.long 0x00 6. "ENABLE_HINT_6,Enable for Host Int 6" "0,1"
bitfld.long 0x00 5. "ENABLE_HINT_5,Enable for Host Int 5" "0,1"
bitfld.long 0x00 4. "ENABLE_HINT_4,Enable for Host Int 4" "0,1"
newline
bitfld.long 0x00 3. "ENABLE_HINT_3,Enable for Host Int 3" "0,1"
bitfld.long 0x00 2. "ENABLE_HINT_2,Enable for Host Int 2" "0,1"
bitfld.long 0x00 1. "ENABLE_HINT_1,Enable for Host Int 1" "0,1"
newline
bitfld.long 0x00 0. "ENABLE_HINT_0,Enable for Host Int 0" "0,1"
tree.end
tree "ICSSM0_PR1_ICSS_UART_UART_SLV"
base ad:0x28000
group.long 0x00++0x2B
line.long 0x00 "PR1_ICSS_UART__UART_SLV__REGS_RBR_TBR,RBR_TBR Registers"
hexmask.long.word 0x00 8.--17. 1. "TBR_DATA,Transmit Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. "RBR_DATA,Receive Buffer Register"
line.long 0x04 "PR1_ICSS_UART__UART_SLV__REGS_INT_EN,UART Interrupt Enable Register"
bitfld.long 0x04 3. "EDSSI,Enable for Modem Status Interrupt" "0,1"
bitfld.long 0x04 2. "ELSI,Enable for Receiver Line Status Interrupt" "0,1"
bitfld.long 0x04 1. "ETBEI,Enable for Transmitter Holding Register Empty Interrupt" "0,1"
bitfld.long 0x04 0. "ERBI,Enable for Receiver Data Available Interrupt" "0,1"
line.long 0x08 "PR1_ICSS_UART__UART_SLV__REGS_INT_FIFO,Interrupt Identification Register / FIFO Control Register"
bitfld.long 0x08 14.--15. "FCR_RXFIFTL,Receiver Trigger Level" "0,1,2,3"
bitfld.long 0x08 11. "FCR_DMAMODE1,DMA Mode Select" "0,1"
bitfld.long 0x08 10. "FCR_TXCLR,Transmitter FIFO Reset" "0,1"
bitfld.long 0x08 9. "FCR_RXCLR,Receiver FIFO Reset" "0,1"
bitfld.long 0x08 8. "FCR_FIFOEN,FIFO Enable Register" "0,1"
rbitfld.long 0x08 6.--7. "IIR_FIFOEN,FIFOs enabled" "0,1,2,3"
newline
rbitfld.long 0x08 1.--3. "IIR_INTID,Interrupt Type" "0,1,2,3,4,5,6,7"
rbitfld.long 0x08 0. "IIR_IPEND,Receiver Data Available Interrupt Pending" "0,1"
line.long 0x0C "PR1_ICSS_UART__UART_SLV__REGS_LCTR,Line Control Register"
bitfld.long 0x0C 7. "DLAB,Divisor Latch Access Bit" "0,1"
bitfld.long 0x0C 6. "BC,Break Control" "0,1"
bitfld.long 0x0C 5. "SP,Stick Parity" "0,1"
bitfld.long 0x0C 4. "EPS,Even Parity Select" "0,1"
bitfld.long 0x0C 3. "PEN,Parity Enable" "0,1"
bitfld.long 0x0C 2. "STB,Number of Stop Bits" "0,1"
newline
bitfld.long 0x0C 1. "WLS1,Word Length Select Bit 1" "0,1"
bitfld.long 0x0C 0. "WLS0,Word Length Select Bit 0" "0,1"
line.long 0x10 "PR1_ICSS_UART__UART_SLV__REGS_MCTR,Modem Control Register"
bitfld.long 0x10 5. "AFE,Autoflow Control Enable" "0,1"
bitfld.long 0x10 4. "LOOP,LOOP Bit" "0,1"
bitfld.long 0x10 3. "OUT2,Out2 Bit" "0,1"
bitfld.long 0x10 2. "OUT1,Out1 Bit" "0,1"
bitfld.long 0x10 1. "RTS,Ready to Send" "0,1"
bitfld.long 0x10 0. "DTR,Data Terminal Ready" "0,1"
line.long 0x14 "PR1_ICSS_UART__UART_SLV__REGS_LSR1,Line Status Register1"
bitfld.long 0x14 7. "RXFIFOE,Receiver FIFO Error" "0,1"
bitfld.long 0x14 6. "TEMT,Transmitter Empty" "0,1"
bitfld.long 0x14 5. "THRE,Transmitter Holding Register" "0,1"
bitfld.long 0x14 4. "BI,Break Interrupt" "0,1"
bitfld.long 0x14 3. "FE,Framing Error" "0,1"
bitfld.long 0x14 2. "PE,Parity Error" "0,1"
newline
bitfld.long 0x14 1. "OE,Overrun Error" "0,1"
bitfld.long 0x14 0. "DR,Data Ready" "0,1"
line.long 0x18 "PR1_ICSS_UART__UART_SLV__REGS_MSR,Modem Status Register"
bitfld.long 0x18 7. "CD,Carrier Detect" "0,1"
bitfld.long 0x18 6. "RI,Ring Indicator" "0,1"
bitfld.long 0x18 5. "DSR,Data Set Ready" "0,1"
bitfld.long 0x18 4. "CTS,Clear To Send" "0,1"
bitfld.long 0x18 3. "DCD,Delta Carrier Detect" "0,1"
bitfld.long 0x18 2. "TERI,Trailing Edge Ring Indicator" "0,1"
newline
bitfld.long 0x18 1. "DDSR,Delta Set Ready" "0,1"
bitfld.long 0x18 0. "DCTS,Delta Clear To Send" "0,1"
line.long 0x1C "PR1_ICSS_UART__UART_SLV__REGS_SCRATCH,UART Scratch Register"
hexmask.long.byte 0x1C 0.--7. 1. "DATA,Scratch Register Bits"
line.long 0x20 "PR1_ICSS_UART__UART_SLV__REGS_DIVLSB,UART Divisor Register"
hexmask.long.byte 0x20 0.--7. 1. "DLL,Divisor Latch [LSB]"
line.long 0x24 "PR1_ICSS_UART__UART_SLV__REGS_DIVMSB,UART Divisor Register"
hexmask.long.byte 0x24 0.--7. 1. "DLH,Divisor Latch [MSB]"
line.long 0x28 "PR1_ICSS_UART__UART_SLV__REGS_PID,Peripheral ID Register"
group.long 0x30++0x07
line.long 0x00 "PR1_ICSS_UART__UART_SLV__REGS_PWR,UART PowerManagement and Emulation Register"
bitfld.long 0x00 15. "URST,UART Reset Bit" "0,1"
bitfld.long 0x00 14. "UTRST,UART Transmitter Reset Bit" "0,1"
bitfld.long 0x00 13. "URRST,UART Receiver Reset Bit" "0,1"
rbitfld.long 0x00 1. "RES,Free Bit" "0,1"
bitfld.long 0x00 0. "FREE,Free Bit" "0,1"
line.long 0x04 "PR1_ICSS_UART__UART_SLV__REGS_MODE,UART Mode Definition Register"
bitfld.long 0x04 0. "OSM_SEL,Oversampling Mode Select" "0,1"
tree.end
tree "ICSSM0_PR1_MDIO_V1P7_MDIO"
base ad:0x32400
rgroup.long 0x00++0x47
line.long 0x00 "PR1_MDIO_V1P7__MDIO__REGS_MDIO_VERSION_REG,version_reg"
hexmask.long.word 0x00 16.--31. 1. "MODID,Module ID"
hexmask.long.byte 0x00 8.--15. 1. "REVMAJ,Major revision value"
hexmask.long.byte 0x00 0.--7. 1. "REVMINOR,Minor revision value"
line.long 0x04 "PR1_MDIO_V1P7__MDIO__REGS_CONTROL_REG,control_reg"
rbitfld.long 0x04 31. "IDLE,MDIO state machine idle" "0,1"
bitfld.long 0x04 30. "ENABLE,Enable control" "0,1"
rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "0,1"
bitfld.long 0x04 19. "FAULT,Fault indicator" "0,1"
bitfld.long 0x04 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
newline
bitfld.long 0x04 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock divider"
line.long 0x08 "PR1_MDIO_V1P7__MDIO__REGS_ALIVE_REG,alive_reg"
line.long 0x0C "PR1_MDIO_V1P7__MDIO__REGS_LINK_REG,link_reg"
line.long 0x10 "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_RAW_REG,link_int_raw_reg"
bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
line.long 0x14 "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_MASKED_REG,link_int_masked_reg"
bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
line.long 0x18 "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_MASK_SET_REG,link_int_mask_set_reg"
bitfld.long 0x18 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1"
line.long 0x1C "PR1_MDIO_V1P7__MDIO__REGS_LINK_INT_MASK_CLEAR_REG,link_int_mask_clear_reg"
bitfld.long 0x1C 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1"
line.long 0x20 "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_RAW_REG,user_int_raw_reg"
bitfld.long 0x20 0.--1. "USERINTRAW,User interrupt raw" "0,1,2,3"
line.long 0x24 "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_MASKED_REG,user_int_masked_reg"
bitfld.long 0x24 0.--1. "USERINTMASKED,User interrupt masked" "0,1,2,3"
line.long 0x28 "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_MASK_SET_REG,user_int_mask_set_reg"
bitfld.long 0x28 0.--1. "USERINTMASKSET,MDIO user interrupt mask set" "0,1,2,3"
line.long 0x2C "PR1_MDIO_V1P7__MDIO__REGS_USER_INT_MASK_CLEAR_REG,user_int_mask_clear_reg"
bitfld.long 0x2C 0.--1. "USERINTMASKCLR,MDIO user interrupt mask clear" "0,1,2,3"
line.long 0x30 "PR1_MDIO_V1P7__MDIO__REGS_MANUAL_IF_REG,manual_if_reg"
bitfld.long 0x30 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1"
bitfld.long 0x30 1. "MDIO_OE,MDIO Output Enable" "0,1"
bitfld.long 0x30 0. "MDIO_PIN,MDIO Pin" "0,1"
line.long 0x34 "PR1_MDIO_V1P7__MDIO__REGS_POLL_REG,poll_reg"
bitfld.long 0x34 31. "MANUALMODE,MDIO Manual Mode" "0,1"
bitfld.long 0x34 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1"
hexmask.long.byte 0x34 0.--7. 1. "IPG,MDIO IPG"
line.long 0x38 "PR1_MDIO_V1P7__MDIO__REGS_POLL_EN_REG,poll_en_reg"
line.long 0x3C "PR1_MDIO_V1P7__MDIO__REGS_CLAUS45_REG,"
line.long 0x40 "PR1_MDIO_V1P7__MDIO__REGS_USER_ADDR0_REG,MDIO USER Address 0"
hexmask.long.word 0x40 0.--15. 1. "USER_ADDR0,MDIO USER Address 0"
line.long 0x44 "PR1_MDIO_V1P7__MDIO__REGS_USER_ADDR1_REG,MDIO USER Address 1"
hexmask.long.word 0x44 0.--15. 1. "USER_ADDR1,MDIO USER Address 1"
group.long 0x80++0x07
line.long 0x00 "PR1_MDIO_V1P7__MDIO__REGS_USER_ACCESS_REG,user_access_reg"
bitfld.long 0x00 31. "GO,Go" "0,1"
bitfld.long 0x00 30. "WRITE," "0,1"
bitfld.long 0x00 29. "ACK,Acknowledge" "0,1"
newline
bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "DATA,User data"
line.long 0x04 "PR1_MDIO_V1P7__MDIO__REGS_USER_PHY_SEL_REG,user_phy_sel_reg"
bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1"
bitfld.long 0x04 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
bitfld.long 0x04 0.--4. "PHYADR_MON,PHY address whose link status is monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "ICSSM0_PR1_MII_RT_PR1_MII_RT_CFG"
base ad:0x32000
group.long 0x00++0x07
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rxcfg0,MIIRXCFG0Register"
bitfld.long 0x00 9. "RX_EOF_SCLR_DIS0," "0,1"
bitfld.long 0x00 8. "RX_ERR_RAW0," "0,1"
bitfld.long 0x00 7. "RX_SFD_RAW0," "0,1"
bitfld.long 0x00 6. "RX_AUTO_FWD_PRE0," "0,1"
newline
bitfld.long 0x00 5. "RX_BYTE_SWAP0," "0,1"
bitfld.long 0x00 4. "RX_L2_EN0," "0,1"
bitfld.long 0x00 3. "RX_MUX_SEL0," "0,1"
bitfld.long 0x00 2. "RX_CUT_PREAMBLE0," "0,1"
newline
bitfld.long 0x00 1. "RX_DATA_RDY_MODE_DIS0," "0,1"
bitfld.long 0x00 0. "RX_ENABLE0," "0,1"
line.long 0x04 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rxcfg1,MIIRXCFG1Register"
bitfld.long 0x04 9. "RX_EOF_SCLR_DIS1," "0,1"
bitfld.long 0x04 8. "RX_ERR_RAW1," "0,1"
bitfld.long 0x04 7. "RX_SFD_RAW1," "0,1"
bitfld.long 0x04 6. "RX_AUTO_FWD_PRE1," "0,1"
newline
bitfld.long 0x04 5. "RX_BYTE_SWAP1," "0,1"
bitfld.long 0x04 4. "RX_L2_EN1," "0,1"
bitfld.long 0x04 3. "RX_MUX_SEL1," "0,1"
bitfld.long 0x04 2. "RX_CUT_PREAMBLE1," "0,1"
newline
bitfld.long 0x04 1. "RX_DATA_RDY_MODE_DIS1," "0,1"
bitfld.long 0x04 0. "RX_ENABLE1," "0,1"
group.long 0x10++0x07
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_txcfg0,MIITXCFG0Register"
bitfld.long 0x00 28.--30. "TX_CLK_DELAY0," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--25. 1. "TX_START_DELAY0,"
bitfld.long 0x00 12. "TX_IPG_WIRE_CLK_EN0," "0,1"
bitfld.long 0x00 11. "TX_32_MODE_EN0," "0,1"
newline
bitfld.long 0x00 10. "PRE_TX_AUTO_ESC_ERR0," "0,1"
bitfld.long 0x00 9. "PRE_TX_AUTO_SEQUENCE0," "0,1"
bitfld.long 0x00 8. "TX_MUX_SEL0," "0,1"
bitfld.long 0x00 3. "TX_BYTE_SWAP0," "0,1"
newline
bitfld.long 0x00 2. "TX_EN_MODE0," "0,1"
bitfld.long 0x00 1. "TX_AUTO_PREAMBLE0," "0,1"
bitfld.long 0x00 0. "TX_ENABLE0," "0,1"
line.long 0x04 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_txcfg1,MIITXCFG1Register"
bitfld.long 0x04 28.--30. "TX_CLK_DELAY1," "0,1,2,3,4,5,6,7"
hexmask.long.word 0x04 16.--25. 1. "TX_START_DELAY1,"
bitfld.long 0x04 12. "TX_IPG_WIRE_CLK_EN1," "0,1"
bitfld.long 0x04 11. "TX_32_MODE_EN1," "0,1"
newline
bitfld.long 0x04 10. "PRE_TX_AUTO_ESC_ERR1," "0,1"
bitfld.long 0x04 9. "PRE_TX_AUTO_SEQUENCE1," "0,1"
bitfld.long 0x04 8. "TX_MUX_SEL1," "0,1"
bitfld.long 0x04 3. "TX_BYTE_SWAP1," "0,1"
newline
bitfld.long 0x04 2. "TX_EN_MODE1," "0,1"
bitfld.long 0x04 1. "TX_AUTO_PREAMBLE1," "0,1"
bitfld.long 0x04 0. "TX_ENABLE1," "0,1"
rgroup.long 0x20++0x07
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_crc0,MIITXCRC0Register"
line.long 0x04 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_crc1,MIITXCRC1Register"
group.long 0x30++0x27
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_ipg0,MIITXIPG0Register"
hexmask.long.word 0x00 0.--15. 1. "TX_IPG0,Transmit IPG"
line.long 0x04 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_ipg1,MIITXIPG1Register"
hexmask.long.word 0x04 0.--15. 1. "TX_IPG1,Transmit IPG"
line.long 0x08 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_prs0,MIIPortStatus0Register"
bitfld.long 0x08 1. "SYNC_PORT0_CRS,sync_port0_crs" "0,1"
bitfld.long 0x08 0. "SYNC_PORT0_COL,sync_port0_col" "0,1"
line.long 0x0C "PR1_MII_RT__PR1_MII_RT_CFG__REGS_prs1,MIIPortStatus1Register"
bitfld.long 0x0C 1. "SYNC_PORT1_CRS,sync_port1_crs" "0,1"
bitfld.long 0x0C 0. "SYNC_PORT1_COL,sync_port1_col" "0,1"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_frms0,MIIRXFRMS0Register"
hexmask.long.word 0x10 16.--31. 1. "RX_MAX_FRM0,rx_max_frm0"
hexmask.long.word 0x10 0.--15. 1. "RX_MIN_FRM0,rx_min_frm0"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_frms1,MIIRXFRMS1Register"
hexmask.long.word 0x14 16.--31. 1. "RX_MAX_FRM1,rx_max_frm1"
hexmask.long.word 0x14 0.--15. 1. "RX_MIN_FRM1,rx_min_frm1"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_pcnt0,MIIRXPCNT0Register"
bitfld.long 0x18 4.--8. "RX_MAX_PCNT0,rx_max_pcnt0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x18 0.--3. "RX_MIN_PCNT0,rx_min_pcnt0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_pcnt1,MIIRXPCNT1Register"
bitfld.long 0x1C 4.--8. "RX_MAX_PCNT1,rx_max_pcnt1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x1C 0.--3. "RX_MIN_PCNT1,rx_min_pcnt1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_err0,MIIRXERR0Register"
bitfld.long 0x20 3. "RX_MAX_FRM_ERR0,rx_max_frm_err0" "0,1"
bitfld.long 0x20 2. "RX_MIN_FRM_ERR0,rx_min_frm_err0" "0,1"
bitfld.long 0x20 1. "RX_MAX_PCNT_ERR0,rx_max_pcnt_err0" "0,1"
bitfld.long 0x20 0. "RX_MIN_PCNT_ERR0,rx_min_pcnt_err0" "0,1"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_err1,MIIRXERR1Register"
bitfld.long 0x24 3. "RX_MAX_FRM_ERR1,rx_max_frm_err1" "0,1"
bitfld.long 0x24 2. "RX_MIN_FRM_ERR1,rx_min_frm_err1" "0,1"
bitfld.long 0x24 1. "RX_MAX_PCNT_ERR1,rx_max_pcnt_err1" "0,1"
bitfld.long 0x24 0. "RX_MIN_PCNT_ERR1,rx_min_pcnt_err1" "0,1"
rgroup.long 0x60++0x0F
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_fifo_level0,MIIRXFIFOLEVEL0Register"
hexmask.long.byte 0x00 0.--7. 1. "RX_FIFO_LEVEL0,rx_fifo_level0"
line.long 0x04 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_rx_fifo_level1,MIIRXFIFOLEVEL1Register"
hexmask.long.byte 0x04 0.--7. 1. "RX_FIFO_LEVEL1,rx_fifo_level1"
line.long 0x08 "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_fifo_level0,MIIRXFIFOLEVEL0Register"
hexmask.long.byte 0x08 0.--7. 1. "TX_FIFO_LEVEL0,tx_fifo_level0"
line.long 0x0C "PR1_MII_RT__PR1_MII_RT_CFG__REGS_tx_fifo_level1,MIIRXFIFOLEVEL1Register"
hexmask.long.byte 0x0C 0.--7. 1. "TX_FIFO_LEVEL1,tx_fifo_level1"
tree.end
tree "ICSSM0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G"
base ad:0x33000
group.long 0x00++0x13
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_icss_g_cfg,ICSS_G Ethernet Cfg"
bitfld.long 0x00 10. "RX_SFD_TX_SOF_EN,Enable the remaping of tx_sof to rx_sfd if auto fwd is enable" "0,1"
bitfld.long 0x00 5.--6. "MII1_MODE,MII1 MODE" "MII,RGMII,SGMII,?..."
bitfld.long 0x00 3.--4. "MII0_MODE,MII0 MODE" "MII,RGMII,SGMII,?..."
newline
bitfld.long 0x00 2. "RX_L2_G_EN,Enable the RX L2 G features of filter frags of size TBD and backpressure RX L2" "Disabled,Enabled"
bitfld.long 0x00 1. "TX_L2_EN,Enable the TX L2 Fifo" "Disabled,Enabled"
bitfld.long 0x00 0. "TX_L1_EN,Enable the TX L1 Fifo" "Disabled,Enabled"
line.long 0x04 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_preempt_cfg,"
hexmask.long.byte 0x04 24.--31. 1. "SMD_R,Response frame TAG"
hexmask.long.byte 0x04 16.--23. 1. "SMD_V,Verification frame TAG"
hexmask.long.byte 0x04 8.--15. 1. "EXP_SMD,None preemptable frame start or express frame"
line.long 0x08 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_smdt1s_cfg,"
hexmask.long.byte 0x08 24.--31. 1. "SMDT1S_3,SMDT1S3 pattern"
hexmask.long.byte 0x08 16.--23. 1. "SMDT1S_2,SMDT1S2 pattern"
hexmask.long.byte 0x08 8.--15. 1. "SMDT1S_1,SMDT1S1 pattern"
newline
hexmask.long.byte 0x08 0.--7. 1. "SMDT1S_0,SMDT1S0 pattern"
line.long 0x0C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_smdt1c_cfg,"
hexmask.long.byte 0x0C 24.--31. 1. "SMDT1C_3,SMDT1C3 pattern"
hexmask.long.byte 0x0C 16.--23. 1. "SMDT1C_2,SMDT1C2 pattern"
hexmask.long.byte 0x0C 8.--15. 1. "SMDT1C_1,SMDT1C1 pattern"
newline
hexmask.long.byte 0x0C 0.--7. 1. "SMDT1C_0,SMDT1C0 pattern"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_pool_ptr_cfg,"
hexmask.long.word 0x10 0.--15. 1. "MAX_PKT_SIZE,Max Pkt Size used in pool ptr logic for wrap around"
hgroup.long 0x14++0x03
hide.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_tx_early_eof,"
group.long 0x18++0x03
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_frag_cnt_cfg,"
hexmask.long.byte 0x00 24.--31. 1. "FRAG_CNT_3,FRAG Cnt3 pattern"
hexmask.long.byte 0x00 16.--23. 1. "FRAG_CNT_2,FRAG Cnt2 pattern"
hexmask.long.byte 0x00 8.--15. 1. "FRAG_CNT_1,FRAG Cnt1 pattern"
newline
hexmask.long.byte 0x00 0.--7. 1. "FRAG_CNT_0,FRAG Cnt0 pattern"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xD00)++0x03
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue$1,"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_H_PTR0,Queue 0"
repeat.end
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0xD40)++0x03
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue$1,"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_H_PTR16,Queue 16"
repeat.end
rgroup.long 0xE00++0x3F
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek0,"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_H_PEEK_PTR0,Queue 0 Peek portal"
line.long 0x04 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek1,"
hexmask.long.word 0x04 0.--15. 1. "QUEUE_H_PEEK_PTR1,Queue 1 Peek portal"
line.long 0x08 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek2,"
hexmask.long.word 0x08 0.--15. 1. "QUEUE_H_PEEK_PTR2,Queue 2 Peek portal"
line.long 0x0C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek3,"
hexmask.long.word 0x0C 0.--15. 1. "QUEUE_H_PEEK_PTR3,Queue 3 Peek portal"
line.long 0x10 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek4,"
hexmask.long.word 0x10 0.--15. 1. "QUEUE_H_PEEK_PTR4,Queue 4 Peek portal"
line.long 0x14 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek5,"
hexmask.long.word 0x14 0.--15. 1. "QUEUE_H_PEEK_PTR5,Queue 5 Peek portal"
line.long 0x18 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek6,"
hexmask.long.word 0x18 0.--15. 1. "QUEUE_H_PEEK_PTR6,Queue 6 Peek portal"
line.long 0x1C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek7,"
hexmask.long.word 0x1C 0.--15. 1. "QUEUE_H_PEEK_PTR7,Queue 7 Peek portal"
line.long 0x20 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek8,"
hexmask.long.word 0x20 0.--15. 1. "QUEUE_H_PEEK_PTR8,Queue 8 Peek portal"
line.long 0x24 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek9,"
hexmask.long.word 0x24 0.--15. 1. "QUEUE_H_PEEK_PTR9,Queue 9 Peek portal"
line.long 0x28 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek10,"
hexmask.long.word 0x28 0.--15. 1. "QUEUE_H_PEEK_PTR10,Queue 10 Peek portal"
line.long 0x2C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek11,"
hexmask.long.word 0x2C 0.--15. 1. "QUEUE_H_PEEK_PTR11,Queue 11 Peek portal"
line.long 0x30 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek12,"
hexmask.long.word 0x30 0.--15. 1. "QUEUE_H_PEEK_PTR12,Queue 12 Peek portal"
line.long 0x34 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek13,"
hexmask.long.word 0x34 0.--15. 1. "QUEUE_H_PEEK_PTR13,Queue 13 Peek portal"
line.long 0x38 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek14,"
hexmask.long.word 0x38 0.--15. 1. "QUEUE_H_PEEK_PTR14,Queue 14 Peek portal"
line.long 0x3C "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_peek15,"
hexmask.long.word 0x3C 0.--15. 1. "QUEUE_H_PEEK_PTR15,Queue 15 Peek portal"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0xE40)++0x03
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt$1,"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_CNT_ENTRIES_0,Queue Entry Count0"
repeat.end
repeat 16. (list 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0xE80)++0x03
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_cnt$1,"
hexmask.long.word 0x00 0.--15. 1. "QUEUE_CNT_ENTRIES_16,Queue Entry Count16"
repeat.end
group.long 0xF40++0x03
line.long 0x00 "PR1_MII_RT__PR1_MII_RT_G_CFG__REGS_G_queue_reset,"
bitfld.long 0x00 0.--5. "RESET_QUEUE_ID,Reset Queue ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "ICSSM0_PR1_PROT_SLV"
base ad:0x24C00
group.long 0x00++0x07
line.long 0x00 "PR1_PROTECT__SLV__REGS_unlock_key,"
line.long 0x04 "PR1_PROTECT__SLV__REGS_cfg,Config"
bitfld.long 0x04 6. "PRU1_DMEM1_LOCK_EN,Write Protect DMEM1" "disable,enable When enabled.."
bitfld.long 0x04 5. "PRU0_DMEM0_LOCK_EN,Write Protect DMEM0" "disable,enable When enabled.."
bitfld.long 0x04 4. "ICSS_CFG_WP_EN,Write Protect ICSS_CFG" "disable,enable"
newline
bitfld.long 0x04 3. "RTU1_PRU_WP_EN,Write Protect RTU1_PRU access Debug IMEM" "disable,enable"
bitfld.long 0x04 2. "RTU0_PRU_WP_EN,Write Protect RTU0_PRU access Debug IMEM" "disable,enable"
bitfld.long 0x04 1. "PRU1_WP_EN,Write Protect PRU1 access Debug IMEM" "disable,enable"
newline
bitfld.long 0x04 0. "PRU0_WP_EN,Write Protect PRU0 access Debug IMEM" "disable,enable"
tree.end
tree "ICSSM0_RAT_SLICE0_CFG"
base ad:0x8000
rgroup.long 0x00++0x07
line.long 0x00 "PR1_RAT_SLICE0__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PR1_RAT_SLICE0__CFG__MMRS_config,The Config Register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x04 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x04 0.--7. 1. "REGIONS,Number of regions"
group.long 0x804++0x03
line.long 0x00 "PR1_RAT_SLICE0__CFG__MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x820++0x1B
line.long 0x00 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 12 bits"
line.long 0x14 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
newline
bitfld.long 0x14 9. "PRIV,Priv" "0,1"
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "PR1_RAT_SLICE0__CFG__MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x840++0x13
line.long 0x00 "PR1_RAT_SLICE0__CFG__MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "PR1_RAT_SLICE0__CFG__MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "PR1_RAT_SLICE0__CFG__MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "PR1_RAT_SLICE0__CFG__MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "PR1_RAT_SLICE0__CFG__MMRS_eoi_reg,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
group.long 0x20++0x0F
line.long 0x00 "PR1_RAT_SLICE0__CFG__MMRS_ctrl,The Control for Region a"
bitfld.long 0x00 31. "EN,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "SIZE,Size of the Region in Address Bits" "1 byte,2B,4B,8B etc,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,4GB,?..."
line.long 0x04 "PR1_RAT_SLICE0__CFG__MMRS_base,The Base Address for Region a"
line.long 0x08 "PR1_RAT_SLICE0__CFG__MMRS_trans_l,The Translated Lower Address Bits for Region a"
line.long 0x0C "PR1_RAT_SLICE0__CFG__MMRS_trans_u,The Translated Upper Address Bits for Region a"
bitfld.long 0x0C 0.--3. "UPPER,Translated Upper Address Bits for the Region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "ICSSM0_RAT_SLICE1_CFG"
base ad:0x9000
rgroup.long 0x00++0x07
line.long 0x00 "PR1_RAT_SLICE1__CFG__MMRS_pid,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PR1_RAT_SLICE1__CFG__MMRS_config,The Config Register contains the configuration values for the module"
hexmask.long.byte 0x04 16.--23. 1. "ADDR_WIDTH,Number of address bits"
hexmask.long.byte 0x04 8.--15. 1. "ADDRS,Number of addresses"
hexmask.long.byte 0x04 0.--7. 1. "REGIONS,Number of regions"
group.long 0x804++0x03
line.long 0x00 "PR1_RAT_SLICE1__CFG__MMRS_destination_id,The Destination ID Register defines the destination ID value for error messages"
hexmask.long.byte 0x00 0.--7. 1. "DEST_ID,The destination ID"
group.long 0x820++0x1B
line.long 0x00 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_control,The Exception Logging Control Register controls the exception logging"
bitfld.long 0x00 1. "DISABLE_INTR,Disables logging interrupt when set" "0,1"
bitfld.long 0x00 0. "DISABLE_F,Disables logging when set" "0,1"
line.long 0x04 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_header0,The Exception Logging Header 0 Register contains the first word of the header"
hexmask.long.byte 0x04 24.--31. 1. "TYPE_F,Type"
hexmask.long.word 0x04 8.--23. 1. "SRC_ID,Source ID"
hexmask.long.byte 0x04 0.--7. 1. "DEST_ID,Destination ID"
line.long 0x08 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_header1,The Exception Logging Header 1 Register contains the second word of the header"
hexmask.long.byte 0x08 24.--31. 1. "GROUP,Group"
hexmask.long.byte 0x08 16.--23. 1. "CODE,Code"
line.long 0x0C "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data0,The Exception Logging Data 0 Register contains the first word of the data"
line.long 0x10 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data1,The Exception Logging Data 1 Register contains the second word of the data"
hexmask.long.word 0x10 0.--15. 1. "ADDR_H,Address upper 12 bits"
line.long 0x14 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data2,The Exception Logging Data 2 Register contains the third word of the data"
hexmask.long.word 0x14 16.--27. 1. "ROUTEID,Route ID"
bitfld.long 0x14 13. "WRITE," "0,1"
bitfld.long 0x14 12. "READ," "0,1"
bitfld.long 0x14 11. "DEBUG,Debug" "0,1"
bitfld.long 0x14 10. "CACHEABLE,Cacheable" "0,1"
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bitfld.long 0x14 9. "PRIV,Priv" "0,1"
bitfld.long 0x14 8. "SECURE,Secure" "0,1"
hexmask.long.byte 0x14 0.--7. 1. "PRIV_ID,Priv ID"
line.long 0x18 "PR1_RAT_SLICE1__CFG__MMRS_exception_logging_data3,The Exception Logging Data 3 Register contains the fourth word of the data"
hexmask.long.word 0x18 0.--9. 1. "BYTECNT,Byte count"
group.long 0x840++0x13
line.long 0x00 "PR1_RAT_SLICE1__CFG__MMRS_exception_pend_set,The Exception Logging Interrupt Pending Set Register allows to set the pend signal"
bitfld.long 0x00 0. "PEND_SET,Write a 1 to set the exception pend signal" "0,1"
line.long 0x04 "PR1_RAT_SLICE1__CFG__MMRS_exception_pend_clear,The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal"
bitfld.long 0x04 0. "PEND_CLR,Write a 1 to clear the exception pend signal" "0,1"
line.long 0x08 "PR1_RAT_SLICE1__CFG__MMRS_exception_enable_set,The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal"
bitfld.long 0x08 0. "ENABLE_SET,Write a 1 to set the exception interrupt enable signal" "0,1"
line.long 0x0C "PR1_RAT_SLICE1__CFG__MMRS_exception_enable_clear,The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal"
bitfld.long 0x0C 0. "ENABLE_CLR,Write a 1 to clear the exception interrupt enable signal" "0,1"
line.long 0x10 "PR1_RAT_SLICE1__CFG__MMRS_eoi_reg,EOI Register"
hexmask.long.word 0x10 0.--15. 1. "EOI_WR,EOI Register"
group.long 0x20++0x0F
line.long 0x00 "PR1_RAT_SLICE1__CFG__MMRS_ctrl,The Control for Region a"
bitfld.long 0x00 31. "EN,Enable for the Region" "0,1"
bitfld.long 0x00 0.--5. "SIZE,Size of the Region in Address Bits" "1 byte,2B,4B,8B etc,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,4GB,?..."
line.long 0x04 "PR1_RAT_SLICE1__CFG__MMRS_base,The Base Address for Region a"
line.long 0x08 "PR1_RAT_SLICE1__CFG__MMRS_trans_l,The Translated Lower Address Bits for Region a"
line.long 0x0C "PR1_RAT_SLICE1__CFG__MMRS_trans_u,The Translated Upper Address Bits for Region a"
bitfld.long 0x0C 0.--3. "UPPER,Translated Upper Address Bits for the Region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
endif
autoindent.off
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